WO2025063025A1 - Semiconductor element - Google Patents

Abstract

The present invention provides an insulated gate-type semiconductor element having a semiconductor layer composed of a gallium oxide-based material. The semiconductor element comprises: a substrate (10) including a Si single crystal; a semiconductor layer (17) (a non-doped layer (11), and an n-type layer (12)) which is provided in contact with the substrate (10) and is composed of a uniaxially oriented gallium oxide-based semiconductor; a gate insulating film (16) provided in contact with the semiconductor layer (17); and a gate electrode (13) provided on the gate insulating film (16). The gate insulating film (16) is composed of a gallium oxide-based semiconductor having a resistivity of 1×10⁴ Ω·cm or more.

Description

Semiconductor Device

This disclosure relates to semiconductor devices.

In recent years, gallium oxide has been actively researched as a semiconductor material. In particular, gallium oxide has attracted attention as a semiconductor material for power devices because of its wide band gap and high voltage resistance.

Known semiconductor elements include insulated gate type structures such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and insulated gate bipolar transistors (IGBTs). The insulated gate structure is a structure in which an insulating film is provided between a semiconductor layer and a metal (electrode). _SiO2 is widely used as the material for the gate insulating film.

Insulated gate type semiconductor elements using gallium oxide are also being considered. Patent Document 1 describes the use of gallium oxide as a gate insulating film.

Japanese Patent Application Publication No. 2021-136331

However, the inventors' research revealed that when a conventionally known material is used for the gate insulating film in a gate insulating semiconductor element using gallium oxide, many interface states are formed at the interface between the gallium oxide and the gate insulating film.

The inventors conducted extensive research into gate-insulated semiconductor elements using gallium oxide, leading to the completion of the semiconductor element disclosed herein.

This disclosure has been made in light of this background, and aims to provide an insulated gate type semiconductor element having a semiconductor layer made of a gallium oxide-based material.

One aspect of the present disclosure is
A substrate made of single crystal Si;
a semiconductor layer formed on and in contact with the substrate and made of a uniaxially oriented gallium oxide based semiconductor;
a gate insulating film provided in contact with the semiconductor layer;
a gate electrode provided on the gate insulating film,
The gate insulating film in the semiconductor element is made of a gallium oxide based semiconductor having a resistivity of 1×10 ⁴ Ω·cm or more.

According to the above aspect, it is possible to reduce the interface state density in an insulated gate semiconductor element having a semiconductor layer made of a gallium oxide-based material.

FIG. 1 is a cross-sectional view showing the configuration of a MOSFET according to the first embodiment, taken along a direction perpendicular to a main surface of a substrate.

The semiconductor element has a substrate made of single crystal Si, a semiconductor layer made of a uniaxially oriented gallium oxide-based semiconductor provided on and in contact with the substrate, a gate insulating film provided on and in contact with the semiconductor layer, and a gate electrode provided on the gate insulating film, where the gate insulating film is made of a gallium oxide-based semiconductor having a resistivity of 1 x ¹⁰⁴ Ω-cm or more.

Semiconductors are materials whose electrical conductivity can be controlled, and gallium oxide semiconductors have a wide band gap, making it possible to control their electrical conductivity from insulating to conductive.

The semiconductor element may be a MOSFET, an insulated gate bipolar transistor, or an insulated gate HFET (Heterojunction Field Effect Transistor).

The crystal plane of the main surface of the gate insulating film may be the same as the crystal plane of the main surface of the semiconductor layer.

The gate insulating film may be a film made of a gallium oxide semiconductor having the same composition as the semiconductor layer.

The gallium oxide semiconductor may be β-gallium oxide.

The main surface of the substrate may be a (100) surface, and the main surface of the semiconductor layer may be a (100) surface.

The [001] direction of the substrate and the [0-11] direction of the semiconductor layer may coincide.

(Embodiment 1)
Fig. 1 is a cross-sectional view showing the configuration of a MOSFET in embodiment 1, and is a view showing a cross section in a direction perpendicular to a main surface of a substrate. As shown in Fig. 1, the MOSFET in embodiment 1 has a substrate 10, a semiconductor layer 17, a gate electrode 13, a source electrode 14, a drain electrode 15, and a gate insulating film 16. In embodiment 1, the semiconductor layer 17 includes an undoped layer 11 containing a gallium oxide-based compound, and an n-type layer 12 made of an n-type gallium oxide-based compound.

The substrate 10 is made of a single crystal of silicon in which silicon atoms are arranged in a three-dimensional order. Any conventionally known substrate can be used for the substrate 10. For example, a substrate grown by crystal growth using the Czochralski method or the floating zone (FZ) method can be used.

The plane orientation of the main surface of the substrate 10 is preferably a (100) plane or a (111) plane. These plane orientations make it easy to grow gallium oxide crystals directly on the substrate 10. From an industrial standpoint, it is particularly preferable that the main surface of the substrate 10 be a (100) plane.

The surface of the substrate 10 may be modified. For example, the surface of the substrate 10 may be modified by surface treatment with oxygen plasma.

The non-doped layer 11 is a layer made of non-doped β-gallium oxide, and is provided directly on the substrate 10 without a buffer layer. In other words, the substrate 10 and the non-doped layer 11 are in contact with each other. The non-doped layer 11 is highly resistive, semi-insulating, or insulating. The thickness of the non-doped layer 11 is, for example, 100 nm to 50 μm.

Here, the buffer layer is a layer inserted for the purpose of relaxing the lattice constant, and is usually 20 nm or more thick. The buffer layer is, for example, made of the following materials: the same material as the non-doped layer 11, a material different from the non-doped layer 11, a layer formed by gradually changing the composition of a mixed crystal of the same material as the non-doped layer 11 and a different material, a superlattice structure in which the same material as the non-doped layer 11 and a different material are alternately stacked to a predetermined thickness, etc. In the first embodiment, such a buffer layer is not provided between the substrate 10 and the non-doped layer 11.

The non-doped layer 11 is a layer provided to prevent current from leaking to the substrate 10 side. By making the β-gallium oxide non-doped and forming it using a specific growth method (for example, the PAMBE method), it is possible to control the crystal defect concentration and impurity concentration to make it highly resistive, semi-insulating, or insulating.

Here, high resistance is, for example, a resistivity of 1×10 ⁴ to 1×10 ⁶ Ω·cm. Semi-insulating is, for example, a resistivity exceeding 1×10 ⁶ Ω·cm. Insulating is a state in which there are almost no carriers, for example, a carrier concentration of 1/cm ³ or less. Insulating occurs when the band gap is large and the Fermi level is near the center of the band gap. If the Fermi level is slightly off the center, it is semi-insulating, if it is further off, it is high resistance, and if it is further off and close to a conductor or valence band, it is conductive. β-gallium oxide has a large band gap, so it can be in a state ranging from insulating to conductive depending on the position of the Fermi level.

In the first embodiment, the β-gallium oxide is non-doped to provide high resistance, semi-insulating properties, or insulating properties, but it may also be possible to provide high resistance, semi-insulating properties, or insulating properties by doping the β-gallium oxide with impurities that form deep levels, such as Fe.

The non-doped layer 11 is a uniaxially oriented epitaxial layer on the substrate 10. Here, uniaxial orientation means that at least one of the crystal axes of the β-gallium oxide in the non-doped layer 11 is aligned with one of the crystal axes of the Si in the substrate 10. A layer that is uniaxially oriented in this way may be either single crystal or polycrystal. Whether the non-doped layer 11 is uniaxially oriented can be confirmed, for example, by the diffraction pattern of X-ray diffraction. Also, whether it is single crystal or polycrystal can be confirmed by the diffraction pattern of X-ray diffraction.

When the main surface of the substrate 10 is a (100) plane and the non-doped layer 11 is single crystal, it is preferable that the main surface of the non-doped layer 11 is a (100) plane. The (100) plane of Si and the (100) plane of β-gallium oxide have good lattice matching, allowing the non-doped layer 11 to be formed with high quality. The (100) plane of Si and the (100) plane of β-gallium oxide may form an angle of 10 degrees or less. The crystal plane of the non-doped layer 11 can be identified, for example, by a diffraction peak in θ-2θ measurement of X-ray diffraction.

Furthermore, it is preferable that the [001] direction of the Si of the substrate 10 and the [0-11] direction of the β-gallium oxide of the non-doped layer 11 coincide with each other. This is from the viewpoint of epitaxial growth of the non-doped layer 11. Here, "coincide" does not mean perfect coincidence, but rather that they should substantially coincide with each other. For example, if the [001] direction of the Si of the substrate 10 and the [001] direction of the β-gallium oxide of the non-doped layer 11 form an angle of about 23 to 28°, it can be said that the [001] direction of the Si of the substrate 10 and the [0-11] direction of the β-gallium oxide of the non-doped layer 11 substantially coincide with each other.

The n-type layer 12 is a layer made of n-type β-gallium oxide provided on the non-doped layer 11. The thickness of the n-type layer 12 is, for example, 10 nm to 1 μm. The n-type impurity added to form the n-type layer 12 may be Si, Sn, or the like. The n-type impurity concentration is, for example, 1×10 ¹⁷ to 1×10 ²¹ cm ⁻³ . Other configurations such as the plane orientation are similar to those of the non-doped layer 11.

The gate insulating film 16 is a film made of an insulator provided in contact with the semiconductor layer 17, and in the first embodiment, is provided in a predetermined region on the n-type layer 12. The material of the gate insulating film 16 is a high-resistance, semi-insulating or insulating β-gallium oxide-based semiconductor. That is, it is a β-gallium oxide-based semiconductor having a resistivity of 1×10 ⁴ Ω·cm or more. Here, the gallium oxide-based semiconductor is a gallium oxide in which a part of Ga is replaced with Al or In (Al _2x Ga _2y In _2-2x-2y O ₃ , 0≦x≦1, 0<y≦1) and has a β-phase crystal structure. More preferably, it is Al _2x Ga _2(1-x) O ₃ , 0≦x<1. It is even more preferable that the gate insulating film 16 has the same composition as the n-type layer 12, that is, it is gallium oxide.

A β-gallium oxide semiconductor can be doped with Fe, Si, Mg, etc. to form a deep level, or can be made into a high resistance, semi-insulating, or insulating material by inherent point defects. It is also possible to make it a high resistance, semi-insulating, or insulating material by not doping it. For example, the resistivity can theoretically be 1× ¹⁰ Ω·cm or more. The gate insulating film 16 is preferably semi-insulating or insulating, and more preferably insulating.

When a high-resistance, semi-insulating, or insulating β-gallium oxide-based semiconductor is used as the gate insulating film 16, it is possible to reduce the formation of interface states at the interface between the n-type layer 12 and the gate insulating film 16. This is because the n-type layer 12 and the gate insulating film 16 are made of the same β-gallium oxide-based semiconductor. For example, the interface state density can be set to 1×10 ¹⁰ to 1×10 ¹² cm ^-2 .

The gate insulating film 16 may be single crystal or polycrystalline, but if the n-type layer 12 is single crystal, the gate insulating film 16 is preferably single crystal as well. In this case, the main surface of the gate insulating film 16 is preferably the same crystal plane as the main surface of the n-type layer 12. However, an angle of about 10° is permitted. For example, if the main surface of the n-type layer 12 is a (100) plane, the main surface of the gate insulating film 16 is preferably a (100) plane. If the crystal plane of the gate insulating film 16 is set in this way, the interface state density can be further reduced. Other configurations may be the same as those of the non-doped layer 11.

The gate electrode 13 is an electrode provided on and in contact with the gate insulating film 16. The material of the gate electrode 13 is Ni, Pt, Au, Ag, Cu, Co, Ir, Ru, Pd, Cr, Mo, W, Ni/Au, Ni/Pt, Pt/Au, W/Au, Pt/Ti/Au, Pt/Au/Ni, Ti/Au/Ni, ITO, etc.

The source electrode 14 and the drain electrode 15 are electrodes provided in contact with the semiconductor layer 17, and in the first embodiment, are provided on the n-type layer 12. The source electrode 14 and the drain electrode 15 are provided so as to face each other with the gate electrode 13 therebetween in a plan view. The source electrode 14 and the drain electrode 15 are in ohmic contact with the n-type layer 12. The materials of the source electrode 14 and the drain electrode 15 are Ti, Ti/Au, Ti/Al/Au, Ti/Al/Ti/Au, Ti/Al/Ni/Au, Ti/Au/Ni, Sn, etc.

As described above, in the MOSFET of embodiment 1, the non-doped layer 11 and the n-type layer 12 are made of gallium oxide, which improves the breakdown voltage. In addition, since Si is used as the substrate 10, it can be made larger in diameter, and is excellent in terms of mass productivity and cost reduction. In addition, since a semi-insulating β-gallium oxide-based semiconductor is used as the gate insulating film 16, the formation of interface states at the interface between the n-type layer 12 and the gate insulating film 16 can be reduced.

Next, we will explain the manufacturing method of the MOSFET in embodiment 1.

First, a substrate 10, which is a Si single crystal substrate, is prepared. Then, the substrate 10 is placed in a furnace and heated to the growth temperature, after which the pressure in the furnace is reduced to the growth pressure. The ranges of the growth temperature and growth pressure will be described later.

Before forming the non-doped layer 11, the surface of the substrate 10 may be treated with oxygen plasma. This reduces the surface roughness of the substrate 10, making it easier to grow gallium oxide on the substrate 10.

Next, a non-doped layer 11 made of β-gallium oxide is formed on the substrate 10 by plasma-assisted molecular beam epitaxy (PAMBE). In the PAMBE method, a mixed gas containing oxygen and ozone is turned into plasma and supplied to the substrate 10, and gallium is evaporated and the substrate 10 is irradiated with a molecular beam. By turning the mixed gas containing oxygen and ozone into plasma, the ozone is decomposed to generate oxygen molecules and oxygen radicals. The oxygen radicals contain singlet oxygen atoms O( ¹ D) and triplet oxygen atoms O( ³ P), and the singlet oxygen atoms transition to triplet oxygen atoms at a predetermined ratio. The oxygen radicals react with the gallium from the molecular beam on the substrate surface, causing crystal growth of β-gallium oxide on the substrate 10 surface.

The growth pressure is preferably 0.001 Pa or more and 0.01 Pa or less. The growth temperature (substrate temperature) is preferably 0°C or more and 600°C or less. If the growth temperature and growth pressure are within this range, the non-doped layer 11 and the n-type layer 12 can be grown with good crystallinity.

A mixed gas containing oxygen and ozone can be produced by using an ozonizer to turn oxygen into plasma and converting some of the oxygen into ozone.

In a mixed gas containing oxygen and ozone, the ratio of ozone to the total of oxygen and ozone is preferably 10% by volume or more. There is no particular upper limit, but when a mixed gas containing oxygen and ozone is generated using an ozonizer, it is usually 50% by volume or less. An inert gas such as Ar may be mixed with the mixed gas containing oxygen and ozone before supplying it. This makes it easier to generate plasma.

Next, the n-type layer 12 is formed on the non-doped layer 11. The method for forming the n-type layer 12 may be any conventionally known method, such as CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), sputtering, etc. The non-doped layer 11 and the n-type layer 12 may be grown continuously using the same PAMBE method as for the non-doped layer 11.

Next, the gate insulating film 16 is formed in a predetermined region on the n-type layer 12. The method for forming the gate insulating film 16 is the same as the method for forming the non-doped layer 11. However, in order to form a high-resistance, semi-insulating, or insulating β-gallium oxide-based semiconductor, it is preferable to form it by a method such as the PAMBE method or plasma CVD method. It becomes easy to control the crystal defect concentration and impurity concentration to achieve high resistance. In addition, the non-doped layer 11, n-type layer 12, and gate insulating film 16 may be grown continuously by using the same formation method as the non-doped layer 11. By growing them continuously, it is possible to suppress the incorporation of impurities into the interface between the n-type layer 12 and the gate insulating film 16.

Next, the gate electrode 13 is formed on the gate insulating film 16 by a method such as deposition, and the source electrode 14 and the drain electrode 15 are formed on the n-type layer 12 by a method such as deposition. In this way, the MOSFET of embodiment 1 is manufactured.

(Modification of the first embodiment)
Although the first embodiment is a MOSFET, the present disclosure can be applied to any insulated gate type electronic device. For example, the present disclosure can be applied to an insulated gate bipolar transistor (IGBT) or an insulated gate type HFET. The present disclosure can also be applied to a trench gate type electronic device. The MOSFET in the first embodiment is a horizontal type, but the present disclosure can also be applied to a vertical type.

Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. This application is based on a Japanese patent application (Patent Application No. 2023-150630) filed on September 18, 2023, the contents of which are incorporated herein by reference.

10: Substrate 11: Non-doped layer 12: n-type layer 13: Gate electrode 14: Source electrode 15: Drain electrode 16: Gate insulating film 17: Semiconductor layer

Claims (10)

A substrate made of single crystal Si;
a semiconductor layer formed on and in contact with the substrate and made of a uniaxially oriented gallium oxide based semiconductor;
a gate insulating film provided in contact with the semiconductor layer;
a gate electrode provided on the gate insulating film,
The semiconductor element, wherein the gate insulating film is made of a gallium oxide based semiconductor having a resistivity of 1×10 ⁴ Ω·cm or more. The semiconductor element of claim 1, which is a MOSFET. The semiconductor element according to claim 1, which is an insulated gate bipolar transistor. The semiconductor device according to claim 1, which is an insulated gate HFET. The semiconductor element according to any one of claims 1 to 4, wherein the crystal plane of the main surface of the gate insulating film is the same as the crystal plane of the main surface of the semiconductor layer. The semiconductor element according to any one of claims 1 to 4, wherein the gate insulating film is made of a gallium oxide-based semiconductor having the same composition as the semiconductor layer. The semiconductor element according to any one of claims 1 to 4, wherein the gallium oxide-based semiconductor is β-gallium oxide. The semiconductor element according to any one of claims 1 to 4, wherein the main surface of the substrate is a (100) surface. The semiconductor element according to claim 8, wherein the main surface of the semiconductor layer is a (100) surface. The semiconductor element according to any one of claims 1 to 4, wherein the [001] direction of the substrate and the [0-11] direction of the semiconductor layer are aligned.

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