WO2025058863A1

WO2025058863A1 - Wafer-scale opto-electronic assemblies utilizing passive alignment techniques

Info

Publication number: WO2025058863A1
Application number: PCT/US2024/044585
Authority: WO
Inventors: Kalpendu Shastri; Ravinder Kachru; Anujit Shastri
Original assignee: Aayuna Inc
Current assignee: Aayuna Inc
Priority date: 2023-09-15
Filing date: 2024-08-30
Publication date: 2025-03-20
Anticipated expiration: 2026-03-15

Abstract

Disclosed herein is a scheme for utilizing multiple adjacent die ("tiles") fabricated on a common semiconductor wafer to create an opto-electronic subassembly, providing direct optical coupling between adjacent tiles while retaining the ability to utilize a passive optical alignment arrangement around the perimeter of the collection of tiles to couple fiber (or waveguide) arrays to the subassembly.

Description

WAFER-SCALE OPTO-ELECTRONIC ASSEMBLIES UTILIZING PASSIVE ALIGNMENT TECHNIQUES

Cross-Reference to Related Applications

This application claims the benefit of U . S . Provisional Application No . 63/ 538 , 660 , filed September 15 , 2023 and herein incorporated by reference .

Technical Field

Disclosed herein is a scheme for utilizing multiple adj acent die ("tiles" ) fabricated on a common semiconductor wafer to create an opto-electronic subassembly, providing direct optical coupling between adj acent tiles while retaining the ability to utili ze a passive optical alignment arrangement around the perimeter of the collection of tiles to couple fiber (or waveguide ) arrays to the subassembly .

Background of the Invention

Optical networking technology continues to press for higher switching speeds and larger port count configurations to meet the demands of applications such as cloud computing and data center communications , among others . Conventional silicon-based photonic integrated circuits ( PICs ) configured for these applications utilize standard CMOS processes to fabricate, for example , a complete switch matrix within a standard die area of a silicon wafer . It is contemplated that one approach to increasing the speed and port count for future applications may be reali zed by provisioning a "wafer-scale" type of PIC where multiple contiguous die are used to form a single photonic subassembly .

Standard CMOS processing used in creating PICs on a silicon wafer is based on step-and-repeat photolithography, where , for each mask level of the fabrication process , a mask pattern is defined over the entire area of a wafer by sequentially proj ecting a small- area, high-resolution light pattern ( referred to as a reticle ) onto a series of predefined die locations across the wafer surface . Unfortunately, the re-positioning of the reticle for each exposure field of the step-and-repeat process cannot be perfectly controlled and the relative position between features in adj acent exposure fields can vary . While the variation in reticle placement has little or no effect on traditional electronic IC fabrication, this placement variation ( also referred to as " stitching error" ) can give rise to a high optical loss when contemplating the creation of a wafer-scale optical subsystem by combining a set of die ( referenced to at times hereafter as "tiles" ) together to form a larger PIC configuration .

As such, there is a need to overcome this stitching error and provide a continuity of optical signal paths across the boundary from one tile to another . Another concern relates to the provision of reliable coupling to external signal paths ( fiber and/or waveguide arrays ) for the high count I/O port arrangement created around the perimeter of a collection of tiles . Indeed, a configuration that is able to provide both inter-tile optical waveguide array alignment and passive alignment to external components located around the periphery of the multi-tile assembly is preferred .

Summary of the Invention

The limitations in the art are addressed by a scheme for utilizing multiple adj acent die ("tiles" ) fabricated on a common semiconductor wafer to create an opto-electronic subassembly . Each tile is patterned around its periphery to include features providing for passive alignment to external components ( e . g . , lasers , wavelength division multiplexers , fiber array connects , and the like ) . The patterned edges also include ridge structures used to delineate the location of a waveguide array . In one embodiment of the present invention, the plurality of tiles formed on a wafer are identical , with the reticle used in patterning the tile creating the same pattern of alignment features and ridge structures along each edge ( at times referred to as "north, south, east , and west" edges for the sake of illustration) . The edge pattern is particularly configured to be able to support inter-tile optical coupling as well as passively-aligned coupling of the exposed perimeter ( edges ) of the collection of tiles with external waveguiding elements ( for example , individual fibers and/or fiber arrays ) .

In another embodiment , the tiles are created to include identical patterns on opposing pairs of edges ; that is , the northsouth pair of edges of each tile exhibits a first edge pattern and the east-west pair of edges of each tile exhibits a second edge pattern .

One exemplary arrangement of the present invention may provide a plurality of individual waveguide array configurations ( ridge structures ) as part of an edge connection pattern . In a preferred configuration which addresses the need for a high port count , each waveguide array may be formed with minimal spacing (pitch) between adj acent waveguides . Alignment features are formed at defined locations along each edge of a tile ( again, defined by the reticle pattern) and used to provide passive alignment with external optical signal paths . Selected arrays may include one or more optical port locations (which may be identified by a recessed edge termination) to accommodate the attachment of optical fibers .

An embodiment of the present invention may take the form of a multi-tile opto-electronic assembly comprising a collection of contiguous tiles formed on a wafer, with each tile including at least one waveguide array formed therein and terminating along an edge selected from the set of four edges , and a patterned edge connection formed along each edge . The patterned edge connection includes both a plurality of etched alignment features and a ridge structure for enclosing the at least one waveguide array, the ridge structure including etched vertical sidewalls formed beyond the boundaries of the at least one waveguide array. The collection of contiguous tiles forms a plurality of exposed opto-electronic assembly edges, with the plurality of patterned edge connections configured to provide passive optical alignment with external components .

Other and further embodiments and aspects of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.

Brief Description of the Drawings

Referring now to the drawings, where like reference numerals represent like parts in several views:

FIG. 1 is a simplified view of a conventional silicon wafer, illustrating various individual tiles that are fabricated on the wafer;

FIG. 2 shows an exemplary tile and associated reticle pattern for creating one example of an edge connection pattern;

FIG. 3 is an enlarged view of a portion of the tile shown in FIG. 2, in this case to clearly show a possible edge connection pattern;

FIG. 4 depicts an exemplary 3x3 combination of tiles that may be used to form a desired opto-electronic assembly;

FIG. 5 shows another type of waveguide coupling that may be used to form a signal path from one tile to another;

FIG. 6 illustrates a relatively complex edge connection pattern that may be used in the arrangement of the present invention;

FIG. 7 depicts an exemplary patterned connection region that may be used in the arrangement of FIG. 6; FIG . 8 illustrates an example tile that is formed to use one edge connection pattern along an opposing pair of edges , and another edge connection pattern on the remaining opposing pair of edges ;

FIG . 9 illustrates a set of four di f ferent patterns that may be included within the reticle used in creating waveguide array ridges ; and

FIG . 10 shows an exemplary optical sub-assembly formed by using a pair of contiguous tiles with edge patterning as discussed above .

Detailed. Description

FIG . 1 is a simpli fied view of a conventional silicon wafer 100 including a plurality of individual tiles 10 fabricated within wafer 100 . For illustrative purposes , a first multi-tile optoelectronic assembly Ml is shown as a 3x3 grouping of individual tiles ; a second multi-tile opto-electronic assembly M2 is defined by a 1x4 group of tiles 10 . Standard wafer processing is maintained, regardless of the grouping that will eventually be used, including the formation of the grid of streets 11 that delineate the boundaries of each tile . For the purposes of the present invention, it is fair to presume that any multi-tile optoelectronic assembly will comprise an MxN array of contiguous tiles (where M may equal N, with at least one of M or N being greater than one ) .

FIG . 2 is a view of an exemplary tile 10 which is shown as including an active area 12 within which various optical , electrical , and opto-electronic devices and components may be formed or attached ( e . g . , using flip-chip bonding of electrical ICs ) . Also shown in FIG . 2 is an edge connection pattern 14 created by a reticle template in a manner well-known in the art . The reticle template used in this specific example results in each edge of tile 10 exhibiting the same edge connection pattern 14 . It is to be noted that the use of the same pattern on all four edges of the tile is only one example; indeed, it is possible that each edge exhibits a different pattern of alignment features and waveguide array ridge structures, where in each case the reticle used to pattern the tile exhibits the particular pattern to be formed along each edge. Here, each edge connection pattern is shown as including several alignment features 16 and a ridge structure 18 used to surround a waveguide array 20. In particular, ridge structure 18 is formed to include opposing vertical sidewalls 18L and 18R that define the boundaries of waveguide array 20.

Continuing with reference to FIG. 2, various ones of individual features forming edge connection pattern 14 may comprise different depths, with some formed using a deep reactive ion etching technique (referred to as deep RIE, or simply DRIE) , and used for purposes such as passive alignment to external components.

Also included in the diagram of FIG. 2 are direction designations for identifying the individual edges of tile 10; that is "N" for north, "S" for south, "E" for east, and "W" for west are illustrated and used in describing the combining of individual tiles 10, as well as the directions of optical signal flow within the multi-tile opto-electronic assembly. That is, signals exiting along a south edge of a given tile will couple into waveguides appearing along the north edge of an adjacent tile; signals exiting along the east edge will couple to waveguides appearing along the west edge of another adjacent tile, and the like.

Reference is made to our US Patent 11,886,013 entitled "Passively-Aligned Fiber Array to Waveguide Configuration", issued on January 10, 2024 (as well as its related continuation application Serial No. 18/539,386, filed December 14, 2023) for a complete discussion of the use of alignment features to provide passive alignment between external fiber arrays and waveguide arrays terminating along an end face of a PIC. FIG. 3 is an enlargement of a portion of a tile 10, illustrating an exemplary edge connection pattern 14 as terminating along a defined tile edge 13. Shown in this example is a pair of alignment features 16 and a single waveguide array ridge 18. A waveguide array 20 is shown as disposed within waveguide array ridge 18. The reticle used in this example is particularly defined to etch sidewalls 18L, 18R on either side of a predefined waveguide array location, thus forming the desired ridge structure that will enclose the waveguide array. Waveguide array 20 itself is shown as including a plurality of N individual waveguides 20i - 20_N.

FIG. 4 illustrates a 3x3 combination of a plurality of tiles 10 that may be used to form a desired multi-tile opto-electronic assembly. The east-west and north-south interior optical array couplings between adjacent tiles are shown (one such coupling between tiles lOao and IO31 referenced by the letter C in FIG. 4) , where in this case optical signals propagating along waveguide arrays 20 are coupled from one tile to another (i.e., "inter-tile coupling") . Also defined in FIG. 4 is an exterior connection termination 30, formed by a continuous length of exposed edges (i.e., "exterior edges") from one tile 10 to another. In particular, a set of three edges 13io, 1320, and 1330 of tiles lOio, I O20, and lOso, respectively, is shown as forming exterior connection termination 30 "west" (that is, termination edge 30W) .

Various techniques may be used to ensure that the waveguide- to-waveguide coupling between tiles does not suffer a high degree of optical loss, particularly loss that may be related to stitching error in alignment between adjacent waveguide arrays 20 (identified by coupling C in FIG. 4) . In one case, an index matching epoxy may be used to fill the diced streets 11 that are created between the tiles as part of wafer processing. Alternatively, the individual waveguides within each tile may be formed to exhibit a tapered endface termination along the edges of tiles, where the taper is created to increase the mode field diameter of a propagating optical signal and thus increase the coupling surface area at the intersection between adj acent tiles . Moreover, it is to be understood that an index-matching material may be used in combination with tapered endfaces to further improve the coupling ef ficiency between waveguide arrays .

FIG . 5 illustrates yet another arrangement that may be used to ensure adequate optical coupling from one tile to another, in this case utilizing a two layer arrangement of individual beams to define a single optical signal path that will necessarily illuminate more of the coupled waveguide on an adj acent tile .

This arrangement as shown in FIG . 5 utili zes silicon nitridebased waveguides , as well as structures using a "stack" of waveguides formed through the thickness of each tile . Reference is made to our co-pending application US Serial No . 18 /271 , 878 , filed July 12 , 2023 and entitled "Dual Layer Optical Coupling Configuration Between Photonic Integrated Circuit and External Single Mode Fiber" for a complete and thorough discussion of this topic .

In the particular arrangement 50 as shown in FIG . 5, a set of four individual waveguide terminations , denoted as 52- 1 , 52-2 , 52- 3 , and 52-4 , are used to define a single optical signal path ( equivalent to a waveguide 20 as defined above ) , with the set of four individual beams illuminating a paired waveguide in an adj acent tile . It is to be understood that the illustration of a set of four beams is exemplary only; various configurations of individual beams may use a larger ( or smaller ) number of individual beams , as suitable for a particular application .

An inset is included in FIG . 5 that depicts an exemplary stack arrangement 50 that may be used to create the set of four individual beams . As shown, a waveguide 51 interior within tile 10 is evanescently coupled to a Y-splitter waveguide configuration 53 , which is in turn evanescently coupled to a pair of individual waveguides 55 . All of the waveguides are formed of silicon nitride and are known to allow for evanescent coupling when formed in a silicon substrate material ( such as used in the formation of tile 10 ) . The combination of Y-splitter 53 and waveguides 55 function to form the individual beams 52 which will exit along an edge 13 of tile 10 and collectively illuminate a larger area of a mating waveguide on an adj acent tile for improved coupling ef ficiency .

It is to be understood that the reticle used to create illustrated edge connection pattern 14 as shown in FIGs . 2 and 3 is only one example and is , in fact, a simpli fied example used for the purposes of describing the functionality of the present invention . FIGs . 6 and 7 illustrate a more complex edge connection pattern which may utilized in a speci fic application . Here, a tile 60 is formed to support a pair of electrical circuits 62- 1 and 62-2 that may be flip-chip mounted onto a central area of a photonic IC region 61 of tile 60 . The reticle used in this case creates an edge connection pattern 64 along all four edges that includes alignment features 66 and patterned connection regions 68 .

An exemplary patterned connection region 68 is shown in FIG . 7 as consisting of a plurality of waveguide array ridges 70 ( denoted as individual waveguide array ridges 70i - 70_N) . The reticle used to create pattern 64 may be controlled by lithographic techniques such that each ridge 70i is formed to exhibit a length x on the order of tens of microns (perhaps , for example , 125 pm or 250 pm, or other suitable value ) . Alignment features 66 may include a set of "internal" alignment features 66i formed between selected, adj acent waveguide ridges 70_x and 70_x+i , as well as "external" alignment features 66_e formed beyond the extent of a particular patterned connection region 68 . Also depicted in FIG . 7 is an individual waveguide ridge 70i , which is shown as supporting a plurality of N waveguides 72 . In this case , an optical port waveguide 74 is also included and in some configurations may be used as an I /O port with respect to external signal paths . Recall that another embodiment of the present invention may be based upon a reticle that creates a first matching pattern on the north/ south edges of a tile and a second matching pattern on the east/west edges of the same tile . FIG . 8 illustrates an exemplary tile 80i that exhibits the same edge connection pattern 82 on the north and south edges of the tile . For the sake of clarity, the pattern 83 formed along east/west edges of tile 80i is depicted as a box without any detail regarding the individual features .

North/ south connection pattern 82 is formed in this case to include alignment features 84 and a plurality of waveguide array ridges 86 . Each waveguide ridge 86 is configured to enclose a plurality of waveguides 88i and an optical I /O port waveguide 90i , where in this particular example each I /O port waveguide 90i is positioned in the center of the array configured formed by waveguides 88i . Each I /O port waveguide 90i is depicted by a relatively thick line segment in FIG . 8 , where this is only for the purpose of clearly identi fying the port waveguides from the remaining waveguide array . The arrangement as shown in FIG . 8 comprises a set of twelve individual ridges 86i - 8612 and, therefore , a set of twelve I /O port waveguides 90i - 9012.

As will be discussed below in association with FIG . 10 , the specific dimensions involved in providing this arrangement of alignment features 84 and array ridges 861 - 8612 are defined by the reticle pattern and fabrication processes used to form these elements . In particular, the reticle pattern is speci fied to match related features on a standard fiber array unit ( FAU) . By matching these features , an FAU may be attached to tile 80i in a manner that provides passive optical alignment between the fiber array supported in the FAU and the I /O waveguide port "array" within the plurality of array ridges 86. For example , a pitch P between adj acent I/O waveguide ports 90± and 90i+i is shown in FIG . 8 and is controlled by the reticle template to match an inter- fiber pitch on an associated FAU ( as particularly shown below in FIG . 10 ) . FIG. 9 illustrates a set of four different patterns that may be formed by the reticle used in creating waveguide array ridges 861 - 8612 of edge connection pattern 82 as described above in association with FIG. 8. FIG. 9(a) shows the formation of a wide "street" 92 being formed along the south (or north) edge termination, as well as a separate etched feature 94 formed at the interface with optical port waveguide 90. As discussed in various other patents and applications owned by the assignment of this application, feature 94 may be formed using a DRIE process to support the placement of an optical fiber (from an external component) that is to be coupled to I/O port waveguide 90 in a passive alignment system. The configuration shown in FIG. 9(b) differs from that of FIG. 9(a) in that a recessed feature 96 is etched across all of the waveguide terminations (that is, waveguide array 88 as well as I/O port waveguide 90) . FIGs. 9(c) and 9(d) are similar to FIGs. 9(a) and 9(b) , respectively, except that the reticle used in this case creates a "narrow" street demarcation along the north-south edge terminations, including a narrow etch- back 99 within the array waveguide array structure.

FIG. 10 illustrates an optical sub-assembly formed by using a contiguous pair of tiles 110-1 and 110-2. Similar to tile 80i as discussed above in association with FIGs. 8 and 9, only the north and south edges are shown as patterned, for the sake of clarity. Again, it is possible (likely) that the east and west edges of each tile are also patterned. In this particular example, an edge connection pattern 112 is used that creates individual alignment features 114i, 1142, 1143, and 1144 as well as a pair of waveguide array ridge groupings 116i and 116c. More particularly as shown in FIG. 10, an identical reticle-defined pattern is used to form the edge connection pattern 112 on both the "north" and "south" edges of both tiles 110-1 and 110-2. For the purposes of this discussion the specific edge connection pattern created along the north edge of tile 110-1 is referred to as edge connection pattern 112-1, and the edge connection pattern created along the south edge of tile 110-2 is referred to as edge connection pattern 112-2 .

Referring to edge connection pattern 112- 1 , alignment features 114i and 114i are shown as disposed on either side of first waveguide array ridge grouping 116i , with alignment features 1143 and 1144 disposed on either side of second waveguide array ridge grouping 116i .

Each waveguide array grouping 116i is shown as comprising a plurality of individual waveguide structures 118 ( similar to waveguide structures 86 shown in FIG . 8 ) , with each waveguide structure 118 shown as surrounding an array of inter-tile waveguides 120 , with an associated I /O port waveguide 122 positioned in the middle of each array of inter-tile waveguides 120 .

Alignment features 114 as appearing on the exposed north edge of tile 110- 1 and the exposed south edge of tile 110-2 may be utilized to provide alignment between individual fiber arrays and an associated array of I /O port waveguides , as mentioned above in association with FIG . 8 .

FIG . 10 shows a location of a pair of fiber array units ( FAUs ) 200-1 , 200-2 as aligned with the south exposed edge of tile 110-2 . FAU 200- 1 is depicted as including a plurality of V-grooves 210- 1 for supporting an array of optical fibers in alignment with a plurality of I /O port waveguides 122- 1 . FAU 200-1 also includes a pair of alignment V-grooves 220-1 , 220-2 that engage with alignment features 114i and 1142 , respectively, formed as part of edge connection pattern 112-2 .

While not shown in detail , the inter-tile alignments between facing waveguide arrays may utilize any of the various techniques described above ( or other well-known approaches ) to address optical coupling loss (or loss in general ) that may be attributed to stitching error created during the step-and-repeat reticle exposure during wafer processing . While the principles of the present invention have been particularly shown and described with respect to illustrative and preferred embodiments , it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention, which should be limited only by the scope of the claims appended hereto .

Claims

What is claimed is :

1 . A multi-tile opto-electronic assembly comprising a collection of contiguous tiles formed on a wafer, each tile comprising at least one waveguide array formed therein and terminating along an edge selected from the set of four edges ; and a patterned edge connection formed along each edge, the patterned edge connection including a plurality of etched alignment features ; and a ridge structure for enclosing the at least one waveguide array, the ridge structure including etched vertical sidewalls formed beyond the boundaries of the at least one waveguide array, wherein the collection of contiguous tiles forms a plurality of exposed opto-electronic assembly edges , with the plurality of patterned edge connections configured to provide passive optical alignment with external components .

2 . The multi-tile opto-electronic assembly as defined in claim 1 wherein the collection of contiguous tiles forms a plurality of inter-tile interfaces between interior edges of adj acent tiles , with the ridge structure included within each patterned edge connection supporting optical signal coupling between a first waveguide array formed within a first tile of the collection of contiguous tiles and terminating along an interior edge thereof and a second waveguide array formed within a second, adj acent tile of the collection of contiguous tiles and terminating along an interior edge thereof that interfaces with the interior edge of the first tile .

3. The multi-tile opto-electronic assembly as defined in claim 2 wherein the first waveguide array terminates as a first tapered waveguide array along the first tile interior edge and the second waveguide array terminates as a second tapered waveguide array along the second tile interior edge , increasing optical coupling between the first and second waveguide arrays .

4 . The multi-tile opto-electronic assembly as defined in claim 2 , further comprising index matching material disposed along at least one interface of the plurality of inter-tile interfaces .

5 . The multi-tile opto-electronic assembly as defined in claim 2 wherein the first waveguide array terminates as a first multi-layer stack comprising a two layer arrangement of individual beams utili zed to define a single optical signal path for each individual waveguide forming the first waveguide array .

6 . The multi-tile opto-electronic assembly as defined in claim 5 wherein the second waveguide array similarly terminates as a second multi-layer stack comprising a two layer arrangement of individual beams utilized to define a single optical signal path for each individual waveguide forming the second waveguide array .

7 . The multi-tile opto-electronic assembly as defined in claim 1 wherein a first opposing pair of edges of each tile forming the collection of contiguous tiles exhibits a first pattern of alignment features and ridge structures .

8 . The multi-tile opto-electronic assembly as defined in claim 7 wherein a second opposing pair of edges of each tile forming the collection of contiguous tiles also exhibits the first pattern of alignment features and ridge structures .

9 . The multi-tile opto-electronic assembly as defined in claim 7 wherein the second opposing pair of edges exhibits a second, dif ferent pattern of alignment features and ridge structures .

10 . The multi-tile opto-electronic assembly as defined in claim 1 wherein at least one patterned edge connection on each tile of the collection of contiguous tiles comprises a ridge structure disposed between a pair of alignment features .

11 . The multi-tile opto-electronic assembly as defined in claim 1 wherein at least one patterned edge connection on each tile of the collection of contiguous tiles comprises a plurality of ridge structures , each ridge structure enclosing a separate waveguide array .

12 . The multi-tile opto-electronic assembly as defined in claim 11 wherein the at least one patterned edge connection includes at least one alignment feature disposed between a pair of ridge structures forming the plurality of ridge structures .

13. The multi-tile opto-electronic assembly as defined in claim 12 wherein the at least one patterned edge connection further includes a pair of alignment features disposed beyond opposing ends of the plurality of ridge structures .

14 . The multi-tile opto-electronic assembly as defined in claim 1 wherein the at least one waveguide array comprises a plurality of waveguides supporting inter-tile optical communication and at least one waveguide used as an input/output ( I /O) port waveguide between the multi-tile opto-electronic assembly and an external optical fiber .

15 . The multi-tile opto-electronic assembly as defined in claim 14 wherein the patterned edge connection includes an etched feature in alignment with each I/O port waveguide, the etched feature sized to accommodate a diameter of the external optical fiber coupled thereto .

16 . The multi-tile opto-electronic assembly as defined in claim 14 wherein the patterned edge connection includes an etched feature extending between the vertical sidewalls of the ridge structure .

17 . The multi-tile opto-electronic assembly as defined in claim 14 wherein the patterned edge connection comprises a plurality of N separate ridge structures , each ridge structure associated with a separate waveguide array, each waveguide array comprising a plurality of waveguides supporting inter-tile communication and a single optical waveguide used as the I /O waveguide port , wherein the I/O waveguide port is located at a same position with respect to the plurality of waveguides within each waveguide array, the collection of I /O waveguide ports forming a plurality of N input/output external ports separated by a predetermined pitch P; and a pair of alignment features disposed beyond the extent of the plurality of N separate ridge structures , wherein the patterned edge connection is defined such that the predetermined pitch P corresponds to a fiber separation pitch associated with an external fiber array component, providing passive alignment between the external fiber array component and the plurality of ridge structures .