WO2025057937A1 - Data transfer device and computer system - Google Patents

Abstract

A data transfer device (30) is provided with a plurality of transfer destination identifying units (41) which accept input of data of interest of a data flow in which a plurality of arithmetic processes are connected, and which identify the next transfer destination of the input data of interest on the basis of transfer destination information of the data of interest. The data transfer device (30) is provided with a switch (50) configured to be capable of simultaneously connecting any of a plurality of input ports (51) and any of a plurality of output ports (52) in any combination. The transfer destination identifying units (41) each control the switch (50) independently of one other, connect the input port (51) connected thereto to the output port (52) connected to the transfer destination identified by the transfer destination identifying unit (41) itself, and input the data of interest to the input port (52).

Description

Data transfer device and computer system

The present invention relates to a data transfer device and a computer system.

Technological innovation is progressing in many fields, including machine learning, artificial intelligence (AI), and the Internet of Things (IoT), and by utilizing various data, services are being actively improved and added value is being provided. These technologies require large amounts of calculations, for which an information processing infrastructure is essential.

For example, Non-Patent Document 1 points out that modern computers are unable to keep up with the rapid increase in data, and that in order to achieve further evolution in the future, "post-Moore technology" that goes beyond Moore's Law must be established.

As a post-Moore technology, for example, Non-Patent Document 2 discloses a technology called flow-centric computing. Flow-centric computing introduces a new concept that moves data to a location where a computing function is present and processes it there, instead of the conventional computing idea of performing processing where the data is located.

“NTT Technology Report for Smart World 2020,” Nippon Telegraph and Telephone Corporation, 2020, https://www.rd.ntt/_assets/pdf/techreport/NTT_TRFSW_2020_EN_W.pdf R. Takano and T. Kudoh, “Flow-centric computing leveraged by photonic circuit switching for the post-moore era,” Tenth IEEE/AC M International Symposium on Networks-on-Chip (NOCS), Nara, 2016, pp. 1-3.https://ieeexplore.ieee.org/abstract/document/7579339

In flow-centric computing like the one described above, the data that is the subject of a data flow operation must be transferred to the next destination, and reducing the delay during this transfer is important.

The objective of the present invention is to reduce delays in the transfer of target data for data flow calculations.

In order to solve the above problem, the data transfer device of the present invention comprises a plurality of destination specification units that receive target data of a data flow in which a plurality of arithmetic processes are linked and specify the next destination of the input target data based on destination information of the target data, and a switch that has a plurality of input ports and a plurality of output ports and is configured to be able to simultaneously connect any combination of any of the plurality of input ports to any of the plurality of output ports, and each of the plurality of destination specification units independently controls the switch to connect an input port of the plurality of input ports connected to itself to an output port of the plurality of output ports connected to the destination specified by itself, and inputs the target data to the input port.

The computer system of the present invention comprises a data transfer device and a plurality of arithmetic units connected in a one-to-one relationship to a plurality of first destination specification units that are at least a part of the plurality of destination specification units, and the plurality of arithmetic units are respectively connected as the destination to a plurality of first output ports that are at least a part of the plurality of output ports of the switch, and each of the plurality of arithmetic units executes a calculation process that constitutes a data flow.

The computer system of the present invention comprises a data transfer device and a plurality of calculation units connected to a plurality of first destination specification units which are at least a part of the plurality of destination specification units, the plurality of first destination specification units and the plurality of calculation units are connected in a one-to-many relationship, the plurality of calculation units are respectively connected as the destination to a plurality of first output ports which are at least a part of the plurality of output ports of the switch, and each of the plurality of calculation units executes a calculation process which constitutes a data flow.

The present invention reduces delays in the transfer of data subject to data flow calculations.

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention. FIG. 2 shows an example of the structure of data transferred in the computer system of FIG. FIG. 3 is a diagram for explaining the operation of the computer system of FIG. FIG. 4 is a diagram showing an example of the structure of a correspondence table used in the computer system of FIG. FIG. 5 is a block diagram showing the configuration of a computer system according to a modified example of the present invention.

(Embodiment)
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings, however, the present invention is not limited to the following embodiment.

The computer system 10 according to the first embodiment shown in FIG. 1 is configured to execute a data flow that links multiple computational processes.

Computer system 10 comprises arithmetic circuits 20-1 to 20-N that perform arithmetic processing on input data, and a data transfer device 30 that transfers data from outside system 10 and data resulting from processing from each of arithmetic circuits 20-1 to 20-N to one of arithmetic circuits 20-1 to 20-N or to the outside of system 10. Hereinafter, arithmetic circuits 20-1 to 20-N are also collectively referred to as arithmetic circuits 20. Furthermore, the operations executed by arithmetic circuits 20-1 to 20-N are referred to as first to Nth operations, respectively. For example, arithmetic circuit 20-1 executes the first operation.

The computer system 10 is, for example, composed of one server computer. Therefore, the computer system 10 also includes a processor 11 such as a CPU (Central Processing Unit), a main memory 12, and a non-volatile storage 13 for storing programs executed by the processor 11. Each of the arithmetic circuits 20 is composed of a one-chip FPGA (Field-Programmable Gate Array) as an accelerator. Here, one arithmetic circuit 20 executes one type of arithmetic processing. The execution unit that executes the arithmetic processing, which is provided in the arithmetic circuit 20, is configured or deleted at a desired timing. The desired timing includes when the computer system 10 is in operation. The execution unit for the arithmetic processing is configured or deleted by, for example, the processor 11. The arithmetic circuit 20 may be an ASIC (Application Specific Integrated Circuit), a GPU (Graphics Processing Unit), or the like. The arithmetic circuit 20 may be composed of a processor that executes a program.

Each of the first to Nth arithmetic processes may be an arithmetic process on the target data of the data flow. The target data includes data before being input to the data flow (pre-processing data), data resulting from intermediate arithmetic processes included in the data flow (intermediate data), and data resulting from the last arithmetic process of the data flow (final data). Each of the first to Nth arithmetic processes constitutes at least one data flow among a plurality of data flows at least a part of which can be executed by the computer system 10. For example, the first to third arithmetic processes constitute a first data flow when linked together, and the fourth arithmetic process constitutes a second data flow together with an arithmetic process executed by an arithmetic circuit provided in another computer system. Furthermore, for example, the first arithmetic process constitutes a third data flow together with the fifth arithmetic process in addition to the first data flow.

The first through Nth arithmetic processes may be different processes from one another, or some of them may be the same type of process. Arithmetic processes performed on data include arithmetic operations on the data, as well as processes such as decoding encoded video data, reducing or enlarging the image size of image data, detecting specific objects in image data, and decrypting or encrypting image data, as well as arithmetic processes such as processing, aggregating, and combining the target data.

The calculation circuits 20-1 to 20-N are each assigned a calculation circuit ID "#1" to "#N" that identifies the circuit. Note that "#1" to "#N" are simply numbers for convenience, and in reality, IP addresses or the like are assigned.

The data transfer device 30 comprises a plurality of destination specification circuits 41-1 to 41-N respectively connected to the arithmetic circuits 20-1 to 20-N, and one or more destination specification circuits 41-N+1 to 41-L (where L is an integer equal to or greater than N+1; here, L=N+2) to which data supplied from outside the computer system 10 is input. The destination specification circuits 41-1 to 41-L are collectively referred to as destination specification circuits 41. The data transfer device 30 further comprises a switch 50 to which each destination specification circuit 41 is connected.

As described below, the destination specification circuit 41 specifies the next destination of the input data, for example the calculation circuit 20 that will perform the next calculation, and transfers the data to the destination via the switch 50. Each of the destination specification circuits 41-1 to 41-L is configured with an FPGA, ASIC, etc., and is configured to be able to operate independently of each other.

Under the control of the destination specification circuit 41, the switch 50 transmits the data from the destination specification circuit 41 to the next destination.

The switch 50 has a plurality of input ports 51-1 to 51-L to which the destination specification circuits 41-1 to 41-L are respectively connected. The switch 50 further has output ports 52-1 to 52-N to which the arithmetic circuits 20-1 to 20-N are respectively connected, and one or more output ports 52-N+1 to 52-L for transmitting data to the outside of the computer system 10. The input ports 51-1 to 51-L are also collectively referred to as input ports 51. The output ports 52-1 to 52-L are also collectively referred to as output ports 52. The ports 51 and 52 are physical ports, and may be general input/output interfaces, I/O Ethernet ports, PCIe, etc.

The switch 50 is configured to be able to simultaneously connect any combination of input ports 51-1 to 51-L and any combination of output ports 52-1 to 52-L under the control of the destination specification circuit 41. Such a switch 50 is, for example, a crossbar switch.

Here, the target data of the data flow input from the outside to the computer system 10 will be described with reference to FIG. 2. The target data is added with destination information of the target data, that is, information that can identify the destination. Here, the destination information is stored in a header added before the target data, but the position of the destination information relative to the target data is arbitrary. The destination information stores the arithmetic circuit IDs of the arithmetic circuits 20 or external arithmetic circuits of the computer system 10 that perform multiple arithmetic processes on the data body by the data flow, in the order in which the arithmetic processes are performed. For example, the destination information of the target data that is arithmetic processed by the first data flow in which a first arithmetic process is performed, a second arithmetic process is performed, and finally a third arithmetic process includes, from the head of the data, "#1", which is the arithmetic circuit ID of the arithmetic circuit 20-1 that performs the first arithmetic process, "#2", which is the arithmetic circuit ID of the arithmetic circuit 20-2 that performs the second arithmetic process, and "#3", which is the arithmetic circuit ID of the arithmetic circuit 20-3 that performs the third arithmetic process, as shown in FIG. 2. The destination information also includes a processing result destination address (e.g., IP address) at the end that identifies the destination of the data resulting from the processing of the entire data flow.

Next, the operation of the computer system 10 will be described with reference to FIG. 3. Here, target data as pre-processing data to be processed by the data flow is input from the outside to the destination specification circuit 41-L of the computer system 10 (step S11). The target data is also assumed to be data on which arithmetic processing is performed by the first data flow. As described above, destination information is added to the target data (see FIG. 3). Furthermore, data to be transferred below, such as the target data, may be divided into packets before being transferred. In such a case, the destination information is stored in the header of each packet, and the arithmetic circuit 20 and the like combine the data bodies of each packet to obtain the data to be subjected to arithmetic processing.

The destination specification circuit 41-L analyzes the destination information from the input target data and destination information (hereinafter, collectively referred to as input data) and obtains the first arithmetic circuit ID "#1" from among the multiple arithmetic circuit IDs included in the destination information. By obtaining the first arithmetic circuit ID, the arithmetic circuit identified by that arithmetic circuit ID is specified as the next destination of the target data.

The destination specification circuit 41-L holds a correspondence table between the destination and the output port to which the destination is connected, as shown in FIG. 4. In the correspondence table, the destination is represented by the destination's identification information, that is, the calculation circuit ID. The output port is represented by the port number (here, the code of the output port).

The destination specification circuit 41-L refers to the correspondence table using the arithmetic circuit ID "#1" acquired above as a key, and acquires the port number "52-1" corresponding to the arithmetic circuit ID "#1". After that, the destination specification circuit 41-L controls the switch 50 (S12) to connect the input port 51-L connected to itself to the output port 52-1 of the acquired port number (S13). After controlling the connection between the input port 51-L and the output port 52-1, the destination specification circuit 41-L inputs the input data to the switch 50 (S14). As a result, the input data is input to the arithmetic circuit 20-1 connected to the output port 52-1 via the data transfer path connecting the input port 51-L and the output port 52-1 (S15). As a result, the input data is transferred to the destination specified by the destination specification circuit 41-L.

The transfer destination included in the correspondence table may be only the arithmetic circuit 20 included in the computer system 10. If the arithmetic circuit ID obtained above is not included in the correspondence table, the transfer destination specification circuit 41-L may, for example, connect the input port 51-L and the output port 52-L and output the input data directly to the outside of the system 10. Furthermore, a correspondence table is prepared separately for each of the transfer destination specification circuits 41-1 to 41-L. If the transfer destination included in the correspondence table also includes an arithmetic circuit outside the computer system 10, the arithmetic circuit ID of the transfer destination is associated with one of the port numbers 52-N+1 to 52-L of the output port connected to the outside of the computer system 10.

The arithmetic circuit 20-1 performs a first arithmetic process on the target data among the input data. It also deletes the first arithmetic circuit ID "#1" from the destination information. The arithmetic circuit 20-1 uses the data resulting from the first arithmetic process, i.e., the intermediate data, as new target data, and generates intermediate post-operation data by adding the destination information after deleting the arithmetic circuit ID "#1" to the target data. The arithmetic circuit 20-1 transmits the generated intermediate post-operation data to the destination specification circuit 41-1 connected to this arithmetic circuit 20-1 (step S16).

The destination specification circuit 41-1 analyzes the destination information of the received intermediate post-computation data and acquires the first calculation circuit ID "#2" from among the calculation circuit IDs included in the additional data. In other words, the destination specification circuit 41-1 identifies the destination of the current intermediate post-computation data. The destination specification circuit 41-1 refers to its own correspondence table using the acquired calculation circuit ID "#2" as a key, and acquires the port number "52-2" corresponding to the calculation circuit ID "#2". The destination specification circuit 41-1 then controls the switch 50 (S17) and connects the input port 51-1 connected to itself to the output port 52-2 of the acquired port number (S18). The destination specification circuit 41-1 inputs the intermediate post-computation data to the switch 50 after controlling the connection between the input port 51-1 and the output port 52-2 (S19). As a result, the intermediate post-operation data is input to the operation circuit 20-2 connected to the output port 52-2 via the switch 50, more specifically, the input port 51-1, the output port 52-2, and the data transfer path connecting both ports (S20).

After this, like the calculation circuit 20-1, the calculation circuit 20-2 performs a second calculation process on the target data (intermediate data) contained in the intermediate post-calculation data and deletes the leading calculation circuit ID "#2" from the transfer destination information, and outputs the target data and transfer destination information after the second calculation process and after the calculation circuit ID deletion as second intermediate post-calculation data to the transfer destination specification circuit 41-2 (step S21).

The second intermediate post-operation data output to the destination specification circuit 41-2 is input to the operation circuit 20-3 via the destination specification circuit 41-2 and the switch 50 (steps S22 to S25). At this time, the destination specification circuit 41-2, like the destination specification circuit 41-1, references the correspondence table it holds and controls the connection between the input port 51-2 and the output port 52-3.

The calculation circuit 20-3 performs a third calculation process on the target data of the second intermediate post-calculation data and deletes the leading calculation circuit ID "#3" from the destination information, and outputs the target data and destination information after the third calculation process and after the calculation circuit ID deletion as the third intermediate post-calculation data to the destination specification circuit 41-3 (step S26). At this point, the destination information no longer includes the calculation circuit ID, so the third intermediate post-calculation data becomes the final post-calculation data after each calculation process by the data flow has been completed.

If the destination information of the final post-operation data does not include the operation circuit ID, the destination specification circuit 41-3 connects the input port 51-3 of the switch 50 connected to itself to any port among the output ports 52-L+1 to 52-L, here the output port 52-L, in order to transfer the final post-operation data to the outside of the system 10 (steps S27 and S28). The destination specification circuit 41-3 also transmits the final post-operation data, with the destination address of the final post-operation data included at the end of the destination information (e.g., IP address) and the MAC address obtained by referring to a routing table as necessary set in the header as the final destination and the destination of the next device, to the input port 51-3 (step S29). As a result, the processing result of the first data flow is finally transmitted to the final destination (step S30).

In this embodiment, the switch 50 is configured to be able to simultaneously connect multiple pairs of any of the multiple input ports 51-1 to 51-L and any of the multiple output ports 52-1 to 52-L in any combination. For example, the combination of the input port 51-2 and the output port 52-1 and the combination of the input port 51-3 and the output port 52-2 can be simultaneously connected. On the other hand, each of the destination specification circuits 41 can control the switch 50 independently of each other, connect the input port 51 connected to itself and the output port 52 connected to the destination specified by the destination information, and input the target data to the connected input port 51. Therefore, as long as the output port 52 does not overlap, multiple pairs of input ports 51 and output ports 52 can be connected independently, and data transfer is also performed in parallel for each pair. Conventionally, such parallel transfer is not performed, so when multiple types of data flows are executed simultaneously in parallel, data becomes congested during transfer. The parallel transfer of this embodiment eliminates such congestion. In this way, according to this embodiment, delays in the transfer of target data for data flow calculations are reduced (including elimination of delays).

In this embodiment, each transfer destination specification circuit 41 holds a correspondence table between the transfer destination and the output port to which this transfer destination is connected, and specifies the output port 52 to connect to the input port 51 by referring to the correspondence table, so that the connection between the input port 51 and the output port 52 can be realized with a simple circuit configuration.

In this embodiment, the switch 50 is a crossbar switch, which allows parallel data transfer through multiple data flows to be achieved with a simple configuration.

In this embodiment, the destination specification circuits 41-N+1 to 41-L and the output ports 52-N+1 to 52-L are connected to the outside of the computer system 10, so that data supplied from the outside can also pass through the destination specification circuits 41-N+1 to 41-L. In addition, data can be output to the outside from the output ports 52-N+1 to 52-L under the control of the destination specification circuits 41-N+1 to 41-L.

(Variation 1)
In the above embodiment, the arithmetic circuits 20-1 to 20-N are connected to the destination specification circuits 41-1 to 41-N in a one-to-one relationship, but as shown in the computer system 110 of FIG. 5, the multiple destination specification circuits 41 and the multiple arithmetic circuits 20 may be connected in a one-to-multiple relationship (see the destination specification circuit 41-1 and the multiple arithmetic circuits 20-1 and 20-2). In the one-to-multiple relationship, the overall circuit scale of the multiple destination specification circuits 41 can be made smaller than in the one-to-one relationship, and the control cost and implementation cost of the destination specification circuit 41 are reduced. In the one-to-one relationship, multiple data flows are executed independently without interfering with each other. In addition, since multiple data flows do not mix with each other, the system can be isolated, and virtualization is also possible. In addition, when a specific data flow is congested, the impact on other data flows can be suppressed.

(Variation 2)
As a modified example, a plurality of computer systems may be connected. That is, the computer system 10 or 110 may be configured to include an arithmetic circuit provided in each of a plurality of computers, rather than a single computer. That is, the computer system 10 or 110 may include an arithmetic circuit 20 of another computer connected to the data transfer device 30 via a network, a router, a network switch, or the like. In such a case, the transfer destination specification circuit 41 refers to, for example, a predetermined routing table, and includes information such as the IP address of the final transfer destination arithmetic circuit 20 and the MAC address of the next device to send data, in the data to be transferred.

In such a modified example, the correspondence table held by the destination specification circuit 41 may register information on all destinations of the other computer systems (such as arithmetic circuit IDs), or may register information on only some of the destinations. Furthermore, the destinations in the correspondence table may be represented by the addresses of the other computer systems themselves. If the correspondence table contains only a portion of all possible destinations, it is easier to know in advance what should be registered in the correspondence table when setting the target data and destination information that may pass through the destination specification circuit 41 before the start of operation, and the correspondence table can be implemented with less control cost. For example, if the destinations in the correspondence table are the addresses of the other computer systems themselves, the correspondence table does not need to include information on the arithmetic circuits that the other computer systems have, and the correspondence table can be implemented with less control cost.

The function of the destination specification circuit 41 may also be provided in a network switch or host machine that connects computer systems together, allowing data to be transferred to other computer systems in the network switch or host machine.

(Variation 3)
In the above, one execution unit for the arithmetic processing is configured for each arithmetic circuit 20, but multiple types of execution units may be configured. In this case, the arithmetic circuit ID includes, for example, the address of the arithmetic circuit 20 as well as data identifying the execution unit for the arithmetic processing (for example, the address of the execution unit). The arithmetic circuit 20 may perform the arithmetic processing using the execution unit indicated by the data.

(Variation 4)
The destination information does not have to be added to the target data and transferred. For example, a configuration may be adopted in which the destination information is transferred via a separate signal line in synchronization with the target data.

(Variation 5)
The correspondence table is set before the execution of the data flow starts. This setting may be performed inline with the execution line of the data flow by inputting a predetermined control packet to the computer system 10, or may be performed out-of-line using a management port or the like that the system 10 has.

(Variation 6)
Executable data flows may be added or deleted as appropriate. For example, when a data flow is added, it is not necessary to change the settings of all data flows, i.e., to replace the entire correspondence table, and only information about the added data flow (information about the transfer destination and output port) may be added to the correspondence table. The same applies when a data flow is deleted, and only information about the deleted data flow may be deleted from the correspondence table.

(Variation 7)
The destination specification circuit 41 may monitor its own operating status and data flow rate, and may change the correspondence table, i.e., executable data flows, when the operating degree or flow rate exceeds a predetermined threshold. The contents of the change in the correspondence table may be specified from outside. This change reduces the load on a specific destination specification circuit 41 and/or a specific arithmetic circuit 20.

(Variation 8)
The destination specification circuit 41 may change the correspondence table, i.e., the executable data flows, when the data size of the correspondence table held by the destination specification circuit 41 exceeds a predetermined threshold value. In this way, the time required for referencing the correspondence table is reduced, and the time required for transfer processing among a plurality of data flows is equalized.

(Scope of the present invention)
The present invention is not limited to the above-mentioned embodiment and modified examples. For example, the present invention includes various modifications to the above-mentioned embodiment and modified examples that can be understood by a person skilled in the art within the scope of the technical idea of the present invention. The configurations listed in the above-mentioned embodiment and modified examples can be appropriately combined within a range without contradiction. In addition, it is also possible to delete any of the above-mentioned configurations.

(Additional Note)
The configurations disclosed in the above-described embodiments and modifications are exemplified below.
(Appendix 1)
a plurality of destination specification units that receive target data of a data flow in which a plurality of arithmetic processes are linked, and specify a next destination of the input target data based on destination information of the target data;
a switch including a plurality of input ports and a plurality of output ports, the switch being configured to be capable of simultaneously connecting any of the plurality of input ports and any of the plurality of output ports in any combination;
each of the plurality of transfer destination specification units independently controls the switch to connect an input port connected to itself among the plurality of input ports to an output port connected to the transfer destination specified by itself among the plurality of output ports, and inputs the target data to the input port;
Data transfer device.
(Appendix 2)
each of the plurality of transfer destination specification units holds a correspondence table between a transfer destination and an output port to which the transfer destination is connected, and specifies the output port to be connected to the input port by referring to the correspondence table;
2. The data transfer device according to claim 1.
(Appendix 3)
The switch is a crossbar switch.
3. The data transfer device according to claim 1 or 2.
(Appendix 4)
A data transfer device according to any one of appendix 1 to 3;
a plurality of calculation units connected one-to-one to a plurality of first destination determination units that are at least a part of the plurality of destination determination units;
the plurality of calculation units are respectively connected as the transfer destinations to a plurality of first output ports which are at least a part of the plurality of output ports of the switch;
Each of the plurality of calculation units executes a calculation process constituting a data flow.
Computer system.
(Appendix 5)
A data transfer device according to any one of appendix 1 to 3;
a plurality of calculation units connected to a plurality of first destination determination units which are at least a part of the plurality of destination determination units;
the first destination specification units and the calculation units are connected in a one-to-multiple manner, and the calculation units are respectively connected as the destinations to a first output port that is at least a part of the output ports of the switch;
Each of the plurality of calculation units executes a calculation process constituting a data flow.
Computer system.
(Appendix 6)
the plurality of forwarding destination determination units are made up of the plurality of first forwarding destination determination units which are a part of the plurality of forwarding destination determination units and one or more second forwarding destination determination units which are the remaining part of the plurality of forwarding destination determination units,
the plurality of output ports include the plurality of first output ports which are a part of the plurality of output ports and one or more second output ports which are the remaining part of the plurality of output ports;
the second destination specification unit and the second output port are connected to an external device of the computer system;
6. The computer system of claim 4 or 5.

10...Computer system, 11...Processor, 12...Main memory, 13...Storage, 20-1 to 20-N...Arithmetic circuits, 30...Data transfer device, 41-1 to 41-N to 41-L...Destination specification circuit L, 50...Switch, 51-1 to 51-N to 51-L...Input ports, 52-1 to 52-N to 52-L...Output ports, 110...Computer system.

Claims (6)

a plurality of destination specification units that receive target data of a data flow in which a plurality of arithmetic processes are linked, and specify a next destination of the input target data based on destination information of the target data;
a switch including a plurality of input ports and a plurality of output ports, the switch being configured to be capable of simultaneously connecting any of the plurality of input ports and any of the plurality of output ports in any combination;
each of the plurality of transfer destination specification units independently controls the switch to connect an input port connected to itself among the plurality of input ports to an output port connected to the transfer destination specified by itself among the plurality of output ports, and inputs the target data to the input port;
Data transfer device. each of the plurality of transfer destination specification units holds a correspondence table between a transfer destination and an output port to which the transfer destination is connected, and specifies the output port to be connected to the input port by referring to the correspondence table;
2. The data transfer device according to claim 1. The switch is a crossbar switch.
2. The data transfer device according to claim 1. The data transfer device according to claim 1 ;
a plurality of calculation units connected one-to-one to a plurality of first destination determination units that are at least a part of the plurality of destination determination units;
the plurality of calculation units are respectively connected as the transfer destinations to a plurality of first output ports which are at least a part of the plurality of output ports of the switch;
Each of the plurality of calculation units executes a calculation process constituting a data flow.
Computer system. The data transfer device according to claim 1 ;
a plurality of calculation units connected to a plurality of first destination determination units which are at least a part of the plurality of destination determination units;
the first destination specification units and the calculation units are connected in a one-to-multiple manner, and the calculation units are respectively connected as the destinations to a first output port that is at least a part of the output ports of the switch;
Each of the plurality of calculation units executes a calculation process constituting a data flow.
Computer system. the plurality of forwarding destination determination units are made up of the plurality of first forwarding destination determination units which are a part of the plurality of forwarding destination determination units and one or more second forwarding destination determination units which are the remaining part of the plurality of forwarding destination determination units,
the plurality of output ports include the plurality of first output ports which are a part of the plurality of output ports and one or more second output ports which are the remaining part of the plurality of output ports;
the second destination specification unit and the second output port are connected to an external device of the computer system;
6. A computer system according to claim 4 or 5.

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