WO2025057867A1 - Semiconductor device, method for manufacturing semiconductor device, and communication device - Google Patents

Abstract

Provided is a semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer that is laminated on the compound semiconductor layer and has a first opening which exposes a first region on the upper surface of the compound semiconductor layer; a second insulating layer that is laminated on the first insulating layer and inside the first opening and has a second opening which has an opening narrower than the first opening and exposes a second region that is a portion of the first region of the compound semiconductor layer exposed by the first opening; and a gate electrode that is laminated on the upper surface of the second insulating layer and inside the second opening and is in direct contact with the second region on the upper surface of the compound semiconductor layer.

Description

Semiconductor device, semiconductor device manufacturing method, and communication device

This disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a communication device.

HEMT (High Electron Mobility Transistor) devices, which are heterogeneous field effect transistors (FETs) made of gallium nitride (GaN)-based wide-gap semiconductor materials, are capable of low resistance and high-speed, high-voltage operation, and are therefore expected to be used in power devices and RF (Radio Frequency) devices such as switches in 5G high-speed communication systems.

JP 2021-125575 A JP 2020-13883 A

However, in conventional HEMT devices, it has been difficult to reduce the off-state current, which is determined by gate leakage, while suppressing degradation of the on-state characteristics. Even if it were possible to reduce the off-state current while suppressing degradation of the on-state characteristics, it was difficult to avoid making the manufacturing process extremely complicated, and it was also difficult to avoid damage to the semiconductor surface.

This disclosure therefore proposes a semiconductor device that can be manufactured easily and damage-free, and that can reduce the current when off while suppressing deterioration of characteristics when on, a method for manufacturing the semiconductor device, and a communication device equipped with the reaction device.

According to the present disclosure, there is provided a semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and within the first opening and having a second opening that exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and within the second opening and in direct contact with the second region on the upper surface of the compound semiconductor layer.

Furthermore, according to the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: stacking a first insulating layer on a ternary or quaternary compound semiconductor layer, the first insulating layer having a first opening exposing a first region on the upper surface of the compound semiconductor layer; performing a reduction treatment on the first region; stacking a second insulating layer on the first insulating layer and in the first opening, the second insulating layer having a second opening narrower than the first opening, exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening; and forming a gate electrode on the upper surface of the second insulating layer and in the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer.

Further, according to the present disclosure, there is provided a communication device equipped with a semiconductor device, the semiconductor device comprising: a ternary or quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and within the first opening and having a second opening exposing a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and having an opening narrower than the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and within the second opening and in direct contact with the second region on the upper surface of the compound semiconductor layer.

FIG. 1 is an explanatory diagram for explaining an overview of a HEMT device having an MIS gate structure. FIG. 1 is an explanatory diagram illustrating an overview of a HEMT device having a Schottky gate structure. FIG. 1 is a first explanatory diagram for explaining details of the study conducted by the present inventors. FIG. 2 is a second explanatory diagram for explaining details of the study conducted by the present inventors. FIG. 11 is an explanatory diagram (part 3) for explaining details of the study conducted by the present inventors. FIG. 4 is an explanatory diagram (part 4) for explaining details of the study conducted by the present inventors. FIG. 5 is an explanatory diagram (part 5) for explaining details of the study conducted by the present inventors. FIG. 6 is an explanatory diagram (part 6) for explaining details of the study conducted by the present inventors. FIG. 7 is an explanatory diagram (part 7) for explaining details of the study conducted by the present inventors. FIG. 8 is an explanatory diagram (part 8) for explaining details of the study conducted by the present inventors. FIG. 9 is an explanatory diagram (part 9) for explaining details of the study conducted by the present inventors. FIG. 10 is an explanatory diagram (part 10) for explaining details of the study conducted by the present inventors. FIG. 2 is a cross-sectional view of the structure of a HEMT device according to a first embodiment of the present disclosure. FIG. 13B is an enlarged cross-sectional view of region B shown in FIG. 13A. 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a HEMT device according to a first embodiment of the present disclosure. 5A to 5C are cross-sectional views (part 2) illustrating the manufacturing method of the HEMT device according to the first embodiment of the present disclosure. 5A to 5C are cross-sectional views (part 3) illustrating the manufacturing method of the HEMT device according to the first embodiment of the present disclosure. 4 is a cross-sectional view (part 4) illustrating the manufacturing method of the HEMT device according to the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view (part 5) illustrating the manufacturing method of the HEMT device according to the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view (part 6) illustrating the manufacturing method of the HEMT device according to the first embodiment of the present disclosure. FIG. FIG. 7 is a cross-sectional view (part 7) illustrating the manufacturing method of the HEMT device according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view of a structure of a HEMT device according to a second embodiment of the present disclosure. FIG. 15B is an enlarged cross-sectional view of area C shown in FIG. 15A. 11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a HEMT device according to a second embodiment of the present disclosure. 13A to 13C are cross-sectional views (part 2) illustrating a method for manufacturing a HEMT device according to a second embodiment of the present disclosure. 13A to 13C are cross-sectional views (part 3) illustrating a method for manufacturing a HEMT device according to a second embodiment of the present disclosure. FIG. 13 is a cross-sectional view of a structure of a HEMT device according to a third embodiment of the present disclosure. FIG. 17B is an enlarged cross-sectional view of region D shown in FIG. 17A. 11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a HEMT device according to a third embodiment of the present disclosure. 13A to 13C are cross-sectional views (part 2) illustrating a method for manufacturing a HEMT device according to a third embodiment of the present disclosure. 1A to 1C are explanatory diagrams illustrating application examples of HEMT devices according to embodiments of the present disclosure.

Below, a preferred embodiment of the present disclosure will be described in detail with reference to the attached drawings. Note that in this specification and drawings, components having substantially the same functional configuration will be given the same reference numerals to avoid repeated explanation. Also, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different alphabets after the same reference numerals. However, if there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

In addition, the drawings referred to in the following description are intended to explain and facilitate understanding of one embodiment of the present disclosure, and for ease of understanding, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

The explanation will be given in the following order.
1. Background 2. Consideration of embodiments of the present disclosure 3. First embodiment 3.1 Detailed configuration 3.2 Manufacturing method 4. Second embodiment 4.1 Detailed configuration 4.2 Manufacturing method 5. Third embodiment 5.1 Detailed configuration 5.2 Manufacturing method 6. Summary 7. Application example 8. Supplementary

<<1. Background>>
First, the background that led the inventor to create the embodiment of the present disclosure will be described with reference to Figures 1 and 2. Figure 1 is an explanatory diagram for explaining an overview of a HEMT device 10b having a MIS gate structure, and Figure 2 is an explanatory diagram for explaining an overview of a HEMT device 10a having a Schottky gate structure.

GaN, a wide-gap semiconductor material, has characteristics such as a high breakdown voltage, high temperature operation, and high saturated drift velocity. In addition, the two-dimensional electron gas (2DEG) layer generated in GaN-based heterojunctions has the characteristics of high mobility and high sheet electron density. These characteristics allow the GaN HEMT, which is one of the GaN-based hetero-FETs, to operate at high speed and high voltage with low resistance, and is expected to be applied to RF devices such as power devices and switches in 5G high-speed communication systems. GaN HEMTs are particularly expected to be applied to power amplifiers (hereinafter referred to as PAs), where characteristics such as power density, power-added efficiency, and output (Pout) are important in the millimeter wave band, where spatial attenuation is large.

Here, the 2DEG layer is explained. The 2DEG layer is a layer in which electrons are distributed two-dimensionally. More specifically, a sheet-like electron distribution is obtained at the heterojunction interface due to polarization that occurs within the crystal, which is one of the characteristics of Group III nitrides. This sheet-like layer resulting from electron distribution is called the 2DEG layer, and the 2DEG layer functions as the channel of the HEMT device.

First, referring to FIG. 1, the configuration of a HEMT device 10b with a general MIS (Metal-Insulator-Semiconductor) gate structure will be described. As shown in the upper part of FIG. 1, the HEMT device 10b with the MIS structure has a GaN buffer layer 110 on a substrate 100, and a GaN channel layer 112 that forms a 2DEG layer 114 on the GaN buffer layer 110. In the MIS structure, a layer made of AlGaN, AlInN, or the like is heterojunctioned on the GaN channel layer 112 as a barrier layer 120. In the MIS structure, a gate insulating film 140 and a gate electrode 152 sandwiched between the source 160a and the drain 160b are formed on the barrier layer 120 to control the current flowing between the source 160a and the drain 160b.

In such a HEMT device 10b having a MIS gate structure, when stress such as voltage or temperature is applied, electrons are captured in traps present at the interface between the gate insulating film 140 and the semiconductor layer (specifically, the barrier layer 120), or electrons are released from the traps. Therefore, as shown in the lower part of FIG. 1, the actual measured value of the threshold voltage Vth of the HEMT device 10b is likely to fluctuate toward the positive or negative side compared to the theoretical value. If such fluctuations in the threshold voltage Vth occur during operation, it becomes difficult to control the device, and this raises concerns about the reliability of the HEMT device 10b having a MIS gate structure in long-term use.

Due to such concerns, HEMT devices 10a having a Schottky gate structure are preferred for application to RF devices and the like in 5G high-speed communication systems, rather than MIS gate structures. In detail, as shown in the upper part of FIG. 2, the HEMT device 10a having a Schottky gate structure also has a GaN buffer layer 110 on a substrate 100, and a GaN channel layer 112 that forms a 2DEG layer 114 on the GaN buffer layer 110. In addition, in the Schottky gate structure, a barrier layer 120 is heterojunctioned on the GaN channel layer 112. Furthermore, in the Schottky gate structure, a gate electrode 152 is formed on the barrier layer 120. In this way, in the Schottky gate structure, since there is no gate insulating film 140, there are fewer trap sources than in the MIS gate structure, and therefore the threshold voltage Vth is less likely to fluctuate.

However, as shown in the lower part of Figure 2, the HEMT device 10a with a Schottky gate structure does not have a gate insulating film 140, so the off-state current determined by gate leakage is higher than that of the MIS gate structure, and the electric field strength is also high at the gate end of the gate electrode 152, making the leakage current more noticeable.

The off-state current determined by gate leakage is the current that flows between the gate electrode 152 and the 2DEG layer 114, and an effective way to improve this is to alleviate the electric field concentration at the gate end of the gate electrode 152. Therefore, it is conceivable to alleviate the electric field by utilizing the field plate effect (FP effect) by modifying the shape of the gate electrode 152, but there is a limit to the improvement that can be achieved by modifying the shape in this way.

In addition, a means for improving gate leakage is to make the depletion layer 170 (see FIG. 9) that occurs in the region from directly under the gate electrode 152 in the semiconductor layer (specifically, the barrier layer 120) to the drain 160b side when a voltage is applied easier to extend (spread). To achieve this, it is possible to lower the channel electron concentration Ns by changing the composition of the barrier layer 120 (for example, by increasing the In concentration in the barrier layer 120 made of AlInN) or by thinning the barrier layer 120. However, such a means would result in a uniform decrease in the electron concentration Ns in the entire region of the HEMT device 10a, and the resistance would increase, especially on the source 160a side, which could cause deterioration of the on characteristics, such as an increase in the on-resistance (Ron) and a decrease in the on-current (Id) of the HEMT device 10a. This would also cause a decrease in the power density of the HEMT device 10a.

It is also possible to address the above issues by partially changing the composition of the barrier layer 120 or thinning the barrier layer 120, but such an approach would make the manufacturing process extremely complicated and would also make the semiconductor surface more susceptible to damage.

Therefore, in view of these circumstances, the inventors have repeatedly sought to obtain a structure that can be manufactured using a simple and damage-free method, and that can suppress degradation of characteristics when on while reducing the off-state current determined by gate leakage. In the course of such a search, the inventors have come up with an embodiment of the present disclosure that can be manufactured using a simple and damage-free method, and that can suppress degradation of characteristics when on while reducing the off-state current.

<<2. Consideration of embodiments of the present disclosure>>
First, the details of the study conducted by the present inventor in creating the embodiment of the present disclosure will be described with reference to Figures 3 to 12. Figures 3 to 12 are explanatory diagrams for explaining the details of the study conducted by the present inventor.

The inventors used TCAD Sim (Technology Computer-Aided Design Simulation) to study a method for making the depletion layer easier to extend (spread) in order to obtain a structure that can be manufactured using a simple and damage-free method and that can reduce the off-state current determined by gate leakage while suppressing deterioration of on-state characteristics. In detail, the inventors studied a method for lowering the channel electron concentration Ns and making the depletion layer 170 (see FIG. 9 ) easier to extend by making the state of the fixed charges on the surface of the barrier layer 120 (semiconductor layer) negative. In the course of such studies, the inventors focused on the surface of the barrier layer 120 (semiconductor layer) located around the gate electrode 152. It was also found that the depletion layer 170 extends toward the drain 160b as the positive fixed charge decreases or the negative fixed charge increases on the surface of the barrier layer 120 located around the gate electrode 152, which relaxes the electric field at the gate end of the gate electrode 152 and reduces the off-state current determined by the gate leakage.

In detail, the inventor performed TCAD Sim under the conditions of fixed charge density of 5.0e12/cm 2 (positive fixed charge), none, and −5.0e12/cm ² (negative fixed charge) in region A of the surface of the barrier layer 120 located around the gate electrode 152 and sandwiched between the gate electrode 152 and the drain electrode ¹⁵⁴ (and the source electrode) as shown in Fig. 3. Then, the Vg (gate voltage)-Id (drain current) characteristics were calculated under each condition (Vd (drain voltage) = 5 V applied). As a result, it was found that the off-state current determined by the gate leakage is reduced as the positive fixed charge decreases or the negative fixed charge increases in region A.

Furthermore, the inventors used TCAD Sim to divide the surface of the barrier layer 120 (semiconductor layer) located around the gate electrode 152 into multiple regions, and examined how the off-state current determined by the gate leakage changes by changing the surface fixed charge density of each region.

4, the surface of the barrier layer 120 of the HEMT device 10a with a Schottky gate structure was divided into three regions: between the gate electrode 152 and the source 160a (GS) (region a), directly below the gate electrode 152 (region b), and between the gate electrode 152 and the drain 160b (GD) (region b). Furthermore, the fixed charge density of each region was set to 5.0e12/cm ² (positive fixed charge), none, and −5.0e12/cm ² (negative fixed charge). Then, the Vg-Id characteristics were calculated under each condition (Vd=5V applied).

First, Figure 5 shows the results of changing the fixed charge density in all of the regions a, b, and c. In this case, the less positive fixed charge there is in regions a, b, and c, or the more negative fixed charge there is, the more the off-state current determined by gate leakage is reduced. Also, the less positive fixed charge there is in regions a, b, and c, or the more negative fixed charge there is, the more the on-state current (Id) when on (linear scale on vertical axis) is reduced, raising concerns about a reduction in the power density of the HEMT device 10a.

Next, FIG. 6 shows the results of changing the fixed charge density in regions a and c, i.e., in the regions outside the gate electrode 152. In this case, the results for both the off-current and on-current were similar to those when the fixed charge density was changed in all of regions a, b, and c in FIG. 5. This result is thought to suggest that the effect of changes in the fixed charge density on the off-current and on-current is predominantly due to changes in the fixed charge density in the regions outside the gate electrode 152.

Next, Figure 7 shows the results of changing the fixed charge density in region a, i.e., in the region between G and S. In this case, the off current does not change (has no sensitivity). Furthermore, in region a, the on current (Id) when on (linear scale on vertical axis) decreases as the positive fixed charge decreases or the negative fixed charge increases. This is because when the fixed charge density in region a is changed, the extension of the depletion layer 170 toward the drain 160b does not change, and only the source resistance increases. This state is the most unfavorable state in terms of device characteristics.

Next, Figure 8 shows the results of changing the fixed charge density in region c, i.e., in the region between G and D. In region c, the less positive fixed charge there is, or the more negative fixed charge there is, the more the off-state current determined by gate leakage is reduced. Furthermore, even if the fixed charge density in region c is changed, there is no significant change in the on-state current (Id). This result suggests that changing the fixed charge density in region c in the negative direction results in the extension of the depletion layer 170 toward the drain 160b side and a small increase in source resistance. This state is the most favorable state in terms of device characteristics.

The inventor's own investigations have revealed that if the fixed charge density can be changed in the negative direction in region c, i.e., in the region between G and D, it is possible to reduce the off-state current determined by gate leakage while suppressing degradation of the on-state characteristics.

The inventor therefore investigated how much of the region between G and D the fixed charge density needs to be changed in the negative direction in order to reduce the off-state current determined by gate leakage.

9, in order to define the range of the region in which the fixed charge density between G and D is changed in the negative direction, the distance from the end face on the drain 160b side of the part of the gate electrode 152 that is in direct contact with the surface of the barrier layer 120 to the end of the region in which the fixed charge density is changed in the negative direction on the drain 160b side is defined as Ld. The fixed charge density in the surface region is set to -5.0e12/cm ² (negative fixed charge), and the result of calculating the Vg-Id characteristic (Vd=5V applied) when the distance Ld is changed is shown in FIG. 11.

As can be seen from Figure 11, when the distance Ld was 5 nm or more, the off-state current was rapidly reduced. Furthermore, as the distance Ld was increased, the effect of reducing the off-state current gradually saturated, and at around 100 nm the effect became difficult to see. In other words, in order to reduce the off-state current determined by the gate leakage, it is considered effective to set the range of the region in which the fixed charge density is changed in the negative direction to a position 5 nm or more and 100 nm or less away from the end face on the drain 160b side of the part of the gate electrode 152 that is in direct contact with the surface of the barrier layer 120.

Furthermore, the inventors investigated to what extent the expansion of the region between G and S where the fixed charge density changes in the negative direction needs to be suppressed in order to suppress the deterioration of characteristics when the transistor is on.

9, in order to define the range of the region in which the fixed charge density between G and S is changed in the negative direction, the distance Ls is defined as the distance from the end face on the source 160a side of a part of the gate electrode 152 that is in direct contact with the surface of the barrier layer 120 to the end of the region in which the fixed charge density is changed in the negative direction on the source 160a side. The fixed charge density in the surface region is set to -5.0e12/cm ² (negative fixed charge), and the Vg-Id characteristics are calculated (Vd=5V applied) when the distance Ls is changed. The drain current value at Vg=0V is plotted against the distance Ls, as shown in FIG.

As can be seen from Figure 12, as the distance Ls increases, the on-current (Id) decreases accordingly. In other words, in order to suppress the decrease in the on-current, it is considered effective for the region between GS that changes the fixed charge density in the negative direction not to extend as far as possible toward the source 160a.

Then, based on the results of the investigations, the present inventor created the following structure of the HEMT device 10. In detail, in the HEMT device 10 (see FIG. 13A) according to the embodiment of the present disclosure created by the present inventor, when forming the gate electrode 152, the gate opening on the surface of the barrier layer 120 is opened wider on the drain 160b side than on the source 160a side, and a reduction treatment is performed on the surface of the barrier layer 120 exposed by the opening, changing the fixed charge density on the surface in the negative direction. Furthermore, in the embodiment of the present disclosure, after the reduction treatment, the gate electrode 152 is formed on the source 160a side from the center of the gate opening. In this way, the surface of a specific semiconductor layer (specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b can be selectively negatively charged. As a result, according to the embodiment of the present disclosure, it is possible to suppress the decrease in the on-current and reduce the off-current determined by the gate leakage.

Below, we will sequentially explain the details of the structure of the HEMT device 10 according to each embodiment of the present disclosure, which has been created by the inventor and enables the surface of such a specific semiconductor layer (specifically, the barrier layer 120) to be selectively negatively charged.

<<3. First embodiment>>
3.1 Detailed configuration
First, a detailed structure of the HEMT device 10 according to the first embodiment of the present disclosure will be described with reference to Fig. 13A and Fig. 13B. Fig. 13A is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Fig. 13B is an enlarged cross-sectional view of region B shown in Fig. 13A. Note that in all figures referred to in the following description, the reduction treatment surface 122 is indicated by a thick line.

As shown in FIG. 13A, the HEMT device 10 according to this embodiment has a buffer layer 110 on a substrate 100, and a channel layer 112 on the buffer layer 110, which forms a 2DEG layer 114. In this embodiment, a barrier layer 120 is heterojunctioned on the channel layer 112. In this embodiment, a source 160a and a drain 160b are formed on either side of the barrier layer 120. The thickness of the barrier layer 120 located below the insulating layer 132 (described later) is the same as the thickness of the barrier layer 120 located below the gate electrode 152 (described later). In other words, the barrier layer 120 is a continuous layer with a uniform thickness. In the following description, the stack from the substrate 100 to the barrier layer 120 is also referred to as a compound semiconductor layer.

Furthermore, in this embodiment, an insulating layer (first insulating layer) 132 having an opening (first opening) 132a exposing a reduced surface (first region) 122, which is a part of the upper surface of the barrier layer 120, is laminated on the barrier layer 120. In addition, an insulating layer (second insulating layer) 130 is laminated on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening (second opening) 130a that exposes a part (second region) of the reduced surface 122 of the upper surface of the barrier layer 120 exposed by the opening 132a and has an opening narrower than the opening 132a.

In detail, the center of opening 130a is located closer to source 160a than the center of opening 132a. Also, the inner surface of opening 132a on the source 160a side is located closer to source 160a than the inner surface of opening 130a on the source 160a side. Furthermore, the inner surface of opening 132a on the drain 160b side is located closer to drain 160b than the inner surface of opening 130a on the drain 160b side.

Furthermore, in this embodiment, a gate electrode 152 is formed on the insulating layer 130 located between the source 160a and the drain 160b and within the opening 130a, so as to be in direct contact with the upper surface (second region) of the barrier layer 120 exposed by the opening 130a.

In this embodiment, by using such a structure, a specific area of the surface of the semiconductor layer located between the gate electrode 152 and the drain 160b is subjected to a reduction process and selectively becomes negatively charged.

In this embodiment, the reduced treatment surface 122 is a region d (first region) that is a part of the upper surface of the barrier layer 120 between the source 160a and the drain 160b, as shown in FIG. 13B. In detail, the reduced treatment surface 122 includes a region c (third region) located on the drain 160b side relative to a region b (second region) where the gate electrode 152 and the barrier layer 120 are in direct contact with each other. The reduced treatment surface 122 also includes a region b where the gate electrode 152 and the barrier layer 120 are in direct contact with each other. Furthermore, the reduced treatment surface 122 includes a region a (fourth region) located on the source 160a side relative to region b. In this embodiment, region c is wider than region a.

Furthermore, in this embodiment, it is preferable that the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is 5 nm or more and 100 nm or less. Also, in this embodiment, it is preferable that the distance Ls between the end of region a on the source 160a side and the end face of the gate electrode 152 on the source 160a side that is in direct contact with region b is as short as possible.

In this embodiment, the reduced surface 122 (region d) that is in direct contact with the gate electrode 152 and the insulating layer 130 has been subjected to a reduction treatment, and therefore has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 other than region d, specifically, the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132. In this embodiment, by doing so, the channel electron concentration Ns of the reduced surface 122 can be lowered compared to the upper surface of the barrier layer 120 other than region d, specifically, the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132. For example, the reduced surface 122 may have a smaller amount of oxygen or a larger amount of hydrogen than the upper surface of the barrier layer 120 other than region d. The amount of oxygen and the amount of hydrogen can be analyzed using, for example, SIMS (Secondary Ion Mass Spectrometry) or the like.

In this embodiment, the gate electrode 152 is in direct contact with the barrier layer 120. Furthermore, in this embodiment, the gate electrode 152 has a structure in which it protrudes onto the insulating layer 130 in a part of region c shown in FIG. 13B. In this embodiment, the thickness t1 of the insulating layer 130 is thinned (for example, 5 nm to 50 nm) to narrow the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) in region c. In this embodiment, by doing so, a field plate effect due to the shape of the gate electrode 152 appears, and the electric field at the gate end of the gate electrode 152 can be alleviated.

Further details will be provided for each layer.

The substrate 100 is made of a semiconductor material and can be formed from a ternary or quaternary compound semiconductor material such as a III-V group compound semiconductor material, and more specifically, it is made of, for example, a semi-insulating single crystal GaN substrate. The substrate 100 may have a different lattice constant from that of the channel layer 112 by controlling the lattice constant with a buffer layer 110 described below. Specifically, the substrate 100 may be made of silicon carbide (SiC), sapphire, silicon (Si) substrate, or the like. In particular, when using a Si substrate, the advantage is that it is inexpensive and can be made large in diameter.

The buffer layer 110 is composed of, for example, a compound semiconductor epitaxially grown on the substrate 100. When the lattice constants of the substrate 100 and the channel layer 112 are different, the lattice constant can be controlled by the buffer layer 110 to improve the crystal state of the channel layer 112 and control the warping of the entire compound semiconductor layer. For example, when the substrate 100 is made of single crystal silicon and the channel layer 112 is made of GaN, the buffer layer 110 can be made of, for example, aluminum nitride (AlN), AlGaN, GaN, etc. Also, the buffer layer 110 does not necessarily have to be a single layer, and may be a laminate of different layers. Furthermore, when the buffer layer 110 is made of a ternary or quaternary compound semiconductor, the buffer layer 110 may have a composition that gradually changes along the thickness of the film.

The channel layer 112 is a region where carriers accumulate due to polarization with the barrier layer 120, which will be described later. Such a channel layer 112 is made of a compound semiconductor in which carriers tend to accumulate due to polarization. An example of the channel layer 112 is a GaN epitaxial growth layer. The channel layer 112 may also be a u (undoped)-GaN layer to which no impurities have been added. This suppresses impurity scattering of carriers in the channel layer 112, and enables carrier movement with high mobility. In this embodiment, the film thickness of the channel layer 112 is preferably, for example, 50 nm to 300 nm.

The barrier layer 120 is made of a compound semiconductor in which a two-dimensional electron gas is generated in the channel layer 112 (heterojunction interface) due to polarization with the channel layer 112, and carriers are accumulated. Such a barrier layer 120 is made of a group III nitride containing at least one of indium (In), gallium (Ga), and aluminum (Al), and specifically, for example, an epitaxial growth layer of Al _1-x-y Ga _x In _y N (0≦x<1, 0≦y<1) can be used. The barrier layer 120 may also be u-Al _1-x-y Ga _x In _y N to which no impurities are added. This suppresses impurity scattering of carriers in the channel layer 112, and allows carrier movement with high mobility. The barrier layer 120 does not necessarily have to be a single layer, and may be a stack of different layers, for example, an Al _1-x-y Ga _x In _y N layer with different compositions. Alternatively, the barrier layer 120 may have a composition that gradually changes along the thickness. In this embodiment, the thickness of the barrier layer 120 is preferably, for example, 3 nm to 20 nm. Furthermore, a cap layer (not shown) may be provided on the upper surface of the barrier layer 120 to protect it from oxidation processes and thermal processes. For example, the cap layer is made of a layer of GaN or silicon nitride (Si _x N _y ) having a thickness of 0.2 nm to 5 nm.

In this embodiment, a back barrier layer (not shown) may be provided between the channel layer 112 and the buffer layer 110. The back barrier layer is made of a semiconductor having a wider energy gap than the channel layer 112. As an example of the back barrier layer, an epitaxially grown layer of Al _1-x-y Ga _x In _y N (0≦x<1, 0≦y<1) or u-Al _1-x-y Ga _x In _y N may be used. The back barrier layer does not necessarily have to be a single layer, and may be a laminate of different layers, for example, a laminate of Al _1-x-y Ga _x In _y N layers having different compositions. Alternatively, the back barrier layer may have a composition that gradually changes along the film thickness.

In addition, both the insulating layer 132 and the insulating layer 130 are laminated on the source 160a and the drain 160b, and although not shown, a source electrode 150 and a drain electrode 154 electrically connected to the source 160a and the drain 160b may be provided on the source 160a and the drain 160b. In addition, it is preferable to use a material for the insulating layer 132 that has insulating properties against the barrier layer 120, has a property of not deteriorating the device characteristics by forming a good interface with the barrier layer 120, and can be etched by wet etching. Specifically, the insulating layer 132 is made of an oxide, for example, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), silicon oxide (SiO ₂ ), or a laminate of these. In addition, it is preferable to use a material for the insulating layer 130 that has insulating properties against the insulating layer 132, and has a property of not deteriorating the device characteristics by forming a good interface with the barrier layer 120 because the insulating layer 130 is in direct contact with the barrier layer 120 in the opening 132a. In addition, a material that can be etched by dry etching is preferably used for the insulating layer 130. Specifically, the insulating layer 132 is made of _a nitride, for example, _Si3N4 .

The gate electrode 152 can have a laminated structure of, for example, nickel (Ni) and gold (Au). In addition, in order to reduce the gate impedance, the gate electrode 152 is generally formed in a T-gate shape. In order to suppress metal diffusion, a barrier metal (not shown) such as titanium (Ti) may be formed to cover the surface of the gate electrode 152.

As described above, in this embodiment, by adopting such a structure, it is possible to selectively reduce the surface area of a specific semiconductor layer located between the gate electrode 152 and the drain 160b, thereby making it negatively charged. In detail, in this embodiment, by selectively negatively charging the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b, the electron concentration of the channel on the drain 160b side is reduced, and the depletion layer 170 is likely to extend to the drain 160b side. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 is relaxed, and the off-state current determined by the gate leakage can be reduced. In addition, according to this embodiment, the negatively charged area located on the source 160a side is narrower than the negatively charged area located on the drain 160b side, so that the deterioration of the on-characteristics can be suppressed.

In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in Figures 13A and 13B, but can be modified into various other structures.

<3.2 Manufacturing method>
Next, a method for manufacturing the HEMT device 10 according to this embodiment will be described with reference to Figures 14A to 14G. Figures 14A to 14G are cross-sectional views for explaining the method for manufacturing the HEMT device according to this embodiment, and in detail, each figure is a cross-sectional view at each manufacturing stage corresponding to Figure 13A.

First, a GaN buffer layer 110 is formed on a GaN substrate 100, a GaN channel layer 112 is formed on the GaN buffer layer 110, and a barrier layer 120 is formed on the GaN buffer layer 110 in this order. Next, a high concentration N-type (N+) region or the like is formed in the region that will become the source 160a and the drain 160b. In detail, the source 160a and the drain 160b are formed by, for example, forming ohmic electrodes (not shown) on both sides of the region where the gate electrode 152 is formed, and performing annealing or the like. A high concentration N-type region is formed on the substrate side by, for example, selectively implanting ions. In this way, the contact resistance can be reduced (both the source 160a and the drain 160b are electrically connected to the above-mentioned 2DEG layer 114). Alternatively, instead of ion implantation, the source 160a and the drain 160b may be formed by selectively re-growing crystals on the substrate. In this case, the layer to be re-grown may be, for example, an n (N-type)-In _1-x Ga _x N layer. In this embodiment, the high concentration N-type regions that become the source 160a and the drain 160b do not necessarily have to be a single layer, but may be a stack of different layers, for example, a stack of layers with different compositions of In _1-x Ga _x N (0≦x<1) layers. Alternatively, the high concentration N-type region may have a composition that gradually changes along the film thickness. Furthermore, as the N-type dopant (impurity), Si, germanium (Ge), etc. can be used, and the impurity concentration is preferably, for example, 1×10 ¹⁸ cm ⁻³ or more. In addition, the above-mentioned ohmic electrodes are preferably ones that cover the high concentration N-type regions and connect with each other with low resistance. As such an ohmic electrode, for example, a structure in which titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) are stacked in order from the substrate side can be used.

Furthermore, an element isolation portion (not shown) that divides the region of the HEMT device 10 is formed on the substrate side. The element isolation portion can be formed by forming an inactive region that is made highly resistive by, for example, ion implantation of boron (B). In this way, the configuration shown in FIG. 14A can be obtained. Also, in this case, the source 160a and drain 160b are formed first, but this is not limiting, and the source 160a and drain 160b may be formed after the formation of the gate electrode 152, which will be described later.

Next, as shown in FIG. 14B, an insulating layer (first insulating layer) 132 is formed on the barrier layer 120 (semiconductor layer). For the insulating layer 132, it is preferable to use a material that has insulating properties with respect to the barrier layer 120, has properties that do not deteriorate device characteristics by forming a good interface with the barrier layer 120, and can be etched by wet etching. For example, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ ) having a film thickness of about 1 nm to 50 nm formed by the atomic layer deposition (ALD) method is used for the insulating layer 132. Alternatively, for example, SiO ₂ formed by the chemical vapor deposition (CVD) method may be used for the insulating layer 132.

Next, as shown in FIG. 14C, isotropic wet etching is performed on the insulating layer 132 until a part of the surface of the barrier layer 120 is exposed, forming an opening (first opening) 132a. For example, BHF (buffered hydrofluoric acid) or diluted TMAH (tetramethylammonium hydroxide aqueous solution) can be used for wet etching. By performing such wet etching, damage to the surface of the barrier layer 120, etc. can be reduced. At this time, the opening 132a is formed so as to open wider on the drain 160b side than the actual gate length. Specifically, the opening 132a is formed so as to open in the range of 5 nm to 200 nm starting from the gate end on the drain 160b side.

Next, as shown in FIG. 14D, a reduction treatment is performed on the surface (first region) of the barrier layer 120 exposed from the opening 132a to form a reduced surface 122. By performing such treatment, it is possible to reduce the amount of positive fixed charge and increase the amount of negative fixed charge on the surface of the barrier layer 120 exposed from the opening 132a. For example, the reduction treatment may be a treatment using a gas or treatment liquid containing fluorine (F), chlorine (Cl), hydrogen (H), etc., and the reduced surface 122 can be formed by performing a hydrogen plasma treatment for about 0.3 min to 3 min.

In this manner, in this embodiment, a selective reduction process is performed on the surface area of a specific semiconductor layer (specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b, rather than ion implantation, etc., thereby making it possible to prevent damage to the inside of the barrier layer 120, etc.

Next, as shown in FIG. 14E, an insulating layer (second insulating layer) 130 is formed on the insulating layer 132 and in the opening 132a. In addition, as the insulating layer 130, it is preferable to use a material that has insulating properties with respect to the insulating layer 132 and has a property of not degrading device characteristics by forming a good interface with the barrier layer 120 because the insulating layer 130 is in direct contact with the barrier layer 120 in the opening 132a. In addition, it is preferable to use a material that can be etched by dry etching as the insulating layer 130. Therefore, as the insulating layer 130, for example, p (P-type)-SiN with a film thickness of about 5 nm to 200 nm formed by a plasma CVD method can be used. Specifically, the insulating layer 130 can be formed by reacting silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) with plasma energy to generate a silicon nitride film and hydrogen, which are then deposited on the substrate.

Next, as shown in FIG. 14F, dry etching is performed on the insulating layer 130 using a carbon fluoride (CF)-based gas to form an opening (second opening) 130a having a narrow opening 132a. The opening width of the opening 130a corresponds to the gate length, and is preferably set to, for example, 0.1 μm to 1.0 μm. As a result, the insulating layer 130 protrudes so as to directly contact the barrier layer 120 (reduced surface 122) within the opening 132a of the insulating layer 132, and the amount of protrusion is greater on the drain 160b side than on the source 160a side.

Next, as shown in FIG. 14G, a gate electrode 152 is formed on the insulating layer 130 and in the opening 130a. The gate electrode 152 can be formed, for example, by stacking Ni and Au from the substrate side using mask vapor deposition. As explained above, in order to reduce the gate impedance, the gate electrode 152 is generally formed in a T-gate shape. Also, in order to suppress diffusion of the upper metal Au, a barrier metal such as Ti (not shown) may be formed between the upper metal Au and the lower metal Ni.

In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be fabricated in a simple and damage-free manner without making significant changes to the conventional manufacturing process. In other words, according to this embodiment, it is possible to obtain a HEMT device 10 that can be fabricated in a simple and damage-free manner, and that can reduce the current when off while suppressing degradation of the characteristics when on.

<<4. Second embodiment>>
4.1 Detailed configuration
First, a detailed structure of the HEMT device 10 according to the second embodiment of the present disclosure will be described with reference to Fig. 15A and Fig. 15B. Fig. 15A is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Fig. 15B is an enlarged cross-sectional view of a region C shown in Fig. 15A. This embodiment differs from the first embodiment in that the film thickness t1 of the insulating layer 130 is thicker than that of the first embodiment.

As in the first embodiment, in this embodiment, as shown in FIG. 15A, the HEMT device 10 according to this embodiment has a buffer layer 110, a channel layer 112, and a barrier layer 120 on a substrate 100. Furthermore, in this embodiment, a source 160a and a drain 160b are formed so as to sandwich the barrier layer 120.

Furthermore, in this embodiment, an insulating layer 132 having an opening 132a exposing a part of the reduced surface 122 of the upper surface of the barrier layer 120 is laminated on the barrier layer 120. Also, in this embodiment, an insulating layer 130 is laminated on the insulating layer 132 and in the opening 132a. The insulating layer 130 has an opening 130a that exposes a part of the reduced surface 122 of the upper surface of the barrier layer 120 exposed by the opening 132a and has an opening narrower than the opening 132a. Also, in this embodiment, the center of the opening 130a is located closer to the source 160a than the center of the opening 132a. Also, in this embodiment, the inner surface of the opening 132a on the source 160a side is located closer to the source 160a than the inner surface of the opening 130a on the source 160a side. Furthermore, in this embodiment, the inner surface of the opening 132a on the drain 160b side is located on the drain 160b side relative to the inner surface of the opening 130a on the drain 160b side.

Furthermore, in this embodiment, a gate electrode 152 is formed on the insulating layer 130 located between the source 160a and the drain 160b, and within the opening 130a, so as to be in direct contact with the upper surface of the barrier layer 120 exposed by the opening 130a.

In this embodiment, the reduced surface 122 is a region d, which is a part of the upper surface of the barrier layer 120 between the source 160a and the drain 160b, as shown in FIG. 15B. In detail, the reduced surface 122 includes a region b where the gate electrode 152 and the barrier layer 120 are in direct contact with each other, a region c located on the drain 160b side of the region b, and a region a located on the source 160a side of the region b. In this embodiment, the region c is wider than the region a. In detail, in this embodiment, the distance Ld between the end of the region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with the region b is preferably 5 nm or more and 100 nm or less. In this embodiment, the distance Ls between the end of the region a on the source 160a side and the end face of the gate electrode 152 on the source 160a side that is in direct contact with the region b is preferably as short as possible.

In this embodiment, the reduced surface 122 that is in direct contact with the gate electrode 152 and the insulating layer 130 has also been subjected to a reduction treatment, and therefore has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 other than region d, specifically, the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132. In this manner, in this embodiment, the channel electron concentration Ns of the reduced surface 122 can be reduced compared to the upper surface of the barrier layer 120 that is in direct contact with the insulating layer 132.

Furthermore, in this embodiment, the gate electrode 152 also has a structure in which it protrudes onto the insulating layer 130 in a part of the region c shown in FIG. 15B. In this embodiment, the thickness t1 of the insulating layer 130 is made thicker (for example, 50 nm to 200 nm) than in the first embodiment described above. In this way, the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) is widened, so that the capacitance Cgd between the gate electrode 152 and the drain 160b can be reduced. As a result, according to this embodiment, the gain characteristics of the HEMT device 10 are improved. Thus, in each embodiment of the present disclosure, it is preferable to adjust the thickness t1 of the insulating layer 130 according to the required characteristics.

As described above, in this embodiment, by adopting such a structure, the surface region of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can be selectively reduced and negatively charged. In detail, in this embodiment, the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b is selectively negatively charged, thereby lowering the electron concentration of the channel on the drain 160b side and making it easier for the depletion layer 170 to extend to the drain 160b side. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 is relaxed, and the off-state current determined by the gate leakage can be reduced. In addition, according to this embodiment, the negatively charged region located on the source 160a side is narrower than the negatively charged region located on the drain 160b side, so that the deterioration of the on-characteristics can be suppressed.

In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in Figures 15A and 15B, but can be modified into various other structures.

<4.2 Manufacturing method>
Next, a method for manufacturing the HEMT device 10 according to this embodiment will be described with reference to Figures 16A to 16C. Figures 16A to 16C are cross-sectional views for explaining the method for manufacturing the HEMT device according to this embodiment, and in detail, each figure is a cross-sectional view at each manufacturing stage corresponding to Figure 15A.

First, similar to the manufacturing method of the HEMT device 10 according to the first embodiment described with reference to Figures 14A to 14E, layers are stacked up to the insulating layer 130, and the configuration shown in Figure 16A can be obtained. Note that this embodiment differs from the first embodiment in that the thickness of the insulating layer 130 is made thicker.

Next, as shown in FIG. 16B, dry etching is performed on the insulating layer 130 in the same manner as in the first embodiment, forming an opening 130a that is narrower than the opening 132a.

Next, as shown in FIG. 16C, a gate electrode 152 is formed on the insulating layer 130 and in the opening 130a, similar to the first embodiment.

In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be fabricated in a simple and damage-free manner without making significant changes to the conventional manufacturing process. In other words, according to this embodiment, it is possible to obtain a HEMT device 10 that can be fabricated in a simple and damage-free manner, and that can reduce the current when off while suppressing degradation of the characteristics when on.

<<5. Third embodiment>>
5.1 Detailed configuration
First, a detailed structure of the HEMT device 10 according to the third embodiment of the present disclosure will be described with reference to Fig. 17A and Fig. 17B. Fig. 17A is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Fig. 17B is an enlarged cross-sectional view of a region D shown in Fig. 17A. This embodiment is different from the first and second embodiments in that the reduction treatment surface 122 is provided only on the drain 160b side of the gate electrode 152, and is not provided on the source 160a side of the gate electrode 152.

As in the first embodiment, in this embodiment, as shown in FIG. 17A, the HEMT device 10 according to this embodiment has a buffer layer 110, a channel layer 112, and a barrier layer 120 on a substrate 100. Furthermore, in this embodiment, a source 160a and a drain 160b are formed so as to sandwich the barrier layer 120.

Furthermore, in this embodiment, an insulating layer 132 having an opening 132a exposing a part of the reduced surface 122 of the upper surface of the barrier layer 120 is laminated on the barrier layer 120. In addition, an insulating layer 130 is laminated on the insulating layer 132 and in the opening 132a. The insulating layer 130 has an opening 130a that exposes the upper surface of the barrier layer 120 exposed by the opening 132a and has an opening narrower than the opening 132a. In this embodiment, unlike the embodiments described so far, the opening 130a does not expose the reduced surface 122. Also, in this embodiment, the center of the opening 130a is located closer to the source 160a than the center of the opening 132a. Furthermore, in this embodiment, unlike the embodiments described so far, the inner surface of the opening 132a on the source 160a side is flush with the inner surface of the opening 130a on the source 160a side. However, in this embodiment, the inner surface of the opening 132a on the source 160a side is not limited to being flush with the inner surface of the opening 130a on the source 160a side, and the inner wall of the opening 132a on the source 160a side may be closer to the source 160a side than the inner surface of the opening 130a on the source 160a side. Furthermore, in this embodiment, the inner surface of the opening 132a on the drain 160b side is located on the drain 160b side relative to the inner surface of the opening 130a on the drain 160b side.

Furthermore, in this embodiment, a gate electrode 152 is formed on the insulating layer 130 located between the source 160a and the drain 160b, and within the opening 130a, so as to be in direct contact with the upper surface of the barrier layer 120 exposed by the opening 130a. In this embodiment, unlike the embodiments described so far, the gate electrode 152 is not in direct contact with the reduction treatment surface 122.

In detail, in this embodiment, unlike the embodiments described so far, the reduction treatment surface 122 includes only a region c located on the drain 160b side relative to a region b where the gate electrode 152 and the barrier layer 120 are in direct contact, as shown in FIG. 17B. Furthermore, in this embodiment, the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is preferably 5 nm or more and 100 nm or less.

In this embodiment as well, the reduced surface 122 in direct contact with the insulating layer 130 has been subjected to a reduction treatment, and therefore has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 in direct contact with the gate electrode 152 and the insulating layer 132. By doing this in this embodiment as well, the channel electron concentration Ns of the reduced surface 122 can be lowered compared to the upper surface of the barrier layer 120 in direct contact with the gate electrode 152 and the insulating layer 132.

Furthermore, in this embodiment, the gate electrode 152 also has a structure in which it protrudes onto the insulating layer 130 in a part of the region c shown in FIG. 17B. In this embodiment, when the thickness t1 of the insulating layer 130 is made thicker, the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) becomes wider, so that the capacitance Cgd between the gate electrode 152 and the drain 160b can be reduced. As a result, the gain characteristics of the HEMT device 10 can be improved. In addition, in this embodiment, when the thickness t1 of the insulating layer 130 is made thin, the gap between the gate electrode 152 and the barrier layer 120 (reduced surface 122) in the region c becomes narrower, so that the field plate effect due to the shape of the gate electrode 152 appears, and the electric field at the gate end of the gate electrode 152 can be relaxed. Thus, in this embodiment, it is preferable to adjust the thickness t1 of the insulating layer 130 according to the required characteristics.

As described above, in this embodiment, by adopting such a structure, the surface region of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can be selectively reduced and negatively charged. In detail, in this embodiment, the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b is selectively negatively charged, thereby lowering the electron concentration of the channel on the drain 160b side and making it easier for the depletion layer 170 to extend to the drain 160b side. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 is relaxed, and the off-state current determined by the gate leakage can be reduced. Furthermore, in this embodiment, since the reduction treatment surface 122 is not provided on the source 160a side of the gate electrode 152, there is no increase in the resistance on the source 160a side, and deterioration of the on-characteristics can be further suppressed. Furthermore, in this embodiment, since the reduction treatment is not performed on the upper surface (region b) of the barrier layer 120 directly below the gate electrode 152, the characteristic fluctuation of the HEMT device 10 can be suppressed.

In this embodiment, the structure of the HEMT device 10 is not limited to the structure shown in Figures 17A and 17B, but can be modified into various other structures.

<5.2 Manufacturing method>
Next, a method for manufacturing the HEMT device 10 according to this embodiment will be described with reference to Figures 18A and 18B. Figures 18A and 18B are cross-sectional views for explaining the method for manufacturing the HEMT device according to this embodiment, and in detail, each figure is a cross-sectional view at each manufacturing stage corresponding to Figure 18A.

First, similarly to the manufacturing method of the HEMT device 10 according to the first embodiment described with reference to FIGS. 14A to 14E and the manufacturing method of the HEMT device 10 according to the second embodiment described with reference to FIG. 16A, layers are stacked up to the insulating layer 130. Furthermore, in this embodiment, as shown in FIG. 16A, dry etching is performed on the insulating layer 130 to form an opening 130a on the source 160a side having an opening narrower than the opening 132a. At this time, it is preferable that the end of the reduced surface 122 on the source 160a side and the inner side of the opening 130a on the drain 160b side are in the same position. However, this embodiment is not limited to this form, and a part of the reduced surface 122 may be present within the opening of the opening 130a. In addition, in this embodiment, it is preferable that the inner side of the opening 132a on the source 160a side is flush with the inner side of the opening 130a on the source 160a side.

Next, as shown in FIG. 18B, a gate electrode 152 is formed on the insulating layer 130 and in the opening 130a, similar to the first embodiment.

In this manner, the HEMT device 10 according to this embodiment can be fabricated. As described above, in this embodiment, the HEMT device 10 can be fabricated in a simple and damage-free manner without making significant changes to the conventional manufacturing process. In other words, according to this embodiment, it is possible to obtain a HEMT device 10 that can be fabricated in a simple and damage-free manner, and that can reduce the current when off while suppressing degradation of the characteristics when on.

<<6. Summary>>
As described above, in each embodiment of the present disclosure, a region of the surface of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can be selectively reduced to be negatively charged. In particular, in this embodiment, the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b is selectively negatively charged to reduce the electron concentration of the channel on the drain 160b side, and the depletion layer 170 is likely to extend to the drain 160b side. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 is relaxed, and the off-state current determined by the gate leakage can be reduced. In addition, according to each embodiment of the present disclosure, the negatively charged region located on the source 160a side is narrower than the negatively charged region located on the drain 160b side, or a negatively charged region is not provided on the source 160a side, thereby suppressing deterioration of the on-characteristics.

Furthermore, in each embodiment of the present disclosure, a surface region of a specific semiconductor layer (specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b is selectively reduced rather than ion implanted, thereby preventing damage to the inside of the barrier layer 120, etc. Furthermore, according to each embodiment of the present disclosure, the HEMT device 10 can be manufactured by a simple method without significantly changing the conventional manufacturing process. In other words, according to each embodiment of the present disclosure, it is possible to provide a HEMT device 10 that can be manufactured by a damage-free method and that can reduce the current when off while suppressing deterioration of the characteristics when on.

Note that, although the HEMT device 10 according to each embodiment of the present disclosure is a GaN-based compound semiconductor, the present disclosure is not limited to this, and may be, for example, a compound semiconductor such as GaAs, or a semiconductor using a Si substrate, etc.

In addition, the materials, film thicknesses, film formation methods, and film formation conditions of each layer in each of the above-mentioned embodiments are not limited to those described, and can be changed as appropriate. In other words, in this embodiment, it is possible to manufacture the device using methods, equipment, and conditions that are used in the manufacture of general semiconductor devices.

The above-mentioned techniques include, for example, PVD (Physical Vapor Deposition), CVD, and ALD. PVD techniques include vacuum deposition, EB (Electron Beam) deposition, various sputtering techniques (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) combined bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer. Examples of the CVD method include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Examples of the patterning method include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light, laser, and the like. In addition, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

<<7. Application Examples>>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to a communication device. As an example of the application of the technology according to the present disclosure, a wireless communication device (communication device) 500 will be described with reference to FIG. 19. FIG. 19 is an explanatory diagram for explaining an application example of the HEMT device 10 according to each embodiment of the present disclosure.

The wireless communication device 500 shown in FIG. 19 is a mobile phone system having multiple functions such as voice, data communication, and LAN (Local Area Network) connection. For example, the wireless communication device 500 has an antenna (ANT) 510, an antenna switch circuit 520, a high-frequency integrated circuit RFIC (Radio Frequency Integrated Circuit) 530, a baseband unit 540, a high-power amplifier (HPA) 550, and an output unit 560 including a voice output unit (MIC), a data output unit (DT), and an interface (IF) unit. The interface (IF) unit can connect devices that perform wireless communication such as wireless LAN and Bluetooth (registered trademark). The high-frequency integrated circuit RFIC 530 and the baseband unit 540 are connected by an internal bus.

During transmission, the transmission signal output from the baseband unit 540 is output to the antenna 510 via the radio frequency integrated circuit RFIC 530, the high power amplifier 550, and the antenna switch circuit 520. During reception, the received signal received by the antenna 510 is input to the baseband unit 540 via the antenna switch circuit 520 and the radio frequency integrated circuit RFIC 530. The baseband unit 540 processes the input signal and outputs it from the output unit 560 to an external device, etc.

For example, the technology disclosed herein can be applied to the antenna switch circuit 520, the radio frequency integrated circuit RFIC 530, and the high power amplifier 550. In particular, the effect of the technology disclosed herein is exhibited in wireless communication devices in which the communication frequency is in the UHF (Ultra High Frequency) band or higher. That is, by using the HEMT device 10 according to each embodiment of the present disclosure, which has excellent high frequency characteristics and high efficiency characteristics, as the antenna switch circuit 520, the radio frequency integrated circuit RFIC 530, and the high power amplifier 550, it is possible to achieve high speed, high efficiency, and low power consumption in the wireless communication device 500. In particular, when applied to a mobile communication terminal as the wireless communication device 500, the high speed processing, high efficiency, and low power consumption make it possible to extend the battery life and improve portability.

The above shows an example of the configuration of wireless communication device 500. Each of the above components may be configured using general-purpose parts, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

<<8. Supplementary Information>>
Although the preferred embodiment of the present disclosure has been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person having ordinary knowledge in the technical field of the present disclosure can conceive of various modified or amended examples within the scope of the technical ideas described in the claims, and it is understood that these also naturally belong to the technical scope of the present disclosure.

Furthermore, the effects described in this specification are merely descriptive or exemplary and are not limiting. In other words, the technology disclosed herein may achieve other effects that are apparent to a person skilled in the art from the description in this specification, in addition to or in place of the above effects.

The present technology can also be configured as follows.
(1)
a ternary or quaternary compound semiconductor layer;
a first insulating layer disposed on the compound semiconductor layer and having a first opening exposing a first region of an upper surface of the compound semiconductor layer;
a second insulating layer that is laminated on the first insulating layer and in the first opening, and that has a second opening that exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening;
a gate electrode that is laminated on an upper surface of the second insulating layer and in the second opening and that is in direct contact with the second region on the upper surface of the compound semiconductor layer;
Equipped with
Semiconductor device.
(2)
the first region includes a third region that is an upper surface of the compound semiconductor layer and is located on a drain side with respect to the second region;
The third region is a reduction-treated surface.
The semiconductor device according to (1) above.
(3)
The semiconductor device according to (2) above, wherein the reduction treatment surface has a larger amount of negative fixed charges than other regions of the upper surface of the compound semiconductor layer.
(4)
The semiconductor device according to (2) above, wherein the reduction treatment surface has a smaller amount of positive fixed charges than other regions of the upper surface of the compound semiconductor layer.
(5)
The semiconductor device according to (2) above, wherein the reduction treatment surface has a smaller amount of oxygen than other regions of the upper surface of the compound semiconductor layer.
(6)
The semiconductor device according to any one of (2) to (5) above, wherein the reduction treatment surface extends to a portion of an upper surface of the compound semiconductor layer located under the gate electrode.
(7)
The reduction treatment surface is
the second region and a fourth region of the upper surface of the compound semiconductor layer located on a source side with respect to the second region;
The third region is larger than the fourth region.
The semiconductor device according to (6) above.
(8)
The semiconductor device according to any one of (2) to (7) above, wherein the distance between the drain side end face of a portion of the gate electrode that is in direct contact with the second region and the drain side end face of the third region is 5 nm or more.
(9)
The semiconductor device according to (8) above, wherein a distance between an end surface on the drain side of a portion of the gate electrode that is in direct contact with the second region and an end portion on the drain side of the third region is 100 nm or less.
(10)
The semiconductor device according to any one of (2) to (6) above, wherein the center of the second opening is located closer to the source than the center of the first opening.
(11)
The semiconductor device according to (10) above, wherein an inner surface of the first opening on the source side and an inner surface of the second opening on the source side are flush with each other.
(12)
The semiconductor device according to (10) above, wherein an inner surface on the source side of the first opening is located on the source side relative to an inner surface on the source side of the second opening.
(13)
The semiconductor device according to (12) above, wherein an inner surface of the first opening on the drain side is located on the drain side relative to an inner surface of the second opening on the drain side.
(14)
The compound semiconductor layer is
the compound semiconductor layer comprises a Group III nitride including at least one of gallium, indium, and aluminum;
The semiconductor device according to any one of (1) to (13) above.
(15)
The first insulating layer is made of an oxide.
The semiconductor device according to any one of (1) to (14) above.
(16)
The first insulating layer is made of aluminum oxide, hafnium oxide, silicon oxide, or a laminate thereof.
The semiconductor device according to (15) above.
(17)
The second insulating layer is made of a nitride.
The semiconductor device according to any one of (1) to (16) above.
(18)
The second insulating layer is made of silicon nitride.
The semiconductor device according to (17) above.
(19)
a first insulating layer having a first opening exposing a first region of an upper surface of a ternary or quaternary compound semiconductor layer;
performing a reduction treatment on the first region;
a second insulating layer is laminated on the first insulating layer and within the first opening, the second insulating layer having a second opening which exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening;
forming a gate electrode on the upper surface of the second insulating layer and in the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer;
A method for manufacturing a semiconductor device, comprising:
(20)
A communication device equipped with a semiconductor device,
The semiconductor device includes:
a ternary or quaternary compound semiconductor layer;
a first insulating layer disposed on the compound semiconductor layer and having a first opening exposing a first region of an upper surface of the compound semiconductor layer;
a second insulating layer that is laminated on the first insulating layer and in the first opening, and that has a second opening that exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening;
a gate electrode that is laminated on an upper surface of the second insulating layer and in the second opening and that is in direct contact with the second region on the upper surface of the compound semiconductor layer;
having
Communications equipment.

10, 10a, 10b HEMT device 100 Substrate 110 Buffer layer 112 Channel layer 114 2DEG layer 120 Barrier layer 122 Reduced surface 130, 132 Insulating layer 130a, 132a Opening 140 Gate insulating film 150 Source electrode 152 Gate electrode 154 Drain electrode 160a Source 160b Drain 170 Depletion layer 500 Wireless communication device 510 Antenna 520 Antenna switch circuit 530 High frequency integrated circuit RFIC
540 Baseband section 550 High power amplifier 560 Output section

Claims (20)

a ternary or quaternary compound semiconductor layer;
a first insulating layer disposed on the compound semiconductor layer and having a first opening exposing a first region of an upper surface of the compound semiconductor layer;
a second insulating layer that is laminated on the first insulating layer and in the first opening, and that has a second opening that exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening;
a gate electrode that is laminated on an upper surface of the second insulating layer and in the second opening and that is in direct contact with the second region on the upper surface of the compound semiconductor layer;
Equipped with
Semiconductor device. the first region includes a third region that is an upper surface of the compound semiconductor layer and is located on a drain side with respect to the second region;
The third region is a reduction-treated surface.
The semiconductor device according to claim 1 . The semiconductor device according to claim 2, wherein the reduction treatment surface has a greater amount of negative fixed charge than other regions of the upper surface of the compound semiconductor layer. The semiconductor device according to claim 2, wherein the reduction treatment surface has a smaller amount of positive fixed charge than other regions of the upper surface of the compound semiconductor layer. The semiconductor device according to claim 2, wherein the reduction treatment surface has a smaller amount of oxygen than other regions of the upper surface of the compound semiconductor layer. The semiconductor device according to claim 2, wherein the reduction treatment surface extends to a portion of the upper surface of the compound semiconductor layer located under the gate electrode. The reduction treatment surface is
the second region and a fourth region of the upper surface of the compound semiconductor layer located on a source side with respect to the second region;
The third region is larger than the fourth region.
The semiconductor device according to claim 6. The semiconductor device according to claim 2, wherein the distance between the drain side end face of the part of the gate electrode that is in direct contact with the second region and the drain side end face of the third region is 5 nm or more. The semiconductor device according to claim 8, wherein the distance between the drain side end face of the part of the gate electrode that is in direct contact with the second region and the drain side end face of the third region is 100 nm or less. The semiconductor device according to claim 2, wherein the center of the second opening is located closer to the source than the center of the first opening. The semiconductor device according to claim 10, wherein the inner surface of the first opening on the source side and the inner surface of the second opening on the source side are flush with each other. The semiconductor device according to claim 10, wherein the source side inner surface of the first opening is located on the source side relative to the source side inner surface of the second opening. The semiconductor device according to claim 12, wherein the inner surface of the first opening on the drain side is located on the drain side relative to the inner surface of the second opening on the drain side. the compound semiconductor layer comprises a Group III nitride including at least one of gallium, indium, and aluminum;
The semiconductor device according to claim 1 . The first insulating layer is made of an oxide.
The semiconductor device according to claim 1 . The first insulating layer is made of aluminum oxide, hafnium oxide, silicon oxide, or a laminate thereof.
The semiconductor device according to claim 15. The second insulating layer is made of a nitride.
The semiconductor device according to claim 1 . The second insulating layer is made of silicon nitride.
The semiconductor device according to claim 17. a first insulating layer having a first opening exposing a first region of an upper surface of a ternary or quaternary compound semiconductor layer;
performing a reduction treatment on the first region;
a second insulating layer is laminated on the first insulating layer and within the first opening, the second insulating layer having a second opening which exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening;
forming a gate electrode on the upper surface of the second insulating layer and in the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer;
A method for manufacturing a semiconductor device, comprising: A communication device equipped with a semiconductor device,
The semiconductor device includes:
a ternary or quaternary compound semiconductor layer;
a first insulating layer disposed on the compound semiconductor layer and having a first opening exposing a first region of an upper surface of the compound semiconductor layer;
a second insulating layer that is laminated on the first insulating layer and in the first opening, and that has a second opening that exposes a second region that is a part of the first region of the compound semiconductor layer exposed by the first opening and has an opening narrower than the first opening;
a gate electrode that is laminated on an upper surface of the second insulating layer and in the second opening and that is in direct contact with the second region on the upper surface of the compound semiconductor layer;
having
Communications equipment.

Images