WO2025055399A1 - Direct memory access system, data transport method, device and storage medium - Google Patents

Abstract

A direct memory access system, a data transport method, a device and a storage medium, which relate to the technical field of computers. The system comprises a macro instruction memory, a macro instruction controller, a macro instruction parsing engine and a data read-write transmission path. In the present application, a processor issues a macro instruction, wherein the macro instruction is used for instructing the transport of multi-dimensional structured data; the macro instruction controller sends the macro instruction to the macro instruction parsing engine; and the macro instruction parsing engine parses the macro instruction into a micro-operation code, and sends the micro-operation code to the data read-write transmission path, wherein the micro-operation code is used for instructing the transport of one-dimensional structured data in the multi-dimensional structured data. By means of the direct memory access system, the time required by the processor to generate an instruction for transporting the one-dimensional structured data, and the configuration overhead for issuing the instruction to the direct memory access system for execution can be greatly reduced, thereby improving the efficiency of data transport.

Description

Direct memory access system, data transfer method, device and storage medium

This application claims priority to Chinese patent application filed on September 13, 2023, with application number 202311177686.7 and invention name “Direct Memory Access System, Data Transfer Method, Device and Storage Medium”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of computer technology, and in particular to a direct memory access system, a data transfer method, a device and a storage medium.

Background Art

The Direct Memory Access (DMA) system is also known as the direct data transfer hardware unit, which can realize data transfer without the participation of the Central Processing Unit (CPU).

In the related technology, when executing data transfer, the processor in the computer device can send a data transfer instruction to the DMA system, and through the instruction, the read address, data length and write address of the data to be transferred are indicated to the DMA system. The DMA system reads the data from the bus according to the read address and data length, and writes the read data back to the bus in sequence starting from the write address.

However, in the above solution, the processor needs to first generate an instruction including a read address, a data length, and a write address according to the structure of the data to be moved. The instruction generation process takes a long time, thereby affecting the efficiency of data transfer.

Summary of the invention

The embodiments of the present application provide a direct memory access system, a data transfer method, a device and a storage medium, which can improve the efficiency of data transfer. The technical solution is as follows.

In one aspect, a direct memory access system is provided, the system comprising: a macro instruction memory, a macro instruction controller, a macro instruction parsing engine, and a data read and write transmission path;

The macro instruction memory and the macro instruction controller are respectively connected to a processor in a computer device, and the macro instruction memory is connected to the macro instruction controller;

The macro instruction controller is connected to the macro instruction parsing engine, the macro instruction parsing engine is connected to the data reading and writing transmission path, and the data reading and writing transmission path is connected to the bus of the computer device;

The macro instruction memory is used to store the macro instructions issued by the processor; the macro instructions are used to instruct the transport of multi-dimensional structure data;

The macro instruction controller is used to receive the trigger instruction sent by the processor, read the macro instruction from the macro instruction memory according to the trigger instruction, and send the macro instruction to the macro instruction parsing engine;

The macro instruction parsing engine is used to parse the macro instruction into a micro operation code and send the micro operation code to the data read and write transmission path; the micro operation code is used to instruct the transfer of one-dimensional structure data in the multi-dimensional structure data;

The data read/write transmission path is used to read and write the one-dimensional structure data to the bus according to the micro-operation code.

On the other hand, a data handling method is provided, the method is used in the direct memory access system as described above, and the method is executed by a macro instruction controller in the direct memory access system, the method comprising:

Receive the trigger instruction sent by the processor;

Reading the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used to instruct the transport of multi-dimensional structure data;

The macroinstruction is sent to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code and sends the micro-operation code to a data read-write transmission path, and the data read-write transmission path converts the micro-operation code into a micro-operation code. The operation code reads and writes one-dimensional structure data to the bus; the micro-operation code is used to instruct the transfer of the one-dimensional structure data in the multi-dimensional structure data.

On the other hand, a data handling device is provided, the device is used for a macro instruction controller in the direct memory access system as described above, the device comprising:

A trigger instruction receiving module, used to receive a trigger instruction sent by a processor;

A macro instruction reading module, used for reading the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used for instructing the transport of multi-dimensional structure data;

A macroinstruction sending module is used to send the macroinstruction to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code and sends the micro-operation code to a data read-write transmission path, and the data read-write transmission path reads and writes one-dimensional structure data to a bus according to the micro-operation code; the micro-operation code is used to indicate the transfer of the one-dimensional structure data in the multi-dimensional structure data.

On the other hand, a computer device is provided, wherein the computer device comprises the direct memory access system as described above.

On the other hand, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a controller to implement the data transfer method described above; the controller is a macro instruction controller in the direct memory access system described above.

On the other hand, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a controller, the data transfer method described above is implemented; the controller is a macro instruction controller in the direct memory access system described above.

On the other hand, a chip is provided, wherein the chip includes the direct memory access system as described above.

On the other hand, a computer device is provided, wherein the computer device comprises the chip as described above.

The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

What the processor sends to the DMA system is a macro instruction for instructing the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read-write transmission path, and the data read-write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above scheme, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system performs the analysis of the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate the instruction for transporting the one-dimensional structure data, and reduce the configuration overhead of the processor sending the above instruction to the DMA system for execution, thereby improving the efficiency of data transport.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a DMA system;

FIG2 is a schematic diagram of a DMA system supporting scatter-gather discrete transfers;

FIG. 3 is a schematic diagram of the format of a DMA instruction or descriptor;

FIG4 is a flow chart of a DMA implementation of data transfer;

FIG5 is a schematic diagram of the structure of a direct memory access system provided by an exemplary embodiment of the present application;

FIG6 is a schematic diagram showing an example of a hardware circuit parsing macro instruction involved in the present application;

FIG7 is a schematic diagram of the structure of a direct memory access system provided by another exemplary embodiment of the present application;

FIG8 is a schematic diagram of the structure of a direct memory access system provided by another exemplary embodiment of the present application;

FIG9 is a schematic diagram showing an example of format conversion involved in the present application;

FIG10 is a structural diagram of a macro instruction provided by an exemplary embodiment of the present application;

FIG11 is a schematic diagram of the process of parsing and generating micro-op codes for macro instructions;

FIG12 is a micro-operation code provided by an exemplary embodiment of the present application;

FIG13 is a timing diagram of a data transport path for stream processing involved in the present application;

FIG14 is a schematic diagram of the structure of a direct memory access system provided by another exemplary embodiment of the present application;

15 is an overall processing flow chart of the DMA system for processing data transfer provided by the present application;

FIG16 is a flow chart of a data transport method provided by an exemplary embodiment of the present application;

FIG. 17 is a schematic diagram of a data handling device provided by an exemplary embodiment of the present application.

DETAILED DESCRIPTION

Direct Memory Access (DMA) system, also known as direct data transfer hardware unit, is a technology that can realize data transfer without the participation of the Central Processing Unit (CPU). DMA transfer copies data from one address space to another, providing high-speed data transfer between peripherals and memory or between memory and memory.

The CPU has many functions such as transferring data, calculating, and controlling program transfer. It is the core of the system operation. The CPU is always processing a large number of transactions, but some transactions are not that important, such as data copying and storing data. If this part of the CPU resources can be saved and used by the CPU to process other complex transactions, the CPU resources can be better utilized.

Among them, data transfer (especially large amounts of data transfer) does not require CPU involvement. For example, if you want to copy data from external device A of a computer device to external device B, as long as external device A and external device B provide a DMA data channel, the data can be directly copied from external device A to external device B, and this process does not require CPU processing. Therefore, DMA can liberate the CPU to a certain extent, which plays an extremely important role in realizing efficient embedded systems and accelerating network data processing.

When implementing DMA transmission, the DMA controller directly controls the bus, so there is a problem of bus control transfer. That is, before DMA transmission, the CPU must hand over the bus control to the DMA controller, and after the DMA transmission ends, the DMA controller should hand over the bus control back to the CPU. A complete DMA transmission process usually requires four steps: DMA request, DMA response, DMA transmission, and DMA end.

FIG1 shows a schematic diagram of a basic DMA system, as shown in FIG1 :

1) The processor sends instructions to the DMA system, instructing the DMA system to perform data transfer operations. The DMA system and the bus perform direct data transfer interactions to achieve the operation of transferring a one-dimensional structured data from one storage address to another storage address;

2) The DMA system consists of a controller, a read data interface, a First Input First Output (FIFO) cache, and a write data interface. The controller is responsible for receiving and parsing instructions from the processor, instructing the read data interface to generate a read data request to the bus, and instructing the write data interface to generate a write data request to the bus; the FIFO cache is used for data caching for asynchronous execution of read and write data operations;

3) The processor sends transfer instructions to the DMA system one by one, instructing the DMA system to perform the transfer operation. One DMA system only corresponds to one instruction at a time.

FIG. 2 shows a schematic diagram of a DMA system supporting scatter-gather discrete transport, as shown in FIG. 2 :

1) In this solution, the DMA system is used to batch transfer multiple discrete data blocks, reducing the number of processor interventions, thereby improving transfer efficiency. It is mainly used in the transfer scenario of fragmented data;

2) In this scheme, a series of transport instructions are defined as descriptors. The processor sends the instructions in batches to the descriptor linked list of the DMA system in advance, and expresses the order relationship between the instructions in a linked list structure;

3) The instructions that the processor uses to instruct the DMA system to work are changed from clear transfer instructions to trigger instructions, which trigger the DMA system to start execution from a certain position in the descriptor list.

FIG. 3 shows a schematic diagram of the format of a DMA instruction or descriptor.

As shown in Figures 1 and 2 above, the DMA instructions or descriptors issued by the processor can instruct the DMA to directly initiate data read and write operations. Their common feature is that they can only handle the transfer of simple one-dimensional data structures, where the one-dimensional structure data refers to a data block indicated by a starting point (such as a starting address) and a length. In other words, the one-dimensional structure data is data with continuous addresses.

Based on the DMA system structures shown in FIG. 1 and FIG. 2 , please refer to FIG. 4 , which shows a flow chart of DMA implementing data transfer. As shown in FIG. 4 , the steps of implementing data transfer in the DMA system structures shown in FIG. 1 and FIG. 2 are consistent:

Step 401, receiving an instruction and determining whether to execute the instruction according to the state of the DMA system;

Step 402, when it is determined that the instruction is to be executed, a read operation is initiated to the bus according to the read address and data size in the instruction, such as Advanced eXtensible Interface (AXI) read transmission, Advanced Peripheral Bus (APB), Advanced High-performance Bus (AHB), AXI Coherence Extension (ACE) and other read operations;

Step 403, receiving the data returned by the bus and buffering it into FIFO;

Step 404, initiating a write operation to the bus according to the write address and data size in the instruction, such as AXI write transfer, APB, AHB, ACE, etc. write operation;

Step 405, write the data in the FIFO into the bus.

However, the DMA system structure shown in FIG. 1 and FIG. 2 is a DMA system structure for performing transfer of one-dimensional structure data, that is, the processor needs to determine the read/write address and data length of the one-dimensional structure data to be transferred in advance, and then notify the DMA system. Since the process of the processor determining the read/write address and data length of the one-dimensional structure data to be transferred is implemented through program code, it takes a long time to generate a transfer instruction for a one-dimensional structure data. Therefore, the efficiency of the processor issuing data transfer instructions has become a bottleneck affecting the data transfer efficiency.

Please refer to FIG. 5 , which shows a schematic diagram of the structure of a direct memory access system provided by an exemplary embodiment of the present application. The system may include: a macro instruction memory 501 , a macro instruction controller 502 , a macro instruction parsing engine 503 , and a data read and write transmission path 504 .

The macro instruction memory 501 and the macro instruction controller 502 are respectively connected to the processor in the computer device, and the macro instruction memory 501 is connected to the macro instruction controller 502 .

The above processor may be a scalar processor.

The processor may be a computing device that implements computing functions by running computer instructions or codes. For example, the processor may be a central processing unit (CPU) of a computer device.

The above-mentioned macroinstruction memory 501 and macroinstruction controller 502 are respectively connected to the processor in the computer device, which means that the macroinstruction memory 501 and macroinstruction controller 502 are respectively electrically connected to the processor in the computer device, and the macroinstruction memory 501 and macroinstruction controller 502 can respectively receive instructions/signals/data sent by the processor.

The above-mentioned macroinstruction memory 501 is connected to the macroinstruction controller 502 , which means that the macroinstruction memory 501 is electrically connected to the macroinstruction controller 502 , and the macroinstruction controller 502 can read instructions/data from the macroinstruction memory 501 .

The above-mentioned macroinstruction memory 501 can be a random access memory (Random Access Memory, RAM), such as resistance random access memory (ReRAM) or dynamic random access memory (DRAM), etc.

The macro instruction controller 502 is connected to the macro instruction parsing engine 503, the macro instruction parsing engine 503 is connected to the data reading and writing transmission path 504, and the data reading and writing transmission path 504 is connected to the bus of the computer device.

The above-mentioned macro instruction controller 502 is connected to the macro instruction parsing engine 503 , which may mean that the macro instruction controller 502 is electrically connected to the macro instruction parsing engine 503 , and the macro instruction controller 502 can send instructions/data to the macro instruction parsing engine 503 .

The above-mentioned macroinstruction parsing engine 503 is connected to the data read/write transmission path 504 , which means that the macroinstruction parsing engine 503 is electrically connected to the data read/write transmission path 504 , and the macroinstruction parsing engine 503 can send instructions/data to the data read/write transmission path 504 .

The data read/write transmission path 504 and the bus of the computer device refer to that the data read/write transmission path 504 is electrically connected to the bus interface of the computer device, and the data read/write transmission path 504 can read data from the bus of the computer device (or, read data from other memory of the computer device/memory connected to the computer device through the bus), and write data to the bus of the computer device (or, write data to other memory of the computer device/memory connected to the computer device through the bus). data to the connected memory).

The macroinstruction memory 501 is used to store the macroinstructions issued by the processor; the macroinstructions are used to instruct the transport of multi-dimensional structured data.

In an embodiment of the present application, when it is necessary to move data of a complex structure (that is, a multi-dimensional structure), the processor of the computer device may not need to disassemble the multi-dimensional structure data, but directly generate a macro instruction indicating information such as the read and write address and data volume of the multi-dimensional structure data, and send the macro instruction to the macro instruction memory 501 for storage by the macro instruction memory 501.

The macro instruction controller 502 is used to receive the trigger instruction sent by the processor, read the macro instruction from the macro instruction storage 501 according to the trigger instruction, and send the macro instruction to the macro instruction parsing engine 503.

When the computer device needs to transfer certain multi-dimensional structure data, the trigger instruction can be used to trigger the macro instruction controller 502 to specify a macro instruction corresponding to the transfer operation of the multi-dimensional structure data.

The trigger instruction may indicate a macro instruction stored in the macro instruction memory 501 . For example, the trigger instruction may include an address of a macro instruction stored in the macro instruction memory 501 .

In some embodiments, one trigger instruction may instruct the macroinstruction controller 502 to extract a single macroinstruction, or one trigger instruction may instruct the macroinstruction controller 502 to extract multiple macroinstructions.

When a trigger instruction instructs the macroinstruction controller 502 to extract multiple macroinstructions, the trigger instruction can include the addresses of the multiple macroinstructions respectively; the macroinstruction controller 502 extracts the multiple macroinstructions respectively according to the addresses of the multiple macroinstructions. This solution has no restrictions on the storage locations of the multiple macroinstructions in the macroinstruction memory 501, and can expand the indication scenarios of multiple macroinstructions.

Alternatively, if the multiple macroinstructions are macroinstructions stored continuously in the macroinstruction memory 501, the trigger instruction may include the starting addresses and instruction numbers of the multiple macroinstructions, and the macroinstruction controller 502 may read the multiple macroinstructions in sequence starting from the starting address. In this scheme, the trigger instruction only needs to carry an address and an instruction number, that is, it can instruct the macroinstruction controller 502 to extract multiple macroinstructions, which can save the transmission resources of the trigger instruction and improve the indication efficiency of the macro instruction.

The macroinstruction parsing engine 503 is used to parse the macroinstructions into micro-operation codes and send the micro-operation codes to the data read/write transmission path 504; the micro-operation codes are used to instruct the transfer of one-dimensional structure data in the multi-dimensional structure data.

In the embodiment of the present application, the macroinstruction parsing engine 503 can parse the macroinstructions through hardware circuits to parse one macroinstruction into multiple micro-operation codes, and send the micro-operation codes to the data read and write transmission path 504.

The multidimensional structure data is composed of multiple one-dimensional structure data. The addresses of the multidimensional structure data may be continuous; or the addresses of the multidimensional structure data may be discontinuous, for example, among the multiple one-dimensional structure data constituting the multidimensional structure data, the addresses of each one-dimensional structure data are continuous, and the addresses of different one-dimensional structure data are discontinuous.

For example, assuming that the multidimensional structure data is an n×m two-dimensional structure data, it can be regarded as a matrix composed of n one-dimensional structure data, and the length of each one-dimensional structure data is m; or, the n×m two-dimensional matrix data can also be regarded as a matrix composed of m one-dimensional structure data, and the length of each one-dimensional structure data is n.

Please refer to FIG. 6 , which shows an example schematic diagram of a hardware circuit parsing macro instruction involved in the present application. As shown in FIG. 6 , a filling instruction of a two-dimensional data block, the instruction configuration of which includes:

Basic configuration:

data_type=INT32, dimen_0_size=0xA, dimen_1_size=0x2, read_addr=0x0, write_addr=0x0;

Extended configuration:

op_type=pad_op, left_pad_size=0x1, right_pad_size=0x1, top_pad_size=0x1, buttom_pad_size=0x1, internal_pad_size=0x1;

Among them, 0x represents a hexadecimal value.

The macro instruction parsing engine 503 performs parsing on a two-dimensional data block and parses it into five one-dimensional transport instructions, namely, three one-dimensional constant filling micro operation codes (micro operations, uOPs) and two one-dimensional transport micro operation codes, specifically including:

uOP 1:

uop_type=constant_filling, data_type=INT32, data_size=left_pad_size+dimen_0_size+right_pad_size+right_pad_size=0xD, read_addr=NA, write_addr=0x0;

uOP 2:

uop_type=read_write, data_type=INT32, data_size=dimen_0_size=0xA, read_addr=0x0, write_addr=uop1_write_addr+uop1_data_size=0xD;

uOP 3:

uop_type=constant_filling, data_type=INT32, data_size=left_pad_size+left_pad_size+dimen_0_size+right_pad_size+right_pad_size=0xE, read_addr=NA, write_addr=uop2_write_addr+uop2_data_size=0xD+0xA=0x17;

uOP 4:

uop_type=read_write, data_type=INT32, data_size=dimen_0_size=10, read_addr=uop2_read_addr+uop2_data_size=0xA, write_addr=uop3_write_addr+uop3_data_size=0x17+0xE=0x25;

uOP 5:

uop_type=constant_filling, data_type=INT32, data_size=left_pad_size+left_pad_size+dimen_0_size+right_pad_size=0xD, read_addr=NA, write_addr=uop4_write_addr+uop4_data_size=0x25+0xA=0x2F;

Among them, 0x represents a hexadecimal value.

The above-mentioned macroinstruction parsing engine 503 can parse macroinstructions through hardware circuits, and determine the read and write addresses and data sizes (the data structure is fixed to one dimension) of each one-dimensional structure data in the multidimensional structure data according to the data structure, read and write addresses and data size of the multidimensional structure data in the macroinstructions, thereby generating corresponding micro-operation codes.

The data read/write transmission path 504 is used to read and write one-dimensional structured data to the bus according to the micro-operation code.

For example, for a micro-operation code, which includes the read address, write address and data size of one-dimensional structure data, the above-mentioned read address can be the starting address for data reading, and the above-mentioned write address can be the starting address for data writing; the data read and write transmission path 504 can first read the one-dimensional structure data of the length corresponding to the above-mentioned data size through the bus starting from the read address according to the read address, and then cache the one-dimensional structure data in the data read and write transmission path 504, and then, according to the write address, write the above-mentioned one-dimensional structure data in sequence starting from the write address through the bus, thereby completing the transfer of the one-dimensional structure data from the read address to the write address; wherein, for multiple micro-operation codes obtained by parsing a macro instruction, when the above-mentioned multiple micro-operation codes are processed, it can be considered that the transfer of the multi-dimensional structure data corresponding to the above-mentioned macro instruction is completed.

In summary, the scheme shown in the embodiment of the present application is that the processor sends a macro instruction to the DMA system, which is used to instruct the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read and write transmission path, and the data read and write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above scheme, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system performs the analysis of the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate the instruction for transporting the one-dimensional structure data, as well as the configuration overhead of sending the above instruction to the DMA system for execution, thereby improving the efficiency of data transport.

Based on the DMA system structure shown in Figure 1 or Figure 2 above, the transfer of complex data structures in the computing system is generally broken down by the processor into specific transfer data sizes and source and destination addresses (corresponding to the above read addresses and write addresses), and then sent to the DMA for transfer. This system cannot meet the storage and computing bandwidth requirements of heterogeneous processors (such as AI processors, image/video encoding chips) for parallel data transmission, as well as the transfer requirements of complex data structures.

Specifically, the DMA system structure shown in Figure 1 or Figure 2 can only handle the transfer of simple one-dimensional data structures, that is, data blocks with only a starting point and a length. This feature cannot be directly processed by DMA in the current popular AI inference training processors when faced with complex and diverse data structures. It needs to be processed by software, that is, the internal processor uses a line of labels to The instruction data structure is disassembled into segments of exact length and read/write address data blocks before being sent to DMA for transfer. This often requires a large amount of processor hardware resources and time, resulting in a decrease in the effective performance of other business programs executed by the processor.

At the same time, the powerful computing power in artificial intelligence (AI) reasoning training processors requires very high data transfer bandwidth support to be fully utilized. The more serious impact of the above problem is that the conventional processor executes the data structure disassembly and then generates the transfer instruction processing process, which takes too long, resulting in the data transfer bandwidth failing to meet expectations. The bottleneck is not the DMA transfer performance, but the processor disassembles the complex data structure and then generates DMA instructions. The specific reason is that the disassembly process of a complex data structure may be implemented by the processor through a program segment, which requires a series of links such as instruction fetch, instruction parsing, instruction emission, instruction execution pipeline, instruction write back, instruction retirement, etc., and it is necessary to deal with the dependency relationship between the previous and next instructions. This results in the disassembly of a complex data structure and the execution process of the program segment that generates DMA instructions, which requires the processor to go through dozens or even hundreds of clock cycles to complete.

Based on the technical solution of the embodiment shown in FIG. 5 of the present application, a DMA system is provided which can parse complex instruction sequences by itself and efficiently transfer them, and has the function of executing data synchronization with the processor and other subsystems:

1) The DMA system can be applied to AI reasoning and training chips, the handling of complex data structures, and scenarios where high computing power requires high handling bandwidth;

2) The DMA system can also be used in image codec chips, where image codec chips also have the same usage scenarios as AI reasoning and training, namely, the scenario of moving complex data structures.

Based on the embodiment shown in FIG5 , please refer to FIG7 , which shows a schematic diagram of the structure of a direct memory access system provided by another exemplary embodiment of the present application. As shown in FIG7 , in the DMA system shown in FIG5 , a data read and write transmission path 504 includes a plurality of processing units, and the plurality of processing units at least include a read data interface unit 504 a, a cache unit 504 b, and a write data interface unit 504 c;

The macro instruction parsing engine 503 is connected to the read data interface unit 504a, and the macro instruction parsing engine 503 is used to send the micro operation code to the read data interface unit 504a;

The above-mentioned micro-operation codes are used to be transmitted sequentially among multiple processing units.

In the embodiment of the present application, the macroinstruction parsing engine 503 is connected to the read data interface unit 504a, which means that the macroinstruction parsing engine 503 is electrically connected to the read data interface unit 504a, so that the macroinstruction parsing engine 503 can send a signal to the read data interface unit 504a, thereby being able to send the micro-operation code to the read data interface unit 504a.

In an embodiment of the present application, multiple processing units in the above-mentioned data read and write transmission path 504 are connected in sequence, and, during the data transfer process, starting from the read data interface unit 504a, the read data interface unit 504a receives the micro-operation code sent by the macro instruction parsing engine 503, reads the one-dimensional structure data from the bus according to the micro-operation code, and sends the one-dimensional structure data and the micro-operation code together to the next processing unit. After a processing unit receives the one-dimensional structure data and micro-operation code sent by the previous processing unit, it passes the one-dimensional structure data and the micro-operation code to the next processing unit. If the micro-operation code instructs the current processing unit to perform a certain processing on the one-dimensional structure data, the current processing unit can also perform corresponding processing on the one-dimensional structure data, and then pass the processed one-dimensional structure data and the micro-operation code to the next processing unit. After the write data interface unit 504c receives the one-dimensional structure data and micro-operation code sent by the previous processing unit, it writes the one-dimensional structure data to the bus according to the micro-operation code. In the above process, the macroinstruction parsing engine 503 only needs to send the micro-operation code to the read data interface unit 504a, and does not need to send it to each processing unit that needs the micro-operation code, thereby reducing the design and wiring difficulty of the DMA system. At the same time, it also reduces the bandwidth requirement between the macroinstruction parsing engine 503 and the data read and write transmission path 504, and improves the efficiency of the macroinstruction parsing engine 503 in transmitting micro-operation codes to the data read and write transmission path 504.

Based on the embodiments shown in FIG. 5 or 7 , in some embodiments, the macroinstruction parsing engine 503 is used to parse the data structure of the multidimensional structure data when parsing the macroinstruction into a micro-operation code, and determine the read and write addresses and data size of the one-dimensional structure data in the multidimensional structure data; and generate a micro-operation code based on the read and write addresses and data size of the one-dimensional structure data.

The above-mentioned macro instruction may include information such as the read address, write address, data structure, and data size of the multi-dimensional structure data. Combined with the data structure and data size of the multi-dimensional structure data, the macro instruction parsing engine 503 may determine the data size of each one-dimensional structure data in the multi-dimensional structure data, and then combine the read address and write address of the multi-dimensional structure data to determine the data size of each one-dimensional structure data. The read address and write address of each one-dimensional structure data are determined, and then the macro instruction parsing engine 503 can generate a micro operation code including the read address, write address and data size of the one-dimensional structure data, and each one-dimensional structure data can correspond to a micro operation code.

Among them, the data structure of the above-mentioned multidimensional structured data may include the original data structure of the multidimensional structured data (also called the source-end data structure), and may also include the data structure of the multidimensional structured data after being moved (also called the destination-end data structure); among them, if the data structure of the multidimensional structured data only includes the source-end data structure, it can be considered that the data structure of the multidimensional structured data after being moved remains unchanged; if the data structure of the multidimensional structured data also includes the destination-end data structure, it can be considered that the data structure of the multidimensional structured data after being moved changes.

Based on the embodiment shown in FIG. 7 , please refer to FIG. 8 , which shows a schematic diagram of the structure of a direct memory access system provided by another exemplary embodiment of the present application. As shown in FIG. 8 , in the DMA system shown in FIG. 7 , the macro instruction is also used to instruct to perform format conversion processing on multi-dimensional structure data, and the micro operation code is also used to instruct to perform format conversion processing on one-dimensional structure data;

The multiple processing units also include at least one of a pre-format conversion processing unit 504d and a post-format conversion processing unit 504e, the pre-format conversion processing unit 504d is located before the cache unit, and the post-format conversion processing unit 504e is located after the cache unit; wherein the pre-format conversion processing unit 504d is located before the cache unit, which may mean that in the order in which the multiple processing units are connected in sequence, the pre-format conversion processing unit is located before the cache unit; correspondingly, the post-format conversion processing unit 504e is located after the cache unit, which may mean that in the order in which the multiple processing units are connected in sequence, the post-format conversion processing unit is located after the cache unit;

The format conversion pre-processing unit 504d is used to perform format conversion pre-processing on the one-dimensional structure data according to the format conversion processing processing mode indicated by the micro-operation code, and write the result data of the format conversion pre-processing into the cache unit 504b;

The format conversion post-processing unit 504e is used to perform format conversion post-processing on the data in the cache unit 504b according to the format conversion processing method indicated by the micro-operation code, and then send it to the next processing unit.

The format conversion of data may include one or more combinations of data space conversions such as data type conversion, shifting, splicing, deletion, interleaving, mirroring, and filling. In traditional DMA systems, these are usually implemented by the processor through a combination of executing program instructions; in an embodiment of the present application, at least one processing unit of the format conversion pre-processing unit and the format conversion post-processing unit is set at least one place before or after the cache unit to implement data format conversion through hardware circuits, thereby improving the efficiency of data format conversion.

Some format conversion operations need to be completed in several steps. Therefore, in the embodiment of the present application, a "pre-processing-cache-post-processing" structure is set in the data read and write transmission path 504 to process the data format conversion process step by step. For example, the format conversion operation of data mirroring + tail padding requires that a piece of data be segmented and reversed in the pre-processing, stored in the cache, and then the data is taken out in reverse order during the post-processing process, and finally output to the downstream after the tail is filled. There are many types of data format conversion operations, and each format conversion operation can correspond to a different format conversion pre-processing unit 504d or format conversion post-processing unit 504e. Generally speaking, a DMA structure can support a limited number of conversion types.

Please refer to Figure 9, which shows an example schematic diagram of the format conversion involved in the present application. As shown in Figure 9, the data format conversion operation is to broadcast a group of one-dimensional data (7, 8, 9) into a group of two-dimensional arrays ((7, 7, 7), (8, 8, 8), (9, 9, 9)), and the hardware circuit involved includes at least the following circuit units: a multiplexer, a counter and a replication unit.

Among them, the counter accumulates from 0 to N-1 (N is the number of elements in the input one-dimensional array) as the selection signal of the multiplexer, selects each element of the read-in data in turn, and copies each element through the broadcast number of the replication unit and writes it into the cache unit. The number of copies is the broadcast number configured by the instruction.

As shown in FIG9 , broadcasting a set of one-dimensional data (7, 8, 9) into a set of two-dimensional arrays ((7, 7, 7), (8, 8, 8), (9, 9, 9)) requires one read operation and three copy operations, which specifically include the following steps:

Step 1: Perform a read operation to input the one-dimensional data (7, 8, 9) into the format conversion pre-processing unit, and then perform a copy operation to obtain (7, 7, 7);

Step 2: Perform the second copy operation to obtain ((7, 7, 7), (8, 8, 8));

Step 3: Perform the third copy operation and finally obtain the two-dimensional array ((7, 7, 7), (8, 8, 8), (9, 9, 9)).

In some embodiments, the macro instruction includes a first format conversion configuration, which is a configuration for performing format conversion on the multi-dimensional structure data; for example, the first format conversion configuration may indicate a method for performing format conversion on the multi-dimensional structure data;

The macro instruction parsing engine 503 is used to generate a second format conversion configuration according to the first format conversion configuration when generating a micro operation code according to the read/write address and data size of the one-dimensional structure data, wherein the second format conversion configuration is a configuration for performing format conversion on the one-dimensional structure data; for example, the second format conversion configuration may indicate a method for format conversion of the one-dimensional structure data;

A micro-operation code is generated according to the read and write addresses, data size, and the second format conversion configuration of the one-dimensional structure data.

In an embodiment of the present application, when the DMA system supports data format conversion, a format conversion configuration can be set in the micro-operation code to support control of the format conversion operation and improve the application flexibility of the format conversion.

In order to implement the format conversion configuration set in the micro-op code, it is necessary to indicate it in the macro instruction. Since the macro instruction is an instruction set for multi-dimensional structure data, the format conversion configuration therein is also the format conversion configuration corresponding to the multi-dimensional structure data setting. Therefore, when the macro instruction parsing engine 503 parses the macro instruction to generate the micro-op code, it is necessary to generate the format conversion configuration for the one-dimensional structure data in the micro-op code according to the format conversion configuration set for the multi-dimensional structure data in the macro instruction. In other words, according to the format conversion configuration set for the multi-dimensional structure data in the macro instruction, the format conversion configuration is updated to obtain the format conversion configuration for the one-dimensional structure data in the micro-op code.

In one possible implementation, in the process of generating a format conversion configuration for one-dimensional structure data in a micro-operation code according to a format conversion configuration set for multi-dimensional structure data in a macro instruction, the macro instruction parsing engine 503 can query a pre-stored correspondence between a first format conversion configuration and a second format conversion configuration, and determine a second format conversion configuration corresponding to the first format conversion configuration.

In some embodiments, as shown in FIG8 , in the DMA system shown in FIG7 , the macroinstruction is further used to instruct the execution of an operation process on multi-dimensional structure data, and the micro-operation code is further used to instruct the execution of an operation process on one-dimensional structure data;

The plurality of processing units also include a data operation unit 504f;

The data operation unit is used to perform operation processing on the input data according to the operation processing method indicated by the micro-operation code, and then send it to the next processing unit.

The above-mentioned data operations may include data type conversion, for example, 32-bit integer type (32bit integer, INT32) to FP32, and data calculation, such as addition, subtraction, multiplication and division of the arithmetic and logic unit (Arithmetic and Logic Unit, ALU). These calculation operations can be implemented through hardware circuits, so that some data operations are pre-executed in the DMA system to facilitate subsequent data processing, such as subsequent AI reasoning or training, or subsequent image encoding and decoding.

In some embodiments, the macroinstructions and micro-operation codes respectively include operation configurations, which are configurations of operation processing. For example, the operation configurations can be used to indicate the operation processing method, for example, the operation configurations can indicate that the operation processing method is a combination of one or more operation methods such as addition, subtraction, multiplication, and division.

In the embodiment of the present application, when the DMA system supports data operations, the operation configuration can be set in the micro-operation code to support the control of the operation operation and improve the application flexibility of the operation operation. To achieve the setting of the operation configuration in the micro-operation code, it is necessary to indicate it in the macro instruction.

In some embodiments, as shown in FIG8 , in the DMA system shown in FIG7 , the macroinstruction and the micro-operation code further include a synchronization configuration, the synchronization configuration is used to instruct to perform a status check on a target address, the target address being at least one of a read address and a write address of data;

The macro instruction controller 502 is used to check the state of the target address according to the synchronization configuration in the macro instruction when sending the macro instruction to the macro instruction parsing engine 503, and send the macro instruction to the macro instruction parsing engine 503 when the state of the target address meets the specified conditions; the specified conditions include: when the target address includes a read address, the state of the read address is readable; when the target address includes a write address, the state of the write address is writable;

A read data interface unit 504a, configured to read one-dimensional structure data from the read address when the target address includes the read address and the state of the read address is readable;

The write data interface unit 504c is used to send a write address to the write address when the target address includes the write address and the state of the write address is writable. address to write data.

The above-mentioned synchronization status refers to the source end (i.e., the external device or memory from which data is read) to be read by DMA, and the state of the destination end (i.e., the external device or memory from which data is written), that is, whether the source end is readable and whether the destination end is writable, which is generally represented by a 1-bit status bit. These status bits are stored in the processor and are globally visible, generally containing multiple groups, such as 32 groups, to meet the read and write requirements of multiple DMA or computing units. Optionally, each group of status can have a number (Identity Document, ID).

For example, when a macro instruction is configured with "ID0, check its read status, do not check the write status", that is, before the DMA system executes the read operation of the address corresponding to the macro instruction, it will first check whether ID0 is readable, and only initiate the read operation after checking that it is readable. After reading, the processor is notified to update the read status. For the write operation, since it is configured not to check, the write operation is directly initiated. Through the above processing, macro instructions that can immediately execute data transfer can be issued first, thereby improving the efficiency of data transfer.

Among them, the above-mentioned synchronization check operation can be executed respectively in the macroinstruction controller 502, the read data interface unit 504a and the write data interface unit 504c, which requires setting the above-mentioned synchronization configuration in both the macroinstruction and the micro-operation code. Accordingly, the macroinstruction controller 502, the read data interface unit 504a and the write data interface unit 504c can first check the status of the read address/write address before executing the macroinstruction issuance, reading data and writing data, and determine whether to perform the corresponding operation according to the status of the read address/write address.

Among them, for the macroinstruction controller 502, when the result of the synchronization check is that the condition is not met, the current macroinstruction can be stored in the instruction waiting queue, and the next macroinstruction can be processed. After waiting for a period of time, the macroinstructions in the instruction waiting queue can be synchronized and checked again to improve the concurrent processing capability of the macroinstructions.

Please refer to Figure 10, which shows a structure diagram of a macro instruction provided by an exemplary embodiment of the present application. As shown in Figure 10, the present application provides a DMA macro instruction for expressing multi-dimensional complex data structures and data operations such as transport, format conversion, and calculation.

Except for the read and write addresses, which describe the start and destination addresses of the transfer like ordinary DMA instructions, the contents of other fields are described as follows.

1) Source data structure:

a. Source data block structure information, which includes data types, such as half-precision floating point (Floating Point 16, FP16), 8-bit integer type (8bit integer, INT8), single-precision floating point (Floating Point 32, FP32), etc.

b. Data dimension information, i.e., the size of dimension 0, dimension 1, dimension 2, dimension 3, etc., that is, a data block is no longer described in traditional bytes, but in a data structure.

2) Destination data structure: The destination data structure information also includes data type and data dimension information, but its type and size may be different from those of the source. That is, it expresses the operation of taking out a part of a multidimensional data block from a multidimensional data block and performing data type conversion. This operation is particularly common in AI reasoning and training.

3) Format conversion operation configuration: including but not limited to matrix transposition, data broadcasting, data mirroring, data padding, data shifting, data splicing and other operations.

4) Operation configuration: including but not limited to data type conversion (such as FP32 to FP16), data accumulation, activation (RELU) operations, etc.

5) Number of loops: a macro instruction can be executed once or multiple times.

6) Read stepping and write stepping: in conjunction with the loop operation, the read and write address are stepped in each loop.

7) Synchronization configuration: mainly includes synchronization check enable, synchronization update enable, and synchronization relationship ID of the source and sink.

Based on the macro instruction shown in FIG. 10 , a schematic diagram of the process of parsing the macro instruction to generate a micro operation code may be shown in FIG. 11 . FIG. 11 shows a schematic diagram of the process of parsing the macro instruction to generate a micro operation code, which specifically includes the following steps:

Step 1101: parse the macro instruction loop operation and update the read and write start address according to the read and write step;

Step 1102: parse the multi-dimensional data structure (corresponding to the multi-dimensional structure data), extract the one-dimensional vector (corresponding to the one-dimensional structure data), and calculate the vector read and write address and size;

Step 1103: Update other format conversion configurations according to the parsed one-dimensional vector;

Step 1104: Generate DMA micro-operation code (uOP).

In the above step 1103, updating other format conversion configurations refers to updating the size of the data involved in the format conversion, as well as updating the dimension, because the complex data at this time has been reduced from multi-dimensional to one-dimensional.

Please refer to Figure 12, which shows a micro-op code provided by an exemplary embodiment of the present application. As shown in Figure 12, the present application describes a DMA micro-op code, which is similar to the content of the instruction or descriptor of the traditional DMA, consisting of "read and write address + data size", and newly adds format conversion configuration and operation configuration fields, which are used to indicate the format conversion pre/post processing module and data operation module respectively.

Based on the micro-op code shown in FIG. 12 above, please refer to FIG. 13, which shows a working timing diagram of a data handling path for streaming processing involved in the present application. As shown in FIG. 13, the micro-op code generated by the parsing engine only needs to be passed to the read data interface module of the first-level link. In each subsequent link, the module only extracts the domain segment that the module needs to use, and after processing, the micro-op code and data (Date, D) are synchronously passed to the next-level module. This solves the problem of the front-to-back dependency of the control unit in the traditional DMA that it needs to pass the control word to each module in the data channel and coordinate the working rhythm of each module.

Based on the embodiments shown in FIG. 5 , FIG. 7 or FIG. 8 , the DMA system may further support multiple virtual channels to support simultaneous scheduling of multiple processors.

In some embodiments, based on the embodiment shown in Figure 8, please refer to Figure 14, which shows a structural diagram of a direct memory access system provided by another exemplary embodiment of the present application. As shown in Figure 14, in the DMA system shown in Figure 8, the macroinstruction controller 502 is used to receive macroinstructions respectively sent by multiple processors through multiple virtual channels 505, and send the macroinstructions respectively sent by multiple processors to the macroinstruction parsing engine 503 in sequence according to the priorities of the multiple virtual channels 505.

As shown in Figure 14, the DMA system involved in the embodiment of the present application can also add virtual channels to support simultaneous use by multiple users. As shown in Figure 14, multiple processors can issue instructions to the DMA system at the same time, each processor can register a DMA virtual channel, and the controller of the DMA system can execute the corresponding trigger instructions in sequence according to the priority of each virtual channel.

As shown in any one of FIG. 5 , FIG. 7 , FIG. 8 and FIG. 14 , the DMA system provided in the present application has the following characteristics.

1) In this application, the processor sends a macro instruction to the DMA system, which describes a multi-dimensional complex data structure and its data operations such as transportation, format conversion, and calculation.

2) The processor can issue macro instructions of the DMA system in batches and write them into the macro instruction memory of the DMA system.

3) The processor issues a trigger instruction to instruct the DMA system to start executing the macro instruction. The content of the trigger instruction may be the starting execution address in the macro instruction memory of the DMA system and the number of instructions.

4) The DMA system can execute multiple macroinstructions in batches. Since each macroinstruction may have data dependencies with other components in the chip, each macroinstruction can be configured with synchronization information. The DMA system checks the synchronization relationship and makes its own decisions on the timing of executing each instruction.

5) The macroinstruction controller of the DMA system receives the trigger instruction of the processor, reads the macroinstruction from the macroinstruction memory, performs pre-analysis, checks the synchronization relationship, and determines whether to send the instruction to the analysis engine or store it in the waiting queue.

6) The DMA system has a built-in macro-instruction parsing engine that parses complex instructions through hardware circuits, rather than having the processor execute a program to parse complex instructions. The macro-instruction parsing engine mainly handles the parsing of data structures, decomposing abstract multi-dimensional data structures into multiple micro-operation codes that can be recognized by downstream data paths, namely "read and write address + data size + configuration".

7) In the component units of the data read and write transmission path of the DMA system of the present application, in addition to the traditional DMA read and write interface module and cache module, a format conversion module and a data operation module can be newly added. The purpose is to perform format conversion and some calculation operations along the data transmission path to achieve data processing without bandwidth loss.

8) The present application provides a streaming processing DMA system. After the module processing of each link is completed, the load (data or instruction) and control word (synchronization relationship, instruction or micro-operation code) are passed to the next link module, and then new processing operations can be received. There is no dependency between the modules in the previous and next links.

The overall processing flow chart of the DMA system for processing data transfer provided by the present application may be shown in FIG15. Please refer to FIG15, the specific process is as follows:

Step 1501: receiving a DMA trigger instruction;

Step 1502: Read the DMA macro instruction according to the address carried by the trigger instruction;

Step 1503: pre-analyze the macro instruction and perform synchronization relationship check according to the synchronization configuration;

If synchronization fails, the macro instruction is transferred to the instruction waiting queue and synchronization check is performed until synchronization succeeds;

If the synchronization is successful, proceed to the next step;

Step 1504: Parse the macroinstruction into micro-operation code;

Step 1505: Generate a read operation to the bus according to the instruction read address and data size, such as AXI read transfer, APB, AHB, ACE and other read operations;

Step 1506: Perform format conversion pre-processing according to the format conversion configuration;

Step 1507: Write the data and micro-op code into the cache;

Step 1508: Perform format conversion post-processing according to the format conversion configuration;

Step 1509: Execute data computing operations according to the computing configuration;

Step 1510: Generate a write operation to the bus according to the instruction write address and data size, such as AXI write transfer, APB, AHB, ACE, etc. write operation;

Finally, return to step 1503 and execute the instruction completion report to instruct the controller to update the synchronization relationship.

Please refer to FIG. 16 , which shows a flow chart of a data transfer method provided by an exemplary embodiment of the present application. The method is used in the above-mentioned direct memory access system, and the method is executed by a macro instruction controller in the direct memory access system, and the method includes:

Step 1601, receiving a trigger instruction sent by a processor;

Step 1602, reading a macro instruction from a macro instruction memory according to a trigger instruction; the macro instruction is used to instruct the transfer of multi-dimensional structure data;

Step 1603, sending the macroinstruction to the macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code and sends the micro-operation code to the data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to the bus according to the micro-operation code; the micro-operation code is used to indicate the transfer of one-dimensional structure data in multi-dimensional structure data.

In some embodiments, the macroinstruction and the micro-operation code further include a synchronization configuration, the synchronization configuration being used to instruct to perform a status check on a target address, the target address being at least one of a read address and a write address of the data;

The above sending of macro instructions to the macro instruction parsing engine includes:

Check the status of the target address according to the synchronization configuration;

When the state of the target address meets the specified condition, the macro instruction is sent to the macro instruction parsing engine;

The specified conditions include:

When the target address includes a read address, the state of the read address is readable;

When the target address includes a write address, the state of the write address is writable.

In some embodiments, receiving a trigger instruction sent by a processor includes:

receiving macro instructions respectively sent by a plurality of processors through a plurality of virtual channels;

Send the macro to the macro parsing engine, including:

According to the priorities of the multiple virtual channels, the macro instructions respectively sent by the multiple processors are sent to the macro instruction parsing engine in sequence.

In summary, in the scheme shown in the embodiment of the present application, the processor sends a macro instruction to the DMA system, which is used to instruct the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read and write transmission path, and the data read and write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above scheme, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system performs the analysis of the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate instructions for transporting one-dimensional structure data, thereby improving the efficiency of data transport.

Please refer to FIG. 17 , which shows a schematic diagram of a data handling device provided by an exemplary embodiment of the present application. The device is used for a macro instruction controller in the above direct memory access system, and the device comprises:

The trigger instruction receiving module 1701 is used to receive the trigger instruction sent by the processor;

The macro instruction reading module 1702 is used to read the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used to instruct the transport of multi-dimensional structure data;

The macroinstruction sending module 1703 is used to send macroinstructions to the macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstructions into micro-operation codes and sends the micro-operation codes to the data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to the bus according to the micro-operation codes; the micro-operation codes are used to indicate the movement of one-dimensional structure data in multi-dimensional structure data.

In some embodiments, the macroinstruction and the micro-operation code further include a synchronization configuration, the synchronization configuration being used to instruct to perform a status check on a target address, the target address being at least one of a read address and a write address of the data;

The macro instruction sending module 1703 is used to check the status of the target address according to the synchronization configuration;

When the state of the target address meets the specified condition, the macro instruction is sent to the macro instruction parsing engine;

The specified conditions include:

When the target address includes a read address, the state of the read address is readable;

When the target address includes a write address, the state of the write address is writable.

In some embodiments, the trigger instruction receiving module 1701 is used to receive macro instructions respectively sent by multiple processors through multiple virtual channels;

The macro instruction sending module 1703 is used to send the macro instructions sent by the multiple processors to the macro instruction parsing engine in sequence according to the priorities of the multiple virtual channels.

In summary, in the scheme shown in the embodiment of the present application, the processor sends a macro instruction to the DMA system, which is used to instruct the transport of multi-dimensional structure data; the macro instruction controller in the DMA system sends the macro instruction to the macro instruction parsing engine; the macro instruction parsing engine parses the macro instruction into a micro operation code for instructing the transport of one-dimensional structure data in the multi-dimensional structure data, and sends it to the data read and write transmission path, and the data read and write transmission path executes the relocation of the one-dimensional structure data according to the micro operation code. In the above scheme, the processor directly instructs the DMA system to transport the multi-dimensional structure data, and then the macro instruction parsing engine in the DMA system disassembles the transport operation of the multi-dimensional structure data into multiple transport operations of one-dimensional structure data. Since the speed at which the DMA system performs the analysis of the macro instruction is much faster than the speed at which the processor disassembles the transport operation of the multi-dimensional structure data, the above DMA system can greatly reduce the time required for the processor to generate instructions for transporting one-dimensional structure data, thereby improving the efficiency of data transport.

An embodiment of the present application further provides a computer device, which includes a direct memory access system as shown in any one of FIG. 5 , FIG. 7 , FIG. 8 and FIG. 14 .

The embodiment of the present application further provides a chip, which includes the direct memory access system shown in any one of Figures 5, 7, 8 and 14. The chip can be a chip other than a processor for executing a direct memory access process, for example, the chip can be implemented as a DMA controller, or the chip can include one or more DMA controllers; the DMA controller includes the direct memory access system shown in any one of Figures 5, 7, 8 and 14.

An embodiment of the present application further provides a computer device, which may include the above chip, and the chip includes the direct memory access system shown in any one of Figures 5, 7, 8 and 14.

An embodiment of the present application also provides a computer-readable storage medium, in which at least one program is stored, and the at least one program is loaded and executed by a controller to implement the above-mentioned data transfer method; the controller is a macro instruction controller in the direct memory access system shown in any of the above-mentioned Figures 5, 7, 8 and 14.

Optionally, the computer readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a solid state drive (SSD) or an optical disk, etc. Among them, the random access memory may include a resistance random access memory (ReRAM) and a dynamic random access memory (DRAM). The serial numbers of the above embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned data transfer method when the computer program is executed by a controller; the controller can be a macro instruction controller in the direct memory access system shown in any of the above-mentioned Figures 5, 7, 8 and 14.

Claims (19)

A direct memory access system, characterized in that the system comprises: a macro instruction memory, a macro instruction controller, a macro instruction parsing engine and a data read and write transmission path; The macro instruction memory and the macro instruction controller are respectively connected to a processor in a computer device, and the macro instruction memory is connected to the macro instruction controller; The macro instruction controller is connected to the macro instruction parsing engine, the macro instruction parsing engine is connected to the data reading and writing transmission path, and the data reading and writing transmission path is connected to the bus of the computer device; The macro instruction memory is used to store the macro instructions issued by the processor; the macro instructions are used to instruct the transport of multi-dimensional structure data; The macro instruction controller is used to receive the trigger instruction sent by the processor, read the macro instruction from the macro instruction memory according to the trigger instruction, and send the macro instruction to the macro instruction parsing engine; The macro instruction parsing engine is used to parse the macro instruction into a micro operation code and send the micro operation code to the data read and write transmission path; the micro operation code is used to instruct the transfer of one-dimensional structure data in the multi-dimensional structure data; The data read/write transmission path is used to read and write the one-dimensional structure data to the bus according to the micro-operation code. The system according to claim 1, characterized in that the data read and write transmission path comprises a plurality of processing units, the plurality of processing units at least comprising a read data interface unit, a cache unit and a write data interface unit; The macro instruction parsing engine is connected to the read data interface unit, and the macro instruction parsing engine is used to send the micro operation code to the read data interface unit; The micro-operation code is used to be transmitted sequentially among the multiple processing units. The system according to claim 1 or 2, characterized in that the macroinstruction parsing engine is used to parse the macroinstruction into micro-operation code. Parsing the data structure of the multi-dimensional structure data to determine the read and write address and data size of the one-dimensional structure data in the multi-dimensional structure data; The micro-operation code is generated according to the read and write addresses and data size of the one-dimensional structure data. The system according to any one of claims 1 to 3, characterized in that the macro instruction is also used to instruct to perform format conversion processing on the multi-dimensional structure data, and the micro operation code is also used to instruct to perform format conversion processing on the one-dimensional structure data; The multiple processing units further include at least one of a pre-format conversion processing unit and a post-format conversion processing unit, wherein the pre-format conversion processing unit is located before the cache unit, and the post-format conversion processing unit is located after the cache unit; The format conversion pre-processing unit is used to perform format conversion pre-processing on the one-dimensional structure data according to the processing mode of the format conversion processing indicated by the micro-operation code, and write the result data of the format conversion pre-processing into the cache unit; The format conversion post-processing unit is used to perform format conversion post-processing on the data in the cache unit according to the format conversion processing processing mode indicated by the micro-operation code, and then send it to the next processing unit. The system according to any one of claims 1 to 4, characterized in that the macro instruction includes a first format conversion configuration, and the first format conversion configuration is a configuration for performing format conversion on the multi-dimensional structure data; The macro instruction parsing engine is used to generate a second format conversion configuration according to the first format conversion configuration when generating the micro operation code according to the read and write addresses and data size of the one-dimensional structure data, wherein the second format conversion configuration is a configuration for performing format conversion on the one-dimensional structure data; The micro-operation code is generated according to the read and write addresses, data size, and the second format conversion configuration of the one-dimensional structure data. The system according to any one of claims 1 to 5, characterized in that the macro instruction is also used to instruct to perform arithmetic processing on the multi-dimensional structure data, and the micro operation code is also used to instruct to perform arithmetic processing on the one-dimensional structure data; The multiple processing units also include a data computing unit; The data operation unit is used to perform operation processing on the input data according to the operation processing mode indicated by the micro-operation code, and then send it to the next processing unit. The system according to any one of claims 1 to 6 is characterized in that the macro instruction and the micro operation code respectively include operation configurations, and the operation configurations are configurations of the operation processing. The system according to any one of claims 1 to 7, characterized in that the macro instruction and the micro operation code further include a synchronization configuration, the synchronization configuration is used to instruct to perform a status check on a target address, the target address is at least one of a read address and a write address of data; The macroinstruction controller is used to check the state of the target address according to the synchronization configuration in the macroinstruction when sending the macroinstruction to the macroinstruction parsing engine, and send the macroinstruction to the macroinstruction parsing engine when the state of the target address meets a specified condition; the specified condition includes: when the target address includes a read address, the state of the read address is readable; when the target address includes a write address, the state of the write address is writable; The read data interface unit is used to read the one-dimensional structure data from the read address when the target address includes the read address and the state of the read address is readable; The write data interface unit is used to write data to the write address when the target address includes the write address and the state of the write address is writable. The system according to any one of claims 1 to 8, characterized in that The macroinstruction controller is used to receive macroinstructions respectively sent by multiple processors through multiple virtual channels, and send the macroinstructions respectively sent by the multiple processors to the macroinstruction parsing engine in sequence according to the priorities of the multiple virtual channels. A data handling method, characterized in that the method is used in a direct memory access system as shown in any one of claims 1 to 9, and the method is executed by a macro instruction controller in the direct memory access system, and the method comprises: Receive the trigger instruction sent by the processor; Reading the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used to instruct the transport of multi-dimensional structure data; The macroinstruction is sent to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code, and the micro-operation code is sent to a data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to a bus according to the micro-operation code; the micro-operation code is used to indicate the movement of the one-dimensional structure data in the multi-dimensional structure data. The method according to claim 10, characterized in that the data read and write transmission path comprises a plurality of processing units, and the plurality of processing units at least comprises a read data interface unit, a cache unit and a write data interface unit; The macro instruction parsing engine is connected to the read data interface unit, and the macro instruction parsing engine is used to send the micro operation code to the read data interface unit; The micro-operation code is used to be transmitted sequentially among the multiple processing units. The method according to claim 10 or 11, characterized in that the macro instruction and the micro operation code further include a synchronization configuration, the synchronization configuration is used to instruct to perform a status check on a target address, the target address is at least one of a read address and a write address of data; The step of sending the macro instruction to the macro instruction parsing engine includes: checking the status of the target address according to the synchronization configuration; When the state of the target address satisfies a specified condition, sending the macro instruction to the macro instruction parsing engine; The specified conditions include: When the target address includes a read address, the state of the read address is readable; When the target address includes a write address, the state of the write address is writable. A data handling device, characterized in that the device is used as a macro instruction controller in a direct memory access system as shown in any one of claims 1 to 9, and the device comprises: A trigger instruction receiving module, used to receive a trigger instruction sent by a processor; A macro instruction reading module, used for reading the macro instruction from the macro instruction storage according to the trigger instruction; the macro instruction is used for instructing the transport of multi-dimensional structure data; A macroinstruction sending module is used to send the macroinstruction to a macroinstruction parsing engine so that the macroinstruction parsing engine parses the macroinstruction into a micro-operation code and sends the micro-operation code to a data read and write transmission path, and the data read and write transmission path reads and writes one-dimensional structure data to a bus according to the micro-operation code; the micro-operation code is used to indicate the transfer of the one-dimensional structure data in the multi-dimensional structure data. The device according to claim 13, characterized in that the data read and write transmission path comprises a plurality of processing units, the plurality of processing units at least comprising a read data interface unit, a cache unit and a write data interface unit; The macro instruction parsing engine is connected to the read data interface unit, and the macro instruction parsing engine is used to send the micro operation code to the read data interface unit; The micro-operation code is used to be transmitted sequentially among the multiple processing units. The device according to claim 13 or 14, characterized in that the macro instruction and the micro operation code further include a synchronization configuration, the synchronization configuration is used to instruct to perform a status check on a target address, the target address is at least one of a read address and a write address of data; The macro instruction sending module is used to check the state of the target address according to the synchronization configuration; when the state of the target address meets the specified condition, send the macro instruction to the macro instruction parsing engine; The specified conditions include: When the target address includes a read address, the state of the read address is readable; When the target address includes a write address, the state of the write address is writable. A computer device, characterized in that the computer device comprises the direct memory access system according to any one of claims 1 to 9. A computer-readable storage medium, characterized in that at least one program is stored in the storage medium, and the at least one program is loaded and executed by a controller to implement the data transfer method as described in any one of claims 10 to 12; the controller is a macro instruction controller in the direct memory access system as described in any one of claims 1 to 9. A chip, characterized in that the chip comprises the direct memory access system as described in any one of claims 1 to 9. A computer device, characterized in that the computer device comprises the chip as claimed in claim 18.