WO2025052366A1

WO2025052366A1 - A method for multiple passivation approach in p-gan gate e-mode hemts

Info

Publication number: WO2025052366A1
Application number: PCT/IB2024/060969
Authority: WO
Inventors: Rasik Rashid Malik; Mayank Shrivastava
Original assignee: Indian Institute of Science IISC
Current assignee: Indian Institute of Science IISC
Priority date: 2023-09-06
Filing date: 2024-11-06
Publication date: 2025-03-13
Anticipated expiration: 2026-03-06

Abstract

A semiconductor device 100 and a method 200 for multiple passivation approach in p-GaN gate e-mode HEMTs is provided. The device 100 includes a gallium nitride (GaN) layer 111 formed on a first barrier layer 103, a metal layer 105 formed on the GaN layer 111, and one or more dielectric layers 600. The second barrier layer 104 is of aluminum Nitride (AIN), and the first barrier layer 103 is of aluminum gallium nitride (AlGaN). The second dielectric layer 600-2 can be of AlyTiyO, and the first dielectric layer 600-1 and the third dielectric layer 600-3 can be made of SiOx. The device 100 can further include a source contact 107 and a drain contact 108, a first passivation layer 601, and any one or a combination of a source field plate 112, a spacer 113, a drain field plate 114, and a gate field plate 115.

Description

A METHOD FOR MULTIPLE PASSIVATION APPROACH IN P-GAN

GATE E-MODE HEMTS

FIELD OF INVENTION

[0001] The present invention pertains to semiconductor devices. In particular, the present invention relates to a method and a system for multiple passivation approach in p-GaN Gate e-mode high electron mobility transistors (HEMTs) for enhancing performance and reliability of p-GaN gate AlGaN/GaN devices specifically through multiple (dual and triple) passivation approach.

BACKGROUND

[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.

[0003] M. J. Scott et al., 2013, in their paper, disclosed that in power switch applications, normally-OFF high electron mobility transistors (HEMTs) are essential for ensuring safety. G. Greco et al., 2018, in their paper, disclosed that these devices, particularly p-GaN gate HEMTs, which elevate the conduction band, are seen as a promising solution. However, A. Stockman et al., 2018, in their paper, disclosed that despite their potential, there are still challenges that need to be addressed in order to improve the performance of p-GaN gate HEMTs.

[0004] One of the main issues is the high gate leakage current, both in the forward and reverse directions. N. Xu et al., 2018, in their paper, disclosed that high forward gate leakage current restricts the gate voltage swing and leads to drive losses, while the reverse leakage can cause OFF-state power consumption. Furthermore, A. Stockman et al., 2018, in their paper, disclosed that it is known that higher gate leakage can limit the device's lifespan. M. Meneghini et al., 2017, and S. Stoffels et al., 2019, in their paper disclosed that gate degradation in p-GaN gate HEMTs can be attributed to either sidewall conduction or an avalanche multiplication near the Schottky metal's depletion region. The sidewall conduction acts as a parasitic leakage path, which can lead to the premature breakdown of the gate stack.

[0005] Another challenge is the need to improve the breakdown voltage (BV) of the gate in the p-GaN gate HEMTs. Higher BV is crucial for ensuring the reliability and robustness of the devices, particularly in high-power applications. Enhancing the BV of the gate is essential to prevent excessive leakage and breakdown, which can result in device failure and reduced performance.

[0006] Various techniques, such as buffer engineering through doping control, multilayer buffer stacks, buffer-free stacks, Al(Ga)N back barriers, and surface passivation techniques like GaN cap layers or in-situ passivation, have been proposed in the past to address increase in ON resistance (dynamic RON), a critical issue limiting the device performance and reliability. However, the p-GaN gated devices, which offer efficient normally OFF operation with HEMT architecture, present another challenge in controlling dynamic RON- This primarily arises from the fact that p-GaN needs to be etched from the gate-drain and gatesource access region. The etching process introduces traps on the AlGaN surface, making it very sensitive to the etching process. Furthermore, this also necessitates an ex-situ passivation, making development of a passivation scheme to passivate surface traps of paramount importance.

[0007] There is, therefore, a need for a method and a system for multiple passivation approach in p-GaN Gate e-mode HEMTs that can effectively reduce gate leakage current, improve BV, suppresses dynamic ON resistance and enhance the overall performance and reliability of the p-GaN gate HEMTs.

SUMMARY

[0008] Within the scope of this application, it is expressly envisaged that the various aspects, embodiments, examples, and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. Features described in connection with one embodiment are applicable to all embodiments, unless such features are incompatible.

[0009] The present invention provides a dual and triple passivation approach in p-GaN sidewall and access region in p-GaN gate AlGaN/GaN devices. This approach aims to enhance the performance and reliability of these devices.

[0010] In an aspect, the present invention provides a bilayer access region passivation scheme using a SiCMAITiO stack. This scheme demonstrates improved electric field distribution and breakdown performance, while also suppressing dynamic RON instability.

[0011] In another aspect, the present invention provides a triple passivation scheme including the steps of- a) carrying out SiCU passivation with an O2 flow rate of 7.2 seem to enhance gate performance and stability; b) carrying out S i O 2 passivation with a charge profile corresponding to an O2 flow rate of 9.8 seem to enhance the overall breakdown voltage and RON performance; and c) carrying out the bilayer access region passivation scheme (SiCMAITiO) to improve the dielectric breakdown strength and electric field distribution.

[0012] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated herein, and constitute a part of this invention, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that the invention of such drawings includes the invention of electrical components, electronic components or circuitry commonly used to implement such components.

[0014] FIG. 1A illustrates an exemplary block diagram of a semiconductor device with a triple passivation scheme, in accordance with an embodiment of the present disclosure.

[0015] FIG. IB illustrates an exemplary representation of a) a flow chart representing a fabrication process steps for HEMT fabrication, and b) a schematic of a system cross-section with a triple passivation scheme, in accordance with an embodiment of the present disclosure. [0016] FIGs. 2 (a-c) illustrates an exemplary representation the electric field distribution in p-GaN as a function of sidewall surface (SS) donors, in accordance with an embodiment of the present disclosure.

[0017] FIGs. 3 (a-c) illustrates a) the impact of O2 flow rate on capacitance-voltage characteristics of SiOx/p-Si MOS test structures, b) gate leakage characteristics at VDS=0V, and c) distribution of ON-state gate leakage for fixed gate voltage and maximum gate overdrive voltage, in accordance with an embodiment of the present disclosure.

[0018] FIGs. 4 (a-c) illustrates an exemplary representation of a) EL intensity distribution under semi-ON conditions with (IDS ~ 2mA, VDS ~ 100V) of SiO2/AlTiO systems, revealing an electric field peak at the gate edge for an O2 flow rate of 4.8 seem and distributed electric field for passivations at 7.2sccm and 9.8sccm, b) comparison of VBR- QN among different access region passivations demonstrates improved breakdown performance with bilayer passivation, and c) the dynamic increase in RON ( RQN) post-off-state stress was found to be suppressed with AlTiO integration due to improved channel distribution, in accordance with an embodiment of the present disclosure.

[0019] FIGs. 5 (a-c) illustrates an exemplary representation of the 02 flow rate variation results in the SiO$_X$ passivation stoichiometry, which was confirmed through XPS analysis, in accordance with an embodiment of the present disclosure.

[0020] FIGs. 6 (a-b) illustrates an exemplary representation of the non-stoichiometric single-layer passivation is able to suppress dynamic Ron (a), and AlTiO integrated on stoichiometric passivation results in the improved dynamic Ron (b), in accordance with an embodiment of the present disclosure.

[0021] FIGs. 7 (a-c) illustrates an exemplary representation of the design variations that includes the GaN layer (111) may be of p-type Gallium Nitride (p-GaN), p-type oxide, crystalline, or amorphous form (a), the semiconductor device that include a dielectric layer (instead of GaN layer 111), SiN, A12O2, TiO2, AlTiO or any combination thereof, amorphous or crystalline form (b), the semiconductor device that exclude the GaN layer 111 (c), in accordance with an embodiment of the present disclosure.

[0022] FIG. 8 illustrates an exemplary representation of the design variation of the semiconductor device that includes the metal layer may not be fully extended to the p-GaN layer 111 comers and spacer disposed in those gaps (or gaps may be empty), in accordance with an embodiment of the present disclosure.

[0023] FIGs. 9 (a-c) illustrates an exemplary representation of the field plate design variations of the semiconductor device which connected to source (a), or connected to gate (b), or connected to drain electrode (c) (or may be combination of three of these design variations, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0024] The following is a detailed description of embodiments of the present invention. The embodiments are in such detail as to clearly communicate the invention. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

[0025] Unless the context requires otherwise, throughout the specification which follow, the word “comprise” and variations thereof, such as, “comprises” and “comprising” are to be construed in an open, inclusive sense that is as “including, but not limited to.”

[0026] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0027] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

[0028] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein.

[0029] All methods described herein can be performed in suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

[0030] The headings and abstract of the invention provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0031] Various terms are used herein. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.

[0032] It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the fiinctionality/acts involved.

[0033] The present invention provides a dual and triple passivation approach in p-GaN sidewall and access region in p-GaN gate AlGaN/GaN devices. This approach aims to enhance the performance and reliability of these devices.

[0034] FIG. 1A illustrates exemplary block diagram 100A of a semiconductor device 100 with a triple passivation scheme, in accordance with an embodiment of the present disclosure. [0035] In a first embodiment of the present invention, a semiconductor device 100 is disclosed. The device includes one or more dielectric layers 600, wherein a first dielectric layer 600-1 is adapted to cover a gallium nitride (GaN) layer and disposed on a first barrier layer 103, and a second dielectric layer 600-2 is disposed on the first dielectric layer 600-1. The gallium nitride (GaN) layer 111 is at least partially covered by a third dielectric layer 600-3 and disposed on a portion 103-1 of the first barrier layer 103, and the third dielectric layer 600-3 forms a part of the first dielectric layer 600-1.

[0036] In an exemplary implementation of the first embodiment, the present invention provides a bilayer access region passivation scheme using a SiCMAITiO stack. This scheme demonstrates improved electric field distribution and breakdown performance, while also suppressing dynamic RON instability.

[0037] In the exemplary implementation of the first embodiment, the semiconductor device 100 can be a high-electron-mobility transistor (HEMT) structure based on Gallium Nitride (GaN) on Silicon (Si) technology. The device can include a substrate 101 having 650V class GaN, a buffer layer 106 of gallium nitride (GaN) formed on the substrate 101, a channel layer 102 of unintentionally doped (UID) GaN formed on the buffer layer 106, a two- dimensional electron gas (2D EG) region 110 formed at the interface between a first barrier layer 103 and the channel layer 102, a second barrier layer 104 of aluminum Nitride (AIN) formed on the channel layer 102, and a first barrier layer 103 of aluminum gallium nitride (AlGaN) formed on the second barrier layer 104. The gallium nitride (GaN) layer 111 can be formed on the first barrier layer 103, and a metal layer 105 of Titanium or Titanium Nitride (Ti/TiN) can be formed on the GaN layer 111.

[0038] In the exemplary implementation of the first embodiment, the substrate 101 may be made of GaN on Si, AI2O3, Sapphire, or QST.

[0039] In the exemplary implementation of the first embodiment, the GaN layer 111 can be of p-type Gallium Nitride (p-GaN), p-type oxide, crystalline, or amorphous form, or a dielectric such as SiN, A12O2, TiO2, AlTiO or any combination thereof, amorphous or crystalline form. The dielectric layer can be of SiO2, A12O3, AlTiO, TiO2 or AIN, A1ON, amorphous or crystalline. The metal layer 105 can be formed on the GaN layer 111. The second dielectric layer 600-2 can be of AlyTiyO, and the first dielectric layer 600-1 and the third dielectric layer 600-3 can be made of SiOx. [0040] In the exemplary implementation of the first embodiment, the first dielectric layer (600-1) and the third dielectric layer is not used in the semiconductor device 100

[0041] In the exemplary implementation of the first embodiment, the semiconductor device (100) includes the metal layer (105) is directly disposed on the first barrier layer (103), the second dielectric layer (600-2) is of Al_yTi_yO, and the first dielectric layer (600-1) and the third dielectric layer is not used.

[0042] In the exemplary implementation of the first embodiment, the metal layer 105 can be disposed on the first barrier layer 103, and the metal layer 105 can be of Ti, TiN, Ti/TiN, Sc, Ta, W, Ti/Al, or Ni/Au. The second dielectric layer 600-2 can be of AlyTiyO. The first dielectric layer 600-1 and the third dielectric layer 600-3 can be made of SiOx.

In the exemplary implementation of the first embodiment, the semiconductor device 100 can further include a source contact 107 and a drain contact 108 formed on the channel layer 102, configured to facilitate current flow across the 2DEG region 110 under an applied voltage. The first passivation layer 601 can operate as a gate insulator, providing electrical isolation between the gate stack 105 the source contact 107, and the drain contact 108. The device can also include any one or a combination of a source field plate 112, a spacer 113, a drain field plate 114, and a gate field plate 115.

[0043] In the exemplary implementation of the first embodiment, the pre -determined flow rate of oxygen in the first passivation layer/ first dielectric layer 600-1 can be greater than 6 seem, and the pre-determined flow rate of oxygen in the third side-wall passivation layer/ a third die-electric layer 600-3 can be less than 6 seem. The second passivation layer i.e second dielectric layer 600-2 can be based on the alloyed oxide of A12O3 and TiO2 in a predefined ratio (1:2 to 1:20) to get AlTiO.

[0044] In the exemplary implementation of the first embodiment, the first passivation layer can be close to non-stoichiometric si-rich oxide with predefined stoichiometry (SiO1.2- SiO1.6), the third passivation layer can be close to stoichiometric oxide with predefined stoichiometry (SiO1.6- SiO2), and the second passivation layer can have a stoichiometry AlyTil-yO where y = 0.1-0.9.

[0045] In the exemplary implementation of the first embodiment, channel layer 102 can have a thickness of between 170-180 nanometers (nm), the second barrier layer 103 can have a thickness of between 0.5-1.5 nanometers (nm), the first barrier layer 104 can have a thickness of between 11-13 nanometers (nm), the GaN layer 111 can have a thickness of between 75-85 nanometers (nm), the buffer layer 106 can have a thickness of between 4.5-5.5 micrometers (mm), the first dielectric layer 600-1 can have a thickness of between 95-105 nanometers (nm), and the second dielectric layer 600-2 can have a thickness of between 9-11 nanometers (nm).

[0046] In a second embodiment of the present invention, the present invention provides a triple passivation scheme including the steps of: a) carrying out SiO₂ sidewall passivation with an O₂ flow rate of 7.2 seem to enhance gate performance and stability; b) carrying out SiO₂ passivation in the access region with a charge profde corresponding to an O₂ flow rate of 9.8 seem to enhance the overall breakdown voltage and RON performance; and c) carrying out the bilayer access region passivation scheme (SiO₂/AlTiO) to improve the dielectric breakdown strength and electric field distribution.

[0047] In a third embodiment of the present invention, the optimization of sidewall and access region passivation schemes, along with the introduction of a bilayer access region passivation scheme, results in improved gate performance, stability, field distribution, breakdown strength, and RON performance.

[0048] In a fourth embodiment of the present invention, the present invention provides a system for enhancing the performance and reliability of p-GaN gate HEMTs. The system includes a commercial grade 600V E-mode GaN-on-Si wafer for system fabrication; a Ti/TiN gate metal deposited by sputtering, serving as the gate; a self-align p-GaN etching process to define the p-GaN cap in the gate region; an O₂/C1₂/N₂ based plasma chemistry for etching the p-GaN, ensuring precise self-termination at the AlGaN surface; MESA isolation using C1₂/BC13 chemistry; and source(s)/drain(D) ohmic contact formation using Ti(20nm)/Al(120nm)/Ni(30nm)/Au(50nm) annealed at 800°C for 30 seconds in N₂.

[0049] In a fifth embodiment of the present invention, the method 200 and device 100 for multiple passivation approach in p-GaN Gate e-mode HEMTs is disclosed. The innovative approach employed in the fabrication process helps to significantly reduce gate leakage current in p-GaN gate HEMTs. This reduction in leakage current allows for improved gate voltage swing and minimizes drive losses, resulting in enhanced system performance. The invention addresses the challenge of enhancing the BV of the gate in p-GaN gate HEMTs. By implementing the proposed fabrication process, the BV of the gate is improved, thereby ensuring the reliability and robustness of the systems, especially in high-power applications. The combination of reduced gate leakage current and improved BV leads to enhanced overall system performance. The system fabricated using this invention exhibits improved gate control, reduced power losses, and increased efficiency, making them suitable for a wide range of power switch applications. The reduction in gate leakage current and improved BV contribute to extending the lifespan of p-GaN gate HEMTs. By mitigating the factors that contribute to gate degradation, such as sidewall conduction and premature breakdown of the gate stack, the system can operate reliably over an extended period of time. The passivation technique employed in the fabrication process plays a crucial role in enhancing system reliability. The bilayer SiCMAIxTi 1 -xO/passivation with a controlled charge profde effectively reduces gate leakage and protects against potential system failures, ensuring longterm reliability and stable operation. The proposed fabrication process utilizes commercially available materials and standard techniques, making it cost-effective for large-scale production. By incorporating the process into existing manufacturing infrastructure, the invention enables the mass production of p-GaN gate HEMTs with improved performance and reliability. The advantages offered by this invention make p-GaN gate HEMTs suitable for various applications, including power electronics, renewable energy systems, electric vehicles, and more. The improved performance and reliability of these systems contribute to the advancement and efficiency of these industries.

[0050] In a sixth embodiment of the present invention, the system also includes a bilayer SiCMAIxTi 1-xO/passivation with x = 0.5 for passivating the systems; SiCh deposition using the C>2/SiH4-based ICP-CVD deposition technique; variation of O2 flow rate to control the charge profile of passivation; opening of the passivation in the S/D and gate pad region; and metal thickening using a Ti/Al/Ni/Au stack.

[0051] In a seventh embodiment of the present invention, the GaN-on-Si wafer provides a suitable substrate 101 for fabricating p-GaN gate HEMTs. GaN-on-Si technology involves depositing a layer of gallium nitride on a substrate 101, combining the desirable properties of both materials. Gallium nitride is known for its excellent electronic properties, such as high electron mobility and high breakdown voltage, making it an ideal material for high- performance electronic systems like HEMTs. Silicon, on the other hand, is widely used in the semiconductor industry, offering cost-effective and large-scale manufacturing capabilities. By utilizing the GaN-on-Si wafer as the substrate, the fabrication process for p-GaN gate HEMTs can benefit from the advantages of both materials. The GaN layer provides the desired electronic properties necessary for high-performance systems, while the substrate 101 offers a well-established platform for semiconductor manufacturing. The GaN layer on the substrate allows for the growth of p-GaN layers and subsequent system fabrication processes. This combination enables the integration of p-GaN gate HEMTs with existing silicon-based technologies, facilitating the development of power switch applications with enhanced performance and reliability.

[0052] In an exemplary implementation of the seventh embodiment, the self-align p-GaN etching process ensures a precise definition of the p-GaN cap in the gate region, enhancing the gate control of the system. In the fabrication process of p-GaN gate HEMTs, it is crucial to accurately define the p-GaN cap, which acts as the gate region of the system. The selfalign p-GaN etching process refers to a technique that allows for precise and controlled etching of the p-GaN layer, ensuring the formation of a well-defined and uniform p-GaN cap. The self-align aspect of the etching process means that the etching automatically stops at a specific point, precisely at the AlGaN surface. This self-termination is achieved by utilizing an O2/C12/N2-based plasma chemistry, which carefully controls the etching process. This ensures that only the desired region, i.e., the p-GaN cap, is etched, while other areas remain unaffected. By achieving this precise and self-aligned etching of the p-GaN cap, the gate control of the system is significantly enhanced. The well-defined p-GaN cap allows for better control over the flow of current through the system, enabling more efficient switching operations and improved performance. The enhanced gate control obtained through the self- align p-GaN etching process contributes to minimizing gate leakage current, reducing power losses, and improving the overall efficiency of the p-GaN gate HEMTs. It also helps to ensure the reliability and stability of the system, as the precise definition of the p-GaN cap reduces the possibility of parasitic effects or unintended current leakage.

[0053] In the exemplary implementation of the seventh embodiment, the MESA isolation using CI2/BCI3 chemistry provides effective isolation between adjacent systems, reducing parasitic effects and enhancing system performance. The MESA isolation is a method used to electrically separate adjacent devices on a semiconductor wafer. In this case, the isolation is achieved using Q2/BCI3 chemistry, which refers to the use of chlorine (Ch) and boron trichloride (BCI3) as reactive gases during the etching process. The CI2/BCI3 chemistry is carefully designed to selectively etch away the unwanted material, leaving behind isolated mesa structures. These mesa structures act as physical barriers, preventing electrical interaction between adjacent devices. The effective isolation provided by the MESA isolation technique has several advantages for p-GaN gate HEMTs. It reduces parasitic effects, which can occur due to unwanted electrical coupling between neighboring devices. Parasitic effects can lead to undesirable phenomena such as cross-talk, increased noise, and reduced device performance. By implementing MESA isolation, these parasitic effects are minimized, allowing each device to operate independently and without interference. The MESA isolation technique enhances system performance by reducing leakage currents and improving the device's ability to handle high voltages. The isolation barriers created by the mesa structures prevent leakage currents from flowing between adjacent devices, improving the overall efficiency and reliability of the system. Additionally, MESA isolation using C12/BC13 chemistry provides a robust and stable isolation method. The selective etching process ensures that only the desired regions are etched, leaving the rest of the device unaffected. This contributes to the preservation of the system’s integrity and prevents any unintended damage during the isolation process.

[0054] In an eighth embodiment of the present invention, the source(s)/drain(D) ohmic contact formation using Ti/Al/Ni/Au stack ensures low contact resistance and efficient current flow in the system. In p-GaN gate HEMTs, achieving low contact resistance is crucial for efficient current flow and optimal device performance. The Ti/Al/Ni/Au stack is employed as the material combination for forming the ohmic contacts due to its favorable electrical and mechanical properties. The Ti layer serves as an adhesion layer, ensuring good bonding between the semiconductor material (p-GaN) and the subsequent layers. It also acts as a diffusion barrier, preventing the intermixing of different materials and maintaining the integrity of the contact. The Al layer is the primary conductive layer in the stack, responsible for providing low resistance electrical connections. Aluminum has excellent conductivity and forms a reliable electrical contact with p-GaN, allowing for efficient current flow between the source/drain regions and the metal electrodes. The Ni layer serves as a barrier layer, preventing the diffusion of aluminum into the subsequent gold (Au) layer. This prevents any potential reaction or degradation of the gold layer, ensuring the long-term stability and reliability of the contacts. Finally, the Au layer is used as a top layer in the stack, providing excellent electrical conductivity and good resistance against oxidation. Gold is known for its low contact resistance and stable electrical properties, making it an ideal material for ensuring efficient current flow and minimizing power losses. By utilizing the Ti/Al/Ni/Au stack for source/drain ohmic contact formation, the p-GaN gate HEMTs achieve low contact resistance. This low resistance facilitates efficient current flow, reducing power losses and improving overall system performance. Additionally, the use of this specific stack ensures the stability and reliability of the contacts over an extended period of operation.

[0055] In an ninth embodiment of the present invention, the bilayer SiCMAlxTi l - xO/passivation with x = 0.52 provides effective passivation, reducing gate leakage and enhancing the reliability of the system. Passivation is a process that involves the deposition of a thin layer of material on the surface of a device to protect it from environmental factors and improve its electrical performance. In this case, a bilayer passivation structure is employed, consisting of SiO₂ (silicon dioxide) and AlxTil-xO (aluminum titanium oxide) with a specific aluminum composition of x = 0.5. The SiO₂ layer acts as the bottom layer of the passivation structure. SiO₂ is an insulating material that provides electrical isolation and protects the underlying device from moisture, contaminants, and other environmental factors. It also helps to reduce surface imperfections and traps that can cause gate leakage or unwanted current flow. The AlxTil-xO layer, with a specific composition of x = 0.52, is the top layer of the passivation structure. This layer is specifically designed to provide effective passivation and reduce gate leakage. The aluminum titanium oxide layer helps to create a barrier between the gate electrode and the surrounding environment, preventing the ingress of moisture and other contaminants that could affect the system’s performance. The bilayer passivation structure of SiCMAlxTi 1 -xO provides effective passivation by combining the insulating properties of SiO₂ and the barrier properties of AlxTil-xO. This combination reduces gate leakage, which refers to the undesired current flow between the gate electrode and other parts of the device. By minimizing gate leakage, the passivation structure enhances the reliability and performance of the p-GaN gate HEMTs. In addition to reducing gate leakage, the SiO₂/AlxTil-xO passivation structure also helps to improve the long-term stability and reliability of the device. It protects the underlying materials from degradation caused by environmental factors such as moisture, temperature variations, and chemical reactions.

[0056] In an exemplary implementation of the eighth embodiment, the variation of O₂ flow rate during SiO₂ deposition allows control over the charge profde of passivation, optimizing system performance. During the deposition of SiO₂, the flow rate of O₂ can be controlled to modify the properties of the passivation layer. The passivation layer plays a critical role in protecting the underlying system and improving its electrical performance. By varying the O₂ flow rate, it is possible to control the amount of oxygen incorporated into the SiO₂ layer. Oxygen atoms can introduce charges into the passivation layer, affecting its electrical properties. These charges can influence the behavior of the passivation layer, such as its ability to trap or release charges, its dielectric constant, and its interface properties. The ability to control the charge profde of the passivation layer through the O₂ flow rate variation allows for optimization of system performance. By adjusting the O₂ flow rate, it is possible to tailor the passivation layer to meet specific requirements and improve the overall performance of the system. For example, in certain applications, it may be desirable to reduce the presence of interface traps, which can negatively impact device performance. By carefully adjusting the O₂ flow rate, it is possible to minimize the creation of interface traps and enhance the interface properties of the passivation layer. Furthermore, the charge profile of the passivation layer can also influence other factors such as the breakdown voltage, leakage current, and reliability of the device. By controlling the O2 flow rate, the charge profile can be optimized to achieve the desired electrical characteristics, ensuring stable and efficient operation of the system.

[0057] In a ninth embodiment of the present invention, the metal thickening using the Ti/Al/Ni/Au stack provides improved conductivity and durability of the system’s metal components. The thickening of the metal layers in the system is beneficial for several reasons as it improves conductivity by reducing resistance. Thicker metal layers offer lower resistance to the flow of electrical current, allowing for more efficient transmission of signals and power throughout the system. This can enhance the overall performance of the device, especially in high-frequency applications where low resistance is crucial.

EXAMPLES

[0058] The present invention is further explained in the form of the following examples. However, it is to be understood that the foregoing examples are merely illustrative and are not to be taken as limitations upon the scope of the invention. Various changes and modifications to the disclosed embodiments will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the scope of the invention.

Example 1

System Fabrication

[0059] Systems or devices for this study were fabricated on a commercial grade 600V E- mode GaN-on-Si wafer. FIG. IB illustrates the process flow and cross-sectional schematic of the devices. Sputtered Ti/TiN gate metal was used as a gate, and later self-align p-GaN etching was performed to define the p-GaN cap in the gate region. The p-GaN was etched using an CMCL/^-bascd plasma chemistry, which ensures precise self-termination of the etching process at the AlGaN surface. The process was followed by MESA isolation using Q2/BCI3 chemistry and the source(s)/drain(D) ohmic contact formation using Ti(20nm)/Al(120nm)/Ni(30nm)/Au(50nm) annealed at 800°C 30 seconds in N2. The devices were passivated by bilayer SiO₂/AlxTi 1 -xO/passivation with x = 0.52. SiC>2 was deposited using the Oi/SiEU -based ICP-CVD deposition technique, with parameters given in Table 1, and the O2 flow rate was varied to control the charge profile of passivation. The passivation was opened in the S/D and gate pad region, followed by metal thickening using Ti/Al/Ni/Au stack. [0060] FIG. IB illustrates an exemplary representation 100B of a) a flow chart representing a fabrication process steps for HEMT fabrication, and b) a schematic of a system cross-section with a triple passivation scheme, in accordance with an embodiment of the present disclosure.

[0061] Referring to FIG. 1 b), the method of fabricating the semiconductor device 100 is disclosed. The method includes the steps of - forming a buffer layer 106 of gallium nitride (GaN) on a substrate 101, forming a channel layer 102 of unintentionally doped (UID) GaN on the buffer layer 106, creating a two-dimensional electron gas (2DEG) region 110 at the interface between a second barrier layer 104 and the channel layer 102, forming the second barrier layer 104 of aluminum Nitride (AIN) formed on the channel layer 102, forming a first barrier layer 103 of aluminum gallium nitride (AlGaN) formed on the second barrier layer 104, forming a Gallium Nitride (GaN) layer 111 on the first barrier layer 103, and forming a metal layer 105 of Titanium or Titanium Nitride (Ti/TiN) on the GaN layer 111.

[0062] In these embodiments, the semiconductor device 100 includes one or more dielectric layers 600, wherein a first dielectric layer 600-1 is adapted to cover a gallium nitride (GaN) layer and disposed on a first barrier layer 103, and a second dielectric layer 600-2 is disposed on the first dielectric layer 600-1. The gallium nitride (GaN) layer 111 is at least partially covered by a third dielectric layer 600-3 and disposed on a portion 103-1 of the first barrier layer 103, and the third dielectric layer 600-3 forms a part of the first dielectric layer 600- 1.

[0063] Table 1 enlists the process parameters of ICP-CVD SiC deposition.

[0064] FIGs. 2 (a-c) illustrates an exemplary representation 200 of the electric field distribution in p-GaN as a function of sidewall surface (SS) donors, in accordance with an embodiment of the present disclosure.

[0065] Example 2

[0066] Sidewall Passivation

According to M. Meneghini et al., 2017, sidewall leakage is known to be a dominant gate leakage component. This can be attributed to non-ideal electric field conditions along the side walls and plasma etching-induced damage and dangling bonds resulting in trap formation. The gate leakage in such cases can be controlled by managing the electric field along the side wall. According to Fig. 2, the distribution of the electric field along the p-GaN side wall can effectively be modulated by introducing donor traps along the p-GaN side wall to SiCh passivation. As the interface donor trap concentration reduces, the electric field peak shifts from the p-GaN/AlGaN comer (Fig. 2(a)) to the Metal/p-GaN comer (Fig. 2(c)). Electric field peaking at the Metal/p-GaN comer may enhance hole tunneling, and at the p- GaN/AlGaN comer, it can result in a conductive electron sidewall channel. Fig. 2(b) shows that the interface donor trap concentration can be optimized to result in an ideal electric field distribution along the sidewall leading to a suppressed peak at both comers. Such conditions will lead to reduced sidewall leakage.

[0067] In a tenth embodiment of the present invention, the SS donors' concentration was extracted at VG = 7V . It indicates the shift of the electric field peak from the p-GaN/AlGaN comer towards the Gate/p-GaN comer with a decreasing concentration of SS donors. The electric field peaking at either location may increase the gate leakage and degrade gate performance. The computations indicate that an optimized SS profile can help attenuate sidewall leakage.

[0068] Experimental demonstration: Taking advantage of the fact that ionized donor states present a positive charge, the positive fixed charge density of the Si O2 sidewall was experimentally modified by controlling the O2 flow rate. MOS test stmctures on p-Si were fabricated to determine the charge profile of various passivations. A right shift in CV of the MOS test stmctures with these oxides, as shown in Fig. 3(a), established a reduction in the fixed charge density as the O2 flow rate was increased. Reduction in Si-dangling bonds in the SiO2 layer with O2 flow rate explains this reduction in positive fixed charge density. As seen in Fig. 3(b) and Fig. 3(c), as the O2 flow rate is increased from 4.8sccm to 7.6sccm, the gate leakage is significantly reduced. A further increase in the O2 flow rate to 9.6sccm again increases the gate leakage. These observations are in agreement with the TCAD-based predictions discussed above and suggest 7.6sccm to represent the condition of ideal field distribution along the sidewall giving the best possible gate leakage behavior. This improved field also results in higher gate overdrive achieved with the O2 flow rate of 7.6sccm.

[0069] FIGs. 3 (a-c) illustrates (a) the impact of O2 flow rate on capacitance-voltage characteristics of SiOx/p-Si MOS test structures, (b) gate leakage characteristics at VDS=0V, and (c) distribution of ON-state gate leakage for fixed gate voltage and maximum gate overdrive voltage, in accordance with an embodiment of the present disclosure.

[0070] In (3a), a positive shift in flat-band voltage is observed with increasing flow rate, indicating a reduction in positive fixed charge density.

[0071] In an eleventh embodiment of the present invention, the impact of passivating the sidewalls of the reference 80nm p-GaN stack with SiC>2, having variation in O2 flow rate. A non-monotonic relationship is observed between gate leakage and O2 flow rate, initially decreasing and then increasing. This suggests the presence of an optimum flow rate (7.2sccm) to minimize sidewall-induced gate leakage. The optimum O2 flow rate (7.2sccm) may correspond to an optimized charge profile near the SiCh/p-GaN sidewall interface thereby minimizing gate leakage. Additionally, the right axis of (c) illustrates the distribution of maximum gate overdrive voltage for the three SiC>2 passivation schemes, indicating improved performance for devices corresponding to the leakage-optimized O2 flow rate of 7.2sccm.

Example 3

Access Region Passivation

[0072] The breakdown (VBR)-ON-resistance (RON) performance of AlGaN/GaN HEMTs is significantly influenced by the dielectric breakdown strength and its charge profile in the access region. A method to enhance the breakdown strength is proposed, involving a bilayer passivation using a SiCMAlTiO stack. The effect of the passivation charge profile was investigated by varying the O2 flow rate.

[0073] Electroluminescence (EL) microscopy was employed with the Andor iXON Ultra EMCCD camera to examine the electric field distribution under semi-ON conditions. The drain current (IDS) was set to approximately 2mA by applying an appropriate gate voltage (VGS) and a drain voltage (VDS) of 100V. Figure 4(a) compares the EL intensity distribution of SiCMAlTiO systems. It reveals that an O2 flow rate of 4.8sccm leads to an electric field peak at the gate edge, while passivations at 7.2sccm and 9.8sccm result in a distributed electric field. Without integration of the AlTiO layer, the field redistribution weakens, as observed in the single-layer SiC>2 passivation case (O2 flow rate ~9.8sccm). Thus, the bilayer passivations with O2 flow rates of 7.2sccm and 9.8sccm are expected to enhance breakdown performance by optimizing the channel field engineering and improving the dielectric breakdown strength.

[0074] FIGs. 4 (a-c) illustrates an exemplary representation 400 of a) EL intensity distribution under semi-ON conditions with (I_DS ~ 2mA, VDS ~ 100V) of SiCMAITiO systems, revealing an electric field peak at the gate edge for an O2 flow rate of 4.8sccm and distributed electric field for passivations at 7.2sccm and 9.8sccm, b) comparison of VBR-RQN among different access region passivations demonstrates improved breakdown performance with bilayer passivation, and c) the dynamic increase in RON (ARQN) post-off-state stress was found to be suppressed with AlTiO integration due to improved channel distribution, in accordance with an embodiment of the present disclosure.

[0075] In FIG. 4(b), a comparison of VBR-RON among different access region passivations demonstrates improved breakdown performance with bilayer passivation. However, the bilayer passivation optimized for sidewall (7.2sccm) exhibits high VBR but suffers from significant RON degradation. On the other hand, passivation with an 02 flow rate of 4.8sccm results in low RON but also low VBR, which can be attributed to the single electric field peaking at the gate edge. The bilayer passivation corresponding to 9.6sccm, however, demonstrates moderate VBD and comparable RON, making it a recommended choice for passivation. Furthermore, systems with AlTiO integration have been shown to highly suppress dynamic RON issues induced by OFF-state stress conditions, as shown in Fig. 4(c), discussed in S. D. Gupta et al., 2021. This suppression is attributed to the improved electric field distribution.

[0076] In FIG. 4 (a), the redistribution of the field weakens without integration of the AlTiO layer, as observed in the single layer SiO2 passivation case (O2 flow rate ~9.8sccm). Thus, bilayer passivation with O2 flow rates of 7.2sccm and 9.8sccm is expected to enhance breakdown performance due to channel field engineering and improved dielectric breakdown strength. In b) although the bilayer passivation optimized for sidewall (7.2sccm) exhibits high VBR, it suffers from significant RON degradation. On the other hand, passivation with an O2 flow rate of 4.8sccm results in low RON but also low VBR, which can be attributed to the single electric field peaking at the gate edge. However, the bilayer passivation corresponding to 9.6sccm demonstrates moderate VBD and comparable RON, making it a recommended choice for passivation.

[0077] FIGs. 5 (a-c) illustrates an exemplary representation 500 of the 02 flow rate variation results in the SiO$_X$ passivation stoichiometry, which was confirmed through XPS analysis, in accordance with an embodiment of the present disclosure. [0078] FIGs 5(a-c) shows that O$_2$ flow rates of 4.8 seem resulted in non- stoichiometric SiO1.37and 7.2 and 9.8 seem resulted into close to the stoichiometric (S) SiO 1.96 and SiO i,98 layers, respectively.

[0079] FIGs. 6 (a-b) illustrates an exemplary representation 600 of the non-stoichiometric single-layer passivation is able to suppress dynamic Ron (a), and AlTiO integrated on stoichiometric passivation results in the improved dynamic Ron (b), in accordance with an embodiment of the present disclosure.

[0080] FIGs. 7 (a-c) illustrates an exemplary representation of the design variations that includes the GaN layer (111) may be of p-type Gallium Nitride (p-GaN), p-type oxide, crystalline, or amorphous form (a), the semiconductor device that include a dielectric layer (instead of GaN layer 111), SiN, A12O2, TiO2, AlTiO or any combination thereof, amorphous or crystalline form (b), the semiconductor device that exclude the GaN layer 111 (c), in accordance with an embodiment of the present disclosure.

[0081] FIG. 8 illustrates an exemplary representation of the design variation of the semiconductor device that includes the metal layer may not be fully extended to the p-GaN layer 111 comers and the spacer 113 disposed in those gaps, in accordance with an embodiment of the present disclosure.

[0082] In these embodiments, the semiconductor device 100 may have gaps with empty space.

[0083] FIGs. 9 (a-c) illustrates an exemplary representation of the field plate design variations of the semiconductor device 100 which connected to source (a), or connected to gate (b), or connected to drain electrode (c), in accordance with an embodiment of the present disclosure.

[0084] In these embodiments, the semiconductor device may be implemented with a combination of the design variations illustrated in FIG. 9a, FIG. 9b, and FIG. 9c.

[0085] While the foregoing description discloses various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope of the disclosure. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art. ADVANTAGES OF THE PRESENT INVENTION

[0086] A general advantage of the present disclosure provides a semiconductor device and a method of fabricating the semiconductor device with a multiple passivation approach [0087] The present disclosure provides the method and system that involves a dual and triple passivation approach in p-GaN sidewall and access region in p-GaN gate AlGaN/GaN devices.

[0088] The present disclosure provides a method that includes a triple passivation scheme including carrying out SiO2 sidewall passivation with a predefined 02 flow rate to suppress sidewall gate leakage and enhance gate performance. [0089] The present disclosure provides a device and a method to carry out the bilayer access region passivation scheme (SiO2/AlTiO) to improve the dielectric breakdown strength and electric field distribution. This approach aims to enhance the performance and reliability of these devices.

[0090] The present disclosure provides a device and a method that addresses the challenge of suppressing gate leakage thereby enhancing gate performance in p-GaN gate HEMTs, while also enhancing the overall breakdown-RON performance.

Claims

We Claim:

1. A semiconductor device (100) comprising: one or more dielectric layers (600), wherein a first dielectric layer (600-1) is adapted to cover a gallium nitride (GaN) layer (111) and disposed on a first barrier layer (103), and a second dielectric layer (600-2) disposed on the first dielectric layer (600-1), wherein the gallium nitride (GaN) layer (111) is at least partially covered by a third dielectric layer (600-3).

2. The semiconductor device (100) as claimed in claim 1, wherein the third dielectric layer (600-3) is disposed on a portion (103-1) of the first barrier layer (103), and the third dielectric layer (600-3) forms a part of the first dielectric layer (600-1).

3. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) is a high-electron-mobility transistor (HEMT) structure based on Gallium Nitride (GaN) on Silicon (Si) technology.

4. A semiconductor device (100) comprising: a substrate (101); a buffer layer (106) of gallium nitride (GaN) formed on the substrate (101); a channel layer (102) of unintentionally doped (UID) GaN formed on the buffer layer (106); a two-dimensional electron gas (2DEG) region (110) formed at the interface between a first barrier layer (103) and the channel layer (102); a second barrier layer (104) of aluminium nitride (AIN) formed on the channel layer (102); a first barrier layer (103) of aluminium gallium nitride (AlGaN) formed on the second barrier layer (104); the Gallium Nitride (GaN) (111) is formed on the first barrier layer (103); and a metal layer(105) of Titanium or Titanium Nitride (Ti/TiN) formed on the GaN layer (H l), wherein the semiconductor device (100) comprises: one or more dielectric layers (600), wherein a first dielectric layer (600-1) is adapted to cover the almunium gallium nitride (AlGaN) layer and disposed on the first barrier layer 103, and a second dielectric layer (600-2) is adapted to at least partially accommodate the metal layer 105, wherein the GaN layer is at least partially covered by a third dielectric layer (600-3), and the third dielectric layer (600-3) forms a part of the first dielectric layer (600-1).

5. The semiconductor device (100) as claimed in claim 1, wherein; the GaN layer (111) is of p-type Gallium Nitride (p-GaN), p-type oxide, crystalline, or amorphous form; or a dielectric such as SiN, A12O2, TiO2, AlTiO or any combination thereof, or in amorphous or crystalline form; the second dielectric layer (600-2) is of Al_yTi_yO; and the first dielectric layer (600-1) and the third dielectric layer (600-3) are made of SiO_x , SIN_X„ and A1O_X.

6. The semiconductor device (100) as claimed in claim 1, wherein: the metal layer (105) is disposed on the first barrier layer (103), the metal layer (105) is of titanium (Ti), titanium nitride (TiN), combination of Ti and TiN, scandium (Sc), tantalum (Ta), tantalum nitride(TaN), combination of Ta and TaN, tungsten (W), a mixture or a multilayer stack of titanium and aluminum (Ti/Al), or a multilayer combination involving Nickel, platinum, palladium, and Gold .

7. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) further comprising: a source contact (107) and a drain contact (108) formed on the channel layer (102), configured to facilitate current flow across the 2DEG region (110) under an applied voltage, and wherein the first passivation layer (601) operates as a gate insulator, providing electrical isolation between the gate stack (105) and source contact (107) and a drain contact (108); and any one or a combination of a source field plate 112, a spacer 113, a drain field plate 114, and a gate field plate 115.

8. The semiconductor device (100) as claimed in claim 1, wherein: the second dielectric layer (600-2) is based on alloyed oxide of A12O3 and TiO2 in a predefined ratio of 1 :2 to 1 :20 to get AlTiO.

9. The semiconductor device (100) as claimed in claim 1, wherein: the first dielectric layer (600-1) is close to non-stoichiometric si-rich oxide with predefined stoichiometry (SiOi.2-SiOi.6); the third dielectric layer (600-3) is close to stoichiometric oxide with predefined stoichiometry (SiOi.6- SiCh); and the second dielectric layer (600-2) having a stoichiometry Al_yTii._yO where y = 0.1- 0.9.

10. A method (200) of fabricating a semiconductor device (100), comprising: forming (201) a buffer layer (106) of gallium nitride (GaN) on a substrate (101); forming (202) a channel layer (102) of unintentionally doped (UID) GaN on the buffer layer (106); creating (203) a two-dimensional electron gas (2DEG) region (110) at the interface between a second barrier layer (104) and the channel layer (102); forming (204) the second barrier layer (104) of aluminium Nitride (AIN) formed on the channel layer (102); forming (205) a first barrier layer (103) of aluminium gallium nitride (AlGaN) formed on the second barrier layer (104); forming (206) a Gallium Nitride (GaN) (111) on the first barrier layer (103); and forming (207) a metal layer (105) of Titanium or Titanium Nitride (Ti/TiN) on the GaN layer (111); wherein the semiconductor device (100) having one or more dielectric layers (600) such that a first dielectric layer (600-1) is adapted to cover a gallium nitride (GaN) layer (111) and disposed on a first barrier layer (103), and a second dielectric layer (600-2) disposed on the first dielectric layer (600-1), wherein the gallium nitride (GaN) layer (111) is at least partially covered by a third dielectric layer (600-3).