WO2025048779A1

WO2025048779A1 - Three-dimensional photomask transmission with kernel-based modeling

Info

Publication number: WO2025048779A1
Application number: PCT/US2023/031287
Authority: WO
Inventors: Christopher Clifford
Original assignee: Siemens Industry Software Inc
Current assignee: Siemens Industry Software Inc
Priority date: 2023-08-28
Filing date: 2023-08-28
Publication date: 2025-03-06
Anticipated expiration: 2026-02-28

Abstract

This application discloses a computing system to simulate three-dimensional light transmission in a near-field of a lithographic mask using a thin mask approximation of the lithographic mask rasterized from a mask layout design describing the lithographic mask and using a compact mask model including a plurality of directional kernels representing light diffraction in the near-field of the lithographic mask. The computing system can generate a wafer image or resist contours based on the simulated three-dimensional light transmission in the near-field of the lithographic mask, and utilize an optical proximity correction (OPC) process to modify the mask layout design based on the wafer image or the resist contours. The lithographic mask corresponding to the mask layout design is configured for use in the manufacturing of an integrated circuit.

Description

THREE-DIMENSIONAL PHOTOMASK TRANSMISSION WITH KERNEL-BASED MODELING TECHNICAL FIELD [0001] This application is generally related to electronic design automation and, more specifically, to three-dimensional photomask transmission with kernel-based modeling. BACKGROUND [0002] In a design flow for fabricating integrated circuits, a physical design of an integrated circuit can describe specific geometric elements, often referred to as a layout design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the integrated circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices. [0003] Descriptions for physical designs of integrated circuits can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway, EDDM, and Open Artwork System Interchange Standard (OASIS). These various industry formats are used to define the geometrical information in layout designs that are employed to manufacture integrated circuits. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process. [0004] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured. [0005] Each time that a layer of material is exposed to radiation, a mask is created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a layout design define the relative locations or areas of the circuit that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design, after which the mask can be used in a photolithographic process. [0006] As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. The diffractive effects of light often result in defects where the intended image is not accurately printed onto the substrate during the photolithographic process, creating flaws in the manufactured device. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. [0007] One of these resolution enhancement techniques—optical proximity correction (OPC)—adjusts the amplitude of the light transmitted through a lithographic mask by modifying the mask layout design data employed to create the mask. For example, edges in the mask layout design may be adjusted to make certain portions of the geometric elements larger or smaller, in accordance with how much additional light exposure (or lack of exposure) is desired at certain points on the substrate. When these adjustments are appropriately calibrated, overall pattern fidelity can be increased. [0008] A specific form of optical proximity correction, called model-based optical proximity correction, can utilize the mask layout design data along with one or more compact models, such as a compact mask model, a compact optical model, and/or a compact resist model, to predict a printed image or resist contours on a substrate resulting from the light exposure through one or more masks described by the mask layout design data and then modify the mask layout design data. Since most masks include Manhattan shapes, the model-based optical proximity correction typically simulates the mask layout design data using a compact mask model implementing a Domain Decomposition Method (DDM) that adds one- dimensional signals corresponding to light transmission in a near-field of the masks. As optical proximity correction has evolved to allow design of masks with non-Manhattan or curvilinear shapes, the model-based optical proximity correction using compact mask model to add one-dimensional signals can inaccurately describe light transmissions in the near-field of the masks, reducing the accuracy of wafer image simulation and any resulting modifications to the mask layout design data during the optical proximity correction process. SUMMARY [0009] This application discloses a computing system to simulate three-dimensional light transmission in a near-field of a lithographic mask using a compact mask model and edge grids associated with the lithographic mask. The computing system can generate the edge grids by rasterizing a mask layout design describing the lithographic mask into a grid corresponding to the thin mask approximation of the lithographic mask, and then divide the thin mask approximation into the edge grids representing edges of shapes in the thin mask approximation of the lithographic mask in differing directions. The computing system can generate the compact mask model by performing a three-dimensional simulation of geometrical mask patterns to determine corresponding through the lens (TTL) target orders for the geometrical mask patterns, extracting edge grids from the geometrical mask patterns, determining TTL orders for the edge grids of the geometrical mask patterns, and generating directional kernels in the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the TTL orders for the edge grids of the geometrical mask patterns. [0010] The computing system can simulate the three-dimensional light transmission in the near-field of the lithographic mask by convolving the edge grids with the directional kernels in the compact mask model based on the directions associated with the edge grids and the directional kernel, which identifies directional light transmission at the edges of the thin mask approximation of the mask layout design. The computing system can aggregate the thin mask approximation of the mask layout design with the directional light transmission at the edges of the thin mask approximation of the mask layout design to determine the simulated three-dimensional light transmission in the near-field of the lithographic mask. [0011] The computing system can utilize the simulated three-dimensional light transmission in the near-field of the lithographic mask in a variety of ways. In some embodiments, the computing system can generate a wafer image or resist contours based, at least in part, on the simulated three-dimensional light transmission in the near-field of the lithographic mask. The computing system can implement an optical proximity correction (OPC) process to modify the mask layout design based on the wafer image and/or the resist contours. The computing system can utilize the simulated three-dimensional light transmission in the near- field of the lithographic mask to train a compact resist model used to simulate the resist contours, or utilize the simulated three-dimensional light transmission in the near-field of the lithographic mask in an OPC verification process to verify the mask layout design. Embodiments of will be described below in greater detail. DESCRIPTION OF THE DRAWINGS [0012] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments. [0013] Figure 3 illustrates an example of a manufacturing simulation system 300 implementing three-dimensional photomask transmission with kernel-based modeling according to various embodiments. [0014] Figure 4 illustrates a flowchart showing an example compact mask model calibration according to various examples. [0015] Figure 5 illustrates a flowchart showing example mask near-field simulation using a kernel-based compact mask model according to various examples. DETAILED DESCRIPTION Illustrative Operating Environment [0016] Various examples may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105. [0017] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and/or removable, a removable optical disk drive 119, and/or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection. [0018] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail. [0019] It should be appreciated that the computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both. [0020] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and/or instructions for execution. [0021] Each processor core 201A and 201B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input/output interface 209 and a memory controller 210. The input/output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments. Three-Dimensional Photomask Transmission with Kernel-Based Modeling [0022] Figure 3 illustrates an example of a manufacturing simulation system 300 implementing three-dimensional photomask transmission with kernel-based modeling according to various embodiments. Referring to Figure 3, the manufacturing simulation system 300 can receive a mask layout design 301 describing a lithographic mask used to manufacture an integrated circuit. In some embodiments, the lithographic mask described in the mask layout design 301 can include non-Manhattan or curvilinear shapes associated with apertures or openings of the lithographic mask. The manufacturing simulation system 300 also can receive optical system characterization data 302, which can describe the physical printing system utilized to manufacture the integrated circuit with the lithographic mask, for example, including a description of the light source, a numerical aperture of a lens, a description of the mask material and thickness, a description of resist material used on a semiconductor substrate, or the like. [0023] The manufacturing simulation system 300 can include a mask model calibration system 310 to create a compact mask model 311 for use in determining the three-dimensional light transmission in a near-field of the lithographic mask described by the mask layout design 301. In some embodiments, the compact mask model 311 can include a plurality of directional kernels representing light diffraction in cardinal directions in the near-field of the lithographic mask. Embodiments of compact mask model creation will be described below in greater detail with reference to Figure 4. [0024] Figure 4 illustrates a flowchart showing an example compact mask model calibration according to various examples. Referring to Figures 3 and 4, the mask model calibration system 310, in a block 401, can perform a three-dimensional simulation of geometrical mask patterns to determine corresponding through the lens (TTL) target orders for the geometrical mask patterns. The geometrical mask patterns can correspond to two-dimensional patterns of one or more mask shapes having various curvilinear edges. In some embodiments, the mask model calibration system 310 can include a simulator, such as a Finite Difference Time- Domain (FDTD) simulator, to perform the three-dimensional simulation of light diffraction through the geometrical mask patterns. [0025] The mask model calibration system 310 can utilize the three-dimensional simulation of light diffraction through the geometrical mask patterns to generate target grids for each of the geometrical mask patterns. In some embodiments, the mask model calibration system 310 can generate the target grids for each of the geometrical mask patterns by determining a difference between a thin mask approximation of the geometrical mask patterns and the simulated light diffraction through the geometrical mask patterns. The mask model calibration system 310 can generate the thin mask approximation of the geometrical mask patterns by rasterizing the geometrical mask patterns into a grid having an array of pixels with values corresponding to locations of the mask and aperture in the geometrical mask patterns. [0026] The mask model calibration system 310 can utilize the target grids representing mask near-field light transmission in cardinal directions for each of the geometrical mask patterns to determine through the lens (TTL) target orders for the geometrical mask patterns. In some embodiments, the mask model calibration system 310 can perform a Fourier transform of the target grids to obtain a set of diffracted orders of transmitted light in the mask near- field, eliminate one or more of the diffracted orders of transmitted light corresponding to light that would not be collected by a lens in the lithographic system used to manufacture the integrated circuit, and then perform an inverse Fourier transform of the modified set of the diffracted orders of the transmitted light. The modified set of diffracted orders of transmitted light can correspond to the through the lens (TTL) target orders for the geometrical mask patterns. [0027] The mask model calibration system 310, in a block 402, can extract edge grids from the geometrical mask patterns. In some embodiments, the mask model calibration system 310 can divide the thin mask approximation of the geometrical mask patterns into the edge grids by identifying pixels in the thin mask approximation have a gray-scale value and then separating the pixels having gray-scale values into different edge orientations in cardinal directions, such as up, down, left, right, or north, south, east, west, or the like. The edge grids can have pixel values associated with edges of apertures in the geometric mask patterns corresponding to their respective edge orientations. [0028] The mask model calibration system 310, in a block 403, can determine TTL orders for the edge grids of the geometrical mask patterns. In some embodiments, the mask model calibration system 310 can perform a Fourier transform of the edge grids to obtain a set of diffracted orders of transmitted light in the mask near-field, eliminate one or more of the diffracted orders of transmitted light corresponding to light that would not be collected by a lens in the lithographic system used to manufacture the integrated circuit, and then perform an inverse Fourier transform of the modified set of the diffracted orders of the transmitted light. The modified set of diffracted orders of transmitted light can correspond to the through the lens (TTL) orders for the edge grids. [0029] The mask model calibration system 310, in a block 404, can generate directional kernels based on the TTL target orders for the simulated geometrical mask patterns and the TTL orders for the edge grids of the geometrical mask patterns. In some embodiments, the mask model calibration system 310 can build a matrix for the TTL orders for the edge grids and then use the matrix to generate directional kernels. The matrix for the TTL orders for the edge grids can have a row-column format with each row of the matrix corresponding to a specific target TTL order for a single geometry of the geometrical mask patterns, each column of the matrix corresponds to a specific pairing of a basis function, such as a Zernike coefficient, and a directional kernel, and each row-column intersection of the matrix corresponding to a product of the specific target TTL order for the single geometry and a specific pairing of a basis function and the directional kernel. The mask model calibration system 310 can generate the directional kernels by determining complex basis function coefficients, such as Zernike coefficients, using a linear system including the TTL target orders for the simulated geometrical mask patterns and the matrix and then summing a set of complex polynomials, such as Zernike polynomials, weighted by the complex coefficients to generate the directional kernels. [0030] The mask model calibration system 310, in a block 405, can calibrate a compact mask model 311 to include the directional kernels. The mask model calibration system 310 can incorporate each of the directional kernels into the compact mask model 311, which can calibrate the compact mask model 311 for use in the manufacturing simulation system 300. [0031] Referring back to Figure 3, the manufacturing simulation system 300 can include mask near-field simulation system 320 to determine a mask near-field 321 for the lithographic mask using the compact mask model 311. In some embodiments, the mask near- field simulation system 320 can determine the mask near-field 321 by simulating the three- dimensional light transmission in the near-field of the lithographic mask using directional kernels in the compact mask model 311 and the mask layout design 301 for the lithographic mask. Embodiments of mask near-field simulation using a kernel-based compact mask model will be described below in greater detail with reference to Figure 5. [0032] Figure 5 illustrates a flowchart showing example mask near-field simulation using a kernel-based compact mask model according to various examples. Referring to Figures 3 and 5, the mask near-field simulation system 320 can include a rasterization system 322 that, in a block 501 of Figure 5, can rasterize the mask layout design 301 into a grid corresponding to a thin mask approximation of a lithographic mask. In some embodiments, the grid can correspond to pixelated data coded in gray-scale according to whether the pixel corresponds to a portion of the lithographic mask, an aperture or opening in the lithographic mask, or a combination thereof. [0033] The mask near-field simulation system 320 can include an edge grid system 324 that, in a block 502, can divide the thin mask approximation into a plurality of edge grids representing edges of shapes in the thin mask approximation of the lithographic mask in differing directions. In some embodiments, the edge grids can correspond to four cardinal directions, such as up, down, left, right, or north, south, east, west, etc. [0034] The mask near-field simulation system 320 can include a near-field simulator 326 that, in a block 503, can simulate three-dimensional light transmission in the near-field of the lithographic mask using the compact mask model 311 and the edge grids from the thin mask approximation of the lithographic mask. In some embodiments, the near-field simulator 326 can simulate the three-dimensional light transmission in the near-field of the lithographic mask in each cardinal direction, for example, by convolving each edge grid with a corresponding directional kernel in the compact mask model 311. For example, the near- field simulator 326 can identify an edge grid corresponding to a first cardinal direction, identify a complex directional kernel also corresponding to the first cardinal direction, and convolve them to determine a light diffraction in the near-field of the lithographic mask associated with the first cardinal direction. The near-field simulator 326 can repeat the convolution process with the edge grids and complex directional kernels in the other cardinal directions. In some embodiments, the near-field simulator 326, rather than convolve the edge grids and the complex directional kernels, can perform a Fourier transform on the edge grids and the complex directional kernels, multiple the transformed the edge grids and the complex directional kernels, and then perform an inverse Fourier transform to determine the light diffraction in the near-field of the lithographic mask. [0035] The mask near-field simulation system 320 can include an aggregation system 328 to combine the simulated three-dimensional light transmission in the near-field of the lithographic mask in each of the cardinal directions along with the thin mask approximation of the lithographic mask. The combination of the simulated three-dimensional light transmission in the near-field of the lithographic mask in each of the cardinal directions and the thin mask approximation of the lithographic mask can correspond to the mask near-field 321 for the lithographic mask. [0036] The manufacturing simulation system 300 can include an optical simulator 330 that, in a block 504, can generate a wafer image 303 based, at least in part, on the mask near- field 321. The optical simulator 330 can receive the compact optical model 331 that models the optical characteristics in the physical printing system utilized to manufacture the integrated circuit with the lithographic mask. The optical simulator 330 can utilize the mask near-field 321 and a compact optical model 331 to predict a printed image on a substrate resulting from the light exposure through one or more masks described by the mask layout design 301. The wafer image 303 can correspond to the patterns of light shown on a semiconductor wafer after passing through the lithographic mask and the lens of the physical printing system. [0037] The manufacturing simulation system 300 can include a resist simulator 340 that, in the block 504, can generate resist contours 304 based, at least in part, on wafer image 303. The resist simulator 340 can receive the compact resist model 341 that models the characteristics resist when exposed to light in the physical printing system utilized to manufacture the integrated circuit with the lithographic mask. The resist simulator 340 can utilize the wafer image 303 and a compact resist model 341 to predict resulting contours in the resist on a substrate resulting from the light exposure through one or more masks described by the mask layout design 301. In some embodiments, the manufacturing simulation system 300 can include a calibration system for the compact resist model 341, which can utilize the mask near-field 321 to create or modify the compact resist model 341. [0038] The wafer image 303 and the resist contours 304 generated by the manufacturing simulation system 300 can be utilized by downstream design and analysis tools, such as an optical proximity correction tool 350, a verification tool, a mask or reticle writing tool, or the like. In this example, the optical proximity correction tool 350 can receive the wafer image 303 and/or the resist contours 304 from the manufacturing simulation system 300 and perform model-based optical proximity correction on the mask layout design 301, which, in a block 505, can modify the mask layout design 301 based, at least in part, on the wafer image 303 and/or the resist contours 304 to increase overall pattern fidelity. [0039] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and/or methods described herein may be performed by an apparatus, a device, and/or a system substantially similar to those as described herein and with reference to the illustrated figures. [0040] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission. [0041] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I/O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device. [0042] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini- computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and/or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof. [0043] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Conclusion [0044] While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of electronic design automation processes. [0045] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure. [0046] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

CLAIMS 1. A method comprising: simulating, by a computing system, three-dimensional light transmission in a near- field of a lithographic mask using a thin mask approximation of the lithographic mask from a mask layout design and using a compact mask model including a plurality of directional kernels representing light diffraction in the near-field of the lithographic mask; generating, by the computing system, a wafer image or resist contours based, at least in part, on the simulated three-dimensional light transmission in the near-field of the lithographic mask; and utilizing, by the computing system, an optical proximity correction (OPC) process to modify the mask layout design based, at least in part, on the wafer image or the resist contours, wherein the lithographic mask corresponding to the mask layout design is configured for use in the manufacturing of an integrated circuit.

2. The method of claim 1, further comprising rasterizing, by the computing system, the mask layout design into a grid corresponding to the thin mask approximation of the lithographic mask; and dividing, by the computing system, the thin mask approximation into a plurality of edge grids representing edges of shapes in the thin mask approximation of the lithographic mask in differing directions, wherein the simulating of the three-dimensional light transmission in the near-field of the lithographic mask uses the edge grids representing edges of shapes in the thin mask approximation of the lithographic mask.

3. The method of claim 2, wherein simulating the three-dimensional light transmission in the near-field of the lithographic mask further comprises: convolving the edge grids with the directional kernels based on the directions associated with the edge grids and the directional kernel, which identifies directional light transmission at the edges of the thin mask approximation of the mask layout design; and aggregating the thin mask approximation of the mask layout design with the directional light transmission at the edges of the thin mask approximation of the mask layout design to determine the simulated three-dimensional light transmission in the near- field of the lithographic mask.

4. The method of claim 1, further comprising generating, by the computing system, the compact mask model by: performing a three-dimensional simulation of geometrical mask patterns to determine corresponding through the lens (TTL) target orders for the geometrical mask patterns; extracting edge grids from the geometrical mask patterns; determining TTL orders for the edge grids of the geometrical mask patterns; and generating the directional kernels of the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the TTL orders for the edge grids of the geometrical mask patterns.

5. The method of claim 4, wherein generating the compact mask model further comprises: combining the TTL orders for the edge grids of the geometrical mask patterns with Zernike coefficients to generate complex Zernike polynomials; and generating the directional kernels of the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the complex Zernike polynomials, wherein each of the directional kernels in the compact mask model corresponds to a sum of the complex Zernike polynomials.

6. The method of claim 1, wherein simulating the three-dimensional light transmission in the near-field of the lithographic mask further comprises determining diffracted orders of light transmission through the lithographic mask and removing any diffracted orders of the light transmission not capable of being collected by a lens in an optical system to manufacture the integrated circuit.

7. The method of claim 1 further comprising calibrating, by the computing system, a resist compact model based, at least in part, on the simulated three-dimensional light transmission in the near-field of the lithographic mask.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: simulate three-dimensional light transmission in a near-field of a lithographic mask using a thin mask approximation of the lithographic mask from a mask layout design and using a compact mask model including a plurality of directional kernels representing light diffraction in the near-field of the lithographic mask; generate a wafer image or resist contours based, at least in part, on the simulated three-dimensional light transmission in the near-field of the lithographic mask; and utilize an optical proximity correction (OPC) process to modify the mask layout design based, at least in part, on the wafer image or the resist contours, wherein the lithographic mask corresponding to the mask layout design is configured for use in the manufacturing of an integrated circuit.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: rasterize the mask layout design into a grid corresponding to the thin mask approximation of the lithographic mask; and divide the thin mask approximation into a plurality of edge grids representing edges of shapes in the thin mask approximation of the lithographic mask in differing directions, wherein the simulating of the three-dimensional light transmission in the near-field of the lithographic mask uses the edge grids representing edges of shapes in the thin mask approximation of the lithographic mask.

10. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to simulate the three- dimensional light transmission in the near-field of the lithographic mask by: convolving the edge grids with the directional kernels based on the directions associated with the edge grids and the directional kernel, which identifies directional light transmission at the edges of the thin mask approximation of the mask layout design; and aggregating the thin mask approximation of the mask layout design with the directional light transmission at the edges of the thin mask approximation of the mask layout design to determine the simulated three-dimensional light transmission in the near- field of the lithographic mask.

11. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to generate the compact mask model by: performing a three-dimensional simulation of geometrical mask patterns to determine corresponding through the lens (TTL) target orders for the geometrical mask patterns; extracting edge grids from the geometrical mask patterns; determining TTL orders for the edge grids of the geometrical mask patterns; and generating the directional kernels of the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the TTL orders for the edge grids of the geometrical mask patterns.

12. The system of claim 11, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to generate the compact mask model by: combining the TTL orders for the edge grids of the geometrical mask patterns with Zernike coefficients to generate complex Zernike polynomials; and generating the directional kernels of the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the complex Zernike polynomials, wherein each of the directional kernels in the compact mask model corresponds to a sum of the complex Zernike polynomials.

13. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to simulate the three- dimensional light transmission in the near-field of the lithographic mask by determining diffracted orders of light transmission through the lithographic mask and removing any diffracted orders of the light transmission not capable of being collected by a lens in an optical system to manufacture the integrated circuit.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: simulating three-dimensional light transmission in a near-field of a lithographic mask using a thin mask approximation of the lithographic mask from a mask layout design and using a compact mask model including a plurality of directional kernels representing light diffraction in the near-field of the lithographic mask; generating a wafer image or resist contours based, at least in part, on the simulated three-dimensional light transmission in the near-field of the lithographic mask; and utilizing an optical proximity correction (OPC) process to modify the mask layout design based, at least in part, on the wafer image or the resist contours, wherein the lithographic mask corresponding to the mask layout design is configured for use in the manufacturing of an integrated circuit.

15. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising: rasterizing the mask layout design into a grid corresponding to the thin mask approximation of the lithographic mask; and dividing the thin mask approximation into a plurality of edge grids representing edges of shapes in the thin mask approximation of the lithographic mask in differing directions, wherein the simulating of the three-dimensional light transmission in the near- field of the lithographic mask uses the edge grids representing edges of shapes in the thin mask approximation of the lithographic mask.

16. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising simulating the three- dimensional light transmission in the near-field of the lithographic mask by: convolving the edge grids with the directional kernels based on the directions associated with the edge grids and the directional kernel, which identifies directional light transmission at the edges of the thin mask approximation of the mask layout design; and aggregating the thin mask approximation of the mask layout design with the directional light transmission at the edges of the thin mask approximation of the mask layout design to determine the simulated three-dimensional light transmission in the near- field of the lithographic mask.

17. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising generating the compact mask model by: performing a three-dimensional simulation of geometrical mask patterns to determine corresponding through the lens (TTL) target orders for the geometrical mask patterns; extracting edge grids from the geometrical mask patterns; determining TTL orders for the edge grids of the geometrical mask patterns; and generating the directional kernels of the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the TTL orders for the edge grids of the geometrical mask patterns.

18. The apparatus of claim 17, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising generating the compact mask model by: combining the TTL orders for the edge grids of the geometrical mask patterns with Zernike coefficients to generate complex Zernike polynomials; and generating the directional kernels of the compact mask model based, at least in part, on the TTL target orders for the simulated geometrical mask patterns and the complex Zernike polynomials, wherein each of the directional kernels in the compact mask model corresponds to a sum of the complex Zernike polynomials.

19. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising simulating the three- dimensional light transmission in the near-field of the lithographic mask by determining diffracted orders of light transmission through the lithographic mask and removing any diffracted orders of the light transmission not capable of being collected by a lens in an optical system to manufacture the integrated circuit.

20. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising calibrating a resist compact model based, at least in part, on the simulated three-dimensional light transmission in the near-field of the lithographic mask.