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WO2024235399A1 - Composant memcapacitif et procédé de fonctionnement du composant memcapacitif - Google Patents

Composant memcapacitif et procédé de fonctionnement du composant memcapacitif Download PDF

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Publication number
WO2024235399A1
WO2024235399A1 PCT/DE2024/100445 DE2024100445W WO2024235399A1 WO 2024235399 A1 WO2024235399 A1 WO 2024235399A1 DE 2024100445 W DE2024100445 W DE 2024100445W WO 2024235399 A1 WO2024235399 A1 WO 2024235399A1
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WIPO (PCT)
Prior art keywords
memcapacitive
electrode
component
doped region
shielding layer
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PCT/DE2024/100445
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German (de)
English (en)
Inventor
Kai-Uwe Demasius
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Semron GmbH
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Semron GmbH
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • Memcapacitive component and method for operating the memcapacitive component
  • the present disclosure relates generally to microelectronic devices. More particularly, the present disclosure relates to a memcapacitive device and a method of operating the memcapacitive device.
  • AI artificial intelligence
  • transformer models increasingly powerful and faster computers are required.
  • New processor and memory architectures which are specifically designed for AI-typical operations, such as tensor multiplication, could help to meet these growing requirements.
  • the patent document US2022059161A1 describes a memcapacitive device or capacitive synaptic device and a matrix of a plurality of capacitive synaptic devices for performing vector-matrix multiplication. Compared to memresistive devices, memcapacitive devices offer some advantages in terms of static power consumption or sneak path problems that can occur with memresistive devices.
  • Volatile and free vector matrix multiplications can play a crucial role in the calculation of transformer models in the so-called attention layers or in the implementation of a short-term memory.
  • free multiplication means that the same multiplication operation can be routinely repeated with different or freely variable weights or matrix parameters.
  • the speed and flexibility of changing weights or matrix elements between individual calculation steps plays a crucial role in increasing the efficiency of small computers and artificial neural networks.
  • An object of embodiments of the present disclosure is to provide a memcapacitive component and a method for operating the memcapacitive component, which enable fast and flexible changing of weights in matrix operations.
  • a memcapacitive component also referred to below as “arrangement” is proposed for operation under non-linear capacitance-voltage curves.
  • the memcapacitive component can be designed as a semiconductor component with a changeable non-linear behavior or with an adjustable non-linear capacitance-voltage curve.
  • the memcapacitive component comprises a number of electrical connections for electrically contacting the memcapacitive component.
  • the number of electrical connections can comprise one, two, three or four electrical connections.
  • the memcapacitive component comprises a first electrode and a second electrode.
  • the memcapacitive component further comprises at least one dielectric arranged between the first electrode and the second electrode, wherein the electrical connections and/or the at least one dielectric has charge traps forming potential wells of different depths for trapping variable, in particular controllably variable, charge quantities.
  • the memcapacitive component can have at least one energetically flat charge trapping point for short-term or fleeting or volatile storage of charges or capacitance values and at least one energetically low charge trapping point for long-term or non-volatile storage of charges or capacitance values.
  • the energetically flat or energetically low charge trapping points can in particular form potential wells with correspondingly low or high threshold or activation energies or barrier heights.
  • the memcapacitive component can be used to store computational parameters and to carry out computational operations.
  • the size of a computational parameter can be represented at least indirectly by a stored charge quantity.
  • the potential wells associated with energetically flat charge traps for short-term storage can have a depth or barrier height of at most 1.2 eV or between 0.2 eV and 1.1 eV or between 0.5 eV and 0.9 eV.
  • the potential wells associated with low energy charge traps for long-term or non-volatile storage may have a depth or barrier height of at least 1.6 eV, or between 1.7 eV and 3.0 eV, or between 2.0 eV and 2.5 eV.
  • the ratio of the depth or barrier height of potential wells associated with low energy charge traps for short-term storage to potential wells associated with low energy charge traps for long-term or non-volatile storage may be at least 0.01 or at most 0.99, or between 0.05 and 0.95, or between 0.1 and 0.9, or between 0.2 and 0.8, or between 0.4 and 0.6.
  • the at least one dielectric can comprise a first dielectric with a first charge trap and a second dielectric with a second charge trap.
  • charge traps with different energetic depths can be realized.
  • the charge trap of the first dielectric can have a lower energetic depth than the charge trap of the second dielectric.
  • the potential well formed by the first charge trap can be used in particular for the volatile storage of charges and the potential well formed by the second charge trap can be used for the non-volatile storage of charges.
  • the memcapacitive component can comprise a shielding layer arranged between the first electrode and the second electrode with a shielding capacity that can be changed in a controlled manner.
  • the shielding layer can be designed to shield an electric field emanating from the first electrode and/or from the second electrode, wherein the shielding layer can have different shielding behavior depending on the operating state.
  • the first dielectric can be arranged between the first electrode and the shielding layer and/or the second dielectric can be arranged between the second electrode and the shielding layer.
  • the two dielectrics can be arranged such that fields prevailing in the first dielectric and in the second dielectric can be shielded from one another.
  • the shielding layer can comprise a semiconductor layer with a charge carrier concentration that can be changed in a controlled manner. Depending on the concentration of the charge carriers, in particular electrons or holes, the field emanating from the first electrode and/or the second electrode can be shielded to varying degrees by the shielding layer.
  • the charge carrier concentration in the shielding layer can thus shielding capability or the measurable capacitance of the memcapacitive component.
  • the capacitance or capacitive behavior of the memcapacitive component can thus be used to represent a variable or volatile parameter.
  • the shielding layer can be designed to assume quasi-static states or charge states with shielding capacity of varying degrees. Quasi-static in this context means that the charge states, in particular charge carrier concentration, or shielding capacity of the shielding layer can be maintained for a certain time or during a certain residence time.
  • the shielding layer can have a certain charge state during the execution of a calculation operation or an elementary calculation step.
  • the residence time of the charge states in the shielding layer can be set or changed in particular by internal factors, such as doping and/or charge trapping sites, as well as externally, such as by applying a voltage or bias voltage.
  • the ability of the shielding layer to maintain or store its state or charge state at least for a short time can represent a further or additional storage mechanism, for example to store parameters that change quickly or frequently for a short time before carrying out a calculation operation.
  • Various mechanisms for storing charges or capacitance values can thus be implemented using the memcapacitive component.
  • the shielding layer similar to the charge traps in the first dielectric and/or in the second dielectric, can be used to store information or parameters.
  • the charge traps of the first and/or the second dielectric and the shielding layer can have different stable charge states. Due to the energetic differences, both volatile and non-volatile memories can be realized using such memcapacitive components.
  • the first dielectric and/or the second dielectric can be designed essentially similarly to a gate stack in a flash memory, wherein the two dielectrics can have charge traps with different energetic depths.
  • the first electrode and/or the second electrode can be designed for short-term storage of a capacitance value by means of charge storage on the electrodes.
  • capacitance values can be used to represent calculation parameters, in particular parameters to be stored volatilely.
  • the memcapacitive component can in particular be used in a Circuit or in a circuit arrangement with an external capacitor.
  • the external capacitor can be connected with a first connection to one of the electrodes of the memcapacitive component and electrically connected to a storage voltage via a switch.
  • the other connection of the capacitor can in particular be connected to a readout signal.
  • the external capacitor can in particular be designed to store a storage voltage, so that a capacitance value of the memcapacitive component can be set using the storage voltage.
  • potential wells of different depths can be implemented using the switch. When writing, the depth of a potential well can be reduced so that charges can be added to the potential well. When saving, the depth of the potential well can be increased so that the charges can be stored. Depending on the height of the potential well, short-term storage or long-term storage can be made possible.
  • a deep potential well means a switch is open, a shallow potential well or no potential well means a switch is closed. In principle, any intermediate stages are possible in order to achieve a different depth of the potential wells, for example with an integrated field effect transistor, see Fig. 8 below.
  • the number of electrical connections can include at least one electrical connection for contacting the shielding layer, so that short-term storage of capacitance values can take place by means of charge storage on the shielding layer.
  • the shielding layer of the memcapacitive component can have at least one of its own electrical connections for directly contacting the shielding layer, via which electrical charges can be injected into the shielding layer or withdrawn from the shielding layer.
  • the memcapacitive component can be used in particular in a circuit or circuit arrangement with an external capacitor connected to the shielding layer for setting the short-term capacitance value.
  • the external capacitor can, for example, be connected to a switch with a first connection that connects or disconnects the storage voltage, wherein the second connection of the capacitor can be connected to ground.
  • capacitance values can be used to represent calculation parameters that are stored too short-term or volatile.
  • the shielding layer has a p-doped region and an n-doped region, wherein the p-doped region or the n-doped region can be designed to be electrically contacted via at least one switch with a bias voltage or with a constant voltage.
  • charge carriers Via the p-doped region and/or the n- doped region, charge carriers can be injected into the shielding layer or withdrawn from the shielding layer in order to modify the charge state or shielding capacity of the shielding layer in a controlled manner.
  • the shielding layer can in particular have a pin diode topology, wherein the dielectric between the p-doped region and the n-doped region can serve as a shielding region for shielding the field emanating from the first electrode or from the second electrode.
  • the memcapacitive component can comprise at least one field effect transistor at least partially integrated into the shielding layer for connecting the p-doped region and/or the n-doped region to a bias voltage.
  • at least some of the components of the at least one field effect transistor and the memcapacitive component can have been manufactured in common process steps.
  • the n-doped region of the memcapacitive component can function as the source or drain of the field effect transistor, whereby a particularly compact structure can be achieved.
  • the field effect transistor can in particular function as the switch for connecting the memcapacitive component and the external capacitor to the storage voltage.
  • the memcapacitive component is designed such that the first electrode and/or the second electrode does not overlap with the n-doped region and/or with the p-doped region.
  • the area between the p-doped region and the n-doped region can extend beyond the lateral extent of the first and/or the second electrodes in at least one lateral direction. In this way, it can be avoided that the p-doped region and/or the n-doped region impairs the shielding function of the shielding layer.
  • a method for operating a memcapacitive component can in particular be designed as a memcapacitive component with an adjustable non-linear capacitance-voltage curve according to an embodiment according to the first aspect.
  • the memcapacitive component has a number of connections, wherein the number of connections comprises a first electrode and a second electrode.
  • the memcapacitive component further comprises at least one dielectric arranged between the first electrode and the second electrode, wherein the electrical connections and/or the at least one dielectric has charge traps of different depths forming potential wells for trapping variable, in particular controlled variable, amounts of charge.
  • the method comprises writing to the memcapacitive component by applying a positive or negative write voltage to the first electrode and/or to the second electrode to change the amount of charge trapped in the potential wells.
  • a measurable change in state of the memcapacitive component can take place.
  • Applying the write voltage can in particular bring about such a measurable change in state of the memcapacitive component.
  • applying the write voltage can lead to tunneling between the first or the second electrode and the at least one charge trapping point, so that the amount of charge stored at the charge trapping point can be changed.
  • This change in state can be measured or read out, for example in a later step.
  • the change in the amount of charge stored at the at least one charge trapping point can have an effect on the capacitive behavior of the memcapacitive component, which can also be measured.
  • the first dielectric may be arranged between the first electrode and the shielding layer and the second dielectric may be arranged between the second electrode and the shielding layer, and wherein the first dielectric and/or the second dielectric may comprise at least one charge trap for storing a variable amount of charge.
  • the method includes setting a non-linear capacitance-voltage curve.
  • the setting of the non-linear capacitance-voltage curve can be carried out in particular by changing the charge states of the at least one charge trap or the shielding layer. This can be carried out in particular by an external voltage or an external field, which can cause charge shifts in the memcapacitive component, in particular in the dielectrics or in the shielding layer.
  • a current non-linear capacitance-voltage curve can be used to describe a current state of the memcapacitive component, so that the capacitance or the non-linear capacitance-voltage curve can be used to represent variable parameters, such as weights in a matrix-vector multiplication.
  • the at least one dielectric can comprise a first dielectric with a first charge trap and a second dielectric with a second charge trap. Using different dielectrics, charge traps with different energetic depths can be realized. For example, the charge trap of the first dielectric can have a lower energetic depth than the charge trap of the second dielectric.
  • the memcapacitive component can comprise a shielding layer arranged between the first electrode and the second electrode with a shielding capacity that can be changed in a controlled manner, wherein the setting of the nonlinear capacitance-voltage curve can comprise applying a bias voltage, in particular a constant bias voltage, to the shielding layer. By applying the bias voltage, in particular the charge state of the shielding layer and thus the shielding behavior of the shielding layer can be changed, whereby the capacitive behavior of the memcapacitive component can be influenced.
  • the first dielectric can be arranged between the first electrode and the shielding layer and/or the second dielectric can be arranged between the second electrode and the shielding layer.
  • the two dielectrics can be arranged such that fields prevailing in the first dielectric and in the second dielectric can be shielded from one another.
  • the shielding layer comprises a p-doped region and an n-doped region, wherein the p-doped region and the n-doped region can be designed to be electrically connected to a bias voltage via at least one switch.
  • the application of the bias voltage can comprise applying a constant voltage in the p-doped region and/or in the n-doped region.
  • the p-doped region and the n-doped region can be connected to a constant voltage or ground during the application of the write voltage, and the n- or p-doped region is separated from the constant voltage or ground before the write voltage is reset to the initial value.
  • the bias of the shielding layer can be maintained over the entire duration of the writing process, so that the writing process can take place under essentially constant conditions.
  • a pin diode formed by the p-doped region and n-doped region in the shielding layer is operated in the forward direction. By operating the pin diode in the forward or forward direction, electrons can be injected into the shielding layer.
  • the method comprises applying a readout voltage to the first electrode and/or to the second electrode for reading the memcapacitive component.
  • the reading can be carried out in a separate method step in order to possibly read out a voltage in the memcapacitive component at a later point in time. to read the stored parameter value or the current state of the memcapacitive component.
  • Fig. 1 shows a schematic cross section through a memcapacitive component according to a first embodiment
  • Fig. 2 shows a schematic cross section through a memcapacitive component according to a second embodiment
  • Fig. 3 shows the memcapacitive component of Fig. 2 together with a nonlinear capacitance-voltage curve
  • Fig. 4 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor according to an embodiment
  • Fig. 5 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor according to a further embodiment
  • Fig. 6 shows an electrical circuit with a memcapacitive component according to a third embodiment
  • Fig. 7 shows an electrical circuit with a memcapacitive component according to a fourth embodiment
  • Fig. 8 shows an electrical circuit with a memcapacitive component according to a fifth embodiment
  • Fig. 9 shows a flowchart of a method for operating a memcapacitive component according to an embodiment.
  • Fig. 1 shows a schematic cross section through a memcapacitive component according to a first embodiment.
  • the memcapacitive component 1 comprises a first electrode 3a, a second electrode 3b and a dielectric 5a arranged between the first electrode 3a and the second electrode 3b.
  • the memcapacitive component 1 has a variable non-linear capacitance-voltage curve and charge traps (not shown) with different energy depths.
  • the first electrode 3a, the second electrode 3b and/or the dielectric 5a can have charge traps of different depths forming potential wells for trapping variable amounts of charge. This is illustrated in Fig. 1 by a simplified potential well 15 with charge carriers 15 trapped therein, on the right in the picture.
  • the left-pointing arrows are intended to indicate those areas of the memcapacitive component 1 where the charge traps can be located.
  • the non-linear capacitance-voltage curve of the memcapacitive component can be shifted depending on the voltage or charge state of the electrodes 3a, 3b and the dielectric 5a.
  • the charge trapping points can in particular be designed such that the respective charge state can be stored quickly and volatilely and can be changed quickly.
  • Fig. 2 shows a schematic cross section of a memcapacitive component according to a second embodiment.
  • the second embodiment essentially corresponds to the first embodiment, wherein the memcapacitive component comprises a first dielectric 5a, a second dielectric 5b and a shielding layer 4, wherein the first dielectric 5a is arranged between the first electrode 3a and the shielding layer 4, and wherein the second dielectric 5b is arranged between the second electrode 3b and the shielding layer 4.
  • the shielding layer 4 has a semiconductor layer with a variable charge carrier concentration.
  • the first dielectric 5a has a first charge trapping point (not shown) for storing a variable amount of charge.
  • the charge trapping point can be designed in particular for non-volatile storage of the charge, which can be used in particular for non-volatile storage of a parameter value.
  • the second dielectric 5b also has a charge trapping point or second charge trapping point for storing a variable amount of charge.
  • Fig. 2 also shows a simplified potential well 15 with Charge carriers 15 and left-facing arrows to indicate the areas of the memcapacitive in which the charge trapping sites can be located.
  • the non-linear capacitance-voltage curve can be shifted depending on the voltage or charge state of the electrodes 3a, 3b, the shielding layer 4 or the dielectrics 5a, 5b.
  • the charge state of the shielding layer 4 or shielding electrode can be stored quickly and volatilely and changed quickly.
  • Fig. 3 shows the memcapacitive component according to Fig. 2 together with a non-linear capacitance-voltage curve.
  • a simplified capacitance-voltage dependence is shown on the right of the image to illustrate the non-linear capacitance-voltage curve.
  • Fig. 4 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor.
  • the external capacitor 5 is designed to store a storage voltage or write voltage.
  • the external capacitor 5 is connected with a first connection to the first electrode 3a of the memcapacitive component 1 and to a storage voltage 6 via a switch 7.
  • the external capacitor 5 is connected with a second connection to a readout signal 8.
  • the stored charge on the capacitor 5 leads to a shift in the capacitance-voltage curve of the memcapacitive component 1 and thus sets the capacitance value of the memcapacitive component 1.
  • Fig. 5 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor 5 according to a further embodiment.
  • the circuit shown in Fig. 5 essentially corresponds to the embodiment of Fig. 4, wherein the external capacitor 5 is connected to the shielding layer 4 of the memcapacitive component 1.
  • the charge on the capacitor 5 also leads to a shift in the capacitance-voltage curve 2 of the memcapacitive component 1.
  • Fig. 6 shows an electrical circuit with a memcapacitive component according to a third embodiment.
  • the memcapacitive component 1 according to the third embodiment is designed essentially similarly to the memcapacitive component 1 according to the second embodiment, see Figures 2 to 4 above.
  • the memcapacitive component 1 of Fig. 5 also comprises a first electrode 3a, a second electrode 3b, a first dielectric 5a, a second dielectric 5b and a shielding layer 4, wherein the shielding layer 4 comprises a p-doped region 9 and an n-doped region 10.
  • the p-doped region 9 and the n-doped region 10 are formed at two opposite lateral ends of the shielding layer 4.
  • a write voltage 11 is applied to the first electrode 3a of the memcapacitive component 1.
  • the n-doped region 10 of the shielding layer is connected to a constant voltage 13 via a switch 12.
  • the switch 12 can be opened after the write voltage 11 has been applied, so that the injected electrons can remain in the shielding layer 4 when the write voltage is reset to its initial value.
  • Fig. 7 shows an electrical circuit with a memcapacitive component according to a fourth embodiment.
  • the fourth embodiment of the memcapacitive component essentially corresponds to the third embodiment shown in Fig. 6, wherein the memcapacitive component 1 is designed such that the first electrode 3a does not overlap with the n-doped region 10 of the shielding layer 4.
  • the first electrode 3a has a smaller lateral extent than, for example, the first electrode 3a according to the embodiment of Fig. 4, so that the first electrode 3a does not reach the n-doped region 10 of the shielding layer 4.
  • the pin diode formed by the p-doped region 9 and the n-doped region 10 in the shielding layer 4 can be operated in the forward direction.
  • Fig. 8 shows an electrical circuit with a memcapacitive component according to a fifth embodiment.
  • the fifth embodiment essentially corresponds to the third embodiment according to Fig. 6, wherein the memcapacitive component 1 further comprises a field effect transistor 14, which is partially integrated in the shielding layer 4.
  • the n-doped region 10 of the memcapacitive component 1 can serve as the source or drain of the field effect transistor, whereby a particularly compact structure can be achieved.
  • the memcapacitive component can be designed as a substantially planar semiconductor component, which can be manufactured using methods known from semiconductor manufacturing, such as photolithography, metallization, wet and dry chemistry, plasma processes.
  • semiconductor manufacturing such as photolithography, metallization, wet and dry chemistry, plasma processes.
  • a silicon-based semiconductor substrate can be used as Shielding layer can be used.
  • the first and second dielectrics can comprise silicon oxide and the charge traps can be implemented in silicon nitride.
  • the charge traps can be designed in particular as inclusions in the dielectrics, comparable to floating gates in flash memories.
  • the p-doped region and the n-doped region can be provided by implantation and oven steps, as known from MOSFET technology, for example.
  • the memcapacitive component can be designed in such a way that the charge trapping points have different energy depths.
  • silicon with a band gap of 1.1 eV other semiconductor materials can also be used to realize potential wells with different barrier heights.
  • the potential wells associated with energetically shallow charge traps for short-term storage may have a depth or barrier height of at most 1.2 eV, or between 0.2 eV and 1.1 eV, or between 0.5 eV and 0.9 eV.
  • the potential wells associated with energetically deep charge traps for long-term or non-volatile storage may have a depth or barrier height of at least 1.6 eV, or between 1.7 eV and 3.0 eV, or between 2.0 eV and 2.5 eV.
  • the ratio of the depth or barrier height of potential wells associated with energetically shallow charge traps for short-term storage to potential wells associated with energetically deep charge traps for long-term or non-volatile storage may be a minimum of 0.01 or a maximum of 0.99 or between 0.05 and 0.95 or between 0.1 and 0.9 or between 0.2 and 0.8 or between 0.4 and 0.6.
  • the energetically flat charge traps can be used in particular for the volatile storage of parameters, while the energetically deep charge traps can be used for longer-term or non-volatile storage of parameters.
  • the shielding layer can also assume energetically flat or quasi-static charge states, which can be used for the volatile or volatile storage of frequently changing weights or matrix element parameters.
  • Fig. 9 shows a flow chart of a method for operating a memcapacitive component according to an embodiment.
  • a memcapacitive component according to the first aspect is provided in a method step 110.
  • the memcapacitive component can be designed similarly to that shown in Figures 1 to 8.
  • the memcapacitive component is written to by applying a write voltage.
  • the memcapacitive component can be written to in method step 120 by applying a positive or negative write voltage to the first electrode 3a and/or to the second electrode 4b to change the amount of charge trapped in the potential wells.
  • charge carriers, driven by the applied write voltage can travel from the first or second electrode or possibly from the shielding layer to the charge trapping points or leave the charge trapping points. This can be done in particular by Fowler-Nordheim tunneling, similar to a flash memory when charge carriers tunnel towards or away from the floating gate under the influence of an electrostatic field.
  • Applying the write voltage can include applying a constant negative, a constant positive and/or an alternating voltage. Applying the write voltage can be done in particular during a predefined time. In particular, the write voltage can be reset after the predefined time, in particular to an initial value.
  • a non-linear capacitance-voltage curve is set.
  • Setting the non-linear capacitance-voltage curve can in particular comprise applying a bias voltage, in particular a constant bias voltage, to the shielding layer 4.
  • a bias voltage in particular a constant bias voltage
  • applying the bias voltage in particular the charge state of the shielding layer 4 and thus the shielding behavior of the shielding layer can be changed, whereby the capacitive behavior of the memcapacitive component can also be changed.
  • applying the bias voltage can comprise applying a constant voltage in the p-doped region and/or in the n-doped region.
  • the p-doped region and the n-doped region may be connected to a constant voltage or ground during application of the write voltage, and wherein the n- or p-doped region is disconnected from the constant voltage or ground before resetting the write voltage to the initial value.
  • the memcapacitive component is read out in a method step 140.
  • a current state or a charge and/or capacitance value currently stored in the memcapacitive component can be read out in method step 140.
  • the reading can take place in a separate method step in order to read out a parameter value stored in the memcapacitive component or the current state of the memcapacitive component at a later point in time if necessary.
  • the reading can take place in particular via an external capacitor, which can be connected to a connection to one of the electrodes of the memcapacitive component, wherein the readout signal can be measured at the second connection of the capacitor, see Fig. 4 above.
  • Example 1 Arrangement, in particular memcapacitive component, characterized in that the arrangement comprises energetically shallow charge traps for short-term storage of capacitance values and energetically deep charge traps for long-term storage of capacitance values.
  • energetically shallow charge traps can be used for the short-term storage of capacity values and energetically deep traps can be used for the long-term storage of capacity values.
  • Example 2 Arrangement according to Example 1, wherein the traps are realized in a silicon nitride, and wherein deep or shallow traps can be generated depending on the selected growth parameters.
  • the charges in the deep traps require a longer programming time and a higher programming voltage, but can be stored for a longer period of time.
  • the shallow traps require a lower programming time/voltage, but the charges are only stored for a short period of time.
  • Example 3 Arrangement according to examples 1 or 2, characterized in that the memcapacitive component has a non-linearity in the capacitance-voltage curve and the two electrodes are designed such that a short-term storage of capacitance values can take place by means of charge storage on the electrodes.
  • the capacitance-voltage curves can be shifted, thereby storing a new capacitance value.
  • Example 4 Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the memcapacitive component has a non-linearity in the capacitance-voltage curve and, in addition to the two electrodes, also contains a shielding layer with its own connections and a short-term storage of capacitance values can take place by means of charge storage on the shielding layer.
  • the shielding layer can be used to store charges and thus to set a capacitance on the capacitance-voltage curve.
  • Example 5 Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that a further capacitor, which stores a storage voltage for setting the short-term capacitance value, is connected to an electrode of the memcapacitive component, and the capacitor is designed to connect to a switch which connects or disconnects the storage voltage, wherein the other terminal of the capacitor is designed to connect to the readout signal.
  • the additional capacitor can store a certain amount of charge/voltage, which is passed on to the electrode. This can achieve a shift along the capacitance-voltage curve.
  • the switch separates the capacitor from the storage voltage so that the value is stored and the storage voltage can be connected to other memcapacitive components and changed.
  • Example 6 Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that a further capacitor, which stores a storage voltage for setting the short-term capacitance value, is connected to the shielding layer of the memcapacitive component, and the capacitor is designed to be connected to a switch which connects or disconnects the storage voltage, wherein the other terminal of the capacitor is designed to be connected to ground.
  • the capacitor is connected to the shielding layer in order to pass the voltage on to it and to achieve a shift along the capacitance-voltage curve.
  • Example 7 Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the shielding layer, in particular laterally, contains a p-doped region and an n-doped region and the positive or negative writing voltage is designed to connect to an electrode, and the n- or p-doped region is connected to a switch.
  • the shielding layer in particular laterally, contains a p-doped region and an n-doped region and the positive or negative writing voltage is designed to connect to an electrode, and the n- or p-doped region is connected to a switch.
  • this embodiment can be supplemented by a method in which the positive or negative writing voltage is applied to an electrode, the p- and n-doped region is connected to a constant voltage or ground during this time, and the n- or p-doped region is separated from the constant voltage or ground before the writing voltage is reset to the initial value.
  • the p- and n-regions enable hole or electron injection when a negative or positive voltage is applied to the electrode. If the connection from the p-region or n-region to ground is broken after the negative or positive voltage has been applied and the voltage is reset, the injected holes or electrons remain in the shielding layer and are stored. The excess charge in the shielding layer leads to a shift in the capacitance-voltage curve and sets a new capacitance value.
  • Example 8 Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the shielding layer contains a p-doped region and an n-doped region and the positive or negative writing voltage is designed to connect to an electrode and the electrode does not overlap with the n- or p-doped region.
  • this embodiment can be supplemented by a method in which the pin diode is operated in the forward direction when the positive or negative write voltage is applied, and the diode is operated with no voltage or in the reverse direction before the positive or negative write voltage is removed.
  • Example 9 Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the switch is implemented in the form of a field effect transistor in the shielding layer.

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Abstract

L'invention concerne un composant memcapacitif (1) destiné à fonctionner avec des courbes capacité-tension non linéaires (2). Le composant memcapacitif (1) comprend un certain nombre de bornes électriques pour la mise en contact électrique du composant memcapacitif, une première électrode (3a) et une seconde électrode (3b). Le composant memcapacitif (1) comprend également au moins un diélectrique (5a, 5b) disposé entre la première électrode et la seconde électrode. Les bornes électriques, les électrodes (3a, 3b) et/ou l'au moins un diélectrique (5a, 5b) comprennent des points de capture de charge pour capturer des quantités de charge variables, lesdits points de capture de charge formant des puits potentiels de profondeur différente. L'invention concerne également un procédé permettant de faire fonctionner le composant memcapacitif (1).
PCT/DE2024/100445 2023-05-16 2024-05-15 Composant memcapacitif et procédé de fonctionnement du composant memcapacitif Pending WO2024235399A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119922922A (zh) * 2025-04-02 2025-05-02 北京航空航天大学 一种忆容器、制备方法和神经网络并行计算芯片及其应用方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120039114A1 (en) * 2009-06-18 2012-02-16 Alexandre Bratkovski Memcapacitor
US20180268970A1 (en) * 2017-03-20 2018-09-20 Gwangju Institute Of Science And Technology Multi-function electronic device having memristor and memcapacitor and method for manufacturing the same
US20220059161A1 (en) 2019-11-21 2022-02-24 Semron Gmbh Capacitive synaptic component and method for controlling same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120039114A1 (en) * 2009-06-18 2012-02-16 Alexandre Bratkovski Memcapacitor
US20180268970A1 (en) * 2017-03-20 2018-09-20 Gwangju Institute Of Science And Technology Multi-function electronic device having memristor and memcapacitor and method for manufacturing the same
US20220059161A1 (en) 2019-11-21 2022-02-24 Semron Gmbh Capacitive synaptic component and method for controlling same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119922922A (zh) * 2025-04-02 2025-05-02 北京航空航天大学 一种忆容器、制备方法和神经网络并行计算芯片及其应用方法
CN119922922B (zh) * 2025-04-02 2025-07-29 北京航空航天大学 一种忆容器、制备方法和神经网络并行计算芯片及其应用方法

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