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WO2024228089A1 - Module d'affichage et appareil électronique - Google Patents

Module d'affichage et appareil électronique Download PDF

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Publication number
WO2024228089A1
WO2024228089A1 PCT/IB2024/053973 IB2024053973W WO2024228089A1 WO 2024228089 A1 WO2024228089 A1 WO 2024228089A1 IB 2024053973 W IB2024053973 W IB 2024053973W WO 2024228089 A1 WO2024228089 A1 WO 2024228089A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
support
layer
pixel
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/IB2024/053973
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English (en)
Japanese (ja)
Inventor
遠藤秋男
池田寿雄
初見亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202480029095.1A priority Critical patent/CN121039726A/zh
Publication of WO2024228089A1 publication Critical patent/WO2024228089A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/90—Assemblies of multiple devices comprising at least one organic light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • One aspect of the present invention relates to a display module, an electronic device, or a semiconductor device.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of one aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.
  • Patent Document 1 discloses a tri-fold type light-emitting panel. By using this light-emitting panel, it is possible to integrate the functions of multiple electronic devices and create an electronic device with a variable size.
  • one aspect of the present invention has an objective to provide a new display module with excellent convenience, usefulness, or reliability.
  • one objective is to provide a new electronic device with excellent convenience, usefulness, or reliability.
  • one objective is to provide a new display module, a new electronic device, or a new semiconductor device.
  • One aspect of the present invention is a display module having a first support, a second support, a first adhesive layer, a gap, a fluid layer, and a display device.
  • the first support overlaps with the second support, the first support has flexibility, and the second support has higher elasticity than the first support.
  • the first adhesive layer bonds the first support and the second support, the first adhesive layer forms a gap between the first support and the second support, and the gap holds the fluid layer.
  • the fluid layer has fluidity in the range of 0°C or more and 80°C or less, and the fluid layer has a refractive index difference between the fluid layer and the first support that is greater than 0 and less than or equal to 0.2.
  • the display device is sandwiched between a first support and a second support, the display device has a function of displaying toward the first support, and the display device has a first display area, a second display area, and a third display area.
  • the first display area is fixed between the first support and the first adhesive layer, and the second display area is sandwiched between the first display area and the third display area.
  • the second display area can be bent, and the second display area is located inside the gap.
  • the third display area is located inside the gap, and slides inside the gap as the second display area bends.
  • the display device slides inside the gap. Furthermore, as the display device is bent with the first support inward, the second display region and the third display region can slide inside the gap. Furthermore, stress concentration associated with bending is less likely to occur in the display device. Furthermore, because the second display region and the third display region are viewed through a fluid layer in which the difference in refractive index between them and the first support is suppressed, degradation of display quality due to the gap is less likely to occur. As a result, a novel display module with excellent convenience, usefulness, and reliability can be provided.
  • Another aspect of the present invention is the above display module having a second adhesive layer.
  • the second adhesive layer bonds the first support and the first display area, and the second adhesive layer has a refractive index difference between itself and the first support that is greater than 0 and less than or equal to 0.2.
  • the second display region and the third display region can slide inside the gap. Furthermore, stress concentration due to bending is unlikely to occur in the display device. Furthermore, since the first display region is viewed through the second adhesive layer, which has a reduced difference in refractive index with the first support, deterioration of display quality is unlikely to occur. As a result, it is possible to provide a novel display module that is highly convenient, useful, and reliable.
  • Another aspect of the present invention is the above display module having a third support and a third adhesive layer.
  • the second support is sandwiched between the first support and the third support, and the third adhesive layer bonds the second support and the third support together.
  • the third support overlaps the first display area and the second display area, the third support has flexibility, and the third support has lower elasticity than the second support.
  • the third support pulls the second support outward.
  • the second support, pulled by the third support stretches, widening the gap between it and the first support.
  • the gap widens the second display area and the third display area can slide easily inside the gap.
  • stress concentration associated with bending is less likely to occur in the display device.
  • the fluid layer can easily flow.
  • a novel display module with excellent convenience, usefulness, and reliability can be provided.
  • Another aspect of the present invention is the above display module having a fourth support, a fifth support, a fourth adhesive layer, and a fifth adhesive layer.
  • the third support is sandwiched between the second support and the fourth support, and the fourth adhesive layer bonds the third support and the fourth support together.
  • the fourth support overlaps the first display area, and the fourth support has lower flexibility than the first support.
  • the second support is sandwiched between the first support and the fifth support, and the fifth adhesive layer bonds the second support and the fifth support together.
  • the fifth support overlaps the third display area, and the fifth support has lower flexibility than the first support.
  • the display device is the above-mentioned display module, which includes a terminal adjacent to the first display area.
  • Another aspect of the present invention is the above display module, in which the display device has an arithmetic surface roughness of 0.5 nm or more and 20 nm or less.
  • Another aspect of the present invention is the above display module, in which the display device has a layer containing polytetrafluoroethylene on the surface facing the second support.
  • Another aspect of the present invention is the above display module, in which the fluidized layer contains glass beads.
  • the glass beads have a diameter of 1.0 ⁇ m or more and 50 ⁇ m or less, and the difference in refractive index between the glass beads and the first support is greater than 0 and less than 0.2.
  • the second display area and the third display area can easily slide inside the gap.
  • FIG. 9 Another embodiment of the present invention is an electronic device having the above-described display module and a housing. Note that the housing includes a hinge, and the hinge can be bent with the second display area facing inward.
  • the term “light-emitting device” includes an image display device that uses a light-emitting device.
  • the term “light-emitting device” may also include a module in which a connector, such as an anisotropic conductive film or TCP (Tape Carrier Package), is attached to a light-emitting device, a module in which a printed wiring board is provided at the end of a TCP, or a module in which an IC (integrated circuit) is directly mounted on a light-emitting device using the COG (chip on glass) method.
  • a connector such as an anisotropic conductive film or TCP (Tape Carrier Package)
  • TCP Transist Carrier Package
  • COG chip on glass
  • lighting fixtures and the like may have a light-emitting device.
  • a novel display module that is highly convenient, useful, or reliable. Also, according to one aspect of the present invention, it is possible to provide a novel electronic device that is highly convenient, useful, or reliable. Also, it is possible to provide a novel display module. Also, it is possible to provide a novel electronic device.
  • FIGS. 1A and 1B are diagrams illustrating a display module according to an embodiment.
  • 2A and 2B are diagrams illustrating a display module according to an embodiment.
  • FIG. 3 is a diagram illustrating a display module according to an embodiment.
  • 4A to 4C are diagrams illustrating a display module according to an embodiment.
  • 5A and 5B are diagrams illustrating a display module according to an embodiment.
  • 6A to 6D are diagrams illustrating a pixel circuit according to an embodiment.
  • 7A to 7D are diagrams illustrating a pixel circuit according to an embodiment.
  • 8A and 8B are diagrams illustrating a pixel circuit according to an embodiment.
  • 9A and 9B are diagrams illustrating a pixel circuit according to an embodiment.
  • 10A and 10B are diagrams illustrating a drive circuit according to an embodiment.
  • 11A to 11G are diagrams illustrating a pixel according to an embodiment.
  • 12A to 12K are diagrams illustrating a pixel according to an embodiment.
  • 13A to 13C are diagrams illustrating a shift register according to an embodiment.
  • FIG. 14 is a diagram illustrating a signal output circuit according to an embodiment.
  • FIG. 15 is a diagram illustrating a signal output circuit according to an embodiment.
  • FIG. 16 is a diagram illustrating a signal output circuit according to an embodiment.
  • 17A to 17D are diagrams illustrating transistors according to an embodiment.
  • 18A to 18F are diagrams illustrating transistors according to an embodiment.
  • 19A and 19B are diagrams illustrating a transistor according to an embodiment.
  • 20A and 20B are diagrams illustrating a transistor according to an embodiment.
  • 21A to 21D are diagrams illustrating a transistor according to an embodiment.
  • 22A to 22D are diagrams illustrating a transistor according to an embodiment.
  • FIG. 23 is a diagram illustrating a signal output circuit according to an embodiment.
  • 24A and 24B are diagrams illustrating a signal output circuit according to an embodiment.
  • 25A and 25B are diagrams illustrating a signal output circuit according to an embodiment.
  • FIG. 26 is a diagram illustrating a signal output circuit according to an embodiment.
  • FIG. 27 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 28 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 29 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 30 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 31 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 32 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 33 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 34 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 35 is a diagram illustrating a signal output circuit according to an embodiment.
  • FIG. 36 is a diagram for explaining the operation of the shift register according to the embodiment.
  • 37A and 37B are diagrams illustrating an electronic device according to an embodiment.
  • 38A to 38C are diagrams illustrating an electronic device according to an embodiment.
  • a display module includes a first support, a second support, a first adhesive layer, a gap, a fluid layer, and a display device, the first support overlapping the second support, the first support having flexibility, the second support having higher elasticity than the first support, the first adhesive layer bonding the first support and the second support, the first adhesive layer forming a gap between the first support and the second support, and the gap holding the fluid layer.
  • the fluid layer has fluidity in the range of 0°C or more and 80°C or less, and the fluid layer has a refractive index difference between the first support and the fluid layer that is greater than 0 and less than 0.2.
  • the display device is sandwiched between the first support and the second support, the display device has a function of displaying toward the first support, and the display device has a first display region, a second display region, and a third display region.
  • the first display region is fixed between the first support and the first adhesive layer
  • the second display region is sandwiched between the first display region and the third display region
  • the second display region is bendable
  • the second display region is located inside the gap.
  • the third display region is located inside the gap, and the third display region slides inside the gap as the second display region bends.
  • the display device slides inside the gap. Furthermore, as the display device is bent with the first support inward, the second display region and the third display region can slide inside the gap. Furthermore, stress concentration associated with bending is less likely to occur in the display device. Furthermore, because the second display region and the third display region are viewed through a fluid layer in which the difference in refractive index between them and the first support is suppressed, degradation of display quality due to the gap is less likely to occur. As a result, a novel display module with excellent convenience, usefulness, and reliability can be provided.
  • Figure 1A is a front view illustrating the configuration of a display module according to one embodiment of the present invention
  • Figure 1B is a cross-sectional view illustrating the configuration of the display module along the cutting line A1-A2 shown in Figure 1A.
  • Figure 2A is a cross-sectional view that explains in detail a portion of the display module shown in Figure 1B
  • Figure 2B is a cross-sectional view that explains a configuration that is different from the configuration shown in Figure 2A.
  • Display module configuration example 1> One aspect of the present invention is a display module having a support SUP1, a support SUP2, an adhesive layer AD1, a gap GAP, a fluidized layer LIQ (not shown), and a display device 700 (see Figures 1A and 1B).
  • the support SUP1 overlaps with the support SUP2, and the support SUP1 has flexibility.
  • the support SUP1 contains silicon oxide.
  • glass having a thickness of 0.03 mm or more and 0.2 mm or less can be used for the support SUP1.
  • glass having a compressive stress layer formed on the surface can be used for the support SUP1.
  • chemically strengthened glass can be used for the support SUP1.
  • glass whose surface has been treated to exchange sodium ions for potassium ions can be used for the support SUP1.
  • glass that can be repeatedly bent at a radius of curvature of 2 mm or more and 5 mm or less, 10,000 times or more, preferably about 200,000 times, can be used for the support body SUP1.
  • the support SUP2 has higher elasticity than the support SUP 1. In other words, when the same tensile stress is applied to the support SUP1 and the support SUP2, the support SUP2 is more easily stretched than the support SUP1, and the length of a line drawn on the support SUP2 is more easily changed than the length of a line drawn on the support SUP1.
  • a resin having a thickness of 0.1 mm or more and 0.5 mm or less can be used for the support body SUP2.
  • silicone resin ethylene vinyl acetate (EVA) resin, thermoplastic polyurethane elastomer (TPU), etc.
  • EVA ethylene vinyl acetate
  • TPU thermoplastic polyurethane elastomer
  • the adhesive layer AD1 bonds the supports SUP1 and SUP2 together.
  • the adhesive layer AD1 also forms a gap GAP between the supports SUP1 and SUP2, and the gap GAP holds the fluid layer LIQ. In other words, the fluid layer LIQ fills the gap GAP.
  • organic materials such as reactive curing adhesives, photocuring adhesives, thermosetting adhesives and/or anaerobic adhesives can be used for the adhesive layer AD1.
  • adhesives containing epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide, polyvinyl chloride (PVC), polyvinyl butyral (PVB), ethylene vinyl acetate (EVA) resin, etc. can be used for the adhesive layer AD1.
  • the fluidized layer LIQ has fluidity in the range of 0° C. to 80° C.
  • the fluidized layer LIQ has a refractive index difference of more than 0 and not more than 0.2, preferably not more than 0.1, between itself and the support SUP1.
  • glycerol for example, glycerol, immersion oil, etc. can be used in fluidized bed LIQ.
  • Configuration example 1 of display device 700 The display device 700 is sandwiched between the support bodies SUP1 and SUP2, and has a function of displaying information toward the support body SUP1.
  • the display device 700 has a display area 731.
  • the display area 731 has a display area 731A, a display area 731B, and a display area 731C.
  • Display area 731A The display area 731A is fixed between the support SUP1 and the adhesive layer AD1.
  • Display area 731B Moreover, the display area 731B is sandwiched between the display area 731A and the display area 731C, and the display area 731B is located inside the gap GAP.
  • the display area 731B can be bent.
  • Display area 731C The display area 731C is located inside the gap GAP, and the display area 731C slides inside the gap GAP as the display area 731B bends. In other words, the display area 731C moves while sliding inside the gap GAP. It moves by sliding through the fluidized bed.
  • the display module according to one embodiment of the present invention also includes an adhesive layer AD2.
  • the adhesive layer AD2 bonds the support SUP1 and the display region 731A, and has a refractive index difference between the adhesive layer AD2 and the support SUP1 that is greater than 0 and not greater than 0.2, preferably not greater than 0.1.
  • the adhesive layer AD2 is also translucent to visible light.
  • organic materials such as reactive curing adhesives, photocuring adhesives, thermosetting adhesives and/or anaerobic adhesives can be used for the adhesive layer AD2.
  • adhesives containing epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide polyvinyl chloride (PVC), polyvinyl butyral (PVB), ethylene vinyl acetate (EVA) resin, etc. can be used for the adhesive layer AD2.
  • display area 731A even if display area 731A is fixed, display area 731B and display area 731C can slide inside the gap GAP. Furthermore, in the display device 700, stress concentration due to bending is unlikely to occur. Furthermore, because display area 731A is viewed through adhesive layer AD2, which has a reduced difference in refractive index with support body SUP1, deterioration of display quality is unlikely to occur. As a result, it is possible to provide a novel display module that is highly convenient, useful, and reliable.
  • the display module according to one embodiment of the present invention also includes a support SUP3 and an adhesive layer AD3.
  • the support SUP3 sandwiches the support SUP2 between the support SUP1 and the support SUP3, and the adhesive layer AD3 bonds the support SUP2 and the support SUP3 together.
  • organic materials such as reactive curing adhesives, photocuring adhesives, thermosetting adhesives and/or anaerobic adhesives can be used for the adhesive layer AD3.
  • adhesives containing epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide, polyvinyl chloride (PVC), polyvinyl butyral (PVB), ethylene vinyl acetate (EVA) resin, etc. can be used for the adhesive layer AD3.
  • the support body SUP3 overlaps with the display area 731A and the display area 731B, and has flexibility. Furthermore, the support body SUP3 has lower elasticity than the support body SUP2. In other words, when the support body SUP2 and the support body SUP3 are deformed so as to generate the same amount of displacement, a greater stress is generated in the support body SUP3 than in the support body SUP2.
  • a resin having a thickness of 0.1 mm or more and 1 mm or less can be used for the support body SUP3.
  • silicone resin EVA (ethylene vinyl acetate) resin, etc. can be used for the support body SUP3.
  • the support SUP1 As a result, as the support SUP1 is bent inward, a stress ST3 that repels the bending stress is generated, and the support SUP3 pulls the support SUP2 outward. Furthermore, the support SUP2, pulled by the support SUP3, stretches, and the gap between the support SUP1 and itself widens. Furthermore, as the gap widens, the display area 731B and the display area 731C can easily slide inside the gap GAP. Furthermore, in the display device 700, stress concentration associated with bending is less likely to occur. Furthermore, as the gap widens, the fluid layer LIQ can easily flow. As a result, a novel display module with excellent convenience, usefulness, and reliability can be provided.
  • the display module according to one embodiment of the present invention includes a support SUP41, a support SUP42, an adhesive layer AD41, and an adhesive layer AD42.
  • organic materials such as reactive curing adhesives, photocuring adhesives, thermosetting adhesives and/or anaerobic adhesives can be used for the adhesive layers AD41 and AD42.
  • adhesives containing epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide, polyvinyl chloride (PVC), polyvinyl butyral (PVB), ethylene vinyl acetate (EVA) resin, etc. can be used for the adhesive layer AD41 and the adhesive layer AD42.
  • the support SUP41 overlaps the display area 731A, and has lower flexibility than the support SUP1. In other words, when the same bending stress is applied to the support SUP1 and the support SUP41, the support SUP41 is less likely to bend than the support SUP1.
  • ⁇ Support SUP42 ⁇ The support SUP2 is sandwiched between the support SUP1 and the support SUP42, and an adhesive layer AD42 bonds the support SUP2 and the support SUP42 together.
  • the support SUP42 overlaps with the display area 731C, and the support SUP42 has lower flexibility than the support SUP1. In other words, when the same bending stress is applied to the support SUP1 and the support SUP42, the support SUP42 is less likely to bend than the support SUP1.
  • a resin or metal having a thickness of 0.2 mm or more and 0.7 mm or less can be used for the support body SUP3.
  • the display device 700 includes a terminal 519B1.
  • the terminal 519B1 is adjacent to the display area 731A.
  • Terminal 519B1, terminal 519B2, or terminal 519B3 can be electrically connected to, for example, a power line or a drive device.
  • the drive circuit unit DRV1, drive circuit unit DRV2, and touch sensor provided in the display device can be electrically connected to the drive device.
  • the display device 700 has an arithmetic surface roughness of 0.5 nm to 20 nm (see FIG. 2A). This allows, for example, the fluidized layer LIQ to easily enter between the display area 731C and the support SUP2. In addition, it is possible to prevent the display area 731C from sticking to the support SUP2 and becoming difficult to move.
  • the display device 700 includes a layer TEF on the surface facing the support SUP2, and the layer TEF contains polytetrafluoroethylene. This reduces friction between the display area 731C and the support SUP2, for example. It is also possible to prevent the display area 731C from sticking to the support SUP2 and becoming difficult to move.
  • the fluidized bed LIQ contains glass beads GB (see FIG. 2B).
  • the glass beads GB have a diameter of 1.0 ⁇ m or more and 50 ⁇ m or less, and have a refractive index difference between the glass beads GB and the support SUP1 that is greater than 0 and less than 0.2, preferably less than 0.1. This reduces friction between the display area 731C and the support SUP2, for example. It also makes it possible to prevent the display area 731C from sticking to the support SUP2 and becoming difficult to move.
  • display area 731A even if display area 731A is fixed, display area 731B and display area 731C can easily slide inside the gap GAP. As a result, a new display module with excellent convenience, usefulness, and reliability can be provided.
  • Figure 3 is a perspective view explaining the configuration of the display module.
  • Figure 4A is a cross-sectional view illustrating the configuration of a display module.
  • Figures 4B and 4C are cross-sectional views illustrating the configuration of a transistor that can be used as part of Figure 4A.
  • the display module has a display device 700, an IC (integrated circuit), and an FPC (flexible printed circuit board) or a connector (see Figure 3).
  • the display device 700 is electrically connected to the IC 178 and the FPC 177.
  • the FPC 177 receives signals and power from the outside and supplies the signals and power to the display device 700.
  • the connector is a mechanical component that electrically connects conductors, and the conductors can electrically connect the display device 700 to a component to which it is connected.
  • the FPC 177 can be used as the conductor.
  • the connector can also disconnect the display device 700 from the component to which it is connected.
  • the display module has an IC178.
  • the IC178 can be provided on the substrate 17 using a COG (chip on glass) method or the like.
  • the IC178 can be provided on the FPC using a COF (chip on film) method or the like.
  • a gate driver circuit or a source driver circuit or the like can be used for the IC178.
  • the display device 700 includes a display unit 37b, a connection unit 140, a drive circuit unit DRV1, and wiring 165.
  • the display device 700 also includes a substrate 17 and a substrate 18, and the substrate 18 is bonded to the substrate 17. Both the substrate 17 and the substrate 18 are flexible.
  • the display device 700 is flexible. In other words, the display device 700 is a flexible display.
  • the display device 700 has one or more connection parts 140.
  • the connection part 140 can be provided outside the display part 37b.
  • the connection part 140 can be provided along one side of the display part 37b.
  • the connection part 140 can be provided so as to surround multiple sides, for example, all four sides.
  • the common electrode of the light-emitting device is electrically connected to a conductive layer, and the conductive layer supplies a predetermined potential to the common electrode.
  • Wiring 165 receives signals and power from FPC 177 or IC 178. Wiring 165 supplies signals and power to display unit 37b and drive circuit unit DRV1.
  • a gate driver circuit can be used for the drive circuit section DRV1.
  • the display device 700 has a transistor 201, a transistor 205, a light-emitting device 63R, a light-emitting device 63G, and a light-emitting device 63B, etc. (see FIG. 4A).
  • the light-emitting device 63R emits red light 83R
  • the light-emitting device 63G emits green light 83G
  • the light-emitting device 63B emits blue light 83B.
  • Various optical components can be arranged on the outside of the substrate 18.
  • a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light-collecting film can be arranged.
  • the light-emitting device has a conductive layer 171, which functions as a pixel electrode.
  • the conductive layer 171 has a recess, which overlaps with openings provided in the insulating layer 214, the insulating layer 215, and the insulating layer 213.
  • the transistor 205 also has a conductive layer 222b, which is electrically connected to the conductive layer 171.
  • the display device 700 has an insulating layer 272.
  • the insulating layer 272 covers the ends of the conductive layer 171 and fills the recesses of the conductive layer 171 (see FIG. 4A).
  • the display device 700 has a protective layer 273 and an adhesive layer 142.
  • the protective layer 273 covers the light-emitting device 63R, the light-emitting device 63G, and the light-emitting device 63B.
  • the adhesive layer 142 bonds the protective layer 273 and the substrate 18.
  • the adhesive layer 142 fills the space between the substrate 18 and the protective layer 273.
  • the adhesive layer 142 may be formed in a frame shape so as not to overlap the light-emitting device, and a resin different from the adhesive layer 142 may be filled in the area surrounded by the adhesive layer 142, the substrate 18, and the protective layer 273.
  • organic materials such as reactive curing adhesives, photocuring adhesives, thermosetting adhesives and/or anaerobic adhesives can be used for the adhesive layer 142.
  • adhesives containing epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide, polyvinyl chloride (PVC), polyvinyl butyral (PVB), ethylene vinyl acetate (EVA) resin, etc. can be used for the adhesive layer 142.
  • the display device 700 has a connection portion 140, which includes a conductive layer 168.
  • the conductive layer 168 is supplied with a power supply potential.
  • the light-emitting device also has a conductive layer 173, which is electrically connected to the conductive layer 173 and is supplied with a power supply potential.
  • the conductive layer 173 functions as a common electrode.
  • the conductive layer 171 and the conductive layer 168 can be formed by processing one conductive film.
  • the display device 700 is a top emission type.
  • the light emitting device emits light toward the substrate 18 side.
  • the conductive layer 171 contains a material that reflects visible light, and the conductive layer 173 transmits visible light.
  • the display device 700 has an adhesive layer 56 and an insulating layer 162.
  • the adhesive layer 56 bonds the insulating layer 162 to the substrate 17.
  • the material that can be used for the adhesive layer 142 can be used for the adhesive layer 56.
  • An insulating layer 162, an insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided on the substrate 17 in this order. Note that the number of insulating layers is not limited, and each may be a single layer or two or more layers. In addition, the transistor 201 and the transistor 205 are provided on the insulating layer 162.
  • an inorganic insulating film can be used for the insulating layer 162, the insulating layer 211, the insulating layer 213, and the insulating layer 215.
  • a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, or the like can be used.
  • a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, or the like may also be used. Two or more of the above insulating films may also be stacked.
  • the insulating layer 215 and the insulating layer 214 cover the transistor.
  • the insulating layer 214 functions as a planarization layer.
  • an organic insulating layer can be suitably used for the insulating layer 214.
  • acrylic resin, polyimide, epoxy resin, polyamide, polyimideamide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins can be used for the organic insulating layer.
  • a laminated structure of an organic insulating layer and an inorganic insulating layer can be used for the insulating layer 214. This allows the outermost layer of the insulating layer 214 to be used as an etching protection layer. For example, it is possible to suppress the phenomenon in which recesses are formed in the insulating layer 214 when the conductive layer 171 is processed into a predetermined shape.
  • Transistor 201 Transistor 205
  • the transistor 201 and the transistor 205 can be manufactured using the same material and in the same process.
  • an insulating layer 162 is formed on a fabrication substrate, and each transistor, light-emitting device, etc. are formed on the insulating layer 162.
  • an adhesive layer 142 is formed on the light-emitting device, and the fabrication substrate and substrate 18 are bonded together using the adhesive layer 142.
  • the fabrication substrate is separated from the insulating layer 162 to expose the surface of the insulating layer 162.
  • an adhesive layer 56 is formed on the exposed surface of the insulating layer 162, and the insulating layer 162 and substrate 17 are bonded together using the adhesive layer 56. In this way, each component formed on the fabrication substrate can be transferred onto the substrate 17 to fabricate the display device 700.
  • the transistor 201 and the transistor 205 have a conductive layer 221, an insulating layer 211, a conductive layer 222a and a conductive layer 222b, a semiconductor layer 231, an insulating layer 213, and a conductive layer 223.
  • the insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231.
  • the conductive layer 221 functions as a gate, and the insulating layer 211 functions as a first gate insulating layer.
  • the conductive layer 222a and the conductive layer 222b function as a source and a drain.
  • the insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.
  • the conductive layer 223 functions as a gate, and the insulating layer 213 functions as a second gate insulating layer.
  • the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.
  • the structure of the transistor included in the display device of this embodiment is not particularly limited.
  • a planar type transistor, a staggered type transistor, an inverted staggered type transistor, or the like can be used.
  • either a top-gate type or a bottom-gate type transistor structure may be used.
  • a gate may be provided above and below a semiconductor layer in which a channel is formed.
  • Transistor 201 and transistor 205 are configured to sandwich a semiconductor layer in which a channel is formed between two gates.
  • the two gates may be connected and the same signal may be supplied to drive the transistor.
  • the threshold voltage of the transistor may be controlled by supplying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.
  • the crystallinity of the semiconductor layer of the transistor is not particularly limited, and any of an amorphous semiconductor and a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the semiconductor layer of the transistor preferably contains a metal oxide.
  • an OS transistor as the transistor included in the display device of this embodiment.
  • the metal oxide preferably has two or three selected from indium, element M, and zinc.
  • the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M is preferably one or more selected from aluminum, gallium, tin, and yttrium.
  • the metal oxide used in the semiconductor layer it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO).
  • an oxide containing indium, tin, and zinc also referred to as ITZO (registered trademark)
  • ITZO registered trademark
  • it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) also referred to as IAZO
  • it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) also referred to as IAGZO.
  • the metal oxide used in the semiconductor layer is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the semiconductor layer may have two or more metal oxide layers with different compositions.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • crystalline oxide semiconductors examples include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS.
  • a transistor using silicon in the channel formation region may be used.
  • silicon examples include single crystal silicon, polycrystalline silicon, and amorphous silicon.
  • a transistor having low temperature polysilicon (LTPS: Low Temperature Polysilicon) in the semiconductor layer also called an LTPS transistor
  • LTPS transistors have high field effect mobility and good frequency characteristics.
  • Si transistors such as LTPS transistors
  • circuits that need to be driven at high frequencies can be built on the same substrate as the display unit. This simplifies the external circuits mounted on the display device, reducing component and mounting costs.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • the leakage current between the source and drain of an OS transistor in an off state (also called off-state current) is extremely small, and the charge accumulated in a capacitor connected in series with the transistor can be held for a long period of time.
  • the use of an OS transistor can reduce the power consumption of a display device.
  • the OS transistor when the transistor is driven in the saturation region, the OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by controlling the gate-source voltage. This makes it possible to control the amount of current flowing through the light-emitting device. This allows the gradation in the pixel circuit to be increased.
  • an OS transistor can flow a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. For this reason, by using an OS transistor as a driving transistor, a stable current can be flowed to the light-emitting device, for example, even when the current-voltage characteristics of the light-emitting device vary. In other words, when the OS transistor is driven in the saturation region, the source-drain current hardly changes even when the source-drain voltage is increased. Therefore, the light emission luminance of the light-emitting device can be stabilized.
  • an OS transistor as the driving transistor included in the pixel circuit, it is possible to suppress black floating, increase light emission luminance, achieve multiple gradations, and suppress variation in light-emitting devices.
  • the transistors in the drive circuit unit DRV1 and the transistors in the display area 731 may have the same structure or different structures.
  • the structures of the multiple transistors in the drive circuit unit DRV1 may all be the same, or there may be two or more types.
  • the structures of the multiple transistors in the display area 731 may all be the same, or there may be two or more types.
  • All of the transistors in the display region 731 may be OS transistors, or all of the transistors in the display region 731 may be Si transistors. In addition, some of the transistors in the display region 731 may be OS transistors and the rest may be Si transistors.
  • LTPS transistor For example, by using both an LTPS transistor and an OS transistor in the display region 731, a display device with low power consumption and high driving capability can be realized.
  • a configuration in which an LTPS transistor and an OS transistor are combined is sometimes called LTPO.
  • an OS transistor it is preferable to use an OS transistor as a transistor that functions as a switch for controlling the conduction/non-conduction of wiring, and to use an LTPS transistor as a transistor for controlling current.
  • one of the transistors in the display region 731 functions as a transistor for controlling the current flowing through the light-emitting device, and can be called a driving transistor.
  • One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting device. It is preferable to use an LTPS transistor as the driving transistor. This allows the current flowing through the light-emitting device to be increased.
  • the other transistor in the display region 731 functions as a switch for controlling pixel selection/non-selection and can be called a selection transistor.
  • the gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a signal line. It is preferable to use an OS transistor as the selection transistor. This allows the gradation of the pixel to be maintained even if the frame frequency is significantly reduced (for example, 1 fps or less), so that power consumption can be reduced by stopping the driver when displaying a still image.
  • the display device of one embodiment of the present invention can combine a high aperture ratio, high definition, high display quality, and low power consumption.
  • the display device of one embodiment of the present invention has a structure including an OS transistor and a light-emitting device having an MML (metal maskless) structure.
  • MML metal maskless
  • the leakage current that may flow through the transistor and the lateral leakage current between the light-emitting devices are extremely low, it is possible to achieve a display with extremely low light leakage (so-called black floating) that may occur during black display, for example.
  • light-emitting devices with an MML structure can greatly reduce the current flowing between adjacent light-emitting devices.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • Transistor 209, Transistor 210 are cross-sectional views illustrating other examples of the cross-sectional structure of a transistor that can be used in the display device 700.
  • FIG. 1 is a diagrammatic representation of a transistor that can be used in the display device 700.
  • the transistor 209 and the transistor 210 have a conductive layer 221, an insulating layer 211, a semiconductor layer 231, a conductive layer 222a, a conductive layer 222b, an insulating layer 225, a conductive layer 223, and an insulating layer 215.
  • the semiconductor layer 231 has a channel formation region 231i and a pair of low resistance regions 231n.
  • the insulating layer 211 is located between the conductive layer 221 and the channel formation region 231i.
  • the conductive layer 221 functions as a gate, and the insulating layer 211 functions as a first gate insulating layer.
  • the insulating layer 225 is located at least between the conductive layer 223 and the channel formation region 231i.
  • the conductive layer 223 functions as a gate, and the insulating layer 225 functions as a second gate insulating layer.
  • the conductive layer 222a is electrically connected to one of the pair of low resistance regions 231n, and the conductive layer 222b is electrically connected to the other of the pair of low resistance regions 231n.
  • Insulating layer 215 covers conductive layer 223. Insulating layer 218 further covers the transistor.
  • the insulating layer 225 covers the top surface and side surfaces of the semiconductor layer 231 (see FIG. 4B ).
  • the insulating layer 225 and the insulating layer 215 have openings, and the conductive layers 222a and 222b are electrically connected to the low-resistance region 231n in the openings.
  • One of the conductive layers 222a and 222b functions as a source, and the other functions as a drain.
  • the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 but does not overlap with the low-resistance region 231n (see FIG. 4C ).
  • the insulating layer 225 can be processed into a predetermined shape by using the conductive layer 223 as a mask.
  • the insulating layer 215 covers the insulating layer 225 and the conductive layer 223.
  • the insulating layer 215 has an opening, and the conductive layer 222a and the conductive layer 222b are electrically connected to the low-resistance region 231n.
  • connection portion 204 is provided on the substrate 17.
  • the connection portion 204 includes a conductive layer 166, and the conductive layer 166 is electrically connected to the wiring 165. Note that the connection portion 204 does not overlap with the substrate 18, and the conductive layer 166 is exposed. Note that the conductive layer 166 and the conductive layer 171 can be formed by processing one conductive film.
  • the conductive layer 166 is electrically connected to the FPC 177 via a connection layer 242.
  • an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used for the connection layer 242.
  • FIG. 5A shows a perspective view of display device 700.
  • Display device 700 has a configuration in which substrate 152 and substrate 148 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 700 has a display unit 235, a connection unit 140, a drive circuit unit DRV1, a drive circuit unit DRV2, wiring 165, etc.
  • FIG. 5A shows an example in which an IC 178 and an FPC 179 are mounted on the display device 700. Therefore, the configuration shown in FIG. 5A can also be said to be a display module having the display device 700, an IC (integrated circuit), and an FPC.
  • connection portion 140 is provided on the outside of the display portion 235.
  • the connection portion 140 can be provided along one or more sides of the display portion 235. There may be one or more connection portions 140.
  • FIG. 5A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion.
  • the connection portion 140 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode.
  • the wiring 165 has a function of supplying signals and power to the display unit 235, the driving circuit unit DRV1, and the driving circuit unit DRV2.
  • the signals and power are input to the wiring 165 from the outside via the FPC 179, or are input to the wiring 165 from the IC 178.
  • FIG. 5A shows an example in which an IC 178 is provided on a substrate 148 by a COG (chip on glass) method or a COF (chip on film) method.
  • the IC 178 may have, for example, a scanning line driver circuit or a signal line driver circuit.
  • the display device 700 and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method or the like.
  • the display unit 235 has a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n is an integer of 1 or more).
  • the plurality of pixels 230 are further classified into, for example, pixels 230a, 230b, and 230c.
  • the pixels 230a, 230b, and 230c each have a function of emitting light of a different color.
  • the pixel 230a may have a function of emitting red (R) light
  • the pixel 230b may have a function of emitting green (G) light
  • the pixel 230c may have a function of emitting blue (B) light.
  • the pixel 230a may have a function of emitting yellow (Y) light
  • the pixel 230b may have a function of emitting cyan (C) light
  • the pixel 230c may have a function of emitting magenta (M) light.
  • the pixel 230 functions as a subpixel.
  • the display device 700 shown in FIG. 5A shows an example in which the pixels 230 functioning as subpixels are arranged in a stripe array.
  • the number of subpixels constituting one pixel 240 is not limited to three, and may be four or more.
  • the pixel may have four subpixels that emit R, G, B, and white (W) light.
  • the pixel may have four subpixels that emit R, G, B, and Y light.
  • FIG. 5B is a block diagram illustrating the display device 700.
  • the display device 700 has a display unit 235, a drive circuit unit DRV1, and a drive circuit unit DRV2.
  • the pixel 230 in the first row and nth column is indicated as pixel 230[1,n]
  • the pixel 230 in the mth row and first column is indicated as pixel 230[m,1]
  • the pixel 230 in the mth row and nth column is indicated as pixel 230[m,n].
  • any pixel 230 included in the display unit 235 may be indicated as pixel 230[r,s].
  • r is an integer between 1 and m
  • s is an integer between 1 and n.
  • the circuit included in the drive circuit unit DRV1 functions as, for example, a scanning line drive circuit.
  • the circuit included in the drive circuit unit DRV2 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the drive circuit unit DRV1 across the display unit 235. Note that some kind of circuit may be provided at a position facing the drive circuit unit DRV2 across the display unit 235. Note that the circuits included in the drive circuit unit DRV1 and the drive circuit unit DRV2 are collectively referred to as the peripheral drive circuit 233.
  • the driving circuit unit DRV1 which functions as a scanning line driving circuit, has the function of selecting the pixels 230 row by row.
  • the driving circuit unit DRV1 sequentially selects the pixels 230 arranged in the first row to the pixels 230 arranged in the mth row, and writes an image signal supplied from the driving circuit unit DRV2 to the selected pixels 230, thereby rewriting the image displayed on the display unit 235.
  • the frame period is the period required to rewrite the image displayed on the display unit 235 once.
  • the number of times the image is rewritten per second is called the "frame frequency.”
  • the frame frequency is equivalent to the reciprocal of the frame period. Note that the "frame frequency” is sometimes called the "drive frequency.”
  • the frame frequency can be set to 60 Hz or higher, preferably 120 Hz or higher, and more preferably 240 Hz or higher.
  • the power consumption of the display device 700 increases.
  • the peripheral drive circuit 233 can use various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit.
  • the peripheral driver circuit 233 can include a transistor 10 according to one embodiment of the present invention or the like.
  • the shift register circuit can include a shift register 100, a signal output circuit 110, or the like according to one embodiment of the present invention. Note that structures of the transistor 10, the shift register 100, and the signal output circuit 110 will be described in detail in Embodiment 4.
  • the transistor included in the peripheral driver circuit and the transistor included in the pixel 230 may be formed in the same process. By using the transistor 10 according to one embodiment of the present invention or the like for the peripheral driver circuit 233, the area occupied by the peripheral driver circuit 233 can be reduced.
  • the display device 700 also has m wirings 236 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the drive circuit unit DRV1, and n wirings 237 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the drive circuit unit DRV2.
  • FIG. 5B shows an example in which wiring 236 and wiring 237 are connected to pixel 230.
  • wiring 236 and wiring 237 are just an example, and wirings connected to pixel 230 are not limited to wiring 236 and wiring 237.
  • the display device 700 can be of various forms or have various display elements.
  • the display element include an EL (electroluminescence) element (organic EL element, inorganic EL element, or EL element including organic and inorganic materials), an LED (white LED, red LED, green LED, blue LED, etc.), a transistor (a transistor that emits light according to a current), an electron emission element, a liquid crystal element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a display element using MEMS (microelectromechanical systems), a digital micromirror device (DMD), a DMS (digital micro shutter), a MIRASOL (registered trademark), an IMOD (interferometric modulation) element, a shutter type MEMS display element, an optical interference type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element using carbon nanotubes, and the like, and have a display medium whose contrast, brightness,
  • An example of a display device using an EL element is an EL display.
  • An example of a display device using an electron-emitting element is a field emission display (FED) or an SED-type flat display (SED: Surface-conduction Electron-emitter Display).
  • An example of a display device using quantum dots is a quantum dot display.
  • An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display).
  • An example of a display device using electronic ink, electronic liquid powder (registered trademark), or electrophoretic elements is electronic paper.
  • the display device may be a plasma display panel (PDP).
  • a part or all of the pixel electrodes can be made to function as reflective electrodes.
  • a part or all of the pixel electrodes can be made to include aluminum, silver, etc.
  • graphene or graphite may be disposed under the electrode of the LED or the nitride semiconductor.
  • a multilayer film may be formed by stacking multiple layers of graphene or graphite.
  • a nitride semiconductor for example, an n-type GaN semiconductor layer having crystals
  • an LED can be constructed by providing a p-type GaN semiconductor layer having crystals thereon.
  • An AlN layer may be provided between the graphene or graphite and the n-type GaN semiconductor layer having crystals.
  • the GaN semiconductor layer of the LED may be formed by MOCVD.
  • the GaN semiconductor layer of the LED can also be formed by sputtering.
  • the pixel 230 includes a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, pixel circuit 51F, pixel circuit 51G, pixel circuit 51H, pixel circuit 51I, pixel circuit 51J, pixel circuit 51K, or pixel circuit 51L) and a light-emitting element 61 or a liquid crystal element 62.
  • pixel circuit 51 pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, pixel circuit 51F, pixel circuit 51G, pixel circuit 51H, pixel circuit 51I, pixel circuit 51J, pixel circuit 51K, or pixel circuit 51L
  • the light-emitting element (also called a light-emitting device) described in this embodiment refers to a self-emitting display element such as an organic EL element (also called an OLED (Organic Light Emitting Diode)).
  • the light-emitting element electrically connected to the pixel circuit can be a self-emitting light-emitting element such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), a semiconductor laser, etc.
  • the pixel circuit 51A shown in FIG. 6A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitance 53.
  • One of the source or drain of transistor 52A is electrically connected to wiring SL, and the gate of transistor 52A is electrically connected to wiring GL.
  • One of the source or drain of transistor 52A is electrically connected to the gate of transistor 52B and one terminal of capacitor 53.
  • One of the source or drain of transistor 52B is electrically connected to wiring ANO.
  • the other of the source or drain of transistor 52B is electrically connected to the other terminal of capacitor 53 and the anode of light-emitting element 61.
  • the cathode of light-emitting element 61 is electrically connected to wiring VCOM.
  • the region to which the other of the source or drain of transistor 52A, the gate of transistor 52B, and one terminal of capacitor 53 are electrically connected functions as node ND.
  • the wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 237.
  • the wiring VCOM is a wiring that provides a potential for supplying a current to the light-emitting element 61.
  • the transistor 52A has a function of controlling the conductive state or non-conductive state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.
  • an image signal is supplied from the wiring SL to the node ND. Then, by turning off the transistor 52A, the image signal is held in the node ND.
  • a transistor with a low off-state current it is preferable to use a transistor with a low off-state current as the transistor 52A.
  • an OS transistor is preferable to use as the transistor 52A.
  • image display on the display unit 235 can be maintained even if the frame frequency is significantly reduced (for example, 1 Hz or less). For example, when displaying a still image that does not need to be rewritten every frame, it is possible to continue displaying the image even if the operation of the peripheral driver circuit 233 is stopped.
  • Such a driving method in which the operation of the peripheral driver circuit 233 is stopped while a still image is being displayed is also called "idling stop driving.” By performing idling stop driving, the power consumption of the display device can be reduced.
  • Transistor 52B has a function of controlling the amount of current flowing through light-emitting element 61.
  • Capacitor 53 has a function of holding the gate potential of transistor 52B. The intensity of light emitted by light-emitting element 61 is controlled according to an image signal supplied to the gate (node ND) of transistor 52B.
  • the pixel circuit 51B shown in FIG. 6B is a 3Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, and a capacitance 53.
  • the pixel circuit 51B shown in FIG. 6B has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in FIG. 6A.
  • One of the source and drain of transistor 52C is electrically connected to the other of the source and drain of transistor 52B.
  • the gate of transistor 52C is electrically connected to wiring GL.
  • the other of the source and drain of transistor 52C is electrically connected to wiring V0.
  • a reference potential is supplied to wiring V0.
  • Transistor 52C has a function of controlling the conductive or non-conductive state between the other of the source or drain of transistor 52B and wiring V0 based on the potential of wiring GL.
  • Wiring V0 is a wiring for providing a reference potential.
  • the reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source potential of transistor 52B.
  • the wiring V0 can be used to obtain a current value that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside.
  • the current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.
  • Pixel circuit 51C shown in FIG. 6C is an example in which transistors having back gates and electrically connected to the gates are used as transistors 52A and 52B of pixel circuit 51A.
  • Pixel circuit 51D shown in FIG. 6D is an example in which the same transistors are used in pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors having gates and back gates electrically connected to each other are used for all transistors here, this is not limited thereto. Also, transistors having gates and back gates and electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gate or the back gate is electrically connected to the source.
  • Pixel circuit 51E shown in FIG. 7A has a configuration in which transistor 52D is added to pixel circuit 51B shown in FIG. 6B.
  • Pixel circuit 51E shown in FIG. 7A is a 4Tr1C type pixel circuit having transistor 52A, transistor 52B, transistor 52C, transistor 52D, and capacitance 53.
  • One of the source or drain of transistor 52D is electrically connected to node ND, and the other is electrically connected to wiring V0.
  • wiring GL1, wiring GL2, and wiring GL3 are electrically connected to the pixel circuit 51E.
  • Wiring GL1 is electrically connected to the gate of transistor 52A
  • wiring GL2 is electrically connected to the gate of transistor 52C
  • wiring GL3 is electrically connected to the gate of transistor 52D.
  • wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL.
  • the number of wirings GL is not limited to one, and may be multiple.
  • transistor 52B By simultaneously turning on transistors 52C and 52D, the source and gate of transistor 52B have the same potential, and transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through light-emitting element 61.
  • Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternated.
  • the pixel circuit 51F shown in FIG. 7B is an example in which a capacitance 53A is added to the pixel circuit 51E.
  • the capacitance 53A functions as a storage capacitance.
  • the pixel circuit 51E shown in FIG. 7A is a 4Tr1C type pixel circuit.
  • the pixel circuit 51F shown in FIG. 7B is a 4Tr2C type pixel circuit.
  • Pixel circuit 51G shown in FIG. 7C and pixel circuit 51H shown in FIG. 7D are examples of pixel circuit 51E and pixel circuit 51F, respectively, to which a transistor having a backgate is applied.
  • Transistors 52A, 52C, and 52D are transistors in which the gate and backgate are electrically connected, and transistor 52B is a transistor in which either the gate or the backgate is electrically connected to the source.
  • the pixel circuit 51I shown in FIG. 8A is a 6Tr1C type pixel circuit having transistor 52A, transistor 52B, transistor 52C, transistor 52D, transistor 52E, transistor 52F, and capacitance 53.
  • One of the source or drain of transistor 52A is electrically connected to wiring SL, and the gate of transistor 52A is electrically connected to wiring GL1.
  • One of the source or drain of transistor 52D is electrically connected to wiring ANO, and the gate of transistor 52D is electrically connected to wiring GL2.
  • the other of the source or drain of transistor 52D is electrically connected to one of the source or drain of transistor 52B.
  • the other of the source or drain of transistor 52B is electrically connected to the other of the source or drain of transistor 52A and one of the source or drain of transistor 52F.
  • the gate of transistor 52F is electrically connected to wiring GL3.
  • One of the source or drain of transistor 52E is electrically connected to the other of the source or drain of transistor 52D and one of the source or drain of transistor 52B.
  • the other of the source or drain of transistor 52E is electrically connected to the gate of transistor 52B and one terminal of capacitor 53.
  • the other terminal of capacitor 53 is electrically connected to the other of the source or drain of transistor 52F, the anode of light-emitting element 61, and one of the source or drain of transistor 52C.
  • the gate of transistor 52E and the gate of transistor 52C are electrically connected to wiring GL4.
  • the other of the source and drain of transistor 52C is electrically connected to wiring V0.
  • a region to which the other of the source and drain of transistor 52E, the gate of transistor 52B, and one terminal of capacitor 53 are electrically connected functions as a node ND.
  • Transistors 52A, 52C, 52D, 52E, and 52F are transistors in which the gate and the back gate are electrically connected, and transistor 52B is a transistor in which the back gate is electrically connected to the other of the source and the drain.
  • Transistor 10 according to one embodiment of the present invention can be used as transistor 52A, transistor 52C, transistor 52D, transistor 52E, and transistor 52F. Transistor 10 according to one embodiment of the present invention can also be used as transistor 52B.
  • the pixel 230 shown in FIG. 9A includes a pixel circuit 51K and a liquid crystal element 62.
  • the pixel circuit 51K also includes a transistor 52A and a capacitor 53.
  • one of the source and drain of the transistor 52A is electrically connected to a wiring SL, and the gate of the transistor 52A is electrically connected to a wiring GL.
  • the other of the source and drain of the transistor 52A is electrically connected to one terminal of the capacitor 53 and the liquid crystal element 62.
  • the other terminal of the capacitor 53 is electrically connected to a wiring VCOM.
  • the region to which the other of the source and drain of the transistor 52A, one terminal of the capacitor 53, and the liquid crystal element 62 are electrically connected functions as a node ND.
  • the orientation state of the liquid crystal element 62 is set by data written to the node ND.
  • the driving method of a display device having a liquid crystal element 62 includes, for example, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, VA mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used.
  • the display device can be driven using ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, etc.
  • ECB Electrode Controlled Birefringence
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • guest-host mode etc.
  • the present invention is not limited to these, and various liquid crystal elements and driving methods thereof can be used.
  • thermotropic liquid crystals low molecular weight liquid crystals
  • polymer liquid crystals polymer-dispersed liquid crystals
  • ferroelectric liquid crystals antiferroelectric liquid crystals, etc.
  • These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, etc., depending on the conditions.
  • liquid crystals showing a blue phase without using an alignment film may be used.
  • the blue phase is one of the liquid crystal phases, and is a phase that appears just before the cholesteric phase transitions to the isotropic phase when the temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used in the liquid crystal layer to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require alignment processing, and has small viewing angle dependency.
  • rubbing processing is also not required, so electrostatic breakdown caused by rubbing processing can be prevented, and defects and damage to liquid crystal display devices during the manufacturing process can be reduced. This makes it possible to improve the productivity of liquid crystal display devices.
  • a method known as multi-domain or multi-domain design can be used, in which a pixel is divided into several regions (subpixels) and the molecules are tilted in different directions in each region.
  • the liquid crystal material has a resistivity of 1 ⁇ 10 9 ⁇ cm or more, preferably 1 ⁇ 10 11 ⁇ cm or more, and more preferably 1 ⁇ 10 12 ⁇ cm or more. Note that the resistivity value in this specification is a value measured at 20° C.
  • pixel 230 may have pixel circuit 51L instead of pixel circuit 51K.
  • Pixel circuit 51L has transistor 52A with a back gate.
  • transistor 52A shown in FIG. 9B the gate is electrically connected to the back gate. Therefore, the gate and back gate are always at the same potential.
  • the area occupied by the pixel circuit can be reduced.
  • the resolution of the display device can be improved.
  • a display device having a resolution of 1000 ppi or more, preferably 2000 ppi or more, more preferably 3000 ppi or more, even more preferably 4000 ppi or more, even more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 10000 ppi or less, 9000 ppi or less, or 8000 ppi or less can be realized.
  • the display device by reducing the area occupied by the pixel circuit, it is possible to increase the number of pixels (increase the resolution) of the display device. For example, it is possible to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).
  • HD high resolution
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K2K 3840 x 2160 pixels
  • 8K4K 8K4K
  • the display quality of the display device can be improved. Furthermore, in a bottom-emission display device using an EL element, the aperture ratio of the pixel can be increased. A pixel with a high aperture ratio can emit light with the same luminance as a pixel with a low aperture ratio, but with a lower current density than a pixel with a low aperture ratio. Therefore, the reliability of the display device can be improved.
  • FIG. 10A shows a configuration example of the driver circuit unit DRV2.
  • the driver circuit unit DRV2 has a shift register 512, a latch circuit 513, and a buffer 514.
  • a wiring 237[1], a wiring 237[2], a wiring 237[3], and a wiring 237[n] are shown as the wiring 237.
  • FIG. 10B shows a configuration example of the driver circuit unit DRV1.
  • the driver circuit unit DRV1 has a shift register 522 and a buffer 523.
  • a wiring 236[1], a wiring 236[2], a wiring 236[3], and a wiring 236[n] are shown as the wiring 236.
  • a start pulse SP, a signal CLK, etc. are input to the shift register 512 and the shift register 522.
  • the shift register 100 disclosed in the above embodiment can be used as the shift register 512 and the shift register 522.
  • ⁇ Pixel layout> 11A to 11G and 12A to 12K pixel layouts different from that of FIG. 5A will be mainly described.
  • the arrangement of sub-pixels There is no particular limitation on the arrangement of sub-pixels, and various pixel layouts can be applied. Examples of the arrangement of sub-pixels include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • planar shapes of the subpixels shown in Figures 5A, 11A to 11G, and 12A to 12K correspond to the planar shapes of the light-emitting regions.
  • the planar shape of the subpixel may be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, or a circle.
  • the pixel circuit 51 of the subpixel may be arranged so as to overlap the light-emitting region, or may be arranged outside the light-emitting region.
  • the pixel 240 shown in FIG. 11A has an S-stripe arrangement.
  • the pixel 240 shown in FIG. 11A is composed of three types of sub-pixels: pixel 230a, pixel 230b, and pixel 230c.
  • the pixel 240 shown in FIG. 11B has a pixel 230a having a planar shape that is approximately trapezoidal with rounded corners, a pixel 230b having a planar shape that is approximately triangular with rounded corners, and a pixel 230c having a planar shape that is approximately rectangular or hexagonal with rounded corners. Pixel 230c also has a larger light-emitting area than pixel 230b. In this way, the shape and size of each sub-pixel can be determined independently. For example, the more reliable the light-emitting device a sub-pixel has, the smaller the size can be.
  • FIG. 11C shows an example in which pixel 240A having pixels 230a and 230b and pixel 240B having pixels 230b and 230c are arranged alternately.
  • Pixel 240A and pixel 240B shown in Figures 11D to 11F are arranged in a delta arrangement.
  • Pixel 240A has two subpixels (pixel 230a and pixel 230b) in the top row (first row) and one subpixel (pixel 230c) in the bottom row (second row).
  • Pixel 240B has one subpixel (pixel 230c) in the top row (first row) and two subpixels (pixel 230a and pixel 230b) in the bottom row (second row).
  • Figure 11D shows an example in which each subpixel has a generally rectangular planar shape with rounded corners
  • Figure 11E shows an example in which each subpixel has a circular planar shape
  • Figure 11F shows an example in which each subpixel has a generally hexagonal planar shape.
  • each subpixel is arranged inside a close-packed hexagonal region.
  • each subpixel is arranged so that it is surrounded by six other subpixels.
  • subpixels that emit light of the same color are arranged so that they are not adjacent to each other. For example, when focusing on pixel 230a, three pixels 230b and three pixels 230c are arranged alternately to surround pixel 230a.
  • Figure 11G shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, in a plan view, the positions of the top sides of two subpixels (e.g., pixels 230a and 230b, or pixels 230b and 230c) aligned in the row direction are misaligned.
  • two subpixels e.g., pixels 230a and 230b, or pixels 230b and 230c
  • pixel 230a is a subpixel R that emits red light
  • pixel 230b is a subpixel G that emits green light
  • pixel 230c is a subpixel B that emits blue light.
  • the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their order of arrangement can be determined appropriately.
  • pixel 230b may be a subpixel R that emits red light
  • pixel 230a may be a subpixel G that emits green light.
  • the finer the pattern to be processed the more the effects of light diffraction cannot be ignored, and this causes a loss of fidelity when the photomask pattern is transferred by exposure, making it difficult to process the resist mask into the desired shape.
  • the photomask pattern is rectangular, a pattern with rounded corners is likely to be formed.
  • the planar shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.
  • the resist film formed on the EL layer needs to be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the material of the EL layer and the curing temperature of the resist material, the resist film may not be cured sufficiently.
  • a resist film that is not cured sufficiently may have a shape that is different from the desired shape during processing.
  • the planar shape of the EL layer may become a polygon with rounded corners, an ellipse, a circle, or the like.
  • a resist mask with a circular planar shape may be formed, and the planar shape of the EL layer may become circular.
  • OPC Optical Proximity Correction
  • a pixel can be configured to have four types of subpixels.
  • the pixel 240 shown in Figures 12A to 12C has a stripe arrangement.
  • Figure 12A shows an example where each subpixel has a rectangular planar shape
  • Figure 12B shows an example where each subpixel has a planar shape that combines two semicircles and a rectangle
  • Figure 12C shows an example where each subpixel has an elliptical planar shape.
  • the pixels 240 shown in Figures 12D to 12F are arranged in a matrix.
  • Figure 12D shows an example where each subpixel has a square planar shape
  • Figure 12E shows an example where each subpixel has a roughly square planar shape with rounded corners
  • Figure 12F shows an example where each subpixel has a circular planar shape.
  • Figures 12G and 12H show an example in which one pixel 240 is composed of sub-pixels arranged in two rows and three columns.
  • the pixel 240 shown in FIG. 12G has three subpixels (pixel 230a, pixel 230b, pixel 230c) in the top row (first row) of the pixel 240, and one subpixel (pixel 230d) in the bottom row (second row).
  • the pixel 240 has pixel 230a in the left column (first column), pixel 230b in the center column (second column), pixel 230c in the right column (third column), and further has pixel 230d across these three columns.
  • the pixel 240 shown in FIG. 12H has three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the top row (first row) and three pixels 230d in the bottom row (second row).
  • the pixel 240 has pixels 230a and 230d in the left column (first column) of the pixel 240, pixels 230b and 230d in the center column (second column), and pixels 230c and 230d in the right column (third column).
  • FIG. 12H by aligning the arrangement of the sub-pixels in the top row and the bottom row, it is possible to efficiently remove dust and the like that may occur in the manufacturing process. Therefore, a display device with high display quality can be provided.
  • Figure 12I shows an example in which one pixel 240 is composed of sub-pixels arranged in three rows and two columns.
  • the pixel 240 shown in FIG. 12I has pixel 230a in the top row (first row), pixel 230b in the center row (second row), pixel 230c from the first row to the second row, and one subpixel (pixel 230d) in the bottom row (third row).
  • the pixel 240 has pixel 230a and pixel 230b in the left column (first column) of the pixel 240, pixel 230c in the right column (second column), and further has pixel 230d across these two columns.
  • the pixel 240 shown in Figures 12A to 12I is composed of four sub-pixels: pixel 230a, pixel 230b, pixel 230c, and pixel 230d.
  • Pixel 230a, pixel 230b, pixel 230c, and pixel 230d can be configured to have light-emitting devices that emit different colors of light.
  • Examples of pixels 230a, pixel 230b, pixel 230c, and pixel 230d include four sub-pixels of R, G, B, and white (W), four sub-pixels of R, G, B, and Y, or sub-pixels of R, G, B, and infrared light (IR).
  • pixel 230a may be a subpixel R that emits red light
  • pixel 230b may be a subpixel G that emits green light
  • pixel 230c may be a subpixel B that emits blue light
  • pixel 230d may be a subpixel W that emits white light, a subpixel that emits yellow light, or a subpixel that emits near-infrared light.
  • the pixel 240 shown in Figures 12G and 12H has a stripe layout of R, G, and B, which can improve display quality.
  • the pixel 240 shown in Figure 12I has a so-called S-stripe layout of R, G, and B, which can improve display quality.
  • pixel 240 may have a sub-pixel having a light receiving element (also called a light receiving device).
  • a light receiving element also called a light receiving device
  • any one of pixels 230a to 230d may be a subpixel having a light receiving device.
  • pixel 230a may be a subpixel R that emits red light
  • pixel 230b may be a subpixel G that emits green light
  • pixel 230c may be a subpixel B that emits blue light
  • pixel 230d may be a subpixel S that has a light receiving device.
  • the pixel 240 shown in Figures 12G and 12H has a stripe layout of R, G, and B, which can improve the display quality.
  • the pixel 240 shown in Figure 12I has a so-called S-stripe layout of R, G, and B, which can improve the display quality.
  • the wavelength of light detected by the subpixel S having a light receiving device is not particularly limited.
  • the subpixel S can be configured to detect either or both of visible light and infrared light.
  • one pixel 240 may have five types of sub-pixels.
  • Figure 12J shows an example in which one pixel 240 is composed of sub-pixels arranged in two rows and three columns.
  • the pixel 240 shown in FIG. 12J has three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the top row (first row) of the pixel 240, and two sub-pixels (pixel 230d, pixel 230e) in the bottom row (second row).
  • the pixel 240 has pixel 230a and pixel 230d in the left column (first column) of the pixel 240, pixel 230b in the center column (second column), pixel 230c in the right column (third column), and further has pixel 230e from the second column to the third column.
  • Figure 12K shows an example in which one pixel 240 is composed of sub-pixels arranged in three rows and two columns.
  • the pixel 240 shown in FIG. 12K has pixel 230a in the top row (first row), pixel 230b in the center row (second row), pixel 230c from the first row to the second row, and two subpixels (pixel 230d, pixel 230e) in the bottom row (third row).
  • pixel 240 has pixel 230a, pixel 230b, and pixel 230d in the left column (first column), and pixel 230c and pixel 230e in the right column (second column).
  • each pixel 240 shown in Figures 12J and 12K for example, it is preferable that pixel 230a is a subpixel R that emits red light, pixel 230b is a subpixel G that emits green light, and pixel 230c is a subpixel B that emits blue light.
  • the subpixels in pixel 240 shown in Figure 12J have a stripe layout, which can improve display quality.
  • the subpixels in pixel 240 shown in Figure 12K have a so-called S-stripe layout, which can improve display quality.
  • a subpixel S having a light receiving device may be applied to at least one of pixel 230d and pixel 230e.
  • the configurations of the light receiving devices may be different from each other.
  • at least a part of the wavelength range of light detected may be different from each other.
  • one of pixel 230d and pixel 230e may have a light receiving device that mainly detects visible light, and the other may have a light receiving device that mainly detects infrared light.
  • one of pixel 230d and pixel 230e may be a subpixel S having a light receiving device, and the other may be a subpixel having a light emitting device that can be used as a light source.
  • one of pixel 230d and pixel 230e may be a subpixel IR (not shown) that emits infrared light, and the other may be a subpixel S (not shown) that has a light receiving device that detects infrared light.
  • an image can be displayed using the sub-pixels R, G, B, IR, and S, while the sub-pixel IR can be used as a light source to detect the reflected infrared light emitted by the sub-pixel IR at the sub-pixel S.
  • various layouts of subpixels can be applied to the pixel 240.
  • a configuration having both a light-emitting device and a light-receiving device may be applied to the pixel 240.
  • various layouts can also be applied.
  • n is an integer equal to or greater than 1 signal output circuits 110.
  • the first-stage (first) signal output circuit 110 may be referred to as signal output circuit 110[1]
  • the n-th stage (n-th) signal output circuit 110 may be referred to as signal output circuit 110[n].
  • the signal output circuit 110 in the i-th stage (i is an integer between 1 and n) may be referred to as signal output circuit 110[i].
  • any stage number is represented as i+ ⁇ , and when ⁇ is positive, i+ ⁇ does not exceed n.
  • any stage number is represented as i- ⁇ , and when ⁇ is positive, i- ⁇ does not fall below 1.
  • the shift register 100 also has two signal output circuits 110 (signal output circuit 110[n+1] and signal output circuit 110[n+2]) which are dummy circuits.
  • the terminals and input/output signals of the signal output circuit 110 may be described in the same manner as above.
  • the signal OUT of the signal output circuit 110[i] may be described as the signal OUT[i].
  • the shift register 100 also has wirings 101 to 104 to which four signals CLK (signals CLK_1 to CLK_4) that are clock signals are supplied, and wirings 105 to 108 to which four signals PWC (signals PWC_1 to PWC_4) are supplied.
  • Signal CLK_1 is supplied to wiring 101
  • signal CLK_2 is supplied to wiring 102
  • signal CLK_3 is supplied to wiring 103
  • signal CLK_4 is supplied to wiring 104.
  • Signal PWC_1 is supplied to wiring 105
  • signal PWC_2 is supplied to wiring 106
  • signal PWC_3 is supplied to wiring 107
  • signal PWC_4 is supplied to wiring 108.
  • the signal output circuit 110 has terminals 111 to 118 (see FIG. 13B).
  • the terminals 111, 112, and 113 are each electrically connected to different wirings among the wirings 101 to 104.
  • the first-stage signal output circuit 110[1] has the terminal 111 electrically connected to the wiring 101, the terminal 112 electrically connected to the wiring 102, and the terminal 113 electrically connected to the wiring 103. That is, the signal CLK_1 is supplied to the terminal 111, the signal CLK_2 is supplied to the terminal 112, and the signal CLK_3 is supplied to the terminal 113.
  • the terminal 111 is electrically connected to the wiring 102
  • the terminal 112 is electrically connected to the wiring 103
  • the terminal 113 is electrically connected to the wiring 104. That is, the signal CLK_2 is supplied to the terminal 111, the signal CLK_3 is supplied to the terminal 112, and the signal CLK_4 is supplied to the terminal 113.
  • a signal CLK_k is supplied to terminal 111[i] of signal output circuit 110[i] (see FIG. 13C).
  • k is an integer between 1 and 4, and when i is 4 or less, k is equal to i, and when i is 5 or more, k is equal to i-4 ⁇ g, where g is the quotient obtained by dividing i by 4.
  • a signal CLK_k+1 is supplied to terminal 112[i] of signal output circuit 110[i].
  • k is an integer between 1 and 4, and when k+1 is 5, k is set to 1.
  • i is 3 or less, k is equal to i, and when i is 4 or more, k is equal to i-4 ⁇ g.
  • a signal CLK_k+2 is supplied to terminal 113[i] of signal output circuit 110[i].
  • k+1 is an integer between 1 and 4, and when k+2 is 5, k+2 is set to 1, and when k+2 is 6, k+2 is set to 2.
  • i is 2 or less, k is equal to i, and when i is 3 or more, k is equal to i-4 ⁇ g.
  • terminal 114[i] is electrically connected to terminal 117[i+1] (not shown) of the next stage signal output circuit 110[i+1] (not shown). Therefore, terminal 117[i] is electrically connected to terminal 114[i-1].
  • terminal 114 of signal output circuit 110[1] is electrically connected to terminal 117 of signal output circuit 110[2]. Furthermore, a start pulse SP is supplied to terminal 117 of signal output circuit 110[1].
  • the terminal 115[i] is electrically connected to the terminal 114[i+2] (not shown) of the signal output circuit 110[i+2] (not shown) two stages later.
  • the terminal 115 of the signal output circuit 110[1] is electrically connected to the terminal 114 of the signal output circuit 110[3]
  • the terminal 115 of the signal output circuit 110[2] is electrically connected to the terminal 114 of the signal output circuit 110[4]. Therefore, the terminal 115 of the signal output circuit 110[n-1] is electrically connected to the terminal 114 of the signal output circuit 110[n+1]
  • the terminal 115 of the signal output circuit 110[n] is electrically connected to the terminal 114 of the signal output circuit 110[n+2]. Note that the signal output circuit 110[n+1] and the signal output circuit 110[n+2] do not have to have the terminal 115.
  • the terminal 118[i] is electrically connected to any one of the wirings 105 to 108.
  • the terminal 118 of the signal output circuit 110[1] is electrically connected to the wiring 105
  • the terminal 118 of the signal output circuit 110[2] is electrically connected to the wiring 106.
  • the signal PWC_k is supplied to the terminal 118[i] of the signal output circuit 110[i].
  • k is an integer of 1 to 4, and when i is 4 or less, k is equal to i, and when i is 5 or more, k is equal to i-4 ⁇ g.
  • a signal OUT[i] is output from terminal 116[i].
  • a signal OUT[1] is output from terminal 116 of signal output circuit 110[1].
  • a signal OUT[n] is output from terminal 116 of n-th stage signal output circuit 110[n]. Note that “Signal OUT[i] is output from terminal 116[i]” can be read as “Signal OUT[i] is supplied to terminal 116[i]."
  • a signal SROUT[i] is supplied to terminal 114[i].
  • a signal SROUT[i] is output from terminal 114[i].
  • a signal SROUT[1] is output from terminal 114 of signal output circuit 110[1].
  • a signal SROUT[n] is output from terminal 114 of n-th stage signal output circuit 110[n]. Note that "Signal SROUT[i] is output from terminal 114[i]” can be read as “Signal SROUT[i] is supplied to terminal 114[i]."
  • the signal output circuit 110a includes transistors 10[1] to 10[11] and capacitors 20[1] to 20[3].
  • the gate of transistor 10[1] is electrically connected to terminal 117 and the gate of transistor 10[6].
  • the source of transistor 10[1] is electrically connected to the drain of transistor 10[2], and the drain of transistor 10[1] is electrically connected to wiring 131.
  • the gate of transistor 10[2] is electrically connected to one terminal of capacitor 20[1].
  • the source of transistor 10[2] is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[6], and wiring 132.
  • the gate of transistor 10[3] is electrically connected to terminal 113, the drain of transistor 10[3] is electrically connected to wiring 131, and the source of transistor 10[3] is electrically connected to the drain of transistor 10[4].
  • the gate of transistor 10[4] is electrically connected to terminal 112, and the drain of transistor 10[4] is electrically connected to the source of transistor 10[3].
  • the source of transistor 10[4] is electrically connected to the gates of transistor 10[2], transistor 10[9], and transistor 10[11], and one terminal of capacitor 20[1].
  • Capacitor 20[1] has the function of suppressing the potential fluctuation of node ND[1] when node ND[1] is in a floating state and maintaining the potential of node ND[1].
  • the gate of transistor 10[5] is electrically connected to terminal 115, and the drain of transistor 10[5] is electrically connected to wiring 131.
  • the source of transistor 10[5] is electrically connected to the gate of transistor 10[2], the gate of transistor 10[9], the gate of transistor 10[11], and the drain of transistor 10[6].
  • the gate of transistor 10[7] is electrically connected to wiring 131, and one of the source and drain of transistor 10[7] is electrically connected to the source of transistor 10[1] and the drain of transistor 10[2].
  • the other of the source and drain of transistor 10[7] is electrically connected to the gate of transistor 10[8], one terminal of capacitor 20[2], the gate of transistor 10[10], and one terminal of capacitor 20[3].
  • node ND[2] the region where the source or drain of transistor 10[7], the source of transistor 10[1], and the drain of transistor 10[2] are electrically connected. Also, in this specification, the region where the source or drain of transistor 10[7], the gate of transistor 10[8], one terminal of capacitor 20[2], the gate of transistor 10[10], and one terminal of capacitor 20[3] are electrically connected is referred to as node ND[3].
  • the drain of transistor 10[8] is electrically connected to terminal 111.
  • the source of transistor 10[8] is electrically connected to the other terminal of capacitance 20[2], terminal 114, and the drain of transistor 10[9].
  • the drain of transistor 10[10] is electrically connected to terminal 118.
  • the source of transistor 10[10] is electrically connected to the other terminal of capacitance 20[3], terminal 116, and the drain of transistor 10[11].
  • the source of transistor 10[9] and the source of transistor 10[11] are electrically connected to wiring 132.
  • drain of transistor 10[1], the drain of transistor 10[3], the drain of transistor 10[5], and the gate of transistor 10[7] may each be electrically connected to different wirings.
  • the source of transistor 10[6], the source of transistor 10[9], and the source of transistor 10[11] may each be electrically connected to different wirings.
  • the drain of transistor 10[1] may be electrically connected to wiring 131[1]
  • the drain of transistor 10[3] may be electrically connected to wiring 131[2]
  • the drain of transistor 10[5] may be electrically connected to wiring 131[3]
  • the gate of transistor 10[7] may be electrically connected to wiring 131[4].
  • the source of transistor 10[6] may be electrically connected to wiring 132[1]
  • the source of transistor 10[9] may be electrically connected to wiring 132[2]
  • the source of transistor 10[11] may be electrically connected to wiring 132[3]. Note that, as shown in FIG. 16, when the capacitance value of capacitor 20[3] can be sufficiently secured, the formation of capacitor 20[2] may be omitted.
  • a signal RIN is supplied to terminal 115, a signal LIN is supplied to terminal 117, a signal SROUT is supplied to terminal 114, and a signal OUT is supplied to terminal 116.
  • a signal CLK_1 is supplied to terminal 111, a signal CLK_2 is supplied to terminal 112, a signal CLK_3 is supplied to terminal 113, and a signal PWC_1 is supplied to terminal 118.
  • the signal CLK_2 is supplied to the terminal 111
  • the signal CLK_3 is supplied to the terminal 112
  • the signal CLK_4 is supplied to the terminal 113
  • the signal PWC_2 is supplied to the terminal 118.
  • FIG. 17A is a plan view of the transistor 10.
  • FIG. 17B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 17A.
  • FIG. 17C is a perspective view showing a cutaway portion of the transistor 10.
  • FIG. 17D is an equivalent circuit diagram of the transistor 10.
  • some of the components of the transistor 10 are omitted in FIGS. 17A and 17C.
  • the insulating layer 164 and the like shown in FIG. 17B are omitted in FIGS. 17A and 17C.
  • FIG. 18A and 18B are enlarged views of the transistor 10 shown in FIG. 17B.
  • FIG. 18C is a view of the opening 159 from the Z direction.
  • Transistor 10 has insulating layer 154 on substrate 153, and conductive layer 155 on insulating layer 154. It also has insulating layer 156 on conductive layer 155, insulating layer 157 on insulating layer 156, and insulating layer 158 on insulating layer 157. It also has conductive layer 160 on insulating layer 158.
  • an opening 159 is provided in the conductive layer 160, the insulating layer 158, the insulating layer 157, and the insulating layer 156 in a region overlapping with a part of the conductive layer 155 (see Figures 17B and 18A).
  • the opening 159 has a semiconductor layer 161.
  • the semiconductor layer 161 has a region overlapping with the bottom of the opening 159 and a region overlapping with the side of the opening 159.
  • the semiconductor layer 161 has a region in contact with the side of the insulating layer 158, a region in contact with the side of the insulating layer 157, and a region in contact with the side of the insulating layer 156.
  • a part of the semiconductor layer 161 is electrically connected to the conductive layer 160, and another part of the semiconductor layer 161 is electrically connected to the conductive layer 155.
  • an insulating layer 162 is provided on the insulating layer 158, the conductive layer 160, and the semiconductor layer 161, and a conductive layer 163 is provided on the insulating layer 162.
  • an insulating layer 164 is provided on the insulating layer 162 and the conductive layer 163.
  • the insulating layer 162 has a region that overlaps with the side of the opening 159 through the semiconductor layer 161.
  • the conductive layer 163 is provided to cover the semiconductor layer 161. Therefore, the conductive layer 163 has a region that extends beyond the end of the semiconductor layer 161.
  • the conductive layer 163 has a region that overlaps with the side of the opening 159 through the insulating layer 162 and the semiconductor layer 161.
  • the conductive layer 155 has a region that functions as one of the source electrode and drain electrode of the transistor 10.
  • the conductive layer 160 has a region that functions as the other of the source electrode and drain electrode of the transistor 10. For example, when the conductive layer 155 functions as the drain electrode of the transistor 10, the conductive layer 160 functions as the source electrode of the transistor 10.
  • the semiconductor layer 161 has a region that functions as a semiconductor layer in which the channel of the transistor 10 is formed, the insulating layer 162 has a region that functions as a gate insulating layer, and the conductive layer 163 has a region that functions as a gate electrode.
  • the transistor 10 is provided in a region that includes the opening 159.
  • the source electrode and drain electrode of transistor 10 are arranged in the Z direction. Therefore, the source and drain of transistor 10 are each arranged at different positions in the Z direction. For example, when the top surface of substrate 153 is taken as the reference, the source and drain of transistor 10 are each arranged at different distances from the top surface of substrate 153, which is the reference.
  • Such a transistor is also called a "vertical channel transistor,” “vertical channel transistor,” “vertical transistor,” or “VFET (Vertical Field Effect Transistor).”
  • VFET Very Field Effect Transistor
  • transistor 10 which is a vertical channel transistor
  • the angle ⁇ (see FIG. 18A) between the surface on which semiconductor layer 161 is formed on conductive layer 155 and the direction in which Id flows is 5 degrees or more and 110 degrees or less, or 10 degrees or more and 90 degrees or less, or 30 degrees or more and 90 degrees or less, or 60 degrees or more and 90 degrees or less.
  • the semiconductor layer 161 has an area that contacts the side of the insulating layer 157. Therefore, Id flows along the side of the insulating layer 157. Therefore, the angle ⁇ between the formation surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which Id flows can be interpreted as the angle ⁇ between the formation surface of the semiconductor layer 161 on the conductive layer 155 and the side of the insulating layer 157.
  • Vertical channel transistors have source and drain electrodes arranged in the Z direction, which reduces the area occupied by the transistor. By using vertical channel transistors in a semiconductor device, the area occupied by the semiconductor device can be significantly reduced.
  • substrate There is no particular limitation on the material used for the substrate 153 and the substrates 148 and 152 described below.
  • the material can be determined in consideration of the presence or absence of light transmission and the heat resistance to a degree that can withstand heat treatment, depending on the purpose.
  • insulating substrates such as glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, and sapphire substrates can be used.
  • semiconductor substrates, flexible substrates, laminated films, base films, and the like may also be used.
  • the semiconductor substrate may be, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
  • a large-area glass substrate such as a sixth generation (1500 mm x 1850 mm), seventh generation (1870 mm x 2200 mm), eighth generation (2200 mm x 2400 mm), ninth generation (2400 mm x 2800 mm), or tenth generation (2950 mm x 3400 mm) substrate can be used.
  • This allows a large display device to be manufactured.
  • by increasing the size of the substrate more display devices can be produced from one substrate, thereby reducing production costs.
  • Materials for flexible substrates, laminated films, base films, etc. that can be used include, for example, polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resins, polyimides, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamides (nylon, aramid, etc.), polysiloxanes, cycloolefin resins, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resins, cellulose nanofibers, etc.
  • polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN)
  • PET polyethylene naphthalate
  • PEN polyacrylonitrile
  • acrylic resins polyimides
  • polymethyl methacrylate polycarbonate
  • PC polyethersulf
  • a lightweight semiconductor device including the transistor 10 can be provided.
  • a semiconductor device that is resistant to shocks can be provided.
  • a semiconductor device that is less likely to break can be provided.
  • the material used for the flexible substrate for the substrate may have a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 /K or less, 5 ⁇ 10 ⁇ 5 /K or less, or 1 ⁇ 10 ⁇ 5 /K or less.
  • aramid is suitable as a flexible substrate because of its low linear expansion coefficient.
  • a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a semiconductor represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and spin coating can be used.
  • a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material.
  • a layer formed of a Cu-X alloy can be processed by a wet etching process, which makes it possible to reduce manufacturing costs.
  • an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.
  • a conductive material that can be used for the conductive layer a conductive material containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide, can be used.
  • a conductive material containing nitrogen such as titanium nitride, tantalum nitride, or tungsten nitride, can be used.
  • the conductive layer can have a layered structure in which a conductive material containing oxygen, a conductive material containing nitrogen, or a material containing the above-mentioned metal element is appropriately combined.
  • the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on an aluminum layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, or a three-layer structure in which a titanium layer is laminated on an aluminum layer on the titanium layer, and a titanium layer is further laminated on the aluminum layer.
  • the conductive layer may have a stacked structure that combines the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • the conductive layer may have a stacked structure that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • the conductive layer may have a stacked structure that combines the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • the conductive layer may have a three-layer structure in which a conductive layer containing copper is laminated on a conductive layer containing at least one of indium or zinc and oxygen, and a conductive layer containing at least one of indium or zinc and oxygen is further laminated on top of that.
  • multiple conductive layers containing at least one of indium or zinc and oxygen may be laminated and used as the conductive layer.
  • Each insulating layer is made of a single layer or a stack of insulating materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. Also, a plurality of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.
  • the method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.
  • an oxynitride refers to a material that contains more nitrogen than oxygen.
  • An oxynitride refers to a material that contains more oxygen than nitrogen.
  • the content of each element can be measured, for example, using Rutherford backscattering spectrometry (RBS).
  • the insulating layer 154 and the insulating layer 164 are preferably formed using an insulating material that is difficult for impurities to penetrate.
  • an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • Examples of insulating materials that are difficult for impurities to penetrate include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.
  • an insulating layer that can function as a planarization layer may be used as the insulating layer.
  • materials for the insulating layer that can function as a planarization layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof.
  • low dielectric constant materials low-k materials
  • siloxane resin PSG (phosphorus glass), BPSG (borophosphorus glass), etc.
  • multiple insulating layers made of these materials may be stacked.
  • the siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material.
  • the siloxane resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent.
  • the organic group may also have a fluoro group.
  • a CMP process may be performed on the surface of the insulating layer, etc.
  • the unevenness of the surface of the insulating layer, etc. can be reduced, and the coverage of the insulating layer and conductive layer that will be formed later can be improved.
  • the semiconductor layer 161 a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • the semiconductor material for example, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor), such as silicon or germanium, can be used.
  • a semiconductor of a single element, a compound semiconductor, or a layered material also referred to as an atomic layer material, a two-dimensional material, or the like
  • an organic material having semiconductor properties or a metal oxide having semiconductor properties also referred to as an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon may be used as the semiconductor layer 161.
  • LTPS low temperature polysilicon
  • Transistors using amorphous silicon for the semiconductor layer 161 can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer 161 have high field effect mobility and can operate at high speed. Transistors using microcrystalline silicon for the semiconductor layer 161 have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.
  • the semiconductor layer 161 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 moly MoTe 2
  • tungsten sulfide typically WS 2
  • tungsten selenide typically
  • an oxide semiconductor has a band gap of 2 eV or more
  • a transistor also referred to as an "OS transistor” that uses an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed has an extremely low off-state current. Therefore, the power consumption of a semiconductor device including an OS transistor can be reduced.
  • an OS transistor operates stably even in a high-temperature environment and has little fluctuation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. In addition, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.
  • an OS transistor as the transistor 10. Since an OS transistor has a high withstand voltage between the source and drain, the channel length can be shortened. Therefore, the on-current can be increased. An OS transistor is suitable for a vertical channel transistor.
  • the channel length can be 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L can be 100 nm or more and 1 ⁇ m or less.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • element M is a metal element or semimetal element that has a high bond energy with oxygen, for example, a metal element or semimetal element that has a higher bond energy with oxygen than indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may contain one or more metal elements having a large periodic number instead of or in addition to indium.
  • metal elements having a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be realized.
  • In-Zn oxide is used for the semiconductor layer of an OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc.
  • an In-Sn oxide is used for the semiconductor layer of an OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin.
  • an In-Sn-Zn oxide is used for the semiconductor layer of an OS transistor
  • a metal oxide in which the atomic ratio of indium is higher than that of tin can be used.
  • a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferable to use.
  • In-Al-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum.
  • a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium.
  • In-M-Zn oxide is used for the semiconductor layer of an OS transistor
  • a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of element M.
  • the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of element M.
  • the atomic ratios of indium, element M, and zinc are within the above-mentioned range.
  • a metal oxide in which the ratio of the number of indium atoms to the sum of the atomic numbers of the metal elements among the main component elements contained in the metal oxide is 30 atomic % or more and 100 atomic %, preferably 30 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 90 atomic %, more preferably 40 atomic % or more and 90 atomic %, more preferably 45 atomic % or more and 90 atomic %, more preferably 50 atomic % or more and 80 atomic %, more preferably 60 atomic % or more and 80 atomic %, more preferably 70 atomic % or more and 80 atomic %.
  • In-M-Zn oxide it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements among the main component elements contained in the metal oxide.
  • a circuit capable of high-speed operation can be manufactured.
  • the area occupied by the circuit can be reduced. For example, when the transistor is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, the signal delay in each wiring can be reduced and display unevenness can be suppressed.
  • the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • composition of metal oxides can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used for the analysis.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide is preferably formed by sputtering or ALD.
  • the atomic ratio of the target may differ from the atomic ratio of the metal oxide.
  • the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.
  • a transistor with high reliability when a positive bias is applied can be obtained.
  • a transistor with a small amount of variation in threshold voltage in a PBTS test can be obtained.
  • defect levels at or near the interface between the semiconductor layer and the gate insulating layer are defect levels at or near the interface between the semiconductor layer and the gate insulating layer.
  • the reason why the use of a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer can suppress the variation in threshold voltage in the PBTS test is thought to be, for example, as follows.
  • the gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to create carrier (here, electron) trap sites. Therefore, it is thought that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing the threshold voltage to vary.
  • a metal oxide in which the atomic ratio of indium is higher than that of gallium can be applied to the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga to the semiconductor layer.
  • the semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is higher than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less.
  • a metal oxide that does not contain gallium may be applied to the semiconductor layer of an OS transistor.
  • In-Zn oxide may be applied to the semiconductor layer.
  • the field effect mobility of the transistor can be increased by increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide.
  • the metal oxide becomes highly crystalline, so that the fluctuation in the electrical characteristics of the transistor is suppressed and the reliability can be increased.
  • a metal oxide that does not contain gallium and zinc, such as indium oxide may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, the fluctuation in the threshold voltage, particularly in a PBTS test, can be made extremely small.
  • an oxide containing indium and zinc can be used for the semiconductor layer.
  • gallium has been used as a representative example, the present invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M for the semiconductor layer. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • Light incident on a transistor may cause the transistor's electrical characteristics to fluctuate.
  • transistors applied to areas where light can be incident have small fluctuations in electrical characteristics under light irradiation and high reliability against light. Reliability against light can be evaluated, for example, by the amount of variation in threshold voltage in an NBTIS test.
  • a transistor with high reliability against light can be obtained.
  • a transistor with a small variation in threshold voltage in an NBTIS test can be obtained.
  • a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and the variation in threshold voltage of the transistor in an NBTIS test can be reduced.
  • the band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, more preferably 2.5 eV or more, more preferably 3.0 eV or more, more preferably 3.2 eV or more, more preferably 3.3 eV or more, more preferably 3.4 eV or more, and more preferably 3.5 eV or more.
  • metal oxides in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less are suitable as semiconductor layers.
  • metal oxides can be used in which the atomic ratio of indium to the atomic number of the metal element is equal to or less than the atomic ratio of gallium.
  • metal oxides in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, more preferably 50 atomic % or more and 60 atomic % or less are particularly suitable.
  • a metal oxide with a high content of element M By applying a metal oxide with a high content of element M to the semiconductor layer, a transistor with high reliability against light can be obtained. By applying this transistor to a transistor that requires high reliability against light, a semiconductor device with high reliability can be obtained.
  • the semiconductor layer may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers of the semiconductor layer may have the same or approximately the same composition.
  • the two or more metal oxide layers in the semiconductor layer may have different compositions.
  • gallium or aluminum as the element M.
  • a laminate structure may be used, which includes any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark).
  • the band gaps of the first and third semiconductor layers are larger than the band gap of the second semiconductor layer is preferable. With this configuration, it is possible to make the main current path the second layer, resulting in a so-called buried channel structure.
  • the semiconductor layer is preferably a metal oxide layer having crystallinity.
  • a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a nano-crystalline (nc: nano-crystal) structure, or the like can be used.
  • CAAC c-axis aligned crystal
  • nc nano-crystalline
  • the density of defect levels in the semiconductor layer can be reduced, and a highly reliable display device can be realized.
  • the semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers with different crystallinity.
  • a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer may be used, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer.
  • the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer.
  • the two or more metal oxide layers in the semiconductor layer may have the same or approximately the same composition.
  • the same sputtering target can be used to form the stacked structure, which can reduce manufacturing costs.
  • the same sputtering target can be used to form a stacked structure of two or more metal oxide layers with different crystallinity by changing the oxygen flow rate ratio. Note that the two or more metal oxide layers in the semiconductor layer may have different compositions.
  • the channel length L is determined by the thickness of the insulating layer provided between the conductive layer 160 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high precision.
  • the characteristic variation between the multiple transistors 10 is also reduced. Therefore, the operation of a semiconductor device including the transistor 10 can be stabilized and the reliability can be improved.
  • the reduction in the characteristic variation increases the degree of freedom in the circuit design of the semiconductor device and the operating voltage can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.
  • the oxide semiconductor in the region in contact with the insulating layer 161 becomes n-type and can function as a source region or a drain region.
  • a material containing silicon, nitrogen, and hydrogen may be used for the insulating layer.
  • silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen may be used.
  • the conductive layer 155 in contact with the semiconductor layer 161 and the conductive layer 160 in contact with the semiconductor layer 161 are preferably made of a conductive material that makes the oxide semiconductor n-type.
  • a conductive material containing nitrogen may be used.
  • a conductive material containing titanium or tantalum and nitrogen may be used.
  • Another conductive material may be provided over the conductive material containing nitrogen.
  • a material in which hydrogen is reduced and which contains oxygen for the insulating layer 157 For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in an oxide semiconductor, when the semiconductor layer 161, which is an oxide semiconductor, is in contact with the insulating layer 157 in which hydrogen is reduced, the semiconductor layer 161 is less likely to become n-type. Furthermore, when the semiconductor layer 161, which is an oxide semiconductor, is in contact with the insulating layer 157 containing oxygen, oxygen vacancies in the semiconductor layer 161 are reduced, and the characteristics of the transistor 10 are stabilized, leading to improved reliability.
  • the insulating layer 157 preferably contains excess oxygen.
  • excess oxygen refers to oxygen that is released by heating.
  • a material containing excess oxygen it is preferable to use a material through which oxygen is difficult to permeate for the insulating layer 156 and the insulating layer 158.
  • an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used as a material through which oxygen is difficult to permeate.
  • insulating layer 157 an insulating layer containing silicon and oxygen (insulating layer 157) is between two insulating layers containing silicon and nitrogen (insulating layer 156, insulating layer 158).
  • the region of the semiconductor layer 161 in contact with the conductive layer 160 and the region of the semiconductor layer 161 in contact with the insulating layer 158 function as one of the source (source region) and the drain (drain region).
  • the region of the semiconductor layer 161 in contact with the conductive layer 155 and the region of the semiconductor layer 161 in contact with the insulating layer 156 function as the other of the source (source region) and the drain (drain region). Therefore, the channel length L of the transistor 10 is determined by the thickness t of the insulating layer 157 (see FIG. 18A).
  • the insulating layer 156 and the insulating layer 158 may be made of a material that does not contain hydrogen or contains very little hydrogen.
  • silicon nitride or silicon oxynitride containing very little hydrogen may be used.
  • the region where the semiconductor layer 161 contacts the insulating layer 156 and the region where the semiconductor layer 161 contacts the insulating layer 158 are not made n-type. Therefore, the region of the semiconductor layer 161 that contacts the conductive layer 160 functions as one of the source (source region) or the drain (drain region).
  • the region of the semiconductor layer 161 that contacts the conductive layer 155 functions as the other of the source (source region) or the drain (drain region).
  • the thickness ts obtained by adding up the thicknesses of the insulating layer 156, the insulating layer 157, and the insulating layer 158 corresponds to the channel length L of the transistor 10 (see FIG. 18A).
  • the channel length L can be controlled by adjusting the thicknesses of insulating layers 156, 157, and 158.
  • the channel length L can be set to 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L can be set to 100 nm or more and 1 ⁇ m or less.
  • insulating layer 156 insulating layer 157, insulating layer 1528 between conductive layer 155 and conductive layer 160 is shown, but the number of insulating layers between conductive layer 155 and conductive layer 160 is not limited to this.
  • the insulating layer between conductive layer 155 and conductive layer 160 can be one layer or two layers. Also, it can be four or more layers.
  • the perimeter p of the opening 159 is the channel width W of the transistor 10 (see FIG. 18C).
  • the perimeter p may be determined, for example, at a position half the thickness t (t/2) or half the thickness ts (ts/2) of the insulating layer 157.
  • the perimeter at any position of the opening 159 may be the channel width W as necessary.
  • the perimeter p at the bottom of the opening 159 may be the channel width W, or the perimeter p at the top of the opening 159 may be the channel width W.
  • the outline (planar shape) of the opening 159 viewed from the Z direction is shown as a circle, but is not limited to this.
  • the outline of the opening 159 viewed from the Z direction can be an ellipse (see FIG. 18D). It can also be a rectangle (see FIG. 18E). Note that FIG. 18E shows a rectangle with rounded corners.
  • the outline of the opening 159 viewed from the Z direction can be a shape that includes one or both of straight and curved portions (see FIG. 18F).
  • the parasitic capacitance occurring between the gate and the source is different from the parasitic capacitance occurring between the gate and the drain.
  • 19A and 19B show plan views similar to those of FIG. 17A.
  • the conductive layer 163 overlaps the conductive layer 160 around the periphery of the opening 159 so as to surround the opening 159, and overlaps the conductive layer 160 at the bottom of the opening 159.
  • FIG 19A the area that functions as capacitance C1 when viewed from the Z direction is indicated by a hatched pattern.
  • the overlap area of the conductive layer 163 and the conductive layer 160 can be easily adjusted, and the electrical characteristics of the transistor 10 are unlikely to be affected. For example, by increasing the overlap area of the conductive layer 163 and the conductive layer 160, the capacitance value of the capacitor C1 can be increased.
  • a conductive layer 166 adjacent to the semiconductor layer 161 may be provided in the insulating layer 157.
  • the conductive layer 166 is provided without contacting the semiconductor layer 161.
  • the conductive layer 166 is preferably provided to surround the semiconductor layer 161.
  • the transistor 10 shown in FIG. 20A functions as a transistor having a backgate (backgate electrode).
  • FIG. 20B is an equivalent circuit diagram of the transistor 10 shown in FIG. 20A.
  • the backgate electrode will be explained.
  • the backgate electrode is formed of a conductive layer, and is arranged so that the gate electrode and the backgate electrode sandwich the channel formation region of the semiconductor layer. Therefore, the backgate electrode can function in the same manner as the gate electrode.
  • the potential of the backgate electrode may be the same as that of the gate electrode, or may be the GND potential or any other potential.
  • the gate electrode and the back gate electrode are formed of a conductive layer, they have a function of preventing an electric field generated outside the transistor from acting on the channel formation region of the semiconductor layer (particularly an electric field shielding function against static electricity, etc.). As a result, the characteristic variation between transistors is reduced. In addition, the deterioration of the transistor characteristics due to the GBTS test is suppressed. For example, by having a back gate electrode, the variation in threshold voltage before and after the GBTS test can be suppressed. Furthermore, the variation in threshold voltage before and after the GBTS test is smaller for a transistor having a back gate electrode than for a transistor without a back gate electrode.
  • GBTS (NBTS and PBTS) testing is a type of accelerated testing that allows for the evaluation, in a short period of time, of changes in transistor characteristics (aging) that occur over a long period of use.
  • the amount of change in a transistor's threshold voltage before and after a GBTS test is an important indicator for examining reliability. The smaller the amount of change in threshold voltage before and after a GBTS test, the more reliable the transistor is.
  • the back gate electrode when light is incident from the back gate electrode side, can be formed from a conductive film having light-shielding properties to prevent the light from entering the semiconductor layer from the back gate electrode side.
  • the gate electrode can be formed from a conductive film having light-shielding properties to prevent the light from entering the semiconductor layer from the gate electrode side.
  • the gate electrode and the back gate electrode can block the electric field generated by the drain electrode from acting on the semiconductor layer. This can suppress the fluctuation in the on-current rise voltage caused by the fluctuation in the drain voltage. This effect is particularly noticeable when a potential is supplied to the gate electrode and the back gate electrode.
  • the apparent channel width W of the transistor 10 can be increased.
  • the resistance between the source and drain when the transistor 10 is in the on state decreases, and Id in the on state can be increased.
  • Figure 21A is a plan view of transistor 10 including transistor 10a and transistor 10b.
  • Figure 21B is a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 21A.
  • Figure 21C is a perspective view showing a cutaway portion of transistor 10 including transistor 10a and transistor 10b.
  • Figure 21D is an equivalent circuit diagram of transistor 10 including transistor 10a and transistor 10b. To make the configuration of transistor 10 easier to understand, some of the components of transistor 10 are omitted in Figures 21A and 21C.
  • Transistors 10a and 10b have the same configuration as transistor 10 described with reference to Figures 17 and 18.
  • Transistor 10a is provided in a region including opening 159a
  • transistor 10b is provided in a region including opening 159b. Openings 159a and 159b can be formed in the same manner as opening 159.
  • a part of the conductive layer 155 functions as one of the source electrode or drain electrode of transistor 10a, and another part of the conductive layer 155 functions as one of the source electrode or drain electrode of transistor 10b.
  • a part of the conductive layer 160 functions as the other of the source electrode or drain electrode of transistor 10a, and another part of the conductive layer 160 functions as the other of the source electrode or drain electrode of transistor 10b.
  • a part of the conductive layer 163 functions as the gate electrode of transistor 10a, and another part of the conductive layer 163 functions as the gate electrode of transistor 10b.
  • one of the source or drain of transistor 10a is electrically connected to one of the source or drain of transistor 10b, and the other of the source or drain of transistor 10a is electrically connected to the other of the source or drain of transistor 10b.
  • the gate of transistor 10a is electrically connected to the gate of transistor 10b.
  • transistors 10a and 10b By connecting multiple transistors 10 (here, transistors 10a and 10b) in series, the apparent channel length L of transistor 10 can be increased. Increasing channel length L can improve the saturation characteristics of transistor 10.
  • Figure 22A is a plan view of transistor 10 including transistor 10a and transistor 10b.
  • Figure 22B is a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 22A.
  • Figure 22C is a perspective view showing a cutaway portion of transistor 10 including transistor 10a and transistor 10b.
  • Figure 22D is an equivalent circuit diagram of transistor 10 including transistor 10a and transistor 10b. To make the configuration of transistor 10 easier to understand, some of the components of transistor 10 are omitted in Figures 22A and 22C.
  • Transistors 10a and 10b have a similar configuration to transistor 10 described using Figure 21, but differ in that conductive layer 155 is separated into conductive layer 155a and conductive layer 155b.
  • the conductive layer 155a functions as one of the source electrode or drain electrode of the transistor 10a, and a part of the conductive layer 160 functions as the other of the source electrode or drain electrode of the transistor 10a. Another part of the conductive layer 160 functions as one of the source electrode or drain electrode of the transistor 10b, and the conductive layer 155b functions as the other of the source electrode or drain electrode of the transistor 10b.
  • a part of the conductive layer 163 functions as the gate electrode of the transistor 10a, and another part of the conductive layer 163 functions as the gate electrode of the transistor 10b.
  • transistor 10a and transistor 10b switch between the on state and the off state simultaneously, and function as one transistor 10.
  • Figure 23 is a diagram showing an example of the planar configuration of the signal output circuit 110a.
  • Figure 24A is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A1-A2 in Figure 23.
  • Figure 24B is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A2-A3 in Figure 23.
  • Figure 25A is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A4-A5 in Figure 23.
  • Figure 25B is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A6-A7 in Figure 23.
  • the signal output circuit 110a has an insulating layer 154 on the substrate 148, and a conductive layer 155 (for example, conductive layer 155[1] and conductive layer 155[3] in FIG. 24A, conductive layer 155[3] and conductive layer 155[4] in FIG. 24B, conductive layer 155[10] and conductive layer 155[11] in FIG. 25A) on the insulating layer 154.
  • a conductive layer 155 for example, conductive layer 155[1] and conductive layer 155[3] in FIG. 24A, conductive layer 155[3] and conductive layer 155[4] in FIG. 24B, conductive layer 155[10] and conductive layer 155[11] in FIG. 25A
  • the stacked configuration of the signal output circuit 110a which uses the VFET described above for the transistor 10, has some common parts with the example configuration of the transistor 10 described above. Therefore, the following mainly describes the parts that differ from the example configuration of the transistor 10 described above.
  • the reference numerals of components related to transistor 10[1] may be given the reference numerals for identifying [1].
  • the conductive layer 163 functioning as the gate electrode of transistor 10[1] may be referred to as conductive layer 163[1].
  • the reference numerals of components common to multiple transistors 10 may be given the reference numerals for identifying one of the multiple transistors 10.
  • the conductive layer 163 functioning as the gate electrode of each of transistors 10[2], transistor 10[9], and transistor 10[11] may be referred to as conductive layer 163[2].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[3] may be referred to as the opening 159[3] and the semiconductor layer 161[3].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[4] may be referred to as the opening 159[4] and the semiconductor layer 161[4].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[7] may be referred to as the opening 159[7] and the semiconductor layer 161[7].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[8] may be referred to as the opening 159[8] and the semiconductor layer 161[8].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[10] may be referred to as the opening 159[10] and the semiconductor layer 161[10].
  • the signal output circuit 110a has conductive layers 181[1] to 181[4] on the insulating layer 158 (see FIG. 23 and FIG. 25A).
  • the conductive layers 181 (conductive layers 181[1] to 181[4]) can be formed using the same material and method as the conductive layer 160. In addition, the conductive layer 181 can be formed at the same time as the conductive layer 160.
  • the signal output circuit 110a also has an insulating layer 187 on the insulating layer 164.
  • the insulating layer 187 preferably functions as a planarizing layer that reduces steps caused by transistors, capacitors, wiring, and the like formed in the lower layers.
  • An organic insulating film is suitable as a material that functions as a planarizing layer. After the insulating layer 187 is formed using an inorganic or organic material, the insulating layer 187 may be subjected to a planarizing process using a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • the signal output circuit 110a also has conductive layers 191 to 199, wiring 131, and wiring 132 on the insulating layer 187 (see FIG. 23, FIG. 24A, FIG. 24B, and FIG. 25A).
  • the conductive layers 191 to 199, wiring 131, and wiring 132 can be formed using the same materials and methods as the other conductive layers.
  • the conductive layer 191 functions as the terminal 111 shown in FIG.
  • the conductive layer 192 functions as the terminal 112
  • the conductive layer 193 functions as the terminal 113
  • the conductive layer 194 functions as the terminal 114
  • the conductive layer 195 functions as the terminal 115
  • the conductive layer 196 functions as the terminal 116
  • the conductive layer 197 functions as the terminal 117
  • the conductive layer 198 functions as the terminal 118.
  • openings penetrating the insulating layers 162, 164, and 187 are provided on the conductive layers 160[2], 160[3], 181[1], 181[2], 181[3], and 181[4], respectively.
  • the wiring 132 and the conductive layer 160[2] are electrically connected in the opening provided on the conductive layer 160[2]. More specifically, the wiring 132 and the conductive layer 160[2] are electrically connected at the bottom of the opening provided on the conductive layer 160[2].
  • Two openings are provided on the conductive layer 160[3]. In one of the two openings, the wiring 131 and the conductive layer 160[3] are electrically connected. In addition, in the other of the two openings, the conductive layer 199 and the conductive layer 160[3] are electrically connected.
  • the conductive layer 191 and the conductive layer 181[1] are electrically connected in an opening provided on the conductive layer 181[1].
  • the conductive layer 194 and the conductive layer 181[2] are electrically connected in an opening provided on the conductive layer 181[3].
  • the conductive layer 198 and the conductive layer 181[3] are electrically connected in an opening provided on the conductive layer 181[4].
  • the conductive layer 196 and the conductive layer 181[4] are electrically connected in an opening provided on the conductive layer 181[4].
  • the signal output circuit 110a has openings penetrating the insulating layer 164 and the insulating layer 187 on each of the conductive layers 163[1], 163[3], 163[4], 163[5], and 163[7].
  • the conductive layer 197 and the conductive layer 163[1] are electrically connected.
  • the conductive layer 193 and the conductive layer 163[3] are electrically connected.
  • the conductive layer 192 and the conductive layer 163[4] are electrically connected.
  • the conductive layer 195 and the conductive layer 163[5] are electrically connected.
  • the conductive layer 199 and the conductive layer 163[7] are electrically connected. Note that the conductive layer 160[3] and the conductive layer 163[7] are electrically connected via the conductive layer 199.
  • the signal output circuit 110a has openings penetrating the insulating layers 156, 157, and 158 on each of the conductive layers 155[1], 155[2], 155[3], 155[4], 155[8], 155[9], 155[10], and 155[11].
  • the conductive layer 160[3] and the conductive layer 155[1] are electrically connected.
  • the conductive layer 160[1] and the conductive layer 155[2] are electrically connected.
  • the conductive layer 160[4] and the conductive layer 155[3] are electrically connected.
  • the conductive layer 181[1] and the conductive layer 155[8] are electrically connected.
  • the conductive layer 181[3] and the conductive layer 155[10] are electrically connected.
  • Two openings are provided on conductive layer 155[9]. In one of the two openings, conductive layer 160[8] and conductive layer 155[9] are electrically connected. In the other of the two openings, conductive layer 181[2] and conductive layer 155[9] are electrically connected.
  • Two openings are provided on the conductive layer 155[11]. In one of the two openings, the conductive layer 160[10] and the conductive layer 155[11] are electrically connected. In the other of the two openings, the conductive layer 181[4] and the conductive layer 155[11] are electrically connected.
  • the signal output circuit 110a has openings penetrating the insulating layers 156, 157, and 158 on the conductive layers 155[4] and 155[7], respectively.
  • the conductive layer 163[2] and the conductive layer 155[4] are electrically connected (see FIG. 25B).
  • the conductive layer 163[8] and the conductive layer 155[7] are electrically connected.
  • the conductive layer 155[4] also functions as the conductive layer 155[5] and the conductive layer 155[6].
  • the conductive layer 160[1] also functions as the conductive layer 160[7].
  • the conductive layer 160[2] also functions as the conductive layer 160[6], the conductive layer 160[9], and the conductive layer 160[11].
  • the conductive layer 160[3] also functions as the conductive layer 160[5].
  • the conductive layer 163[1] also functions as the conductive layer 163[6].
  • the conductive layer 163[2] also functions as the conductive layer 163[9] and the conductive layer 163[11].
  • the conductive layer 163[8] also functions as the conductive layer 163[10].
  • conductive layer 155[4] and conductive layer 160[6] overlap via insulating layer 156, insulating layer 157, and insulating layer 158 functions as capacitance 20[1].
  • the capacitance C1 of the transistor 10[8] can be used as the capacitance 20[2].
  • the capacitance C1 of the transistor 10[8] it is not necessary to separately provide the capacitance 20[2], and therefore a semiconductor device with a small occupancy area can be realized (see FIG. 23). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10[8].
  • the capacitance C1 of the transistor 10[10] can be used as the capacitance 20[3].
  • the capacitance C1 of the transistor 10[10] it is not necessary to separately provide the capacitance 20[3], and therefore a semiconductor device with a small occupancy area can be realized (see FIG. 23 and FIG. 25A). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10[10].
  • Figure 26 shows a circuit diagram of the signal output circuit 110a when the capacitance C1 of the transistor 10[8] is used as the capacitance 20[2] and the capacitance C1 of the transistor 10[10] is used as the capacitance 20[3].
  • Transistors other than transistor 10[10] and transistor 10[10] may be configured with transistors other than VFETs. However, in order to realize a semiconductor device with a reduced occupation area, it is preferable to use many transistors according to one embodiment of the present invention in the signal output circuit 110a. Therefore, it is preferable to use transistors according to one embodiment of the present invention for all transistors included in the signal output circuit 110a.
  • Figure 27 is a timing chart for explaining an example of the operation of the signal output circuit 110a[i].
  • Figures 28 to 34 are circuit diagrams for explaining an example of the operation of the signal output circuit 110a[i].
  • an "H” indicating potential H or an “L” indicating potential L may be written next to the wiring, etc.
  • an "H” or “L” may be enclosed in letters next to an electrode where a potential change has occurred.
  • an "x" symbol may be written over the transistor.
  • a potential H (VDD) is supplied to wiring 131, and a potential L (VSS) is supplied to wiring 132. It is also assumed that a signal CLK_1 is supplied to terminal 111, a signal CLK_2 is supplied to terminal 112, a signal CLK_3 is supplied to terminal 113, and a signal PWC_1 is supplied to terminal 118.
  • the signal CLK_1 is at a potential L
  • the signal CLK_2 is at a potential H
  • the signal CLK_3 is at a potential H
  • the signal PWC_1 is at a potential L
  • the signal LIN is at a potential L.
  • the transistors 10[2], 10[3], 10[4], 10[9], and 10[11] are in an on state.
  • the transistors 10[1], 10[5], 10[6], 10[7], 10[8], and 10[10] are in an off state.
  • the signal CLK_4 and the signals PWC_2 to PWC_4 are at potential L.
  • the signal CLK_4 and the signals PWC_2 to PWC_4 are not related to the operation of the signal output circuit 110a[i] described here, and therefore are not used in describing the operation of the signal output circuit 110a[i].
  • signal CLK_2 becomes potential L
  • signal LIN becomes potential H (see Figures 27 and 28).
  • transistor 10[1] and transistor 10[6] are turned on.
  • the potential of node ND[1] becomes potential L
  • transistor 10[2], transistor 10[9], and transistor 10[11] are turned off.
  • potentials of nodes ND[2] and ND[3] become a potential (potential H-Vth) that is lower than potential H by the Vth of transistor 10[1].
  • potential H-Vth is set to be equal to or higher than the Vth of the transistor. Therefore, transistors 10[8] and 10[10] are turned on.
  • Potential L is output from terminal 116 as signal OUT, and potential L is output from terminal 114 as signal SROUT.
  • signal CLK_1 becomes potential H
  • signal CLK_3 becomes potential L
  • signal PWC_1 becomes potential H
  • transistor 10[3] is turned off.
  • the potential of node ND[3] is potential H-Vth, so the potential of terminal 114 becomes potential H-Vth-Vth, and the potential of terminal 116 becomes potential H-Vth-Vth.
  • terminal 114 and node ND[3] are connected (capacitively coupled) via capacitance 20[2].
  • Terminal 116 and node ND[3] are connected via capacitance 20[3].
  • Capacitor 20[2] and capacitor 20[3] function as bootstrap capacitance. Therefore, as the potentials of terminal 114 and terminal 116 increase, the potential of node ND[3] increases.
  • node ND[2] also rises, but the moment the potential of node ND[2] exceeds the potential H-Vth, transistors 10[1] and 10[7] are turned off, and nodes ND[2] and ND[3] are put into a floating state.
  • the potential of node ND[3] also rises to potential H-Vth+potential H (2 ⁇ potential H-Vth) (time T2b; see Figures 27 and 30). Because this potential is higher than potential H+Vth, the potentials of terminals 114 and 116 can be set to potential H.
  • signal CLK_2 is at potential H
  • signal PWC_1 is at potential L
  • signal LIN is at potential L (see Figures 27 and 31).
  • transistor 10[4] is turned on.
  • the potential of terminal 116 is at potential L.
  • transistor 10[6] is turned off, and nodes ND[1] and ND[2] are in a floating state.
  • signal CLK_1 is at potential L
  • signal CLK_3 is at potential H
  • signal RIN is at potential H (see Figures 27 and 32).
  • transistors 10[3] and 10[5] are turned on, and the potential of node ND[1] is at potential H.
  • transistors 10[2], 10[9], and 10[11] are turned on.
  • transistor 10[2] When transistor 10[2] is turned on, the potential of node ND[2] becomes potential L. Then, transistor 10[7] is turned on, and the potential of node ND[3] also becomes potential L. Therefore, transistors 10[8] and 10[10] are turned off. In addition, when transistors 10[9] and 10[11] are turned on, potential L is supplied to terminal 114, and the potential of terminal 116 (potential L) is maintained.
  • potential L is supplied to terminal 114 and terminal 116 until potential H is supplied to terminal 117 as signal LIN.
  • potential L is output as signal OUT and signal SROUT until potential H is supplied to terminal 117 as signal LIN.
  • signal output circuit [i] can output pulse signals from terminals 114 and 116 in synchronization with a specific combination of signals.
  • the pulse width of signal SROUT which is the pulse signal output from terminal 114 (the time during which potential H is output), is linked to signal CLK.
  • the pulse width of signal OUT which is the pulse signal output from terminal 116 (the time during which potential H is output), is linked to signal PWC.
  • the signal output circuit [i] includes a capacitive element that functions as a bootstrap capacitance, and thus can reliably output a power supply potential (potential H) from the terminal 114 and the terminal 116. Therefore, the signal output circuit [i] according to one embodiment of the present invention has a small output impedance, and can reliably supply potential H to a load such as a circuit connected to the terminal 114 or the terminal 116. Therefore, the operation of a semiconductor device including the signal output circuit [i] according to one embodiment of the present invention is stabilized, and the reliability of the semiconductor device can be improved.
  • the capacitance C1 of the transistor 10[1] is preferably formed between the node ND[1] and the gate of the transistor 10[1].
  • the capacitance C2 of the transistor 10[1] is preferably formed between the wiring 131 to which the power supply potential is supplied and the gate of the transistor 10[1] (see FIG. 35).
  • the node ND[1] is in a floating state except during the period when both the signals CLK_2 and CLK_3 are at the potential H.
  • the capacitance C1 of each of the transistors 10[2], 10[6], 10[9], and 10[11] be formed between the wiring 132 to which the power supply potential is supplied and the gate.
  • the conductive layer 160[2] be electrically connected to the wiring 132 (see FIG. 23).
  • the conductive layer 160[2] functions as a source electrode of each of the transistors 10[2], 10[6], 10[9], and 10[11].
  • each capacitance C1 is connected in parallel to the capacitance 20[1]. This enhances the effect of suppressing the potential fluctuation of the node ND[1] (see FIG. 35).
  • the capacitance C2 of each of the transistors 10[4] and 10[5] between the node ND[1] and the gate. It is also preferable to form the capacitance C1 of the transistor 10[5] between the wiring 131 to which the power supply potential is supplied and the gate.
  • the conductive layer 160[3] is electrically connected to the wiring 131 (see FIG. 23). The conductive layer 160[3] functions as a drain electrode of the transistor 10[5].
  • the capacitance C1 of the transistor 10[4] between the drain and gate of the transistor 10[4].
  • the conductive layer 160[3] functions as the drain electrode of the transistor 10[3].
  • the capacitance value of the parasitic capacitance generated between the node ND [3] and the gate of the transistor 10 [7] is smaller than the capacitance values of the capacitance 20 [2] and the capacitance 20 [3]. Therefore, in the transistor 10 [7], it is preferable that the capacitance C1 is generated between one of the source or drain of the transistor 10 [7] and the gate, and the capacitance C2 is generated between the other of the source or drain of the transistor 10 [7] and the gate (see FIG. 35).
  • Fig. 36 is a timing chart for explaining an operation example of the shift register 100.
  • a signal LIN[1] with a potential H is supplied to the signal output circuit 110[1].
  • a signal with a potential H is output as the signal OUT[1] in synchronization with the signal LIN[1], the signal CLK_1, the signal CLK_4, and the signal PWC_1.
  • a potential L is output as signal OUT[1].
  • a potential H is output as signal OUT[2] in synchronization with signals CLK_1, CLK_2, and PWC_2.
  • a potential L is output as signal OUT[2].
  • a potential H is output as signal OUT[3] in synchronization with signals CLK_3, CLK_4, and PWC_3.
  • potential L is output as signal OUT[3].
  • potential H is output as signal OUT[4] in synchronization with signals CLK_3, CLK_4, and PWC_4. In this manner, potential H is output as signal OUT in order from the 1st stage to the n+2th stage.
  • a transistor used in a semiconductor device such as a signal output circuit according to one embodiment of the present invention
  • a transistor having a structure other than a VFET such as a planar or staggered transistor
  • a VFET may be used in combination with a transistor having a structure other than a VFET.
  • Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, and electronic devices with relatively large screens such as large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • large game machines such as pachinko machines
  • digital cameras digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, or a function to read out programs or data recorded on a recording medium.
  • the electronic device shown in Figures 37A, 37B, and 38A to 38C has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), and a microphone 9008.
  • operation keys 9005 including a power switch or an operation switch
  • connection terminal 9006 includes a connection terminal 9006
  • a sensor 9007 including a function for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or
  • the electronic devices shown in Figures 37A, 37B, and 38A to 38C have various functions. For example, they may have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, or a function of reading and processing programs or data recorded on a recording medium.
  • the functions of the electronic device are not limited to these, and the electronic device may have various functions.
  • the electronic device may have multiple display units.
  • the electronic device may have a camera or the like to capture still images or videos and store them on a recording medium (external or built into the camera), and a function of displaying the captured images on the display unit.
  • Figures 37A and 37B are perspective views showing electronic device 9203.
  • Figure 37A is a perspective view of electronic device 9203 in an unfolded state
  • Figure 37B is a perspective view of electronic device 9203 in a folded state.
  • Electronic device 9203 is capable of executing various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games, by way of example.
  • the electronic device 9203 of one embodiment of the present invention includes a display module of one embodiment of the present invention and a housing 9000 (see FIG. 37A).
  • the housing 9000 includes a hinge 9055, and can be bent with the display region 731B facing inward (see FIG. 37B).
  • the electronic device 9203 also includes a camera 9002, a speaker 9003, operation keys 9005, a connection terminal 9006, a sensor 9007, a microphone 9008, and a battery 6518.
  • Figures 38A to 38C are perspective views showing a foldable mobile information terminal 9201.
  • Figure 38A is a perspective view of the mobile information terminal 9201 in an unfolded state
  • Figure 38C is a perspective view of the mobile information terminal 9201 in a folded state
  • Figure 38B is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of Figures 38A and 38C to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and has excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

La présente invention concerne un nouveau module d'affichage qui excelle en termes de commodité, d'utilité ou de fiabilité. Le module d'affichage comprend un premier support, un deuxième support, une première couche adhésive, un espace, une couche fluidisée et un dispositif d'affichage. Le premier support chevauche le deuxième support, le premier support est doté de flexibilité, le deuxième support présente une élasticité supérieure à celle du premier support, la première couche adhésive lie le premier support et le deuxième support l'un à l'autre, l'espace est formé entre le premier support et le deuxième support, et l'espace contient la couche fluidisée. La couche fluidisée est fluide entre 0 °C et 80 °C inclusivement, et elle présente une différence d'indice de réfraction entre 0 et 0,2 inclusivement par rapport au premier support. Le dispositif d'affichage est pris en sandwich entre le premier corps de support et le deuxième corps de support, il a pour fonction d'exécuter un affichage vers le premier corps de support, et il comprend une première zone d'affichage, une deuxième zone d'affichage et une troisième zone d'affichage. La première zone d'affichage est fixe entre le premier support et la première couche adhésive, la deuxième zone d'affichage est prise en sandwich entre la première zone d'affichage et la troisième zone d'affichage, peut être courbée et est positionnée à l'intérieur de l'espace, et la troisième zone d'affichage est positionnée à l'intérieur de l'espace et coulisse à l'intérieur de l'espace lorsque la deuxième zone d'affichage est courbée.
PCT/IB2024/053973 2023-05-02 2024-04-24 Module d'affichage et appareil électronique Pending WO2024228089A1 (fr)

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JP2023075962 2023-05-02

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1609943A (zh) * 2003-08-22 2005-04-27 旭硝子株式会社 显示装置及其制造方法
JP2015135484A (ja) * 2013-12-20 2015-07-27 株式会社半導体エネルギー研究所 半導体装置
CN107293220A (zh) * 2016-04-13 2017-10-24 摩托罗拉移动有限责任公司 柔性显示器堆叠体和布置方法
JP2018081186A (ja) * 2016-11-16 2018-05-24 株式会社半導体エネルギー研究所 情報処理装置、表示装置および電子機器
CN109377889A (zh) * 2018-12-19 2019-02-22 武汉华星光电半导体显示技术有限公司 柔性显示装置
WO2019070005A1 (fr) * 2017-10-04 2019-04-11 Ａｇｃ株式会社 Dispositif d'affichage et téléviseur
US20200051881A1 (en) * 2018-08-13 2020-02-13 Lg Display Co., Ltd. Foldable Display Device
CN111047980A (zh) * 2018-10-12 2020-04-21 华为技术有限公司 柔性显示面板及终端设备

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1609943A (zh) * 2003-08-22 2005-04-27 旭硝子株式会社 显示装置及其制造方法
JP2015135484A (ja) * 2013-12-20 2015-07-27 株式会社半導体エネルギー研究所 半導体装置
CN107293220A (zh) * 2016-04-13 2017-10-24 摩托罗拉移动有限责任公司 柔性显示器堆叠体和布置方法
JP2018081186A (ja) * 2016-11-16 2018-05-24 株式会社半導体エネルギー研究所 情報処理装置、表示装置および電子機器
WO2019070005A1 (fr) * 2017-10-04 2019-04-11 Ａｇｃ株式会社 Dispositif d'affichage et téléviseur
US20200051881A1 (en) * 2018-08-13 2020-02-13 Lg Display Co., Ltd. Foldable Display Device
CN111047980A (zh) * 2018-10-12 2020-04-21 华为技术有限公司 柔性显示面板及终端设备
CN109377889A (zh) * 2018-12-19 2019-02-22 武汉华星光电半导体显示技术有限公司 柔性显示装置

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