WO2024224954A1 - Imaging device - Google Patents

Abstract

An imaging device comprises: a pixel; an amplifier circuit electrically connected to the pixel, the amplifier circuit amplifying a pixel signal and a reset signal, which are read from the pixel and are each an analog signal, at one amplification factor of a plurality of amplification factors, and outputting the amplified signals; an AD conversion circuit that is electrically connected to the amplification circuit and that converts output from the amplification circuit into digital signals; and a determination circuit that is electrically connected to the pixel and that compares the level of the pixel signal with at least one threshold value. The determination circuit sets the amplification factor of the amplification circuit to one amplification factor of the plurality of amplification factors on the basis of the comparison result between the level of the pixel signal and the at least one threshold value. The amplifier circuit amplifies the pixel signal and the reset signal at the one set amplification factor.

Description

Imaging device

This disclosure relates to an imaging device.

In recent years, proposals have been made to achieve a wide dynamic range in imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide-Semiconductor) image sensors.

Patent Document 1 discloses a photoelectric conversion device having a plurality of analog signal output units that output analog signals based on a plurality of pixels, and a plurality of signal processing units. Each of the plurality of signal processing units is provided corresponding to one of the plurality of analog signal output units, and includes a gain applying unit that applies a gain to the analog signal, and an AD conversion unit. The gain applying unit outputs either a first amplified signal obtained by multiplying the analog signal by a first gain of 1 or less, or a second amplified signal obtained by multiplying the analog signal by a second gain lower than the first gain. The AD conversion unit AD converts the first amplified signal or the second amplified signal output from the gain applying unit. The signal processing unit has a determination unit. The determination unit provides either the first amplified signal or the second amplified signal to the AD conversion unit based on a result of comparing the first amplified signal with a threshold value.

JP 2014-131147 A

There is a demand for improved S/N and dynamic range in imaging devices.

In one non-limiting exemplary embodiment, the imaging device of the present disclosure includes a pixel, an amplifier circuit electrically connected to the pixel, the amplifier circuit amplifying a pixel signal and a reset signal, each of which is an analog signal, read from the pixel at one of a plurality of gains and outputting the amplified signal, an AD conversion circuit electrically connected to the amplifier circuit and converting the output from the amplifier circuit into a digital signal, and a determination circuit electrically connected to the pixel and comparing the level of the pixel signal with at least one threshold value, the determination circuit setting the gain of the amplifier circuit to the one of the plurality of gains based on a comparison result between the level of the pixel signal and the at least one threshold value, and the amplifier circuit amplifying the pixel signal and the reset signal at the one gain that has been set.

In another non-limiting exemplary embodiment, the imaging device of the present disclosure includes a pixel, an AD conversion circuit electrically connected to the pixel, the AD conversion circuit converting a pixel signal and a reset signal, each of which is an analog signal, read from the pixel into a digital signal, a reference signal generation circuit generating and outputting a ramp signal that is a reference signal, an amplifier circuit electrically connected to the reference signal generation circuit amplifying and outputting the ramp signal at one of a plurality of amplification factors, and a judgment circuit electrically connected to the pixel and comparing the level of the pixel signal with at least one threshold value, the AD conversion circuit including a comparison circuit comparing the respective levels of the pixel signal and the reset signal with the amplified ramp signal output from the amplifier circuit, the judgment circuit setting the amplification factor of the amplifier circuit to the one of the plurality of amplification factors based on the comparison result of the level of the pixel signal with the at least one threshold value, and the amplifier circuit amplifying the ramp signal at the one amplification factor set by the judgment circuit during the period in which the pixel signal and the reset signal are converted into a digital signal.

In yet another non-limiting exemplary embodiment, the imaging device of the present disclosure includes a pixel, an AD conversion circuit that converts an analog signal output from the pixel into a digital signal, a determination circuit electrically connected to the pixel that compares the level of the analog signal with at least one threshold value, and a holding circuit that holds the comparison result between the level of the analog signal and the at least one threshold value.

According to one aspect of the present disclosure, an imaging device with improved S/N and dynamic range is provided.

FIG. 1 is a block diagram illustrating a schematic example of a configuration of an imaging device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating a schematic configuration example of a pixel. FIG. 3 is a circuit diagram showing an example of a circuit configuration of a pixel. FIG. 4 is a circuit diagram showing another example of the circuit configuration of a pixel. FIG. 5 is a block diagram illustrating a schematic configuration of a conversion circuit according to the first embodiment of the present disclosure. FIG. 6 is a block diagram illustrating a schematic configuration of the conversion circuit according to the first embodiment of the present disclosure. FIG. 7A is a circuit diagram showing a comparator according to a first configuration example at the functional block level. FIG. 7B is a circuit diagram showing the comparator according to the first configuration example at the symbol level. FIG. 7C is a circuit diagram showing the comparator according to the first exemplary configuration at the transistor level. FIG. 7D is a diagram showing the relationship between the pixel signal, which is the input signal to the comparator, and the output signal. FIG. 8A is a circuit diagram showing a comparator according to the second configuration example at the functional block level. FIG. 8B is a circuit diagram showing the comparator according to the second configuration example at the symbol level. FIG. 8C is a circuit diagram showing the comparator according to the second exemplary configuration at the transistor level. FIG. 8D is a diagram showing the relationship between the pixel signal, which is the input signal of the comparator, and the output signal. FIG. 9A is a circuit diagram showing a comparator according to the third configuration example at the functional block level. FIG. 9B is a circuit diagram showing the comparator according to the third configuration example at the symbol level. FIG. 9C is a circuit diagram showing the comparator according to the third exemplary configuration at the transistor level. FIG. 9D is a diagram showing the relationship between the pixel signal, which is the input signal of the comparator, and the output signal. FIG. 10A is a circuit diagram showing an attenuator according to a first configuration example. FIG. 10B is a circuit diagram showing an attenuator according to the second configuration example. FIG. 11A is a diagram illustrating a first configuration example of the holding circuit. FIG. 11B is a diagram showing a truth table of the latch circuit. FIG. 12 is a diagram illustrating a second configuration example of the holding circuit. FIG. 13 is a timing chart showing an example of the procedure of the operation of an imaging device including the conversion circuit shown in FIG. FIG. 14 is a timing chart showing another example of the procedure of the operation of the imaging device including the conversion circuit shown in FIG. FIG. 15 is a schematic diagram showing the relationship between the range, threshold, and attenuation rate of a pixel signal of the imaging device according to the first embodiment of the present disclosure. FIG. 16 is a schematic diagram showing the relationship between the range, threshold, attenuation rate, and non-operating range of the source follower circuit of the pixel signal of the imaging device according to the first embodiment of the present disclosure. FIG. 17 is a block diagram illustrating a modified example of the conversion circuit according to the first embodiment of the present disclosure. FIG. 18A is a circuit diagram showing a configuration example of an attenuator in a modified example of the conversion circuit according to the first embodiment of the present disclosure. FIG. 18B is a circuit diagram showing another configuration example of the attenuator in the modified example of the conversion circuit according to the first embodiment of the present disclosure. FIG. 19 is a schematic diagram showing the relationship between the range, threshold value, and attenuation rate of a pixel signal in a modified example of the conversion circuit according to the first embodiment of the present disclosure. FIG. 20 is a block diagram illustrating a schematic configuration of a conversion circuit according to a second embodiment of the present disclosure. FIG. 21A is a circuit diagram illustrating a configuration example of an attenuator according to a second embodiment of the present disclosure. FIG. 21B is a circuit diagram showing another configuration example of the attenuator according to the second embodiment of the present disclosure. FIG. 22 is a timing chart showing an example of the procedure of the operation of the imaging device according to the second embodiment of the present disclosure. FIG. 23 is a timing chart showing another example of the procedure of the operation of the imaging device according to the second embodiment of the present disclosure. FIG. 24 is a schematic diagram showing the relationship between the range, threshold value, and AD conversion gain of a pixel signal in an imaging device according to a second embodiment of the present disclosure. FIG. 25 is a block diagram illustrating a modified example of the conversion circuit according to the second embodiment of the present disclosure. FIG. 26 is a schematic diagram showing the relationship between the range of a pixel signal, a threshold value, and an AD conversion gain in a modified example of the conversion circuit according to the second embodiment of the present disclosure. FIG. 27 is a schematic diagram illustrating an example of the configuration of a camera system according to the third embodiment of the present disclosure.

<Knowledge that forms the basis of this disclosure>
Generally, pixel signals output from pixels are analog signals, and when the range of analog-to-digital (AD) conversion is small compared to the maximum range (or full range) of the pixel signal, it is necessary to attenuate the pixel signal so that it falls within the range of AD conversion. On the other hand, when the pixel signal is attenuated, the noise in the processing after AD conversion becomes relatively large compared to the pixel signal. Therefore, when an attenuator is used, the S/N ratio may decrease in the dark or in the case of a subject with low illumination. Here, the ratio of the noise level to the voltage level of the pixel signal is generally called the "S/N ratio" or simply "S/N".

In response to the above problem, the inventors of the present application focused on a configuration that switches the attenuation rate of an attenuator depending on the magnitude of the voltage level of a pixel signal (hereinafter referred to as the "level of the pixel signal"), and arrived at a new imaging device that can attenuate both the pixel signal and the reset signal at the same attenuation rate depending on the magnitude of the level of the pixel signal. According to an imaging device according to one aspect of the present disclosure, it is possible to perform AD conversion of a pixel signal at the maximum range of the pixel signal while avoiding S/N degradation in low illuminance. As a result, the dynamic range can be improved. Furthermore, since the time required for AD conversion is shortened, the technology of the present disclosure can also contribute to higher speeds.

From another perspective, in a typical single-slope AD conversion circuit, the resolution of the AD conversion is controlled by the slope of the reference signal Vramp. For example, when the signal level is relatively large, AD conversion is performed using a reference signal Vramp that changes by 1 V in a given time, and when the signal level is relatively small, AD conversion is performed using a reference signal Vramp that changes by 250 mV in a given time. In the former case, the AD conversion gain is 0 dB, and in the latter case, the AD conversion gain is 12 dB. In this way, by changing the AD conversion gain according to the signal level, AD conversion is performed appropriately with a constant bit width.

When the AD conversion gain is low, large signals can be AD converted, but the resolution decreases. As a result, quantization noise increases. In contrast, when the AD conversion gain is high, quantization noise can be suppressed. However, the signal range that can be handled becomes smaller.

In response to the above problem, the inventors have focused on a configuration in which AD conversion is performed with a relatively low AD conversion gain when the pixel signal level is greater than the threshold, and with a relatively high AD conversion gain when the pixel signal is less than the threshold. With this configuration, it is possible to perform AD conversion of pixel signals in the maximum range of the pixel signal while suppressing quantization noise and avoiding S/N degradation in low illumination. As a result, the dynamic range can be improved.

An overview of one aspect of the present disclosure is as follows:

[Item 1]
Pixels and
an amplifier circuit electrically connected to the pixel, the amplifier circuit amplifying a pixel signal and a reset signal, each of which is an analog signal, read from the pixel by one of a plurality of amplification factors and outputting the amplified signal;
an AD conversion circuit electrically connected to the amplifier circuit and converting an output from the amplifier circuit into a digital signal;
a determination circuit electrically connected to the pixel and configured to compare a level of the pixel signal with at least one threshold;
Equipped with
the determination circuit sets an amplification factor of the amplifier circuit to the one of the plurality of amplification factors based on a comparison result between the level of the pixel signal and the at least one threshold value;
the amplifier circuit amplifies the pixel signal and the reset signal by the one set amplification factor;
Imaging device.

[Item 2]
Pixels and
an AD conversion circuit electrically connected to the pixel, the AD conversion circuit converting a pixel signal and a reset signal, each of which is an analog signal and read out from the pixel, into a digital signal; and a reference signal generation circuit generating and outputting a ramp signal, which is a reference signal;
an amplifier circuit electrically connected to the reference signal generating circuit, amplifying the ramp signal by one of a plurality of amplification factors and outputting the amplified ramp signal;
a determination circuit electrically connected to the pixel and configured to compare a level of the pixel signal with at least one threshold;
Equipped with
the AD conversion circuit includes a comparison circuit that compares the levels of the pixel signal and the reset signal with the amplified ramp signal output from the amplifier circuit,
the determination circuit sets an amplification factor of the amplifier circuit to the one of the plurality of amplification factors based on a comparison result between the level of the pixel signal and the at least one threshold value;
the amplifier circuit amplifies the ramp signal by the one amplification factor set by the determination circuit during a period in which the pixel signal and the reset signal are converted into digital signals.
Imaging device.

[Item 3]
3. The imaging device according to claim 1, wherein the determination circuit includes an inverter circuit.

[Item 4]
the inverter circuit includes an N-type MOS transistor and a P-type MOS transistor;
4. The imaging device according to item 3, wherein the W/L ratio of the N-type MOS transistor is equal to or greater than 1/2 of the W/L ratio of the P-type MOS transistor.

[Item 5]
5. The imaging device according to claim 1, further comprising a holding circuit that holds the comparison result of the determination circuit.

[Item 6]
6. The imaging device according to claim 5, wherein the holding circuit includes a switch electrically connected between the pixel and the inverter circuit.

[Item 7]
6. The imaging device according to claim 5, wherein the holding circuit includes a latch electrically connected to a rear stage of the inverter circuit.

[Item 8]
3. The imaging device according to claim 1, wherein the determination circuit includes a differential amplifier.

[Item 9]
a signal processing circuit to which the digital signal output from the AD conversion circuit is input,
9. The imaging device according to any one of items 1 to 8, wherein the signal processing circuit applies a correction process to the digital signal depending on a comparison result of the determination circuit.

[Item 10]
the determination circuit is a first determination circuit,
a second determination circuit electrically connected to the pixel and configured to compare a level of the pixel signal with at least one other threshold value different from the at least one threshold value;
a first holding circuit electrically connected to the first determination circuit and the amplifier circuit, the first holding circuit holding the comparison result of the first determination circuit;
a second holding circuit electrically connected to the second determination circuit and the amplifier circuit, the second holding circuit holding the comparison result of the second determination circuit;
3. The imaging device according to item 1 or 2, further comprising:

[Item 11]
11. The imaging device according to any one of items 1 to 10, wherein the pixel includes a pixel electrode, a counter electrode facing the pixel electrode, and a photoelectric conversion layer located between the pixel electrode and the counter electrode.

[Item 12]
12. The imaging device according to any one of items 1 to 11, wherein the pixel outputs the reset signal after outputting the pixel signal during one frame period.

[Item 13]
Pixels and
a determination circuit electrically connected to the pixel and configured to compare a level of an analog signal output from the pixel with at least one threshold;
a holding circuit that holds a comparison result between the level of the analog signal and the at least one threshold value;
An imaging device comprising:

Below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, processing contents, processing sequences, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradictions arise. Furthermore, among the components in the following embodiments, components that are not described in an independent claim that indicates a superordinate concept will be described as optional components. In the following description, components that have substantially the same function will be indicated by common reference symbols, and descriptions may be omitted.

<Overall configuration of imaging device>
First, the overall configuration of an imaging device according to an embodiment of the present disclosure will be described with reference to FIG. 1. FIG. 1 is a block diagram that illustrates an example of the configuration of an imaging device according to an embodiment of the present disclosure. The imaging device 200 illustrated in FIG. 1 is, for example, a solid-state imaging device having a so-called stacked type configuration described later. However, the imaging device 200 may be a solid-state imaging device such as a CMOS image sensor. The imaging device 200 includes a pixel unit 201, a vertical scanning circuit 202, a horizontal transfer scanning circuit 203, a reference signal generating circuit 204, a drive control circuit 205, a column processing unit 206, a plurality of vertical signal lines 212, a horizontal signal line 213, and an amplifier circuit 214.

The pixel section 201 includes a plurality of pixels 10 arranged in a matrix. Each pixel 10 generates a signal charge of a magnitude according to the intensity of the incident light by photoelectrically converting the incident light, and generates pixel signals VSIG0 to VSIGp (p is an integer equal to or greater than 1) that are electrical signals based on the signal charge. The pixel signals are an example of signals handled in the embodiments of the present disclosure. Details of the pixels 10 will be described later.

The vertical scanning circuit 202 is configured to control row addresses and row scanning. The vertical scanning circuit 202 generates pixel control signals such as VSEL or VRST, which will be described later, and outputs them to the pixel section 201.

Each of the multiple vertical signal lines 212 is provided for each column, and is connected to the pixels arranged in the corresponding column among the multiple pixels 10. More specifically, each vertical signal line 212 transmits pixel signals VSIG0 to VSIGp output from the pixels 10 arranged in the corresponding column among columns 0 to p of the multiple pixels 10 to the column processing unit 206.

The column processing unit 206 includes a plurality of column circuits 207. Each column circuit 207 is provided for each column of a plurality of pixels 10. The column processing unit 206 generates image data based on a digital signal corresponding to a pixel signal output from each pixel 10. Each column circuit 207 includes a load current circuit 215 and a conversion circuit 220. Each column circuit 207 is connected to the vertical signal line 212 of the corresponding column. When a pixel signal is transmitted to the vertical signal line 212 of the corresponding column, the load current circuit 215 supplies a load current to the vertical signal line 212. The load current circuit 215 forms a source follower circuit together with the vertical signal line 212 and an amplification transistor of the pixel described later. Each column circuit 207 in the embodiment of the present disclosure further includes a counter 209 and a memory 211 described later.

The reference signal generation circuit 204 generates a reference signal Vramp and supplies the generated reference signal Vramp to each of the multiple conversion circuits 220. The reference signal Vramp in the embodiment of the present disclosure is a ramp signal that at least monotonically increases or decreases. The ramp signal indicates a time change in a voltage value that changes at a predetermined rate of change (slope). The conversion circuit 220 compares the reference signal Vramp with the pixel signal transmitted from the pixel 10 to the vertical signal line 212. The configuration and operation of the conversion circuit 220 will be described in detail later.

The horizontal transfer scanning circuit 203 is configured to control column addresses and column scanning. The horizontal signal line 213 transmits a plurality of digital signals generated in the column processing unit 206 sequentially for each column. The amplifier circuit 214 is connected to the column processing unit 206 via the horizontal signal line 213. The digital signals of each column are amplified by the amplifier circuit 214 via the horizontal signal line 213 in order from the digital signal corresponding to the pixel signal output from the pixel of the column selected by the horizontal transfer scanning circuit 203, and are output to the outside of the imaging device.

The imaging device 200 according to an embodiment of the present disclosure further includes a signal processing circuit 208 to which the digital signal output from the conversion circuit 220 is input. However, the signal processing circuit 208 is not essential. The signal processing circuit 208 may be realized by a microcontroller including one or more processors and memories. The signal processing circuit 208 may include a dedicated logic circuit that performs the processing described below. The signal processing circuit 208 may be configured to apply correction processing to the digital signal depending on the comparison result of the determination circuit described below. For example, the signal processing circuit 208 may correct the AD conversion value by applying a shift correction to the AD conversion value depending on the attenuation rate of each pixel, as described below.

The drive control circuit 205 generates signals for driving each circuit inside the imaging device 200. The drive control circuit 205 generates various internal clocks collectively based on a master clock signal input from the MCLK terminal and data signals for various settings input from the DATA terminal, and supplies the generated internal clocks to each circuit inside the imaging device 200. For example, the drive control circuit 205 supplies a control signal CN to the vertical scanning circuit 202. The vertical scanning circuit 202 operates in accordance with this control signal CN.

<Configuration of pixel and conversion circuit>
An example of the configuration of the pixel 10 will be described with reference to FIGS.

2 is a schematic diagram showing an example of the configuration of pixel 10. FIG. 3 is a circuit diagram showing an example of the circuit configuration of pixel 10. Pixel 10 illustrated in FIG. 2 includes a pixel electrode 12, a counter electrode 13 facing pixel electrode 12, and a photoelectric conversion unit 18 including a photoelectric conversion layer 11 located between pixel electrode 12 and counter electrode 13. Photoelectric conversion unit 18 converts incident light into electricity. Pixel electrode 12 and counter electrode 13 are a pair of electrodes stacked on photoelectric conversion layer 11 so as to sandwich photoelectric conversion layer 11. Thus, pixel 10 shown in FIG. 2 is a stacked photoelectric conversion element. However, the pixel in the embodiment of the present disclosure is not limited to a stacked photoelectric conversion element. Photoelectric conversion layer 11 generates excitons, for example, pairs of holes and electrons, upon receiving incident light. Pixel electrode 12 collects one of the generated pairs of holes and electrons as a signal charge. For example, a voltage is supplied to the counter electrode 13 so that a potential difference occurs between the pixel electrode 12 and the counter electrode 13, and one of the pairs of holes and electrons is collected by the pixel electrode 12 based on the potential difference.

The pixel 10 includes a charge storage section (hereinafter referred to as "floating diffusion: FD") that stores the signal charge converted by the photoelectric conversion section 18. The FD is provided in the semiconductor substrate 15. The pixel electrode 12 and the FD are electrically connected via a contact plug 14. The signal charge collected by the pixel electrode 12 is stored in the FD.

The pixel 10 includes a readout circuit provided on the semiconductor substrate 15. The readout circuit of the pixel 10 shown in FIG. 3 includes an amplification transistor M1, a selection transistor M2, and a reset transistor M3. The amplification transistor M1 amplifies a pixel signal according to the magnitude of the charge stored in the FD. The selection transistor M2 selects whether or not to output the pixel signal amplified by the amplification transistor M1 to the vertical signal line 212. In this way, a pixel signal according to the potential of the FD is output to the vertical signal line 212. The reset transistor M3 resets the FD to the desired reset voltage V1.

FIG. 4 is a circuit diagram showing another example of the circuit configuration of pixel 10. Pixel 10 shown in FIG. 4 includes a photodiode PD as a photoelectric conversion unit, and further includes a transfer transistor M4 for transferring the signal charge generated in the photodiode PD to the FD. In this manner, the photoelectric conversion unit may be configured using a photoelectric conversion film, or may be configured using a photodiode. When pixel 10 includes a photodiode PD, it may further include a transistor for discharging the signal charge generated in the photodiode PD. Using this transistor makes multiple exposures possible.

The exposure of the multiple pixels 10 in the pixel section 201 may be by global shutter driving or rolling shutter driving. In the embodiment of the present disclosure, the pixel 10 outputs a pixel signal VSIG and then outputs a reset signal during one frame period. The pixel signal VSIG read out by the readout circuit of the pixel 10 is transmitted to the conversion circuit 220 via the vertical signal line 212.

First Embodiment
A conversion circuit according to a first embodiment of the present disclosure will be described with reference to FIGS.

[1. Configuration of conversion circuit]
5 is a block diagram illustrating a configuration of a conversion circuit 220a according to the first embodiment of the present disclosure. The conversion circuit 220a illustrated in FIG. 5 includes a comparator 240, an attenuator 250, a comparator 260, a holding circuit 270, a capacitance C1, and a Cramp.

The comparator 240 and the attenuator 250 are electrically connected to the pixel 10 via the vertical signal line 212, and the pixel signal VSIG from the pixel 10 is input. The input terminal of the holding circuit 270 is connected to the output terminal of the comparator 240. The output terminal of the holding circuit 270 is connected to the signal line 222. The output signal DOUT2 from the holding circuit 270 is output to the outside of the conversion circuit 220 via the signal line 222. Furthermore, the output terminal of the holding circuit 270 is also connected to the attenuator 250. One end of the capacitance C1 is connected to the output terminal of the attenuator 250, and the other end of the capacitance C1 is connected to the input terminal of the comparator 260. One end of the capacitance Cramp is connected to the reference signal generation circuit 204, and the other end of the capacitance Cramp is connected to another input terminal of the comparator 260.

The output terminal of the holding circuit 270 is connected to the counter 209 (see FIG. 1) via signal line 222, and the output terminal of the comparator 260 is connected to the counter 209 via signal line 221. Note that the output terminal of the comparator 260 may be connected to the memory 211 instead of the counter 209 via signal line 221, or may be connected to both the counter 209 and the memory 211. Also, in the example shown in FIG. 5, the holding circuit 270 is disposed inside the conversion circuit 220a, but may be disposed inside the counter 209 or the memory 211.

FIG. 6 is a block diagram showing a schematic configuration of another conversion circuit according to the first embodiment of the present disclosure. As shown in FIG. 6, the output terminal of the holding circuit 270 can be connected to the input terminal of the comparator 240. In other words, the holding circuit 320 can be connected to the front stage of the comparator 310.

[2. Comparator (judgment circuit)]
The comparator 240 is electrically connected to the pixel 10 and configured to compare the level of the pixel signal VSIG with at least one threshold value. The comparator 240 may include an inverter circuit, as described below. The comparator 240 sets the gain of the attenuator 250 to one of a plurality of gains based on a result of comparing the level of the pixel signal VSIG with at least one threshold value.

In this embodiment, the comparator 240 is configured to compare the pixel signal VSIG of the corresponding column with a predetermined threshold value and output the comparison result. As the comparator 240, a comparator according to the first to third configuration examples described below can be used. Note that the configuration described below is an example, and there are no particular limitations as long as the configuration can compare the pixel signal VSIG with a predetermined threshold value.

(2.1. First Configuration Example of Comparator)
Fig. 7A is a circuit diagram showing the comparator 240a according to the first configuration example at the functional block level. Fig. 7B is a circuit diagram showing the comparator 240a according to the first configuration example at the symbol level. Fig. 7C is a circuit diagram showing the comparator 240a according to the first configuration example at the transistor level. As shown in Figs. 7A to 7C, the comparator 240a is an inverter type comparator. The comparator 240a is composed of two inverter circuits 242 and 243. Hereinafter, the inverter circuit will be simply referred to as an "inverter".

Comparator 240a includes inverter 242 and inverter 243 connected in series. Pixel signal VSIG is input to inverter 242, and the output signal from inverter 242 is input to inverter 243. Inverter 243 outputs output signal DOUT1. The number of inverters connected in series is not limited to two as shown in the example, and may be one or three or more. The more inverters there are, the more the drive capability can be improved.

As shown in FIG. 7C, inverter 242 includes a P-type MOS transistor 242a and an N-type MOS transistor 242b. Inverter 243, like inverter 242, includes a P-type MOS transistor 243a and an N-type MOS transistor 243b.

FIG. 7D is a diagram showing the relationship between pixel signal VSIG, which is an input signal to comparator 240a, and output signal DOUT1. The upper part (a) of FIG. 7D shows the relationship between pixel signal VSIG and the number of accumulated charges in FD, and the lower part (b) of FIG. 7D shows the relationship between pixel signal VSIG and output signal DOUT1.

In this specification, the logical change in the level of a digital signal from low to high may be expressed simply as "the signal level changes to high." Also, the logical change in the level of a digital signal from high to low may be expressed simply as "the signal level changes to low."

As shown in the upper part (a) of Fig. 7D, when a signal charge is generated by the incidence of light and is accumulated in the FD, the number of accumulated charges in the FD increases, and the pixel signal VSIG also increases. Also, as shown in the lower part (b) of Fig. 7D, when the pixel signal VSIG increases and exceeds the threshold voltage VTH0, the level of the output signal DOUT1 changes logically from Low to High. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of one. Therefore, when the number of accumulated charges in the FD gradually increases and the pixel signal VSIG exceeds the threshold voltage VTH0, the level of the output signal DOUT1 from the comparator 240a changes logically from Low to High. In this way, when the voltage level of the pixel signal VSIG input to the comparator 240a is equal to or higher than the threshold voltage VTH0, the output signal DOUT1 becomes High, and conversely, when the voltage level of the pixel signal VSIG is lower than the threshold voltage VTH0, the output signal DOUT1 becomes Low. The threshold voltage VTH0 is the threshold voltage of the inverter 242, and is determined by the characteristics of the P-type MOS transistor 242a and the N-type MOS transistor 242b. Specifically, the threshold voltage VTH0 is determined by the following formula (1).
VTH0 = (Vhigh - |Vtp| + Vtn・(β_n/β_p) ^1/2 )/(1 + (β_n/β_p) ^1/2 ) (1)
Here, Vhigh is the voltage applied to the source of the P-type MOS transistor 242a, Vtp is the threshold voltage of the P-type MOS transistor 242a, and Vtn is the threshold voltage of the N-type MOS transistor 242b. In addition, β_p and β_n are constants defined by the following equations (2) and (3).
β_p = (W_p/L_p)・μ_p・C_ox (2)
β_n = (W_n/L_n)・μ_n・C_ox (3)
Here, W_p is the gate width of the P-type MOS transistor 242a, L_p is the gate length of the P-type MOS transistor 242a, and μ_p is the carrier mobility of the P-type MOS transistor 242a. W_n is the gate width of the N-type MOS transistor 242b, L_n is the gate length of the N-type MOS transistor 242b, and μ_n is the carrier mobility of the N-type MOS transistor 242b. C_ox is the capacitance per unit volume of the gate oxide film of each of the P-type MOS transistor 242a and the N-type MOS transistor 242b.

Inverter 243 is designed, for example, based on equations (1) to (3) so that the threshold voltage of inverter 243 becomes the desired threshold voltage VTH0. For example, the desired threshold voltage VTH0 can be obtained by optimally designing the gate width and gate length of each of P-type MOS transistor 243a and N-type MOS transistor 243b. Taking inverter 242 as an example, the effective gate width or gate length can be adjusted by providing multiple P-type MOS transistors 242a and/or N-type MOS transistors 242b in parallel or in series. The gate width or gate length of inverter 243 can also be adjusted in the same way as inverter 242.

The inverter-type comparator 240a according to the first configuration example can be configured with a small number of transistors, and is therefore characterized by its area-saving and power-saving features.

(2.2. Second Configuration Example of Comparator)
FIG. 8A is a circuit diagram showing the comparator 240b according to the second configuration example at a functional block level. FIG. 8B is a circuit diagram showing the comparator 240b according to the second configuration example at a symbol level. FIG. 8C is a circuit diagram showing the comparator 240b according to the second configuration example at a transistor level. As shown in FIG. 8A to FIG. 8C, the comparator 240b is an inverter threshold variable type comparator. The comparator 240b is composed of two inverters 243 and 244. The comparator 240b has a configuration in which the inverter 242 in the comparator 240a according to the first configuration example is replaced with an inverter 244 whose threshold voltage is variable.

Comparator 240b includes inverter 244 and inverter 243 connected in series. Pixel signal VSIG is input to inverter 244, and the output signal from inverter 244 is input to inverter 243. A control signal V0 is also applied to inverter 244. In inverter 244, the threshold voltage is changed by control signal V0. Note that inverter 243 is not essential in the configuration shown in FIG. 8. Also, the number of inverters 243 is not limited to one, and can be two or more.

As shown in FIG. 8C, the inverter 244 includes one P-type MOS transistor 242a, two N-type MOS transistors 242b, and one transistor 244a. The inverter 244 has a configuration in which one N-type MOS transistor 242b and one transistor 244a are added to the inverter 242 in the first implementation example.

In the inverter 244, two N-type MOS transistors 242b are connected in parallel to the drain of a P-type MOS transistor 242a. The pixel signal VSIG is applied directly to the gate of one of the two N-type MOS transistors 242b without passing through the transistor 244a, and the pixel signal VSIG is applied to the gate of the other N-type MOS transistor 242b via the transistor 244a. The transistor 244a is switched between conductive and non-conductive by a control signal V0. The control signal V0 is output from, for example, the drive control circuit 205.

FIG. 8D is a diagram showing the relationship between pixel signal VSIG, which is an input signal to comparator 240b, and output signal DOUT1. The upper part (a) of FIG. 8D shows the relationship between pixel signal VSIG and the number of accumulated charges in FD, and the lower part (b) of FIG. 8D shows the relationship between pixel signal VSIG and output signal DOUT1.

In the comparator 240b, the basic relationship between the pixel signal VSIG and the output signal DOUT1 is as described with reference to FIG. 7D. It differs from the comparator 240a according to the first configuration example in that the threshold voltage can be changed to the threshold voltage VTH0 or the threshold voltage VTH1 by switching the level of the control signal V0 between High and Low.

In the second configuration example, the judgment level of the comparator 240b can be changed by the control signal V0. As shown in FIG. 8D, when the level of the control signal V0 is low, the number of accumulated charges in the FD gradually increases, and when the pixel signal VSIG exceeds the threshold voltage VTH0, the level of the output signal DOUT1 of the comparator 240b changes logically from low to high. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of one. When the level of the control signal V0 is low, the transistor 244a is in a non-conductive state, so that the pixel signal VSIG is applied to only one of the two N-type MOS transistors 242b. As a result, the threshold voltage VTH0 of the inverter 244 is the same as the threshold voltage of the inverter 242 in the first configuration example.

When the level of the control signal V0 is high, the number of accumulated charges in the FD gradually increases, and when the pixel signal VSIG exceeds the threshold voltage VTH1, the level of the output signal DOUT1 of the comparator 240b changes logically from low to high. When the level of the control signal V0 is high, the transistor 244a is in a conductive state, so that the pixel signal VSIG is applied to both of the two N-type MOS transistors 242b. As a result, the gate width W_n of the N-type MOS transistor 242b is substantially increased. Therefore, as can be seen from the above equations (1) to (3), the threshold voltage of the inverter 244 changes from the threshold voltage VTH0 to the threshold voltage VTH1. In this way, it is possible to change the threshold voltage of the comparator 240b according to the control signal V0.

In the example shown in FIG. 8A to FIG. 8C, two N-type MOS transistors 242b are provided in parallel, but the number of transistors is not limited to two. For example, three or more N-type MOS transistors 242b may be provided in parallel, and two or more control transistors 244a may also be provided. In this way, a configuration that can change to three or more types of threshold voltages can be realized. Also, two or more P-type MOS transistors 242a may be provided in parallel instead of N-type MOS transistors 242b. Also, two or more N-type MOS transistors 242b or P-type MOS transistors 242a may be connected in series. In this case, it is possible to change the threshold voltage of the inverter 244 by changing the effective gate length using the control signal V0.

(2.3. Third Configuration Example of Comparator)
9A is a circuit diagram showing the comparator 240c according to the third configuration example at a functional block level. FIG. 9B is a circuit diagram showing the comparator 240c according to the third configuration example at a symbol level. FIG. 9C is a circuit diagram showing the comparator 240c according to the third configuration example at a transistor level. As shown in FIGS. 9A to 9C, the comparator 240c is a differential amplifier type comparator, and is configured by a differential amplifier 245 to which a reference signal VTH2 whose voltage value can be changed is input. The pixel signal VSIG and the reference signal VTH2 are input to two input terminals of the differential amplifier 245, respectively. The reference signal VTH2 is output from, for example, the drive control circuit 205.

FIG. 9D is a diagram showing the relationship between the pixel signal VSIG, which is the input signal of the comparator 240c, and the output signal DOUT1. The upper part (a) of FIG. 9D shows the relationship between the pixel signal VSIG and the number of accumulated charges in the FD. The lower part (b) of FIG. 9D shows the relationship between the pixel signal VSIG and the output signal DOUT1.

As shown in FIG. 9D, when the number of accumulated charges in FD gradually increases and the level of the pixel signal VSIG exceeds the level of the reference signal VTH2, the level of the output signal DOUT1 from the comparator 240c changes logically from low to high. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of one.

In the third configuration example, it is possible to change the judgment level of the comparator 240c by changing the reference signal VTH2. When the level of the pixel signal VSIG is less than the level of the reference signal VTH2, which is the threshold value, the level of the output signal DOUT1 becomes Low, and when the level of the pixel signal VSIG is equal to or greater than the level of the reference signal VTH2, the level of the output signal DOUT1 becomes High. In this way, by using the differential amplifier 245, the threshold value for judging the pixel signal VSIG can be flexibly set.

[3. Attenuator (amplifier circuit)]
The attenuator 250 in this embodiment is electrically connected to the pixel 10. The attenuator 250 is configured to amplify the pixel signal and the reset signal, which are analog signals read from the pixel 10, at one of a plurality of amplification factors and output the amplified signal. The attenuator 250 configured in this manner is an example of an amplifier circuit. The attenuator 250 amplifies each of the pixel signal and the reset signal at a single amplification factor set by the comparator 240. The comparator 240 is an example of a determination circuit. The operation of the attenuator 250 will be described later. As the attenuator 250, attenuators according to the first and second configuration examples described below can be used. Note that the configuration of the attenuator described below is an example, and is not particularly limited as long as it is a configuration that can attenuate the pixel signal VSIG.

(3.1. First Configuration Example of Attenuator)
10A is a circuit diagram showing an attenuator 250a according to a first configuration example. The attenuator 250a includes capacitances Ca and Cb, switches S1 and S2, and an inverter 224. The switch S1 is connected to the output terminal of the inverter 224 via a signal line 223. The switch S2 is connected to a signal line 222. The on/off of the switch S1 is controlled by an output signal from the inverter 224, and the on/off of the switch S2 is controlled by an output signal DOUT2 from the holding circuit 270. With this connection, the on/off of the two switches S1 and S2 is selectively controlled. When the switch S1 is on and the switch S2 is off, the voltage value of the pixel signal VSIG is output as it is to the signal line 251 as the output signal AOUT. When switch S1 is off and switch S2 is on, a voltage value calculated from the voltage division ratio of (capacitance value of Cb)/(capacitance value of Ca+capacitance value of Cb) based on the voltage value of pixel signal VSIG is output from signal line 222 as output signal DOUT2.

(3.2. Second Configuration Example of Attenuator)
FIG. 10B is a circuit diagram showing an attenuator 250b according to a second configuration example. In the configuration example shown in FIG. 10B, the capacitance Ca in the configuration example shown in FIG. 10A is replaced with a resistor Ra, and the capacitance Cb is replaced with a resistor Rb. When the switch S1 is off and the switch S2 is on, a voltage value calculated from a voltage division ratio of (resistance value of Rb)/(resistance value of Ra+resistance value of Rb) based on the voltage value of the pixel signal VSIG is output as an output signal VOUT2 from the signal line 222. In the examples of FIG. 10A and FIG. 10B, control signals of different polarities are given to the switches S1 and S2 using the inverter 224, but the inverter 224 is not essential. For example, the comparator 240 may generate an inverted signal of the output signal DOUT1 and input it to the attenuator 250.

[4. Comparator]
The comparator 260 in this embodiment is electrically connected to the attenuator 250. The analog signal output from the attenuator 250 is converted to a digital signal by the comparator 260 and the counter 209 at the downstream side. The comparator 260 compares the pixel signal VSIG of the corresponding column input via either the switch S1 or S2 of the attenuator 250 and the capacitance C1 with the reference signal Vramp input via the capacitance Cramp, and outputs the comparison result. The output terminal of the comparator 260 is connected to the counter 209 at the downstream side via a signal line 221.

[5. Holding Circuit]
5 is connected to the rear stage of the comparator 240, and the holding circuit 270 in the example shown in Fig. 6 is connected to the front stage of the comparator 240. The holding circuit 270 holds the comparison result or pixel signal VSIG output from the comparator 240.

The holding circuit 270 may be a holding circuit according to the first or second configuration example described below. Note that the configuration of the holding circuit described below is just an example, and there are no particular limitations as long as it is capable of holding the comparison result of the comparator 240 or the pixel signal VSIG.

(5.1. First Configuration Example of Holding Circuit)
FIG. 11A is a diagram showing a first configuration example of a holding circuit. The holding circuit 270 according to the first configuration example is a D-type latch circuit. In the D-type latch circuit 271, as shown in the truth table shown in FIG. 11B, for example, when the control signal CNT supplied from the drive control circuit 205 is High, the output Q is determined based on the input of the D terminal, and when the control signal CNT is Low, the output Q is not considered with respect to the input of the D terminal, and the output Q before the control signal CNT becomes Low is held. In the first configuration example, since it is desirable that the input to the D terminal is a voltage of a High or Low level, as shown in FIG. 5, the holding circuit 270 is connected to the rear stage of the comparator 240. The holding circuit 270 in the example of FIG. 5 includes a latch circuit 271 electrically connected to the rear stage of the comparator 240 including an inverter circuit.

In the example shown in FIG. 10A or 10B, instead of signal line 223, signal line 225 connected to output terminal Q# of holding circuit 270 can be connected to switch S1. In this case, the output signal from output terminal Q# is used as the control signal for switch S1.

(5.2. Second Configuration Example of Holding Circuit)
FIG. 12 is a diagram showing a second example of the holding circuit. The holding circuit 270 according to the second example of the configuration includes a switch S4 and a capacitance Cd. When the level of the control signal CNT is High, the switch S4 is turned on and the voltage of the pixel signal VSIG is charged in the capacitance Cd, and when the level of the control signal CNT is Low, the switch S4 is turned off and the voltage of the pixel signal VSIG is held in the capacitance Cd (the input node of the comparator 240). When the second example of the configuration is adopted, it is preferable that the impedance of the rear stage of the holding circuit 270 is large, so that the holding circuit 270 is connected to the front stage of the comparator 240 as shown in FIG. 6. In this example, the holding circuit 270 includes a switch S4 electrically connected between the pixel 10 and the comparator 240.

6. AD Conversion Operation
1 again, an operation of AD conversion by the conversion circuit 220 included in the imaging device 200 according to an embodiment of the present disclosure will be described. The imaging device 200 according to an embodiment of the present disclosure is an image sensor using a column-parallel AD conversion method. When capturing an image using the imaging device 200, light incident on the imaging device 200 is converted into a pixel signal, which is an electrical signal, in the pixel unit 201.

The exposure, readout, and other operations of each of the multiple pixels 10 in the pixel section 201 are controlled row by row by the vertical scanning circuit 202. The pixel signals VSIG0 to VSIGp generated in the multiple pixels 10 belonging to the row selected by the vertical scanning circuit 202 are output simultaneously to multiple vertical signal lines 212. At this time, each of the multiple load current circuits 215 (or source follower circuits) supplies a load current to the corresponding vertical signal line 212 among the multiple vertical signal lines 212.

With reference to Figure 5, the operation of the conversion circuit 220 to AD convert the pixel signal VSIG will be described in detail.

The comparator 260 compares the reference signal Vramp output by the reference signal generation circuit 204 with the pixel signal VSIG of the column corresponding to the comparator 260. The counter 209 counts the time from when it starts counting at a timing corresponding to the start timing of the ramp signal until the magnitude relationship between the level of the pixel signal VSIG and the level of the reference signal Vramp is inverted. This converts the pixel signal VSIG, which is an analog signal, into a digital signal corresponding to the count value of the counter 209. The comparator 260 and the counter 209 function as an AD conversion circuit. The comparator 260 and the counter 209 in the embodiment of the present disclosure exemplify an AD conversion circuit. The pixel signal VSIG of each column is converted from an analog signal to a digital signal by the AD conversion circuit of each column.

The digital signal output from the AD conversion circuit is stored in the memory 211 included in the column circuit 207 of each column. The digital signal stored in the memory 211 of each column is output via the amplifier circuit 214 in the order of the column selected by the horizontal transfer scanning circuit 203.

Comparator 240 compares the level of pixel signal VSIG of the corresponding column with a predetermined threshold voltage. Comparator 240 outputs a high or low voltage signal to signal line 222, indicating whether the level of pixel signal VSIG is equal to or greater than the predetermined threshold. For example, comparator 240 outputs a logically high level signal when the level of pixel signal VSIG is equal to or greater than the predetermined threshold, and outputs a logically low level signal when the magnitude of pixel signal VSIG is less than the predetermined threshold. Naturally, it goes without saying that the logic may be reversed.

If the level of the pixel signal VSIG is equal to or higher than a predetermined threshold, the attenuator 250 attenuates the input pixel signal VSIG to 1/N (N is 1 or more) and outputs the signal to the subsequent stage. The operation of the attenuator 250 will be described in detail later.

[7. Overall Operation of Imaging Apparatus]
As described above, in general, when the AD conversion range is smaller than the maximum range (or full range) of the pixel signal output from the pixel, the pixel signal needs to be attenuated so that it falls within the AD conversion range. On the other hand, when the pixel signal is attenuated, the noise in the processing after the AD conversion becomes larger relative to the pixel signal. Therefore, when an attenuator is used, the S/N ratio may decrease in the dark or when the subject is in low illumination.

In this embodiment, when the level of a pixel signal exceeds the threshold, an attenuation process is applied to the pixel signal before AD conversion, and when the level of the pixel signal falls below the threshold, the pixel signal is not attenuated and is maintained at the original level before AD conversion. With the imaging device according to this embodiment, it is possible to AD convert pixel signals in the maximum range of the pixel signal while avoiding S/N degradation in low illuminance. This can improve the dynamic range. Furthermore, since the time required for AD conversion is shorter, the imaging device according to this embodiment also contributes to higher speeds.

The operation of the imaging device 200 according to this embodiment will be explained with reference to the timing chart in FIG. 13.

FIGS. 13 and 14 are each a timing chart showing an example of the operation procedure of the imaging device 200 including the conversion circuit 220a shown in FIG. 5. FIG. 13 shows an example of each signal waveform when the level of the pixel signal VSIGp exceeds the threshold value of the comparator 240. In the explanation of the operation procedure of the imaging device 200, each of the multiple pixels 10 is a stacked photoelectric conversion element. The comparator 240 of the conversion circuit 220a has the configuration shown in FIG. 7A, the attenuator 250 has the configuration shown in FIG. 10A, and the holding circuit 270 has the configuration shown in FIG. 11A.

A horizontal synchronization signal HD, which is a pulse signal, is input from the vertical scanning circuit 202 to the pixel section 201. Imaging of the nth row of the pixel section 201 begins at the rising edge of the horizontal synchronization signal HD. A selection signal VSELn is input to the gate of a selection transistor M2 (see FIG. 3) included in each of the multiple pixels 10 in the nth row. When the selection signal VSELn is HIGH, the selection transistor M2 turns on, and a pixel signal according to the potential of the FD is output to the vertical signal line 212.

When the selection transistor M2 is turned on, the pixel signal VSIG is read out to the vertical signal line 212, which causes the potential of the vertical signal line 212 to start changing. The timing chart of FIG. 13 shows the pixel signal VSIG as well as the threshold value VTH of the comparator 240. In this embodiment, the threshold value VTH is set to, for example, 1/2 the saturation signal voltage of the pixel 10.

A reset control signal VRSTn is input to the gate of the reset transistor M3 (see FIG. 3) included in each of the multiple pixels 10 in the nth row. When the reset control signal VRSTn is high, the reset transistor M3 turns on and the potential of the FD is reset to the reset voltage V1.

As shown in FIG. 11A, a control signal CNT that controls the latch operation is input to the latch circuit 271. When the level of the control signal CNT is High, the output Q is determined based on the input to the D terminal, and when the level of the control signal CNT is Low, the output Q is not affected by the input to the D terminal, and the output Q before the level of the control signal CNT became Low is maintained.

The timing chart in FIG. 13 shows the time change of output signal AOUT from attenuator 250 (potential change on signal line 251), the time change of output signal DOUT1 from comparator 240, and the time change of output signal DOUT2 from holding circuit 270 (potential change on signal line 222). Output signal DOUT2 is input to attenuator 250 and controls the on/off of switch S2 shown in FIG. 10A. Also shown is the time change of the inverted signal of output signal DOUT2 (potential change on signal line 223) output from inverter 224 of attenuator 250. The inverted signal of output signal DOUT2 controls the on/off of switch S1.

First, at time t0, the level of the horizontal synchronization signal HD changes from low to high, and imaging of the pixel group in the nth row of the pixel section 201 begins. At time t1, the level of the horizontal synchronization signal HD changes from high to low.

Next, at time t2, the selection signal VSELn goes High, the selection transistor M2 turns on, and the pixel signal VSIG of the nth row is output to the vertical signal line 212. In addition, the control signal CNT goes High, and the holding circuit 270 operates in an operation mode in which it outputs an output value based on the pixel signal VSIG.

Next, at time t3 when the level of the pixel signal VSIG exceeds the threshold VTH of the comparator 240, the output signal DOUT1 from the comparator 240 becomes High. As a result, the inverted signal of the output signal DOUT2 output from the inverter 224 of the attenuator 250, which was High when the level of the pixel signal VSIG was below the threshold VTH, becomes Low, and the state of the switch S1 of the attenuator 250 changes from ON to OFF. Then, the output signal DOUT2, which was Low when the level of the pixel signal VSIG was below the threshold VTH, becomes High, and the state of the switch S2 of the attenuator 250 changes from OFF to ON. In this state, the pixel signal VSIG input to the attenuator 250 is subjected to an attenuation process, and as a result, the voltage level of the output signal AOUT from the attenuator 250 becomes capacitance Cb/(capacity Ca+capacity Cb) times the voltage level of the pixel signal VSIG.

In this embodiment, the capacitance Ca is the same as the capacitance Cb. In this case, the attenuation rate of the attenuator 250 is 1/2. By applying an attenuation process to the pixel signal VSIG according to the level of the pixel signal VSIG, the pixel signal VSIG can be kept within the voltage range of the AD conversion circuit.

Next, at time t4, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t4 to time t5, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the output signal AOUT from the attenuator 250, while the counter 209 continues counting until the output levels of the two match. Also, at time t4, the control signal CNT goes low, and the holding circuit 270 holds the current output value. The holding circuit 270 holds the output value until the next time the control signal CNT goes high. As a result, the output signal DOUT2 does not change and remains high.

Next, at time t5, the reset control signal VRSTn applied to the pixels 10 in the nth row goes high, and the reset operation of the pixels 10 in the nth row is started by the reset transistor M3. Then, at time t6 when the potential level of the vertical signal line 212 corresponding to the level of the reset signal falls below the threshold VTH of the comparator 240, the level of the output signal DOUT1 changes from high to low. At this time, since the level of the control signal CNT remains low, the output signal DOUT2 from the holding circuit 270 does not change.

Next, at time t7, the reset control signal RSTn changes from High to Low, completing the reset operation. Also at time t7, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t7 to time t9, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the reset signal, while the counter 209 continues counting until the output levels of the two match.

Next, at time t10, the horizontal synchronization signal HD goes high, and the imaging device 200 transitions to a readout operation of the pixels 10 in the n+1th row.

In this way, while the selection signal VSELn is high, the comparator 260 performs a first comparison between the level of the pixel signal VSIG and the level of the reference signal Vramp, and then, after the reset operation is completed, the comparator 260 performs a second comparison between the reset signal and the reference signal Vramp.

FIG. 14 shows an example of each signal waveform when the level of the pixel signal VSIG falls below the threshold of the comparator 240. Below, the differences from the case where the pixel signal VSIG exceeds the threshold of the comparator 240 described above will be mainly explained.

In the timing chart shown in FIG. 14, because the level of the pixel signal VSIG read out from the pixel 10 is lower than the threshold value VTH of the comparator 240, the output signal DOUT1 from the comparator 240 does not change from Low, and as a result, the output signal DOUT2 from the holding circuit 270 and the output signal from the inverter 224 of the attenuator 250 (the inverted signal of the output signal DOUT2) remain in the Low and High states, respectively. Therefore, the switch S1 of the attenuator 250 is turned on and the switch S2 is turned off. Therefore, the pixel signal VSIG is not attenuated by the attenuator 250, and the output signal AOUT corresponding to the voltage level of the pixel signal VSIG is output from the attenuator 250.

As described above, when the level of the pixel signal VSIG exceeds the threshold value VTH of the comparator 240, the pixel signal VSIG is attenuated by the attenuator 250, and when the pixel signal Vsig falls below the threshold value VTH of the comparator 240, the pixel signal VSIG is not attenuated by the attenuator 250. By operating the conversion circuit 220 according to the operation sequence described above, it is possible to perform AD conversion of the pixel signal VSIG at the maximum range of the pixel signal while avoiding S/N degradation at low illuminance, thereby improving the dynamic range.

The result of the comparison between the level of the pixel signal VSIG and the threshold value of the comparator 240 may be provided to either or both of the counter 209 and the memory 211 in the subsequent stage. For example, the signal processing circuit 208 inside the imaging device 200 or a camera signal processing unit (described later) externally connected to the imaging device may correct the AD conversion value by shifting the AD conversion value according to the attenuation rate of each pixel so that the level of the pixel signal VSIG of each pixel 10 matches the magnitude of the AD conversion value.

According to the pixel configuration and operation sequence of this embodiment, after a pixel signal corresponding to the intensity of incident light is read out, the pixel is reset and a reset signal is read out. In this way, the pixel signal is first read out and the attenuation rate of the attenuator is determined based on the magnitude relationship between the pixel signal level and the threshold value of the comparator, so that the subsequent reset signal can also be read out at the same attenuation rate. By using the same attenuation rate for reading out the pixel signal and the reset signal, it is possible to improve the S/N ratio without causing unnecessary offsets in the processing after AD conversion. In contrast, when using a pixel configuration and operation sequence that reads out the reset signal first, it is difficult to use the same attenuation rate for reading out the pixel signal and the reset signal because the level of the pixel signal is unknown at the time the reset signal is read out.

Table 1 shows theoretical noise values when the attenuation rate of the attenuator is switched according to the pixel signal level according to the pixel configuration and operation sequence of this embodiment. A high-level signal in Table 1 means a pixel signal with a level higher than the threshold VTH of the comparator 240, and a low-level signal in Table 1 means a pixel signal with a level lower than the threshold VTH of the comparator 240. For ease of explanation, it is assumed that there are two noise sources: (1) noise from the pixel and source follower (SF) circuit, and (2) noise from the AD conversion circuit. Here, the combined noise from the pixel and source follower circuit is α [uVrms], and the noise in the AD conversion subsequent to the comparator 260 is β [uVrms]. The observation point of the noise α is on the vertical signal line 212, and the observation point of the noise β is inside the comparator 260. It is also assumed that there is no attenuation processing other than that of the attenuator 250.

The total noise in Table 1 is the sum of the noise α and β converted to FD (FD converted noise). When converting noise β in AD conversion to FD, noise β can be divided by the attenuation rate of the attenuator. When the attenuation rate is smaller than 1, the value of noise β becomes large. In other words, when the signal is attenuated by the attenuator, the noise due to AD conversion appears relatively large.

As shown in Table 1, since a high-level signal is subjected to attenuation processing by attenuator 250, the signal level is attenuated by 1/2. Therefore, the FD-converted noise becomes (α ² + (2β) ² ) ^1/2 . On the other hand, since a low-level signal is not subjected to attenuation processing by attenuator 250, the signal level is not attenuated. Therefore, the FD-converted noise becomes (α ² + β ² ) ^1/2 .

Table 2 shows theoretical noise values when the attenuation rate of the attenuator is switched uniformly across all pixels according to the conventional method. In the conventional method, the attenuation rate is set uniformly across all pixels for each of the low ISO sensitivity modes applied to processing high-level signals and the high ISO sensitivity modes applied to processing low-level signals. As a result, in the low ISO sensitivity mode, both high-level and low-level signals are uniformly attenuated by the attenuator to 1/2, so that the FD-equivalent noise for both becomes (α ² +(2β) ² ) ^1/2 .

The S/N of an image is determined by the signal level of the high luminance parts (bright parts) and the noise level of the low luminance parts (dark parts) in the image. The total noise (FD conversion noise) for low level signals in Table 1 is divided by the total noise for low level signals in Table 2 to obtain the division value of Equation (4).
(α ² + β ² ) ^1/2 /(α ² + (2β) ² ) ^1/2 (4)

When the noise levels of the noises α and β are, for example, 2:1, the value of formula (4) is (5/8) ^1/2 . Thus, according to this embodiment, the total noise is reduced to about 0.79 times. As another example, when the noise levels of the noises α and β are 1:1, the value of formula (4) is (2/5) ^1/2 . Thus, the total noise is reduced to about 0.63 times. As yet another example, when the noise levels of the noises α and β are 1:2, the value of formula (4) is (5/17) ^1/2 . Thus, the total noise is reduced to about 0.54 times. As can be seen from these examples, the noise reduction effect is greater when the noise of the pixel and the source follower circuit is smaller than the AD conversion noise.

FIG. 15 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the attenuation rate of the imaging device 200 according to this embodiment. In this embodiment, as shown in FIG. 15, the threshold VTH is set to 1/2 the saturation signal level of the pixel. The attenuation rate of the attenuator 250 is 1/2. However, by setting the attenuation rate to less than 1/2, a greater noise reduction effect can be obtained. In addition, the level of the threshold VTH is not limited to 1/2 the saturation signal level, and can be varied by either the circuit design, the control signal, or the control voltage, as described above.

16 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, the attenuation rate, and the non-operating range of the source follower circuit of the imaging device 200 according to this embodiment. When the comparator 240 is configured as an inverter type comparator as shown in FIG. 7C, it is desirable to set the threshold voltage of the comparator 240 to be 1/2 or less of the drain voltage VDD of the transistor, taking into account the non-operating range of the source follower circuit and the variation in threshold voltage during circuit design. For example, in the inverter type comparator shown in FIG. 7C, when the power supply voltage is 3.3 V, if the W/L ratio of the N-type MOS transistor 242b of the inverter 242 and the W/L ratio of the P-type MOS transistor 242a of the inverter 242 are designed to be 1:2, the threshold voltage of the inverter will be about 1.5 V. In contrast, if the W/L ratio of N-type MOS transistor 242b and the W/L ratio of P-type MOS transistor 242a are designed to be 1:1, the threshold voltage of the inverter will be about 1.3 V. In this way, although it will vary somewhat depending on the transistor parameters, by designing the W/L ratio of the N-type MOS transistor to be at least half the W/L ratio of the P-type MOS transistor, the threshold voltage can be set to approximately half or less of the voltage VDD.

<Modification of the First Embodiment>
FIG. 17 is a block diagram showing a schematic diagram of a modified example of the conversion circuit according to the present embodiment. The conversion circuit 220b shown in FIG. 17 differs from the conversion circuit 220 shown in FIG. 5 in that it includes a first and a second comparator. The first comparator 240a is electrically connected to the pixel 10 and configured to compare the level of the pixel signal VSIG with at least one threshold value. The second comparator 240b is electrically connected to the pixel 10 and configured to compare the level of the pixel signal VSIG with at least one threshold value different from the at least one threshold value of the first comparator 240a. The conversion circuit 220b further includes a first holding circuit 270a electrically connected to the first comparator 240a and the attenuator 250 and holding the comparison result of the first comparator 240a, and a second holding circuit 270b electrically connected to the second comparator 240b and the attenuator 250 and holding the comparison result of the second comparator 240b. Two paths exist in parallel: a first comparator 240a and a first holding circuit 270a connected in series, and a second comparator 240b and a second holding circuit 270b connected in series.

In this modified example, the threshold of the first comparator 240a is different from the threshold of the second comparator 240b. Therefore, the level of the output signal DOUT1a from the first comparator 240a is different from the level of the output signal DOUT1b from the second comparator 240b. In other words, the output signals DOUT1a and DOUT1b from the first and second comparators 240a and 240b change at different signal levels.

FIG. 18A is a circuit diagram showing an example of the configuration of the attenuator in this modified example. FIG. 18B is a circuit diagram showing another example of the configuration of the attenuator in this modified example. The attenuator 250c shown in FIG. 18A has a configuration in which a capacitance Cc, a switch S3, an inverter 224b, and an AND circuit 252 are added to the attenuator 250a shown in FIG. 10A. The attenuator 250d shown in FIG. 18B has a configuration in which a resistor Rc, a switch S3, an inverter 224b, and an AND circuit 252 are added to the attenuator 250b shown in FIG. 10B. However, the configuration of the attenuator is not limited to these. Any configuration can be adopted as long as it can make the voltage level of the input pixel signal VSIG 1x, Xx, or Yx (X≠Y, X<1, Y<1).

FIG. 19 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the attenuation rate in this modified example. In this modified example, the first comparator 240a has a threshold VTH1, and the second comparator 240b has a threshold VTH2. As shown in FIG. 19, the threshold VTH1 is set to 1/4 of the saturation signal level of the pixel, and the threshold VTH2 is set to 1/2 of the saturation signal level of the pixel.

The attenuator 250c illustrated in FIG. 18A has three types of attenuation rates, 1, 1/2, and 1/4, depending on the level of the pixel signal VSIG. The attenuator 250c does not apply the attenuation process to the pixel signal VSIG whose signal level is less than the threshold VTH1. In this case, the attenuator 250c maintains the level of the pixel signal VSIG, i.e., attenuates it to 1. The attenuator 250c applies the attenuation process to the pixel signal VSIG whose signal level is equal to or greater than the threshold VTH1 and less than the threshold VTH2. In this case, the attenuator 250c attenuates the pixel signal VSIG by 1/2. The attenuator 250c applies the attenuation process to the pixel signal VSIG whose signal level is equal to or greater than the threshold VTH2. In this case, the attenuator 250c attenuates the pixel signal VSIG by 1/4. With this method, even if the AD conversion range is, for example, 1/4 of the pixel saturation level, it is possible to appropriately keep the level of the pixel signal VSIG within the AD conversion range according to the level of the pixel signal. The number of thresholds or attenuation rates is not limited to two or three, but can be four or more.

In this embodiment, a single-slope AD conversion circuit is used as an example of the AD conversion circuit, but the present invention is not limited to this. For example, a successive approximation type AD conversion circuit, a delta-sigma AD conversion circuit, or a cyclic type AD conversion circuit may also be used.

Second Embodiment
A conversion circuit according to a second embodiment of the present disclosure will be described with reference to Fig. 20 to Fig. 25. The conversion circuit according to the second embodiment differs from the conversion circuit according to the first embodiment in that it includes an attenuator electrically connected to the comparator and the reference signal generating circuit. The following mainly describes the difference.

FIG. 20 is a block diagram showing a schematic configuration of a conversion circuit according to a second embodiment of the present disclosure.

The conversion circuit 220c shown in FIG. 20 includes a comparator 260 electrically connected to the pixel 10, which converts the pixel signal VSIG and the reset signal, each of which is an analog signal read from the pixel 10, into a digital signal; a reference signal generation circuit 204 which generates and outputs a ramp signal which is a reference signal Vramp; an attenuator 255 electrically connected to the comparator 260 and the reference signal generation circuit 204, which amplifies the ramp signal by one of a plurality of amplification factors and outputs it to the comparator 260; and a comparator 240 electrically connected to the pixel 10, which compares the level of the pixel signal VSIG with at least one threshold value.

In this embodiment, the attenuator 255 is configured to amplify the ramp signal by the amplification factor set by the comparator 240 during the period in which the pixel signal VSIG and the reset signal are converted into digital signals.

21A and 21B are circuit diagrams showing an example configuration of an attenuator according to the second embodiment of the present disclosure. The configuration of attenuator 255a shown in FIG. 21A differs from the configuration of 250a shown in FIG. 10A in that the polarity of the control signals of switches S1 and S2 is inverted. The reason for inverting the polarity of the control signal is that in the first embodiment, when the level of pixel signal VSIG is relatively large, the signal is attenuated by attenuator 250, whereas in the second embodiment, when the level of pixel signal VSIG is relatively small, conversely, the reference signal Vramp is attenuated by attenuator 255.

The comparator 240 sets the amplification factor of the attenuator 255 to one of a plurality of amplification factors based on the result of comparing the level of the pixel signal VSIG with at least one threshold value. In this embodiment, by connecting the reference signal generation circuit 204 to the attenuator 255, the slope of the reference signal Vramp, i.e., the amount of change in voltage per unit time, changes depending on the attenuation factor set in the attenuator 255. The comparator 260 compares the levels of the pixel signal VSIG and the reset signal with the amplified ramp signal output from the attenuator 255, i.e., the reference signal Vramp with a changed slope. The comparator 260 in this embodiment is an example of a comparison circuit.

As mentioned above, when the AD conversion gain is low, large signals can be AD converted, but the resolution decreases. As a result, quantization noise increases. In contrast, when the AD conversion gain is high, quantization noise can be suppressed. However, the signal range that can be handled becomes smaller.

According to this embodiment, when the level of the pixel signal is greater than the threshold, AD conversion is performed with a relatively low AD conversion gain, and when the pixel signal is less than the threshold, AD conversion is performed with a relatively high AD conversion gain. As a result, it is possible to perform AD conversion of the pixel signal in the maximum range of the pixel signal while suppressing quantization noise and avoiding S/N degradation in low illuminance, thereby improving the dynamic range.

The operation of the imaging device 200 according to this embodiment will be described with reference to Figures 22 and 23.

FIGS. 22 and 23 are timing charts each showing an example of the operation procedure of the imaging device 200. FIG. 22 shows an example of each signal waveform when the level of the pixel signal VSIG falls below the threshold of the comparator 240. In the explanation of the operation procedure of the imaging device 200, each of the multiple pixels 10 is a stacked photoelectric conversion element. The comparator 240 of the conversion circuit 220c has the configuration shown in FIG. 7A, the attenuator 255 has the configuration shown in FIG. 21B, and the holding circuit 270 has the configuration shown in FIG. 12.

First, at time t0, the level of the horizontal synchronization signal HD changes from low to high, and imaging of the pixel group in the nth row of the pixel section 201 begins. At time t1, the level of the horizontal synchronization signal HD changes from high to low.

Next, at time t2, the selection signal VSELn goes High, the selection transistor M2 turns on, and the pixel signal VSIG of the nth row is output to the vertical signal line 212. In addition, the control signal CNT goes High, and the switch S4 of the holding circuit 270 (see FIG. 12) turns on.

Next, at time t4, switch S4 of holding circuit 270 turns off, and a voltage based on the level of pixel signal VSIG is held in capacitance Cd.

In this embodiment, since the output signal SHOUT does not exceed the threshold value VTH during the period from time t2 to time t4 when the control signal CNT is High, the output signal DOUT1 is fixed to Low after time t4, and the inverted signal of the output signal DOUT1 (the output signal of the inverter 224) is fixed to High. As a result, the reference signal Vramp is attenuated to Vramp×Rb/(Ra+Rb) by the attenuator 250, and is output from the attenuator 250 as the output signal AOUT. In other words, a reference signal Vramp with a slope multiplied by Rb/(Ra+Rb) is output.

In this embodiment, resistors Ra and Rb are the same. In this case, the attenuation rate of attenuator 255 is 1/2. By applying the attenuation process of attenuator 255 to reference signal Vramp according to the level of pixel signal VSIG, the slope of reference signal Vramp becomes 1/2, which reduces quantization noise during AD conversion.

Next, at time t4, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t4 to time t5, the comparator 260 compares the voltage corresponding to the attenuated reference signal Vramp with the level of the pixel signal VSIG, while the counter 209 continues counting until the output levels of both signals match.

Next, at time t5, the reset control signal VRSTn applied to the pixels 10 in the nth row goes High, and the reset operation of the pixels in the nth row is started by the reset transistor M3. After that, the potential level of the vertical signal line 212 corresponding to the level of the reset signal does not exceed the threshold value VTH of the comparator 240, so the level of the output signal DOUT1 is maintained at Low.

Next, at time t7, the reset control signal RSTn changes from High to Low, completing the reset operation. Also at time t7, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t7 to time t9, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the reset signal, while the counter 209 continues counting until the output levels of the two match.

Next, at time t10, the horizontal synchronization signal HD goes high, and the imaging device 200 transitions to reading out the pixels in the n+1th row.

In this way, while the selection signal VSELn is high, the comparator 260 performs a first comparison between the pixel signal VSIG and the reference signal Vramp, and then, after the reset operation is completed, the comparator 260 performs a second comparison between the reset signal and the reference signal Vramp.

FIG. 23 shows an example of each signal waveform when the level of the pixel signal VSIG exceeds the threshold of the comparator 240. Below, we will explain the differences from the case where the pixel signal VSIG falls below the threshold of the comparator 240 described above.

In the timing chart shown in FIG. 23, the level of the pixel signal VSIG read out from pixel 10 is held in the holding circuit 270, and since the output signal SHOUT is higher than the threshold value VTH of the comparator 240, the output signal DOUT1 of the comparator 240 changes from low to high. This turns on the switch S1 of the attenuator 255 and turns off the switch S2. Therefore, the reference signal Vramp is not attenuated by the attenuator 250b, and the slope of the reference signal Vramp is output as the output signal AOUT without changing.

As described above, when the level of the pixel signal VSIG is below the threshold value VTH of the comparator 240, the attenuator 255 attenuates the reference signal Vramp, and when the level of the pixel signal VSIG is above the threshold value VTH of the comparator 240, the attenuator 255 does not attenuate the reference signal Vramp. By operating the conversion circuit 220c according to the operation sequence described above, it is possible to suppress quantization noise and perform AD conversion of the pixel signal in the maximum range of the pixel signal while avoiding S/N degradation at low illuminance, thereby improving the dynamic range.

As in the first embodiment, the result of the comparison between the level of the pixel signal VSIG and the threshold value of the comparator 240 may be provided to either or both of the counter 209 and the memory 211 in the subsequent stage. For example, the signal processing circuit 208 inside the imaging device 200 or a camera signal processing unit (described later) externally connected to the imaging device may correct the AD conversion value by shifting the AD conversion value according to the attenuation rate of each pixel so that the level of the pixel signal VSIG of each pixel 10 matches the magnitude of the AD conversion value.

According to the pixel configuration and operation sequence of this embodiment, after a pixel signal corresponding to the intensity of incident light is read out, the pixel is reset and a reset signal is read out. In this way, the pixel signal is first read out and the attenuation rate of the attenuator is determined based on the magnitude relationship between the pixel signal level and the threshold value of the comparator, so that the subsequent reset signal can also be AD converted with the slope of the reference signal Vramp. By using the same waveform of the reference signal Vramp when reading out the pixel signal and the reset signal, it is possible to improve the S/N ratio without causing unnecessary offsets, etc. On the other hand, when using a pixel configuration and operation sequence that first reads out the level of the reset signal, it is difficult to use the same waveform of the reference signal Vramp when reading out the pixel signal and the reset signal, because the level of the pixel signal is unknown at the time the reset signal is read out.

Table 3 shows theoretical noise values when the slope of the reference signal Vramp is changed according to the pixel signal level in accordance with the pixel configuration and operation sequence of this embodiment. As in the first embodiment, a high-level signal in Table 3 means a pixel signal whose level is greater than the threshold VTH of the comparator 240, and a low-level signal in Table 3 means a pixel signal whose level is less than the threshold VTH of the comparator 240. For ease of explanation, it is assumed that there are two noise sources: (1) noise from the pixel and source follower circuit, and (2) quantization noise during AD conversion. Here, the combined noise from the pixel and source follower circuit is α [uVrms], and the quantization noise at an AD conversion gain of 0 dB is β [uVrms]. The observation point of the noise α is on the vertical signal line 212, and the observation point of the noise β is on the digital value after AD conversion.

The total noise in Table 3 is the sum of the noise α and β converted to FD (FD converted noise). There are no circuit elements that amplify or attenuate the signal in the path from FD to after AD conversion, and the quantization noise β has the same magnitude when converted to FD.

As shown in Table 3, for high-level signals, the AD conversion gain is 0 dB, so the quantization noise is β [uVrms], and as a result, the FD-converted noise is (α ² + β ² ) ^1/2 . On the other hand, for low-level signals, the AD conversion gain is 6 dB, so the quantization noise is β/2 [uVrms], and as a result, the FD-converted noise is (α ² + (β/2) ² ) ^1/2 .

Table 4 shows theoretical noise values when the attenuation rate of the attenuator is switched uniformly for all pixels according to the conventional method. In the conventional method, the AD conversion gain is set uniformly for all pixels for each mode of low ISO sensitivity applied to processing of high-level signals and high ISO sensitivity applied to processing of low-level signals. As a result, in the low ISO sensitivity mode, both high-level signals and low-level signals are AD-converted uniformly with an AD conversion gain of 0 dB, so that the FD conversion noise is ( ^α2 + ^β2 ) ^1/2 for both.

The S/N of an image is determined by the signal level of the high luminance parts (bright parts) and the noise level of the low luminance parts (dark parts) in the image. The total noise (FD conversion noise) for low level signals in Table 3 is divided by the total noise for low level signals in Table 4 to obtain the division value of formula (5).
(α ² + (β/2) ² ) ^1/2 /(α ² + β ² ) ^1/2 (5)

For example, when the noise levels of the noises α and β are 2:1, the value of formula (5) is (5/8) ^1/2 . Thus, the total noise is reduced to about 0.79 times. As another example, when the noise levels of the noises α and β are 1:1, the value of formula (5) is (2/5) ^1/2 . Thus, the total noise is reduced to about 0.63 times. As yet another example, when the noise levels of the noises α and β are 1:2, the value of formula (5) is (5/17) ^1/2 . Thus, the total noise is reduced to about 0.54 times. As can be seen from these examples, the noise reduction effect is greater when the noise of the pixel and the source follower circuit is smaller than the quantization noise.

FIG. 24 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold value VTH, and the AD conversion gain of the imaging device 200 according to this embodiment. In this embodiment, as shown in FIG. 24, the threshold value VTH is set to 1/2 the saturation signal level of the pixel, and the AD conversion gain is 6 dB. However, a greater noise reduction effect can be obtained by setting the AD conversion gain to less than 6 dB.

<Modification of the second embodiment>
FIG. 25 is a block diagram showing a modified example of the conversion circuit according to the present embodiment. The conversion circuit 220d shown in FIG. 25 is similar to the configuration of the modified example of the conversion circuit 220 according to the first embodiment shown in FIG. 17, in which two paths, a first comparator 240a and a first holding circuit 270a connected in series, and a second comparator 240b and a second holding circuit 270b connected in series, are connected in parallel in the conversion circuit 220d. The attenuator 255 of the conversion circuit 220d may have the same configuration as that shown in FIG. 18A or FIG. 18B, for example. However, the reference signal Vramp is input from the reference signal generating circuit 204.

FIG. 26 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the AD conversion gain in this modified example. As shown in FIG. 26, the threshold VTH1 is set to 1/4 of the saturation signal level of the pixel, and the threshold VTH2 is set to 1/2 of the saturation signal level of the pixel. The comparator 260 AD converts pixel signals and reset signals whose signal levels are less than the threshold VTH1 with an AD conversion gain of 12 dB. The comparator 260 AD converts pixel signals and reset signals whose signal levels are equal to or greater than the threshold VTH1 and less than the threshold VTH2 with an AD conversion gain of 6 dB. The comparator 260 AD converts pixel signals and reset signals whose signal levels are equal to or greater than the threshold VTH2 with an AD conversion gain of 0 dB. This can further reduce quantization noise for low-level signals, and is expected to improve the S/N ratio and dynamic range.

Third Embodiment
A camera system according to a third embodiment of the present disclosure will be described with reference to FIG.

FIG. 27 shows a schematic configuration example of a camera system 400 according to the third embodiment of the present disclosure. The camera system 400 includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing unit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

The lens optical system 601 includes a lens group including, for example, an autofocus lens and a zoom lens. The lens optical system 601 may include an aperture. The lens optical system 601 focuses light on the imaging surface of the imaging device 200. The imaging devices according to the first and second embodiments described above can be widely used as the imaging device 602.

The system controller 603 controls the entire camera system 400. The system controller 603 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

The camera signal processing unit 604 has a function of processing the output signal from the imaging device 602. The camera signal processing unit 604 is, for example, a DSP (Digital Signal Processor). The camera signal processing unit 604 receives output data from the imaging device 602 and performs processes such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance. The imaging device 602 and the camera signal processing unit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, an electronic device that includes the imaging device 602 as a part thereof can be made smaller.

The imaging device according to the embodiment of the present disclosure does not need to include all of the components described in the first and second embodiments, and may be configured with only the components for performing the intended operation. Also, in the above operational examples, there may be operations that are not performed by the imaging device. In one aspect of the embodiment of the present disclosure, the imaging device includes a pixel, an AD conversion circuit that converts an analog signal output from the pixel into a digital signal, a determination circuit electrically connected to the pixel and that compares the level of the analog signal with at least one threshold value, and a holding circuit that holds the result of the comparison between the level of the analog signal and at least one threshold value.

In the above embodiment, an attenuator having an attenuation factor smaller than 1 is used as the amplifier circuit, but it is possible to use an amplifier having an amplification factor larger than 1 as the amplifier circuit.

In the above embodiment, the processing performed by a specific processing unit such as a signal processing circuit may be executed by another processing unit. In addition, the order of multiple processes may be changed, and multiple processes may be executed in parallel.

The general or specific aspects of the present disclosure may be realized as a system, an apparatus, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM. It may also be realized as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

For example, the present disclosure may be realized as an imaging device according to the above-described embodiments, as a processing circuit for an imaging device having the functions of the signal processing circuit according to the above-described embodiments, as a signal processing method for an imaging device performed by the signal processing circuit according to the above-described embodiments, as a program for causing a computer to execute such a signal processing method, or as a computer-readable non-transitory recording medium on which such a program is recorded.

In addition, as long as they do not deviate from the spirit of this disclosure, various modifications that would occur to those skilled in the art to the embodiments and examples, as well as other forms constructed by combining some of the components in the embodiments and examples, are also included in the scope of this disclosure.

The imaging device disclosed herein is useful as a variety of imaging devices. It can also be used in digital cameras, digital video cameras, camera-equipped mobile phones, medical cameras such as electronic endoscopes, vehicle-mounted cameras, and robot cameras.

10 Pixel 11 Photoelectric conversion layer 12 Pixel electrode 13 Counter electrode 14 Contact plug 15 Semiconductor substrate 18 Photoelectric conversion section,
200, 602 Imaging device 201 Pixel section 202 Vertical scanning circuit 203 Horizontal transfer scanning circuit 204 Reference signal generating circuit 205 Drive control circuit 206 Column processing section 207 Column circuit 212 Vertical signal line 213 Horizontal signal line 214 Amplifier circuit 215 Load current circuit 220 Conversion circuit 240, 260 Comparator 250 Attenuator 270 Holding circuit 400 Camera system 601 Optical system 603 System controller 604 Camera signal processing section

Claims (13)

Pixels and
an amplifier circuit electrically connected to the pixel, the amplifier circuit amplifying a pixel signal and a reset signal, each of which is an analog signal, read from the pixel by one of a plurality of amplification factors and outputting the amplified signal;
an AD conversion circuit electrically connected to the amplifier circuit and converting an output from the amplifier circuit into a digital signal;
a determination circuit electrically connected to the pixel and configured to compare a level of the pixel signal with at least one threshold;
Equipped with
the determination circuit sets an amplification factor of the amplifier circuit to the one of the plurality of amplification factors based on a comparison result between the level of the pixel signal and the at least one threshold value;
the amplifier circuit amplifies the pixel signal and the reset signal by the one set amplification factor;
Imaging device. Pixels and
an AD conversion circuit electrically connected to the pixel, the AD conversion circuit converting a pixel signal and a reset signal, each of which is an analog signal, read out from the pixel into a digital signal;
a reference signal generating circuit that generates and outputs a ramp signal that is a reference signal;
an amplifier circuit electrically connected to the reference signal generating circuit, amplifying the ramp signal by one of a plurality of amplification factors and outputting the amplified ramp signal;
a determination circuit electrically connected to the pixel and configured to compare a level of the pixel signal with at least one threshold;
Equipped with
the AD conversion circuit includes a comparison circuit that compares the levels of the pixel signal and the reset signal with the amplified ramp signal output from the amplifier circuit,
the determination circuit sets an amplification factor of the amplifier circuit to the one of the plurality of amplification factors based on a comparison result between the level of the pixel signal and the at least one threshold value;
the amplifier circuit amplifies the ramp signal by the one amplification factor set by the determination circuit during a period in which the pixel signal and the reset signal are converted into digital signals.
Imaging device. The imaging device according to claim 1 or 2, wherein the determination circuit includes an inverter circuit. the inverter circuit includes an N-type MOS transistor and a P-type MOS transistor;
4. The imaging device according to claim 3, wherein the W/L ratio of the N-type MOS transistor is equal to or greater than half the W/L ratio of the P-type MOS transistor. The imaging device according to claim 1 or 2, further comprising a holding circuit that holds the comparison result of the determination circuit. The imaging device of claim 5, wherein the holding circuit includes a switch electrically connected between the pixel and the inverter circuit. The imaging device according to claim 5, wherein the holding circuit includes a latch electrically connected to a stage subsequent to the inverter circuit. The imaging device according to claim 1 or 2, wherein the determination circuit includes a differential amplifier. a signal processing circuit to which the digital signal output from the AD conversion circuit is input,
The imaging device according to claim 1 , wherein the signal processing circuit applies a correction process to the digital signal in accordance with a comparison result of the determination circuit. the determination circuit is a first determination circuit,
a second determination circuit electrically connected to the pixel and configured to compare a level of the pixel signal with at least one other threshold value different from the at least one threshold value;
a first holding circuit electrically connected to the first determination circuit and the amplifier circuit, the first holding circuit holding the comparison result of the first determination circuit;
a second holding circuit electrically connected to the second determination circuit and the amplifier circuit, the second holding circuit holding the comparison result of the second determination circuit;
The imaging device according to claim 1 , further comprising: The imaging device according to claim 1 or 2, wherein the pixel includes a pixel electrode, a counter electrode facing the pixel electrode, and a photoelectric conversion layer located between the pixel electrode and the counter electrode. The imaging device according to claim 1 or 2, wherein the pixel outputs the reset signal after outputting the pixel signal during one frame period. Pixels and
a determination circuit electrically connected to the pixel and configured to compare a level of an analog signal output from the pixel with at least one threshold;
a holding circuit that holds a comparison result between the level of the analog signal and the at least one threshold value;
An imaging device comprising:

Images