WO2024216674A1 - Method for preparing semiconductor structure, and semiconductor structure - Google Patents

Abstract

The present application relates to the technical field of semiconductors, and in particular, to a method for preparing a semiconductor structure, and the semiconductor structure, which are used for solving the problem of reduction of the mobility of carriers. The method for preparing the semiconductor structure comprises: providing a substrate (10); and executing at least one epitaxial period, so as to form, on the substrate (10), a first epitaxial layer (201) and a second epitaxial layer (202) which are sequentially stacked from bottom to top, wherein the epitaxial period comprises: forming the first epitaxial layer (201) on the substrate (10), the first epitaxial layer (201) comprising a compound of a first element and a second element having a segregation characteristic; performing surface treatment on an upper surface of the first epitaxial layer (201) by using a halogen compound of the first element; and forming the second epitaxial layer (202) on the upper surface of the first epitaxial layer (201) having undergone surface treatment, the second epitaxial layer (202) comprising a first element.

Description

Semiconductor structure preparation method and semiconductor structure

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on April 18, 2023, with application number 202310413590X and invention name “Method for preparing semiconductor structure and semiconductor structure”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure.

Background Art

The statements herein merely provide background information related to the present application and do not necessarily constitute exemplary techniques.

With the development of semiconductor technology, multi-period superlattice structures have been widely studied and applied in semiconductor advanced process nodes and 3D dynamic random access memory (DRAM). An epitaxial period of a superlattice structure is usually composed of a first epitaxial layer and a second epitaxial layer. However, due to the segregation properties of certain elements in the first epitaxial layer, during the formation of the superlattice structure, the atoms corresponding to these elements will diffuse outward at the interface between the first epitaxial layer and the second epitaxial layer, thereby increasing the interface thickness between the first epitaxial layer and the second epitaxial layer. This will cause the surface of the second epitaxial layer to become rough, and a large number of scattering centers will appear at the interface, resulting in a decrease in carrier mobility.

Summary of the invention

According to various embodiments of the present application, a method for preparing a semiconductor structure and a semiconductor structure are provided.

A method for preparing a semiconductor structure, comprising:

providing a substrate;

Performing at least one epitaxial cycle to form a first epitaxial layer and a second epitaxial layer stacked sequentially from bottom to top on the substrate; the epitaxial cycle includes:

forming the first epitaxial layer on the substrate, wherein the first epitaxial layer includes a compound of a first element and a second element having a segregation characteristic;

Performing surface treatment on the upper surface of the first epitaxial layer using a halogen compound of the first element;

The second epitaxial layer is formed on the surface-treated first epitaxial layer, wherein the second epitaxial layer includes the first element.

In one embodiment, the first element includes silicon, the second element includes germanium or phosphorus; the first epitaxial layer includes a silicon germanium layer, a silicon phosphide layer or a phospho-silicon germanium layer, and the second epitaxial layer includes a silicon layer; and the halogen compound of the first element includes SiCl ₂ H ₂ or SiCl ₂ .

In one embodiment, the upper surface of the first epitaxial layer is surface-treated with a halogen compound of the first element under a preset protective atmosphere; the surface treatment temperature is 700° C. to 1200° C.; and the surface treatment time is 0.1s to 120s.

In one embodiment, the preset protective atmosphere includes a reducing atmosphere or a vacuum atmosphere.

In one embodiment, a plurality of the epitaxial cycles are performed to form the first epitaxial layer and the second epitaxial layer stacked sequentially from bottom to top on the substrate.

In one embodiment, the number of epitaxial cycles performed is 1-200.

In one embodiment, before performing at least one epitaxial cycle, the method further includes:

The substrate is pre-treated.

In one embodiment, the pre-processing of the substrate comprises:

Pre-treating the substrate with hydrofluoric acid; and/or

The substrate is subjected to reduction treatment at a preset temperature and a preset reducing atmosphere.

In one embodiment, the preset temperature is 700°C to 1200°C.

A semiconductor structure comprising:

substrate;

A first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate; wherein the first epitaxial layer comprises a compound of a first element and a second element having a segregation characteristic; and the second epitaxial layer comprises the first element;

The interface transition layer is located between the first epitaxial layer and the second epitaxial layer.

In one embodiment, the first element includes silicon, the second element includes germanium or phosphorus; the first epitaxial layer includes a silicon germanium layer, a silicon phosphide layer or a phospho-silicon germanium layer, and the second epitaxial layer includes a silicon layer; and the halogen compound of the first element includes SiCl ₂ H ₂ or SiCl ₂ .

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

FIG2 is a schematic diagram of a cross-sectional structure of a structure obtained in step S101 in a method for preparing a semiconductor structure provided in an embodiment;

FIG3 is a schematic diagram of a cross-sectional structure of a structure obtained in step S102 in a method for preparing a semiconductor structure provided in an embodiment;

FIG4 is a schematic cross-sectional view of a structure obtained in step S1021 in a method for preparing a semiconductor structure provided in an embodiment;

FIG5 is a schematic diagram of a cross-sectional structure of a structure obtained in step S1022 in a method for preparing a semiconductor structure provided in an embodiment;

FIG6 is a schematic diagram of a cross-sectional structure of a structure obtained in step S1023 in a method for preparing a semiconductor structure provided in an embodiment;

FIG. 7 is a comparison diagram of high-resolution transmission electron microscopy of a superlattice structure without surface treatment and a superlattice structure with surface treatment in one embodiment, as well as a comparison diagram after image processing.

DETAILED DESCRIPTION

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or Coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and/or parts, these elements, components, regions, layers, doping types and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below may be represented as a second element, component, region, layer or part; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatially relative terms such as "under," "beneath," "below," "under," "on the surface of," "above," and the like, may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

When used herein, the singular forms "a", "an" and "/the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include/comprise" or "have" and the like specify the existence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the existence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and/or" includes the relevant Any and all combinations of listed items.

Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

With the development of semiconductor technology, multi-period superlattice structures have been widely studied and applied in semiconductor advanced process nodes and 3D dynamic random access memory (DRAM). An epitaxial period of a superlattice structure usually consists of a first epitaxial layer and a second epitaxial layer. However, due to the segregation properties of certain elements in the first epitaxial layer, during the formation of the superlattice structure, the atoms corresponding to these elements will diffuse outward at the interface between the first epitaxial layer and the second epitaxial layer, thereby increasing the interface thickness between the first epitaxial layer and the second epitaxial layer. This will cause the surface of the second epitaxial layer to become rough, and a large number of scattering centers will appear at the interface, resulting in a decrease in carrier mobility.

For example, for the traditional silicon/silicon germanium superlattice structure, due to the segregation property of germanium atoms, during the formation of the silicon germanium layer, the germanium atoms at the silicon/silicon germanium interface will diffuse into the silicon layer, thereby increasing the thickness of the interface transition layer from silicon germanium to silicon, causing the surface of the silicon layer to become rough, thereby causing the carrier mobility to decrease.

Please refer to FIG. 1 . The present application provides a method for preparing a semiconductor structure, comprising the following steps:

S101: providing a substrate;

S102: performing at least one epitaxial cycle to form a first epitaxial layer and a second epitaxial layer stacked sequentially from bottom to top on the substrate; the epitaxial cycle includes:

S1021: forming a first epitaxial layer on a substrate, wherein the first epitaxial layer includes a compound of a first element and a second element having a segregation characteristic;

S1022: performing surface treatment on the upper surface of the first epitaxial layer using a halogen compound of the first element;

S1023: forming a second epitaxial layer on the upper surface of the surface-treated first epitaxial layer, wherein the second epitaxial layer includes the first element.

In step S101 , referring to step S101 in FIG. 1 and FIG. 2 , a substrate 10 is provided.

Among them, the material of the substrate 10 can be any suitable substrate 10 material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon silicon germanium (SiGe C), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGe OI), silicon germanium on insulator (SiGe OI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

Optionally, the substrate 10 may include a first element, and the first element may refer to the most important element in the substrate 10 . For example, when the material of the substrate 10 is silicon, the first element may be silicon.

In step S102 , referring to step S102 in FIG. 1 and FIG. 3 , at least one epitaxial cycle is performed to form a first epitaxial layer 201 and a second epitaxial layer 202 sequentially stacked from bottom to top on the substrate 10 .

As shown in FIG3 , by performing at least one epitaxial cycle, a superlattice structure 20 is finally formed on the substrate 10. The superlattice structure 20 refers to a multilayer film structure in which thin layers of two different components are alternately grown and maintain a strict periodicity, which can be understood as a specific form of layered fine composite material. The lattice structure 20 may include a first epitaxial layer 201 and a second epitaxial layer 202 stacked sequentially from bottom to top. The main semiconductor properties of the first epitaxial layer 201 and the second epitaxial layer 202, such as band gap or doping level, can be independently controlled, and the number of layers of the first epitaxial layer 201 and the second epitaxial layer 202 can also be artificially controlled during growth.

Among them, the epitaxial cycle includes:

S1021: forming a first epitaxial layer on a substrate, wherein the first epitaxial layer includes a compound of a first element and a second element having a segregation characteristic.

As shown in FIG. 4 , the second element can be determined after the first element is determined. For example, when the first element is silicon, the second element can be phosphorus (P), germanium (Ge), and the like. In actual application scenarios, the types of the first element and the second element can be determined by comprehensively considering the actual process requirements and costs, and this embodiment does not limit this. To facilitate understanding of this solution, FIG. 4 is a schematic diagram of forming the first epitaxial layer 201 in the first epitaxial cycle.

S1022: performing surface treatment on the upper surface of the first epitaxial layer using a halogen compound of the first element.

As shown in FIG5 , halogen elements include fluorine, chlorine, bromine, iodine, etc., which are the most typical non-metallic elements. The halogen compound 30 of the first element refers to a class of compounds containing the first element and the halogen element. Taking silicon as the first element as an example, the halogen compound of silicon can include silicon tetrafluoride (SiF ₄ ), silicon dichloride (SiCl ₂ ), silicon dichloride (SiH ₂ Cl ₂ ), etc. In order to facilitate understanding of this solution, FIG5 is a schematic diagram of surface treatment of the first epitaxial layer 201 in the first epitaxial cycle.

S1023: forming a second epitaxial layer on the surface-treated first epitaxial layer, wherein the second epitaxial layer includes the first element.

As shown in FIG. 6, for the sake of understanding the present solution, FIG. 6 is a schematic diagram of forming the second epitaxial layer 202 in the first epitaxial cycle. The remaining epitaxial cycles can be grown with reference to the patterns of FIG. 4 to FIG. 6. For example, in the second epitaxial cycle, the first epitaxial layer 201 of the second epitaxial cycle is formed on the first epitaxial cycle. The number of the epitaxial cycles may be 1-300.

As shown in Fig. 6, when the second epitaxial layer 202 is formed on the upper surface of the first epitaxial layer 201, since the constituent elements of the first epitaxial layer 201 and the second epitaxial layer 202 are different, an interface transition layer 203 is formed at the interface where the first epitaxial layer 201 and the second epitaxial layer 202 contact. At the same time, since the second element has a segregation property, after the second epitaxial layer 202 is formed, the atoms corresponding to the second element diffuse on the surface of the first epitaxial layer 201, resulting in a relatively thick interface transition layer 203.

By using the halogen compound 30 of the first element to perform surface treatment on the upper surface of the first epitaxial layer 201, the thickness of the interface transition layer 203 can be reduced. This is because: on the one hand, the halogen compound 30 of the first element will react with the atoms corresponding to the second element diffused from the upper surface of the first epitaxial layer 201, thereby removing part of the atoms corresponding to the diffused second element; on the other hand, since these halogen compounds contain the first element, they can compensate for the first element on the upper surface of the first epitaxial layer 201. Therefore, when the first epitaxial layer 201 and the second epitaxial layer 202 are in contact to form the interface transition layer 203, the thickness of the interface transition layer 203 can be reduced and the steepness of the interface transition layer 203 can be improved, thereby avoiding the decrease in carrier mobility.

In addition, after the first epitaxial layer 201 is processed with the halogen compound 30 of the first element, the growth rate of the entire superlattice structure 20 is not affected, and the stress state inside the first epitaxial layer 201 is not affected.

The method for preparing the semiconductor structure comprises: providing a substrate; performing at least one epitaxial cycle to form a first epitaxial layer and a second epitaxial layer stacked in sequence from bottom to top on the substrate; the epitaxial cycle comprises: forming a first epitaxial layer on the substrate, the first epitaxial layer comprising a compound of a first element and a second element having segregation characteristics; performing surface treatment on the upper surface of the first epitaxial layer using a halogen compound of the first element; forming a second epitaxial layer on the upper surface of the surface-treated first epitaxial layer, the second epitaxial layer comprising The first element. Since the upper surface of the first epitaxial layer is surface treated with a halogen compound of the first element, the halogen compound of the first element can replenish the first element while removing the diffused second element, so that when the first epitaxial layer contacts the second epitaxial layer to form an interface transition layer, the thickness of the interface transition layer can be reduced and the steepness of the interface transition layer can be improved, thereby avoiding a decrease in carrier mobility.

Optionally, after surface treatment with the halogen compound 30 of the first element, the thickness of the interface transition layer 203 between the first epitaxial layer 201 and the second epitaxial layer 202 is 0.2 nm-0.8 nm.

In one embodiment, the first element includes silicon, the second element includes germanium or phosphorus; the first epitaxial layer 201 includes a silicon germanium layer, a silicon phosphide layer or a phospho-silicon germanium layer, and the second epitaxial layer 202 includes a silicon layer; and the halogen compound 30 of the first element includes SiCl ₂ H ₂ or SiCl ₂ .

For example, taking the case where the first element is silicon, the second element is germanium, and the halogen compound 30 of the first element is SiCl ₂ H ₂ or SiCl ₂ as an example, the substrate 10 may be a silicon substrate, the first epitaxial layer 201 may be a silicon germanium layer, and the second epitaxial layer 202 may be a silicon layer. When forming the first epitaxial layer 201, the thickness of the silicon germanium (Si _1-x Ge _x ,) layer grown by using the precursor of silicon germanium may be 1nm-200nm. Thereafter, the valve of the precursor of silicon germanium is quickly closed, and a halogen compound of silicon such as SiCl ₂ H ₂ or SiCl ₂ is introduced into the growth chamber for surface treatment, and the treatment time of the surface treatment may be 0.1s-120s. Finally, when forming the second epitaxial layer 202, the thickness of the silicon layer grown by using the precursor of silicon may be 1nm-500nm, thereby completing the growth of one epitaxial cycle. The above process of forming the epitaxial cycle may be continuously repeated to form at least one epitaxial cycle, thereby forming the superlattice structure 20.

FIG7 is a comparison diagram of the cross-sectional structure of the interface transition layer 203 not treated with the silicon halogen compound and the interface transition layer 203 treated with the silicon halogen compound in one epitaxial cycle, wherein FIG7 (a) is a high resolution transmission electron microscope image of the superlattice structure without surface treatment, FIG. 7 (b) is a high-resolution transmission electron microscope image of a superlattice structure without surface treatment after image processing, FIG. 7 (c) is a high-resolution transmission electron microscope image of a superlattice structure with surface treatment, and FIG. 7 (d) is a high-resolution transmission electron microscope image of a superlattice structure with surface treatment after image processing. The distance between the two dotted lines in FIG. 7 (a) and FIG. 7 (b) represents the thickness of the interface transition layer 203 that has not been treated with the halogen compound of silicon, and the distance between the two dotted lines in FIG. 7 (c) and FIG. 7 (d) represents the thickness of the interface transition layer 203 that has not been treated with the halogen compound of silicon. As can be seen from FIG. 7, after being treated with the halogen compound of silicon, the thickness of the interface transition layer 203 between the silicon layer/silicon germanium layer is significantly reduced (the thickness of the interface transition layer 203 after surface treatment is about 0.5nm), and the steepness of the interface transition layer 203 is also significantly improved. This can further avoid the decrease in the mobility of carriers.

In one embodiment, the upper surface of the first epitaxial layer 201 is surface treated with a halogen compound 30 of a first element under a preset protective atmosphere; the surface treatment temperature is 700° C. to 1200° C.; and the surface treatment time is 0.1 s to 120 s.

The preset protective atmosphere may be the atmosphere condition when the first epitaxial layer 201 is formed. Still taking the first epitaxial layer 201 as a silicon germanium layer as an example, when forming the first epitaxial layer 201, a silicon germanium (Si _1-x Ge _x , 0＜x＜1) layer is grown using a silicon germanium precursor, and then, only the precursor valve needs to be closed and the valve of the silicon halogen compound needs to be opened to process the upper surface of the first epitaxial layer 201, and in this process, it is not necessary to switch the gas atmosphere. In other words, the first preset protective atmosphere may also be the gas atmosphere when the first epitaxial layer 201 is formed.

In addition, the temperature of the surface treatment may also be the temperature condition when forming the first epitaxial layer 201. Still taking the first epitaxial layer 201 as a silicon germanium layer as an example, when forming the first epitaxial layer 201, a silicon germanium (Si _1-x Ge _x , 0＜x＜1) layer is grown using a silicon germanium precursor. Afterwards, the upper surface of the first epitaxial layer 201 can be treated by simply closing the precursor valve and opening the silicon halogen compound valve. In this process, That is, the temperature of the surface treatment may also be the temperature condition when the first epitaxial layer 201 is formed.

In one embodiment, the preset protective atmosphere includes a reducing atmosphere or a vacuum atmosphere. For example, the preset protective atmosphere can be a pure hydrogen atmosphere, or a mixed atmosphere of hydrogen and an inert gas, or an ultra-high vacuum atmosphere.

In one embodiment, as shown in FIG. 3 , a plurality of epitaxial cycles are performed to form a first epitaxial layer 201 and a second epitaxial layer 202 stacked sequentially from bottom to top on the substrate 10 .

For 3D DRAM and similar semiconductor devices, the substrate 10 is usually a silicon substrate 10, the first epitaxial layer 201 is a silicon germanium layer or a silicon phosphide layer, and the second epitaxial layer 202 is a silicon layer to form a superlattice structure 20. In order to ensure the performance of the above-mentioned semiconductor devices and the requirements of process feasibility, the thickness of the silicon germanium layer or the silicon phosphide layer used as the first epitaxial layer 201 is usually required to reach a certain level (for example, >60nm), and the number of epitaxial periods of the superlattice structure 20 formed by the first epitaxial layer 201 and the second epitaxial layer 202 is as large as possible, that is, for the above-mentioned semiconductor devices, the thicker the superlattice structure 20 is, the better.

In one embodiment, the number of epitaxial cycles performed is 1-200.

In one embodiment, before performing at least one epitaxial cycle, the method for preparing a semiconductor structure further includes: pre-treating the substrate 10 .

In one embodiment, the substrate 10 is pretreated, including: pretreating the substrate 10 with hydrofluoric acid, and/or performing a reduction treatment on the substrate 10 at a preset temperature and a preset reducing atmosphere.

In one embodiment, the preset temperature is 700° C. to 1200° C. For example, the preset reducing atmosphere may be a pure hydrogen atmosphere, or may be a mixed atmosphere of hydrogen and an inert gas.

Furthermore, the preset protective atmosphere and the preset reducing atmosphere may be the same, for example, both may be reducing atmospheres. Thus, during the execution of at least one epitaxial cycle, the gas atmosphere does not need to be switched, thereby being able to Avoiding cumbersome process operations can further save costs.

Furthermore, during the execution of at least one epitaxial cycle, the temperature can be kept at a preset temperature, thereby eliminating the need to frequently switch the temperature range, thereby avoiding cumbersome process operations, and further saving costs.

On the other hand, the present application also provides a semiconductor structure, as shown in Figure 3, the semiconductor structure includes a substrate 10, a first epitaxial layer 201 and a second epitaxial layer 202 stacked in sequence on the substrate 10, and an interface transition layer 203; wherein the first epitaxial layer 201 includes a compound of a first element and a second element having segregation characteristics; the second epitaxial layer 202 includes the first element; and the interface transition layer 203 is located between adjacent first epitaxial layers 201 and second epitaxial layers 202.

Among them, the material of the substrate 10 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon silicon germanium (SiGe C), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGe OI), silicon germanium on insulator (SiGe OI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

Optionally, the substrate 10 may include a first element, and the first element may refer to the most important element in the substrate 10 . For example, when the material of the substrate 10 is silicon, the first element may be silicon.

As shown in FIG3 , the first epitaxial layer 201 and the second epitaxial layer 202 stacked from bottom to top can form a superlattice structure 20. The superlattice structure 20 refers to a multilayer film structure in which two thin layers of different components grow alternately and maintain a strict periodicity, which can be understood as a specific form of layered fine composite material. Among them, the main semiconductor properties of the first epitaxial layer 201 and the second epitaxial layer 202, such as the band gap or doping level, can be independently The number of the first epitaxial layer 201 and the second epitaxial layer 202 can also be controlled manually during their growth.

The second element may be determined after the first element is determined. For example, when the first element is silicon, the second element may be phosphorus (P), germanium (Ge), etc. In actual application scenarios, the types of the first element and the second element may be determined by comprehensively considering the actual process requirements and costs, and this embodiment does not limit this.

The halogen compound 30 of the first element refers to a compound containing the first element and halogen elements, and the halogen elements include fluorine, chlorine, bromine, iodine, etc., which are the most typical non-metallic elements. Taking silicon as an example, the halogen compound of silicon may include silicon tetrafluoride (SiF ₄ ), silicon dichloride (SiCl ₂ ), silicon dichloride (SiH ₂ Cl ₂ ), etc.

When the second epitaxial layer 202 is formed on the upper surface of the first epitaxial layer 201, since the constituent elements of the first epitaxial layer 201 and the second epitaxial layer 202 are different, an interface transition layer 203 is formed at the interface where the first epitaxial layer 201 and the second epitaxial layer 202 contact. At the same time, since the second element has a segregation property, after the second epitaxial layer 202 is formed, the atoms corresponding to the second element diffuse on the surface of the first epitaxial layer 201, resulting in a relatively thick interface transition layer 203.

By using the halogen compound 30 of the first element to perform surface treatment on the upper surface of the first epitaxial layer 201, the thickness of the interface transition layer 203 can be reduced. This is because: on the one hand, the halogen compound 30 of the first element will react with the atoms corresponding to the second element diffused from the upper surface of the first epitaxial layer 201, thereby removing part of the atoms corresponding to the diffused second element; on the other hand, since these halogen compounds contain the first element, they can compensate for the first element on the upper surface of the first epitaxial layer 201. Therefore, when the first epitaxial layer 201 and the second epitaxial layer 202 are in contact to form the interface transition layer 203, the thickness of the interface transition layer 203 can be reduced and the steepness of the interface transition layer 203 can be improved, thereby avoiding the decrease in carrier mobility.

In addition, after the first epitaxial layer 201 is processed with the halogen compound 30 of the first element, the growth rate of the entire superlattice structure 20 is not affected, and the stress state inside the first epitaxial layer 201 is not affected.

The semiconductor structure comprises a substrate 10, a first epitaxial layer 201 and a second epitaxial layer 202 sequentially stacked on the substrate 10, and an interface transition layer 203; wherein the first epitaxial layer 201 comprises a compound of a first element and a second element having segregation characteristics; the second epitaxial layer 202 comprises the first element; and the interface transition layer 203 is located between the adjacent first epitaxial layer 201 and the second epitaxial layer 202. Since the upper surface of the first epitaxial layer 201 is surface treated with the halogen compound 30 of the first element, the halogen compound 30 of the first element can supplement the first element while removing the diffused second element, so that when the first epitaxial layer 201 and the second epitaxial layer 202 contact to form the interface transition layer 203, the thickness of the interface transition layer 203 can be reduced and the steepness of the interface transition layer 203 can be improved, thereby preventing the mobility of carriers from decreasing.

In one embodiment, the first element includes silicon, the second element includes germanium or phosphorus; the first epitaxial layer 201 includes a silicon germanium layer, a silicon phosphide layer or a phospho-silicon germanium layer, and the second epitaxial layer 202 includes a silicon layer; and the halogen compound 30 of the first element includes SiCl ₂ H ₂ or SiCl ₂ .

As shown in FIG. 7 , FIG. 7 is a comparison diagram of the cross-sectional structures of the interface transition layer 203 that has not been treated with a silicon halogen compound and the interface transition layer 203 that has been treated with a silicon halogen compound in an epitaxial cycle, wherein FIG. 7 (a) is a high-resolution transmission electron microscope image of a superlattice structure that has not been surface treated, FIG. 7 (b) is a high-resolution transmission electron microscope image of a superlattice structure that has not been surface treated after image processing, FIG. 7 (c) is a high-resolution transmission electron microscope image of a superlattice structure that has been surface treated, and FIG. 7 (d) is a high-resolution transmission electron microscope image of a superlattice structure that has been surface treated after image processing. The two dotted lines between FIG. 7 (a) and FIG. 7 (b) are as follows: The distance between the two dashed lines in Figures (c) and (d) of Figure 7 represents the thickness of the interface transition layer 203 that has not been treated with the halogen compound of silicon. As can be seen from Figure 7, after being treated with the halogen compound of silicon, the thickness of the interface transition layer 203 between the silicon layer and the silicon germanium layer is significantly reduced (the thickness of the interface transition layer 203 after surface treatment is about 0.5nm), and the steepness of the interface transition layer 203 is also significantly improved. This can further prevent the mobility of carriers from decreasing.

The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above embodiments only express several implementation methods of the present application, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be based on the attached claims.

Claims (11)

A method for preparing a semiconductor structure, comprising: providing a substrate; Performing at least one epitaxial cycle to form a first epitaxial layer and a second epitaxial layer stacked sequentially from bottom to top on the substrate; the epitaxial cycle includes: forming the first epitaxial layer on the substrate, wherein the first epitaxial layer includes a compound of a first element and a second element having a segregation characteristic; Performing surface treatment on the upper surface of the first epitaxial layer using a halogen compound of the first element; The second epitaxial layer is formed on the surface-treated first epitaxial layer, wherein the second epitaxial layer includes the first element. The method for preparing a semiconductor structure according to claim 1, wherein the first element includes silicon, the second element includes germanium or phosphorus; the first epitaxial layer includes a silicon germanium layer, a silicon phosphide layer or a phospho-silicon germanium layer, and the second epitaxial layer includes a silicon layer; and the halogen compound of the first element includes SiCl ₂ H ₂ or SiCl ₂ . The method for preparing a semiconductor structure according to claim 1, wherein the upper surface of the first epitaxial layer is surface-treated with a halogen compound of the first element under a preset protective atmosphere; the surface treatment temperature is 700°C to 1200°C; and the surface treatment time is 0.1s to 120s. The method for preparing a semiconductor structure according to claim 3, wherein the preset protective atmosphere comprises a reducing atmosphere or a vacuum atmosphere. The method for preparing a semiconductor structure according to claim 1, wherein a plurality of said epitaxial cycles are performed to form on said substrate said first epitaxial layer and said second epitaxial layer stacked sequentially from bottom to top. The method for preparing a semiconductor structure according to claim 5, wherein the epitaxial growth is performed The number of cycles ranges from 1 to 200. The method for preparing a semiconductor structure according to any one of claims 1 to 6, wherein before performing at least one epitaxial cycle, the method further comprises: The substrate is pre-treated. The method for preparing a semiconductor structure according to claim 7, wherein the pre-treating the substrate comprises: Pre-treating the substrate with hydrofluoric acid; and/or The substrate is subjected to reduction treatment at a preset temperature and a preset reducing atmosphere. The method for preparing a semiconductor structure according to claim 8, wherein the preset temperature is 700°C to 1200°C. A semiconductor structure, comprising: substrate; A first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate; wherein the first epitaxial layer comprises a compound of a first element and a second element having a segregation characteristic; and the second epitaxial layer comprises the first element; The interface transition layer is located between the first epitaxial layer and the second epitaxial layer. The semiconductor structure according to claim 10, wherein the first element comprises silicon, the second element comprises germanium or phosphorus; the first epitaxial layer comprises a silicon germanium layer, a silicon phosphide layer or a phospho-silicon germanium layer, and the second epitaxial layer comprises a silicon layer; and the halogen compound of the first element comprises SiCl ₂ H ₂ or SiCl ₂ .