WO2024253661A1

WO2024253661A1 - Facilitating alignment between ssb transmissions and tdd pattern

Info

Publication number: WO2024253661A1
Application number: PCT/US2023/024909
Authority: WO
Inventors: Sami-Jukka Hakola; Jorma Johannes KAIKKONEN
Original assignee: Nokia Technologies Oy; Nokia of America Corp
Current assignee: Nokia Technologies Oy; Nokia of America Corp
Priority date: 2023-06-09
Filing date: 2023-06-09
Publication date: 2024-12-12
Anticipated expiration: 2025-12-09
Also published as: WO2024253661A9

Abstract

An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

Description

Facilitating Alignment Between SSB Transmissions And TDD Pattern

TECHNICAL FIELD

[0001] The examples and non-limiting example embodiments relate generally to communications and, more particularly, to a facilitating alignment between SSB transmissions and a TDD pattern.

BACKGROUND

[0002] It is known perform communication using resources such as beams in a communication network.

SUMMARY

[0003] In accordance with an aspect, an apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0004] In accordance with an aspect, an apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determine a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

[0005] In accordance with an aspect, an apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0006] In accordance with an aspect, an apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determine a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The foregoing aspects and other features are explained in the following description, taken in connection with the accompanying drawings.

[0008] FIG. 1 is a block diagram of one possible and non-limiting system in which the example embodiments may be practiced.

[0009] FIG. 2 shows an example time-frequency structure of an SSB.

[0010] FIG. 3 is a table showing that the maximum number of candidate SSBs (L_max) within an SS burst set depends upon the carrier frequency and/or carrier frequency band.

[0011] FIG. 4 is a table showing that within a 5ms half frame, the starting OFDM symbol index for a candidate SSB within an SS burst set depends upon subcarrier spacing (SCS) and a carrier frequency and/or carrier frequency band.

[0012] FIG. 5 is a table illustrating example numerologies for FR3.

[0013] FIG. 6 shows an example SSB burst when using 60 kHz SCS and that typical TDD UL-DL patterns lead to a situation where no 16 SSBs can be transmitted by the gNB.

[0014] FIG. 7 shows an example SSB mapping pattern.

[0015] FIG. 8 shows another example SSB mapping pattern.

[0016] FIG. 9 shows example SSB mapping patterns for different UL-DL TDD patterns.

[0017] FIG. 10 is an example apparatus configured to implement the examples described herein.

[0018] FIG. 11 shows a representation of an example of non-volatile memory media used to store instructions that implement the examples described herein.

[0019] FIG. 12 is an example method, based on the examples described herein.

[0020] FIG. 13 is an example method, based on the examples described herein.

[0021] FIG. 14 is an example method, based on the examples described herein.

[0022] FIG. 15 is an example method, based on the examples described herein.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0023] Turning to FIG. 1, this figure shows a block diagram of one possible and nonlimiting example in which the examples may be practiced. A user equipment (UE) 110, radio access network (RAN) node 170, and network element(s) 190 are illustrated. In the example of FIG. 1, the user equipment (UE) 110 is in wireless communication with a wireless network 100. A UE is a wireless device that can access the wireless network 100. The UE 110 includes one or more processors 120, one or more memories 125, and one or more transceivers 130 interconnected through one or more buses 127. Each of the one or more transceivers 1 0 includes a receiver, Rx, 132 and a transmitter, Tx, 133. The one or more buses 127 may be address, data, or control buses, and may include any interconnection mechanism, such as a series of lines on a motherboard or integrated circuit, fiber optics or other optical communication equipment, and the like. The one or more transceivers 130 are connected to one or more antennas 128. The one or more memories 125 include computer program code 123. The UE 110 includes a module 140, comprising one of or both parts 140-1 and/or 140- 2, which may be implemented in a number of ways. The module 140 may be implemented in hardware as module 140-1, such as being implemented as part of the one or more processors 120. The module 140-1 may be implemented also as an integrated circuit or through other hardware such as a programmable gate array. In another example, the module 140 may be implemented as module 140-2, which is implemented as computer program code 123 and is executed by the one or more processors 120. For instance, the one or more memories 125 and the computer program code 123 may be configured to, with the one or more processors 120, cause the user equipment 110 to perform one or more of the operations as described herein. The UE 110 communicates with RAN node 170 via a wireless link 111.

[0024] The RAN node 170 in this example is a base station that provides access for wireless devices such as the UE 110 to the wireless network 100. The RAN node 170 may be, for example, a base station for 5G, also called New Radio (NR). In 5G, the RAN node 170 may be a NG-RAN node, which is defined as either a gNB or an ng-eNB. A gNB is a node providing NR user plane and control plane protocol terminations towards the UE, and connected via the NG interface (such as connection 131) to a 5GC (such as, for example, the network element(s) 190). The ng-eNB is a node providing E-UTRA user plane and control plane protocol terminations towards the UE, and connected via the NG interface (such as connection 131) to the 5GC. The NG-RAN node may include multiple gNBs, which may also include a central unit (CU) (gNB-CU) 196 and distributed unit(s) (DUs) (gNB-DUs), of which DU 195 is shown. Note that the DU 195 may include or be coupled to and control a radio unit (RU). The gNB-CU 196 is a logical node hosting radio resource control (RRC), SDAP and PDCP protocols of the gNB or RRC and PDCP protocols of the en-gNB that control the operation of one or more gNB-DUs. The gNB-CU 196 terminates the Fl interface connected with the gNB-DU 195. The Fl interface is illustrated as reference 198, although reference 198 also illustrates a link between remote elements of the RAN node 170 and centralized elements of the RAN node 170, such as between the gNB-CU 196 and the gNB- DU 195. The gNB-DU 195 is a logical node hosting RLC, MAC and PHY layers of the gNB or en-gNB, and its operation is partly controlled by gNB-CU 196. One gNB-CU 196 supports one or multiple cells. One cell may be supported with one gNB-DU 195, or one cell may be supported/shared with multiple DUs under RAN sharing. The gNB-DU 195 terminates the Fl interface 198 connected with the gNB-CU 196. Note that the DU 195 is considered to include the transceiver 160, e.g., as part of a RU, but some examples of this may have the transceiver 160 as part of a separate RU, e.g., under control of and connected to the DU 195. The RAN node 170 may also be an eNB (evolved NodeB) base station, for LTE (long term evolution), or any other suitable base station or node.

[0025] The RAN node 170 includes one or more processors 152, one or more memories 155, one or more network interfaces (N/W I/F(s)) 161, and one or more transceivers 160 interconnected through one or more buses 157. Each of the one or more transceivers 160 includes a receiver, Rx, 162 and a transmitter, Tx, 163. The one or more transceivers 160 are connected to one or more antennas 158. The one or more memories 155 include computer program code 153. The CU 196 may include the processor(s) 152, one or more memories 155, and network interfaces 161. Note that the DU 195 may also contain its own memory/memories and processor(s), and/or other hardware, but these are not shown.

[0026] The RAN node 170 includes a module 150, comprising one of or both parts 150-1 and/or 150-2, which may be implemented in a number of ways. The module 150 may be implemented in hardware as module 150-1, such as being implemented as part of the one or more processors 152. The module 150-1 may be implemented also as an integrated circuit or through other hardware such as a programmable gate array. In another example, the module 150 may be implemented as module 150-2, which is implemented as computer program code 153 and is executed by the one or more processors 152. For instance, the one or more memories 155 and the computer program code 153 are configured to, with the one or more processors 152, cause the RAN node 170 to perform one or more of the operations as described herein. Note that the functionality of the module 150 may be distributed, such as being distributed between the DU 195 and the CU 196, or be implemented solely in the DU [0027] The one or more network interfaces 161 communicate over a network such as via the links 176 and 131. Two or more gNBs 170 may communicate using, e.g., link 176. The link 176 may be wired or wireless or both and may implement, for example, an Xn interface for 5G, an X2 interface for LTE, or other suitable interface for other standards.

[0028] The one or more buses 157 may be address, data, or control buses, and may include any interconnection mechanism, such as a series of lines on a motherboard or integrated circuit, fiber optics or other optical communication equipment, wireless channels, and the like. For example, the one or more transceivers 160 may be implemented as a remote radio head (RRH) 195 for LTE or a distributed unit (DU) 195 for gNB implementation for 5G, with the other elements of the RAN node 170 possibly being physically in a different location from the RRH/DU 195, and the one or more buses 157 could be implemented in part as, for example, fiber optic cable or other suitable network connection to connect the other elements (e.g., a central unit (CU), gNB-CU 196) of the RAN node 170 to the RRH/DU 195. Reference 198 also indicates those suitable network link(s).

[0029] A RAN node / gNB can comprise one or more TRPs to which the methods described herein may be applied. FIG. 1 shows that the RAN node 170 comprises two TRPs, TRP 51 and TRP 52. The RAN node 170 may host or comprise other TRPs not shown in FIG. 1.

[0030] A relay node in NR is called an integrated access and backhaul node. A mobile termination part of the IAB node facilitates the backhaul (parent link) connection. In other words, the mobile termination part comprises the functionality which carries UE functionalities. The distributed unit part of the IAB node facilitates the so called access link (child link) connections (i.e. for access link UEs, and backhaul for other IAB nodes, in the case of multi-hop IAB). In other words, the distributed unit part is responsible for certain base station functionalities. The IAB scenario may follow the so called split architecture, where the central unit hosts the higher layer protocols to the UE and terminates the control plane and user plane interfaces to the 5G core network.

[0031] It is noted that the description herein indicates that “cells” perform functions, but it should be clear that equipment which forms the cell may perform the functions. The cell makes up part of a base station. That is, there can be multiple cells per base station. For example, there could be three cells for a single carrier frequency and associated bandwidth, each cell covering one-third of a 360 degree area so that the single base station’s coverage area covers an approximate oval or circle. Furthermore, each cell can correspond to a single carrier and a base station may use multiple carriers. So if there are three 120 degree cells per carrier and two carriers, then the base station has a total of 6 cells.

[0032] The wireless network 100 may include a network element or elements 190 that may include core network functionality, and which provides connectivity via a link or links 181 with a further network, such as a telephone network and/or a data communications network (e.g., the Internet). Such core network functionality for 5G may include location management functions (LMF(s)) and/or access and mobility management function(s) (AMF(S)) and/or user plane functions (UPF(s)) and/or session management function(s) (SMF(s)). Such core network functionality for LTE may include MME (mobility management entity)/SGW (serving gateway) functionality. Such core network functionality may include SON (self- organizing/optimizing network) functionality. These are merely example functions that may be supported by the network element(s) 190, and note that both 5G and LTE functions might be supported. The RAN node 170 is coupled via a link 131 to the network element 190. The link 131 may be implemented as, e.g., an NG interface for 5G, or an SI interface for LTE, or other suitable interface for other standards. The network element 190 includes one or more processors 175, one or more memories 171, and one or more network interfaces (N/W I/F(s)) 180, interconnected through one or more buses 185. The one or more memories 171 include computer program code 173. Computer program code 173 may include SON and/or MRO functionality 172.

[0033] The wireless network 100 may implement network virtualization, which is the process of combining hardware and software network resources and network functionality into a single, software-based administrative entity, or a virtual network. Network virtualization involves platform virtualization, often combined with resource virtualization. Network virtualization is categorized as either external, combining many networks, or parts of networks, into a virtual unit, or internal, providing network- like functionality to software containers on a single system. Note that the virtualized entities that result from the network virtualization are still implemented, at some level, using hardware such as processors 152 or 175 and memories 155 and 171, and also such virtualized entities create technical effects.

[0034] The computer readable memories 125, 155, and 171 may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-transitory memory, transitory memory, fixed memory and removable memory. The computer readable memories 125, 155, and 171 may be means for performing storage functions. The processors 120, 152, and 175 may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on a multi-core processor architecture, as nonlimiting examples. The processors 120, 152, and 175 may be means for performing functions, such as controlling the UE 110, RAN node 170, network element(s) 190, and other functions as described herein.

[0035] In general, the various example embodiments of the user equipment 110 can include, but are not limited to, cellular telephones such as smart phones, tablets, personal digital assistants (PDAs) having wireless communication capabilities, portable computers having wireless communication capabilities, image capture devices such as digital cameras having wireless communication capabilities, gaming devices having wireless communication capabilities, music storage and playback devices having wireless communication capabilities, internet appliances including those permitting wireless internet access and browsing, tablets with wireless communication capabilities, head mounted displays such as those that implement virtual/augmented/mixed reality, as well as portable units or terminals that incorporate combinations of such functions. The UE 1 10 can also be a vehicle such as a car, or a UE mounted in a vehicle, a UAV such as e.g. a drone, or a UE mounted in a UAV. The user equipment 110 may be terminal device, such as mobile phone, mobile device, sensor device etc., the terminal device being a device used by the user or not used by the user.

[0036] UE 110, RAN node 170, and/or network element(s) 190, (and associated memories, computer program code and modules) may be configured to implement (e.g. in part) the methods described herein, including facilitating alignment between SSB transmissions and a TDD pattern. Thus, computer program code 123, module 140-1, module 140-2, and other elements/features shown in FIG. 1 of UE 110 may implement user equipment related aspects of the examples described herein. Similarly, computer program code 153, module 150-1, module 150-2, and other elements/features shown in FIG. 1 of RAN node 170 may implement gNB/TRP related aspects of the examples described herein. Computer program code 173 and other elements/features shown in FIG. 1 of network element(s) 190 may be configured to implement network element related aspects of the examples described herein.

[0037] Having thus introduced a suitable but non-limiting technical context for the practice of the example embodiments, the example embodiments are now described with greater specificity.

[0038] The examples described herein are related to facilitating a multi-beam system that can have multiple SSBs while supporting typical UL-DL TDD patterns.

[0039] Cell search is the procedure for a UE to acquire time and frequency synchronization with a cell and to detect the physical layer cell ID (PCI) of the cell. During cell search operations which are carried out when a UE is powered ON, in mobility in connected mode, idle mode mobility (e.g. reselections), inter-RAT mobility to NR system etc., the UE uses NR synchronization signals and PBCH to derive the necessary information required to access the cell. Similar to LTE, two types of synchronization signals are defined for NR: Primary Synchronization Signal (PSS) and the Secondary Synchronization Signal (SSS). The Synchronization Signal/PBCH block (SSB) consists of PSS, SSS and Physical Broadcast Channel (PBCH). SSS is also used by the UE for Ll-RSRP and RSRQ measurements.

[0040] An example time-frequency structure of an SSB 201 is shown in FIG. 2.

[0041] PSS 202, SSS 206 and PBCH 204 are always together in consecutive OFDM symbols.

[0042] Each SSB 201 occupies 4 OFDM symbols 208 in the time domain and is spread over 240 subcarriers (20 RBs) 210 in the frequency domain.

[0043] PSS 202 occupies the first OFDM symbol 208 and spans over 127 subcarriers.

[0044] SSS 206 is located in the third OFDM symbol 208 and spans over 127 subcarriers. There are 8 unused subcarriers below SSS (refer to 212) and 9 unused subcarriers above SSS (refer to 214).

[0045] PBCH 204 occupies two full OFDM symbols 208 (second and fourth) spanning 240 subcarriers 210 and in the third OFDM symbol 208 spanning 48 subcarriers (216, 218) below and above SSS 206. This results in PBCH occupying 576 subcarriers across three OFDM symbols 208 (240+48+48+240 = 576). [0046] PBCH DM-RS occupies 144 REs which is one-fourth of total Res, where the remaining REs are used for the PBCH payload (576-144 = 432 REs).

[0047] Each SSB 201 spans across 4 OFDM symbols 208 in the time domain.

[0048] An SSB 201 is periodically transmitted with a periodicity of 5ms, 10ms, 20ms, 40ms, 80ms or 160ms.

[0049] While longer SSB periodicities enhance network energy performance, the shorter periodicities facilitate faster cell search for UEs.

[0050] A UE can assume a default periodicity of 20ms during initial cell search or idle mode mobility.

[0051] To enable beam-sweeping for PSS and/or SSS and PBCH, SS burst sets are defined. An SS burst set comprised of a set of SSBs (i.e., an SSB burst), where each SSB potentially be transmitted on a different beam.

[0052] An SS burst set consists of one or more SSBs.

[0053] SSBs in the SS burst set are transmitted in time-division multiplexing fashion.

[0054] An SS burst set may be confined to a 5ms window and is either located in the first- half or in the second-half of a 10ms radio frame.

[0055] The network sets the SSB periodicity via RRC parameter ssb-PeriodicityServingCell which can take values in the range {5ms, 10ms, 20ms, 40ms, 80ms, 160ms}.

[0056] The maximum number of candidate SSBs (Lmax) within an SS burst set depends upon the carrier frequency and/or carrier frequency band as shown as one example in the table provided in FIG. 3.

[0057] Within a 5ms half frame, the starting OFDM symbol index for a candidate SSB within a SS burst set depends upon subcarrier spacing (SCS) and the carrier frequency and/or carrier frequency band (examples illustrated in the table provided in FIG. 4).

[0058] TDD UL-DL patterns define UL and DL allocation in a radio frame. For example, a TDD UL-DL pattern DDDFU means downlink slot - downlink slot - downlink slot - flexible slot (DL + UL) - uplink slot. [0059] 3GPP 6G is about to introduce a new band called FR3 (7-20 GHz). The table provided in FIG. 5 illustrates the envisioned numerologies for FR3.

[0060] As can be seen in FIG. 5, two example subcarrier spacing options are 30 and 60 kHz. 60 kHz SCS would allow e.g. 16 SSBs with the same time domain overhead as 8 SSBs with 30 kHz SCS. One of the requirements for the FR3 operation from operator point of view is to be able to reuse the sites of FR1. Thus, a higher number of SSBs is likely required to achieve the targeted coverage.

[0061] Targeted coverage means that e.g. operation at the 7 and 14 GHz carrier frequency range is required to utilize the site grid of the 3.5 GHz carrier frequency range. In order to provide the same coverage as at 3.5 GHz, higher order of beamforming is needed at 7 and 14 GHz. That means the use of a larger antenna array in terms of number of antenna elements and thus larger beamforming and antenna gains both in downlink and uplink. Larger beamforming gain means more narrow transmission and reception beams at the gNB for DL and UL, respectively. In downlink and regarding the transmission of SSBs that means that a higher number of SSBs are needed due to operating with more narrow beams in order to be able to transmit SSBs throughout the whole cell or the targeted sector.

[0062] Based on TS 38.213, for sub-carrier spacings of 15kHz, 30kHz, 480kHz and 960kHz all SSBs of the SS burst set are transmitted in consecutive slots. For FR2.1 the SSB patterns have a short gap in between sets of SSBs. However, it has not been discussed in 3GPP to align the SSB positions and the used TDD UL-DL pattern.

[0063] In most common TDD UL-DL patterns, there are only few slots allocated for DL before a flexible slot (F) and UL slot(s).

[0064] But due to missing SSB position pattern and TDD UL-DL pattern alignment in current specifications, the gNB needs to operate with less SSBs, thus meaning less transmission beams and thus shorter coverage.

[0065] FIG. 6 shows an envisioned SSB burst when using 60 kHz SCS and that typical TDD UL-DL patterns lead to a situation that no 16 SSBs can be transmitted by the gNB (assuming that in the flexible slot (F) there are e.g. four DL symbols plus six symbols for guard plus four symbols UL symbols, which implies that not any SSB can be transmitted in the F slot). The four DL symbols correspond to the starting position of the first SSB in the slot in NR symbol number 2 or number 4.

[0066] As shown in FIG. 6, for the DDDFU pattern (602) SSBs cannot be transmitted in slots 3 and 4 (refer to item 604), and for the DDDFUUDDDD pattern (612), SSBs cannot be transmitted on slots 3, 4, and 5 (refer to item 614).

[0067] With less SSB positions, the gNB 170 has less beams in use to cover the whole cell sector. That means that the gNB 170 needs to operate with wider beams meaning lower total EIRP (lower beamforming/antenna gain) leading to lower or shorter coverage. The solution described herein is to define SSB position patterns that fit to the typical TDD patterns and the used pattern is indicated e.g. in the PBCH of the SSB. The indication could be that the PBCH indicates the index to the certain SSB location pattern or to the certain TDD pattern. If the latter, then the UE 110 can determine (based on a mapping between the TDD pattern and the SSB location pattern, for example within the specification) that which SSB location pattern is in use.

[0068] The generic problem is that typical TDD UL-DL patterns prevent utilizing all the SSB positions for the SSB transmissions limiting the coverage of the system. The SSB positions and TDD UL-DL pattern alignment has not been discussed in 3GPP. Coverage is one of the most important aspects for the operators. Coverage is reduced if the gNB needs to operate with less SSBs meaning that transmission beams need to be wider meaning lower beamforming gain meaning shorter coverage.

[0069] It is also to be noted that the problem exists with 30 kHz SCS as well that with the above typical TDD UL-DL patterns, all eight SSBs cannot be used that could be available with 30 kHz SCS thus limiting coverage.

[0070] In an example embodiment, the gNB 170 transmits an SSB mapping pattern indication (e.g., in PBCH of the SSB), wherein the SSB mapping pattern indication indicates an SSB mapping pattern that may define at least A) a number of parts of a SSB burst while each part occupies a number of consecutive slots, B) the number of consecutive slots in each part of the SSB burst, and C) the slots between the adjacent parts of the SSB burst that are not used for transmitting any SSBs of the SSB burst. The gNB transmits SSBs on the SSB positions defined by the SSB mapping pattern. The last part of the SSB burst may not have the same number of SSBs as other parts due to reaching a maximum number of SSB positions or SSBs. [0071] The UE 110 detects an SSB (depending on under which SSB beam the UE is) and thus obtains the SSB mapping pattern indication and an SSB index (in the SS burst set) which implies that the UE determines the timing of the cell based on the SSB index and SSB mapping pattern. The UE determines the timing (e.g. slot timing) from the SSB, i.e. in which slot it detected the SSB within a radio frame. For that the UE knows how actually the SSBs are located in this specific cell. In an initial cell search the UE may detect one SSB depending on under which SSB beam the UE is. Thus, each SSB carries information about the SSB mapping pattern so that the UE is able to determine e.g. the slot timing from the SSB index and indicated SSB mapping pattern.

[0072] The idea presented by the examples described herein is to have functionality that can be implemented to maximize the number of SSBs while having one of the typical TDD patterns in use.

[0073] The SSB, e.g. PBCH, provides the UE 110 with information about the SSB mapping pattern in use so that the SSB index and typical TDD UL-DL patterns can be used by the gNB 170 (no need to compromise with the coverage).

[0074] The mapping may have different options and the PBCH’s physical layer bits or MIB would then provide index to the pattern in use. In an example embodiment, the mapping may be provided e.g. by providing: number of consecutive slots, periodicity of the consecutive slots, and/or a number of consecutive slots, and/or a number of slots not having SSBs inbetween, and/or an index to a set of pre-defined TDD UL-DL patterns. For example, the standard provides a set of TDD UL-DL patterns of which one can be indicated to the UE in the PBCH/SSB. The set could be also a subset of the whole set, possibly in a later phase of the signaling.

[0075] The slot timing may be determined by a UE based on both the detected SSB index and determined SSB mapping pattern (described in the following section).

[0076] The UE steps to implement the herein described method include: 1. The UE 110 detects SSB, and an SSB index (which could be a logical index not providing directly the slot timing) is obtained. The UE also demodulates and decodes PBCH, 2. The UE determines the SSB mapping pattern, and 3. The UE determines the slot timing based on the detected SSB index and determined SSB pattern. The SSB pattern (such as the SSB pattern shown in FIG. 7) could be indicated with one or more fields in the PBCH of the SSB, for example the PBCH 204 of the SSB 201 shown in FIG. 2.

[0077] The SSB index could be fully incorporated in the PBCH DMRS or partly incorporated in the PBCH DMRS and partly in PBCH (e.g. physical layer bits of the PBCH payload or as part of MIB content). The SSB pattern may have an SSB pattern index in the PBCH payload (physical layer bits of PBCH payload or as part of MIB content).

[0078] For example, PBCH could indicate the SSB mapping pattern as the number of consecutive slots being 3, and the periodicity of the consecutive slots being 5. Then UE 110 determines the SSB index, and the slot timing based on the SSB index and the pattern shown in FIG. 7. As shown in FIG. 7, the number of consecutive slots is 3 (refer e.g. to items 702, 704), and the periodicity of the consecutive slots is 5 (refer e.g. to items 712, 714).

[0079] For instance, if the UE detects SSB index 8 and the described SSB mapping pattern shown in FIG. 7, the UE 110 can determine that the slot index (timing) is 6 (being that SSB index 8 is in slot 6). Symbol timing within the slot 6 is based on the SSB index 8, i.e. based on the first symbol of the first SSB (SSB #8 in this case) in the slot.

[0080] In another example, the PBCH could indicate the SSB mapping pattern as the number of consecutive slots being 3, and the periodicity of the consecutive slots being 10. Refer to FIG. 8, where the number of consecutive slots is 3 (refer e.g. to items 802, 804), and the periodicity of the consecutive slots is 10 (refer e.g. to items 812, 814).

[0081] For instance, if the UE detects SSB index 8 and the described SSB mapping pattern shown in FIG. 8, the UE 110 can determine that the slot index (timing) is 11 (being that SSB index 8 is in slot 11). Symbol timing within the slot 11 is based on the SSB index 8, i.e. based on the first symbol of the first SSB (SSB #8 in this case) in the slot.

[0082] In order to have signaling in the PBCH it may not be fully dynamic but there may be some structure in order to minimize the number of bits. As described herein it is preferable for the UE to be able to measure cells (SSBs) and thus the information about the SSB positions would be preferable.

[0083] In one example, the PBCH provides an index to the assumed UL-DL TDD pattern for the SSB mapping. For example, referring to FIG. 9, there could be the following set:

- Index 0: DDDFU (item 910) - Index 1 : DDDFUUDDDD (item 911)

- Index 2: DDDDDDDFUU (item 912)

[0084] In the example of FIG. 9, SSBs are not mapped to the F slot. Thus, the SSB positions can be determined by the UE based on the index.

[0085] In the examples shown by FIG. 7, FIG. 8, and FIG. 9, the last part of the SSB burst has fewer consecutive slots than other parts. Refer to FIG. 7 slots 10 and 11 , FIG. 8 slots 20 and 21, FIG. 9 item 910 slots 10 and 11, FIG. 9 item 911 slots 20 and 21, and FIG. 9 item 912 slot 10. This may be due to a maximum number of SSBs, or a maximum number of SSB indexes achieved.

[0086] The gNB steps to implement the herein described examples include (1-3):

[0087] 1. gNB/network (170/190) decides the TDD UL-DL configuration to be used in the cell.

[0088] 2. gNB 170 generates an SSB and/or a PBCH by including the information about the used TDD UL-DL pattern and/or SSB mapping pattern, e.g. one of the following: a. number of consecutive slots, b. periodicity of the consecutive slots, and/or c. number of consecutive slots, d. number of slots not having SSBs in-between and/or e. index to a set of pre-defined TDD UL-DL patterns. For example, the standard provides a set of TDD UL-DL patterns of which one can be indicated to the UE in the PBCH and/or the SSB. The set could be also a subset of the whole set possible in a later phase of the signaling.

[0089] 3. gNB 170 transmits SSBs on the SSB positions in the slot according to the used TDD UL-DL pattern and/or SSB mapping pattern in step 2.

[0090] The information fields would be in the PBCH of the SSB.

[0091] Even though in the context of the description we use the SSB in various example embodiments, it should be evident to a person skilled in the art that the proposed embodiments could be applied to other signal structures assisting the UE 110 to acquire synchronization when the system can apply different TDD (UL and DL) slot configurations.

[0092] FIG. 10 is an example apparatus 1000, which may be implemented in hardware, configured to implement the examples described herein. The apparatus 1000 comprises at least one processor 1002 (e.g. an FPGA and/or CPU), one or more memories 1004 including computer program code 1005, the computer program code 1005 having instructions to carry out the methods described herein, wherein the at least one memory 1004 and the computer program code 1005 are configured to, with the at least one processor 1002, cause the apparatus 1000 to implement circuitry, a process, component, module, or function (implemented with control module 1006) to implement the examples described herein, including facilitating alignment between SSB transmissions and a TDD pattern. The memory 1004 may be a non- transitory memory, a transitory memory, a volatile memory (e.g. RAM), or a non-volatile memory (e.g. ROM). SSB timing 1030 of the control module implements the herein described aspects related to facilitating alignment between SSB transmissions and a TDD pattern.

[0093] The apparatus 1000 includes a display and/or I/O interface 1008, which includes user interface (UI) circuitry and elements, that may be used to display aspects or a status of the methods described herein (e.g., as one of the methods is being performed or at a subsequent time), or to receive input from a user such as with using a keypad, camera, touchscreen, touch area, microphone, biometric recognition, one or more sensors, etc. The apparatus 1000 includes one or more communication e.g. network (N/W) interfaces (I/F(s)) 1010. The communication I/F(s) 1010 may be wired and/or wireless and communicate over the Intemet/other network(s) via any communication technique including via one or more links 1024. The link(s) 1024 may be the link(s) 131 and/or 176 from FIG. 1. The link(s) 131 and/or 176 from FIG. 1 may also be implemented using transceiver(s) 1016 and corresponding wireless link(s) 1026. The communication I/F(s) 1010 may comprise one or more transmitters or one or more receivers.

[0094] The transceiver 1016 comprises one or more transmitters 1018 and one or more receivers 1020. The transceiver 1016 and/or communication I/F(s) 1010 may comprise standard well-known components such as an amplifier, filter, frequency-converter, (de)modulator, and encoder/decoder circuitries and one or more antennas, such as antennas 1014 used for communication over wireless link 1026.

[0095] The control module 1006 of the apparatus 1000 comprises one of or both parts 1006- 1 and/or 1006-2, which may be implemented in a number of ways. The control module 1006 may be implemented in hardware as control module 1006-1, such as being implemented as part of the one or more processors 1002. The control module 1006-1 may be implemented also as an integrated circuit or through other hardware such as a programmable gate array. In another example, the control module 1006 may be implemented as control module 1006-2, which is implemented as computer program code (having corresponding instructions) 1005 and is executed by the one or more processors 1002. For instance, the one or more memories 1004 store instructions that, when executed by the one or more processors 1002, cause the apparatus 1000 to perform one or more of the operations as described herein. Furthermore, the one or more processors 1002, the one or more memories 1004, and example algorithms (e.g., as flowcharts and/or signaling diagrams), encoded as instructions, programs, or code, are means for causing performance of the operations described herein.

[0096] The apparatus 1000 to implement the functionality of control 1006 may be UE 110, RAN node 170 (e.g. gNB), or network element(s) 190. Thus, processor 1002 may correspond to processor(s) 120, processor(s) 152 and/or processor(s) 175, memory 1004 may correspond to one or more memories 125, one or more memories 155 and/or one or more memories 171, computer program code 1005 may correspond to computer program code 123, computer program code 153, and/or computer program code 173, control module 1006 may correspond to module 140-1, module 140-2, module 150-1, and/or module 150-2, and communication I/F(s) 1010 and/or transceiver 1016 may correspond to transceiver 130, antenna(s) 128, transceiver 160, antenna(s) 158, N/W I/F(s) 161, and/or N/W I/F(s) 180. Alternatively, apparatus 1000 and its elements may not correspond to either of UE 110, RAN node 170, or network element(s) 190 and their respective elements, as apparatus 1000 may be part of a self-organizing/optimizing network (SON) node or other node, such as a node in a cloud.

[0097] The apparatus 1000 may also be distributed throughout the network (e.g. 100) including within and between apparatus 1000 and any network element (such as a network control element (NCE) 190 and/or the RAN node 170 and/or the UEs, such as UE 110 UE 110-2, and UE 110-3).

[0098] Interface 1012 enables data communication and signaling between the various items of apparatus 1000, as shown in FIG. 10. For example, the interface 1012 may be one or more buses such as address, data, or control buses, and may include any interconnection mechanism, such as a series of lines on a motherboard or integrated circuit, fiber optics or other optical communication equipment, and the like. Computer program code (e.g. instructions) 1005, including control 1006 may comprise object-oriented software configured to pass data or messages between objects within computer program code 1005. The apparatus 1000 need not comprise each of the features mentioned, or may comprise other features as well. The various components of apparatus 1000 may at least partially reside in a common housing 1028, or a subset of the various components of apparatus 1000 may at least partially be located in different housings, which different housings may include housing 1028.

[0099] FIG. 11 shows a schematic representation of non-volatile memory media 1100a (e.g. computer/compact disc (CD) or digital versatile disc (DVD)) and 1 100b (e.g. universal serial bus (USB) memory stick) and 1100c (e.g. cloud storage for downloading instructions and/or parameters 1102 or receiving emailed instructions and/or parameters 1102) storing instructions and/or parameters 1102 which when executed by a processor allows the processor to perform one or more of the steps of the methods described herein.

[0100] FIG. 12 is an example method 1200, based on the example embodiments described herein. At 1210, the method includes transmitting an indication of a synchronization signal pattern. At 1220, the method includes wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst. At 1230, the method includes transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern. Method 1200 may be performed with RAN node 170, one or more network elements 190, or apparatus 1000.

[0101] FIG. 13 is an example method 1300, based on the example embodiments described herein. At 1310, the method includes receiving an indication of a synchronization signal pattern. At 1320, the method includes wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst. At 1330, the method includes determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern. Method 1300 may be performed with UE 110 or apparatus 1000. [0102] FIG. 14 is an example method 1400, based on the example embodiments described herein. At 1410, the method includes transmitting an indication of a synchronization signal pattern. At 1420, the method includes wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst. At 1430, the method includes wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst. At 1440, the method includes transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern. Method 1400 may be performed with RAN node 170, one or more network elements 190, or apparatus 1000.

[0103] FIG. 15 is an example method 1500, based on the example embodiments described herein. At 1510, the method includes receiving an indication of a synchronization signal pattern. At 1520, the method includes wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst. At 1530, the method includes wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst. At 1540, the method includes determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern. Method 1500 may be performed with UE 110 or apparatus 1000.

[0104] The following examples are provided and described herein.

[0105] Example 1. An apparatus including: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0106] Example 2. The apparatus of example 1, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: transmit the indication of the synchronization signal pattern within a physical broadcast channel of a synchronization signal block in at least a first slot of a first part of the synchronization signal burst.

[0107] Example 3. The apparatus of any of examples 1 to 2, wherein the indication of the synchronization signal pattern indicates a periodicity of the consecutive slots.

[0108] Example 4. The apparatus of any of examples 1 to 3, wherein the indication of the synchronization signal pattern indicates a number of slots between a part of the synchronization signal burst and another part of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst.

[0109] Example 5. The apparatus of any of examples 1 to 4, wherein the indication of the synchronization signal pattern indicates a set of at least one time division duplex uplinkdownlink pattern.

[0110] Example 6. The apparatus of example 5, wherein the synchronization signals are transmitted on the synchronization signal positions indicated by the set of the at least one time division duplex uplink-downlink pattern.

[0111] Example 7. The apparatus of any of examples 5 to 6, wherein the set of the at least one time division duplex uplink-downlink pattern is a subset of another set of the at least one time division duplex uplink-downlink pattern.

[0112] Example 8. The apparatus of any of examples 5 to 7, wherein a physical broadcast channel provides an index corresponding to the at least one time division duplex uplinkdownlink pattern.

[0113] Example 9. The apparatus of any of examples 1 to 8, wherein a timing of a cell is based on a first synchronization signal in a slot.

[0114] Example 10. The apparatus of any of examples 1 to 9, wherein the synchronization signal pattern is configured to be used with a user equipment to determine a timing of a cell. [0115] Example 11 . The apparatus of any of examples 1 to 10, wherein the synchronization signal is a synchronization signal and physical broadcast channel block.

[0116] Example 12. An apparatus including: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determine a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

[0117] Example 13. The apparatus of example 12, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: receive the indication of the synchronization signal pattern within a physical broadcast channel of a synchronization signal block in at least a first slot of a first part of the synchronization signal burst.

[0118] Example 14. The apparatus of any of examples 12 to 13, wherein the indication of the synchronization signal pattern indicates a periodicity of the consecutive slots.

[0119] Example 15. The apparatus of any of examples 12 to 14, wherein the indication of the synchronization signal pattern indicates a number of slots between a part of the synchronization signal burst and another part of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst.

[0120] Example 16. The apparatus of any of examples 12 to 15, wherein the indication of the synchronization signal pattern indicates a set of at least one time division duplex uplinkdownlink pattern.

[0121] Example 17. The apparatus of example 16, wherein the synchronization signals are received on synchronization signal positions indicated by the set of the at least one time division duplex uplink-downlink pattern.

[0122] Example 18. The apparatus of any of examples 16 to 17, wherein the set of the at least one time division duplex uplink-downlink pattern is a subset of another set of the at least one time division duplex uplink-downlink pattern.

[0123] Example 19. The apparatus of any of examples 16 to 18, wherein a physical broadcast channel provides an index corresponding to the at least one time division duplex uplink-downlink pattern.

[0124] Example 20. The apparatus of any of examples 12 to 19, wherein the timing of the cell is determined based on a first synchronization signal in a slot.

[0125] Example 21. The apparatus of any of examples 12 to 20, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: receive the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0126] Example 22. The apparatus of any of examples 12 to 21 , wherein the synchronization signal is a synchronization signal and physical broadcast channel block.

[0127] Example 23. The apparatus of any of examples 12 to 22, wherein determining the timing comprises determining a slot timing and/or determining a slot index.

[0128] Example 24. The apparatus of any of examples 12 to 23, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: perform transmission or reception based on the timing.

[0129] Example 25. The apparatus of any of examples 12 to 24, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: use the timing acquired from the synchronization signal to determine timing occasions for downlink (DL) monitoring and uplink (UL) transmission timing occasions.

[0130] Example 26. The apparatus of example 25, wherein the timing is associated with a symbol, slot, or frame.

[0131] Example 27. An apparatus including: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0132] Example 28. An apparatus including: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determine a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

[0133] Example 29. A method including: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0134] Example 30. A method including: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern. [0135] Example 31. A method including: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0136] Example 32. A method including: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

[0137] Example 33. An apparatus including: means for transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and means for transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0138] Example 34. An apparatus including: means for receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and means for determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern. [0139] Example 35. An apparatus including: means for transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and means for transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0140] Example 36. An apparatus including: means for receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and means for determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

[0141] Example 37. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations including: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0142] Example 38. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations including: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

[0143] Example 39. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations including: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

[0144] Example 40. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations including: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

[0145] References to a ‘computer’, ‘processor’, etc. should be understood to encompass not only computers having different architectures such as single/multi-processor architectures and sequential or parallel architectures but also specialized circuits such as field- programmable gate arrays (FPGAs), application specific circuits (ASICs), signal processing devices and other processing circuitry. References to computer program, instructions, code etc. should be understood to encompass software for a programmable processor or firmware such as, for example, the programmable content of a hardware device whether instructions for a processor, or configuration settings for a fixed-function device, gate array or programmable logic device etc.

[0146] The memories as described herein may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-transitory memory, transitory memory, fixed memory and removable memory. The memories may comprise a database for storing data.

[0147] As used herein, the term ‘circuitry’ may refer to the following: (a) hardware circuit implementations, such as implementations in analog and/or digital circuitry, and (b) combinations of circuits and software (and/or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s)/software including digital signal processor(s), software, and memories that work together to cause an apparatus to perform various functions, and (c) circuits, such as a microprocessor(s) or a portion of a microprocessor(s), that require software or firmware for operation, even if the software or firmware is not physically present. As a further example, as used herein, the term ‘circuitry’ would also cover an implementation of merely a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and/or firmware. The term ‘circuitry’ would also cover, for example and if applicable to the particular element, a baseband integrated circuit or applications processor integrated circuit for a mobile phone or a similar integrated circuit in a server, a cellular network device, or another network device.

[0148] It should be understood that the foregoing description is only illustrative. Various alternatives and modifications may be devised by those skilled in the art. For example, features recited in the various dependent claims could be combined with each other in any suitable combination(s). In addition, features from different example embodiments described above could be selectively combined into a new example embodiment. Accordingly, this description is intended to embrace all such alternatives, modifications and variances which fall within the scope of the appended claims.

[0149] The following acronyms and abbreviations that may be found in the specification and/or the drawing figures are given as follows (the abbreviations and acronyms may be appended with each other or with other characters using e.g. a dash, hyphen, slash, or number, and may be case insensitive): 3GPP third generation partnership project

4G fourth generation

5G fifth generation

5GC 5G core network

6G sixth generation

AMF access and mobility management function

ASIC application-specific integrated circuit

CD compact/computer disc

CPU central processing unit

CU central unit or centralized unit

D downlink (e.g. DDDFU where D indicates a downlink slot)

DL downlink

DM-RS demodulation reference signal

DSP digital signal processor

DVD digital versatile disc

EIRP effective isotropic radiated power eNB evolved Node B (e.g., an LTE base station)

EN-DC E-UTRAN new radio - dual connectivity en-gNB node providing NR user plane and control plane protocol terminations towards the UE, and acting as a secondary node in EN- DC

E-UTRA evolved universal terrestrial radio access, i.e., the LTE radio access technology

E-UTRAN E-UTRA network

F flexible (e.g. flexible slot for uplink or downlink)

Fl interface between the CU and the DU

FFS for further study

FPGA field-programmable gate array

FR frequency range gNB base station for 5G/NR, i.e., a node providing NR user plane and control plane protocol terminations towards the UE, and connected via the NG interface to the 5GC

IAB integrated access and backhaul

ID identifier I/F interface I/O input/output LI layer 1 Lmax, L_max maximum number of SSBs within an SS burst set LMF location management function LP low power LTE long term evolution (4G) MAC medium access control MIB master information block MME mobility management entity MRO mobility robustness optimization NA not applicable NCE network control element ng or NG new generation ng-eNB new generation eNB NG-RAN new generation radio access network NR new radio N/W network OFDM orthogonal frequency division multiplexing PBCH physical broadcast channel PCI physical layer cell ID PDA personal digital assistant PDCP packet data convergence protocol PHY physical layer pos position PSS primary synchronization signal RAM random access memory RAN radio access network RAR random access response RAT radio access technology RB resource block RE resource element RLC radio link control ROM read-only memory RRC radio resource control RSRP reference signal received power RSRQ reference signal received quality

RU radio unit

Rx receiver or reception

SC subcarrier

SCS subcarrier spacing

SDAP service data adaptation protocol

SGW serving gateway

SMF session management function

SON self-organizing/optimizing network ss synchronization signal SSB synchronization signal and PBCH block, or synchronization signal block

SSS secondary synchronization signal

TD time division

TDD time division duplex

TRP transmission reception point

TS technical specification

Tx, TX transmitter or transmission

U uplink (e.g. DDDSU where U indicates an uplink slot)

UAV unmanned aerial vehicle

UE user equipment (e.g., a wireless, typically mobile device)

UI user interface

UL uplink

UPF user plane function

USB universal serial bus wus wake up signal X2 network interface between RAN nodes and between RAN and the core network

Xn network interface between NG-RAN nodes

Claims

CLAIMS What is claimed is:

1. An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

2. The apparatus of claim 1, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: transmit the indication of the synchronization signal pattern within a physical broadcast channel of a synchronization signal block in at least a first slot of a first part of the synchronization signal burst.

3. The apparatus of any of claims 1 to 2, wherein the indication of the synchronization signal pattern indicates a periodicity of the consecutive slots.

4. The apparatus of any of claims 1 to 3, wherein the indication of the synchronization signal pattern indicates a number of slots between a part of the synchronization signal burst and another part of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst.

5. The apparatus of any of claims 1 to 4, wherein the indication of the synchronization signal pattern indicates a set of at least one time division duplex uplink-downlink pattern.

6. The apparatus of claim 5, wherein the synchronization signals are transmitted on the synchronization signal positions indicated by the set of the at least one time division duplex uplink-downlink pattern.

7. The apparatus of any of claims 5 to 6, wherein the set of the at least one time division duplex uplink-downlink pattern is a subset of another set of the at least one time division duplex uplink-downlink pattern.

8. The apparatus of any of claims 5 to 7, wherein a physical broadcast channel provides an index corresponding to the at least one time division duplex uplink-downlink pattern.

9. The apparatus of any of claims 1 to 8, wherein a timing of a cell is based on a first synchronization signal in a slot.

10. The apparatus of any of claims 1 to 9, wherein the synchronization signal pattern is configured to be used with a user equipment to determine a timing of a cell.

11. The apparatus of any of claims 1 to 10, wherein the synchronization signal is a synchronization signal and physical broadcast channel block.

12. An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determine a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

13. The apparatus of claim 12, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: receive the indication of the synchronization signal pattern within a physical broadcast channel of a synchronization signal block in at least a first slot of a first part of the synchronization signal burst.

14. The apparatus of any of claims 12 to 13, wherein the indication of the synchronization signal pattern indicates a periodicity of the consecutive slots.

15. The apparatus of any of claims 12 to 14, wherein the indication of the synchronization signal pattern indicates a number of slots between a part of the synchronization signal burst and another part of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst.

16. The apparatus of any of claims 12 to 15, wherein the indication of the synchronization signal pattern indicates a set of at least one time division duplex uplinkdownlink pattern.

17. The apparatus of claim 16, wherein the synchronization signals are received on synchronization signal positions indicated by the set of the at least one time division duplex uplink-downlink pattern.

18. The apparatus of any of claims 16 to 17, wherein the set of the at least one time division duplex uplink-downlink pattern is a subset of another set of the at least one time division duplex uplink-downlink pattern.

19. The apparatus of any of claims 16 to 18, wherein a physical broadcast channel provides an index corresponding to the at least one time division duplex uplinkdownlink pattern.

20. The apparatus of any of claims 12 to 19, wherein the timing of the cell is determined based on a first synchronization signal in a slot.

21. The apparatus of any of claims 12 to 20, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: receive the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

22. The apparatus of any of claims 12 to 21, wherein the synchronization signal is a synchronization signal and physical broadcast channel block.

23. The apparatus of any of claims 12 to 22, wherein determining the timing comprises determining a slot timing and/or determining a slot index.

24. The apparatus of any of claims 12 to 23, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: perform transmission or reception based on the timing.

25. The apparatus of any of claims 12 to 24, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: use the timing acquired from the synchronization signal to determine timing occasions for downlink (DL) monitoring and uplink (UL) transmission timing occasions.

26. The apparatus of claim 25, wherein the timing is associated with a symbol, slot, or frame.

27. An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: transmit an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmit the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

28. An apparatus comprising: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: receive an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determine a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

29. A method comprising: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

30. A method comprising: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

31. A method comprising: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

32. A method comprising: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

33. An apparatus comprising: means for transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and means for transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

34. An apparatus comprising: means for receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and means for determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

35. An apparatus comprising: means for transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and means for transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

36. An apparatus comprising: means for receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and means for determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.

37. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations comprising: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between the adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

38. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations comprising: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least one of: a number of parts of a synchronization signal burst, wherein each part occupies a number of consecutive slots, the number of consecutive slots in each part of the synchronization signal burst, or the slots between adjacent parts of the synchronization signal burst that are not used for transmitting any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on a respective index of the synchronization signals and the synchronization signal pattern.

39. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations comprising: transmitting an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for transmitting any synchronization signals of the synchronization signal burst; and transmitting the synchronization signals on synchronization signal positions indicated by the synchronization signal pattern.

40. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, the operations comprising: receiving an indication of a synchronization signal pattern; wherein the indication of the synchronization signal pattern indicates at least: a number of consecutive slots in at least a first part of a synchronization signal burst, and a position of a first slot in a second part of the synchronization signal burst; wherein at least one slot between the first part of the synchronization signal burst and the second part of the synchronization signal burst is not used for receiving any synchronization signals of the synchronization signal burst; and determining a timing of a cell based on an index of the synchronization signals and the synchronization signal pattern.