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WO2024247717A1 - Dispositif de commande de mémoire et procédé de commande de mémoire - Google Patents

Dispositif de commande de mémoire et procédé de commande de mémoire Download PDF

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Publication number
WO2024247717A1
WO2024247717A1 PCT/JP2024/017884 JP2024017884W WO2024247717A1 WO 2024247717 A1 WO2024247717 A1 WO 2024247717A1 JP 2024017884 W JP2024017884 W JP 2024017884W WO 2024247717 A1 WO2024247717 A1 WO 2024247717A1
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Prior art keywords
command
data
cas
issuance
read
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English (en)
Japanese (ja)
Inventor
孝博 五十嵐
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

Definitions

  • This disclosure relates to a memory controller and a memory control method.
  • a CAS command is provided as a means of reducing power consumption, taking advantage of the characteristics of the data being transferred to suppress the toggling of the Data Pin or to change the order in which data is transferred (see, for example, Patent Document 1).
  • the CAS command which is used to suppress the toggling of the Data Pin or to change the data transfer order, is restricted to be issued one clock before the WRITE or READ command.
  • the issuance of a CAS command may cause a collision of command issuance requests between different banks, resulting in a decrease in data transfer efficiency. It is desirable to provide a memory controller and a memory control method that can suppress the decrease in data transfer efficiency caused by the use of CAS commands.
  • a first memory controller is capable of controlling access to a DRAM consisting of multiple banks.
  • the first memory controller includes an arbitration unit, a command generation unit, a command scheduler, and a data transmission unit.
  • the arbitration unit is capable of arbitrating the output order of multiple memory access requests related to accepted memory access.
  • the command generation unit is capable of generating a command for the DRAM based on the memory access request output from the arbitration unit.
  • the command scheduler is capable of generating issuance timing information for the command generated by the command generation unit, and issuing the command to the physical layer according to the generated issuance timing information.
  • the data transmission unit is capable of outputting write data corresponding to the generated command to the physical layer in synchronization with the issuance of the command.
  • the data transmission unit when a CAS command is generated in the command generation unit, the data transmission unit is capable of rewriting the write data so that data toggle is reduced, and outputting the rewritten data thus obtained to the physical layer.
  • the command scheduler When a CAS command is generated in the command generation unit, and two commands collide between two banks due to the generation of the CAS command, the command scheduler is capable of determining the priority of the two colliding commands so that a write command corresponding to the two colliding commands can be issued as quickly as possible.
  • the command scheduler is capable of canceling the issuance of the CAS command if a penalty occurs in the write command corresponding to the two colliding commands.
  • the occurrence of a penalty is defined as a penalty occurring in the command of the second bank when the command of the first bank is issued late due to the characteristics of DRAM that cannot issue commands for multiple banks simultaneously, and this delay time is called a penalty.
  • a second memory controller is capable of controlling access to a DRAM consisting of multiple banks.
  • the second memory controller includes an arbitration unit, a command generation unit, a command scheduler, and a data receiving unit.
  • the arbitration unit is capable of arbitrating the output order of multiple memory access requests related to accepted memory access.
  • the command generation unit is capable of generating a command for the DRAM based on the memory access request output from the arbitration unit.
  • the command scheduler is capable of generating issuance timing information for the command generated by the command generation unit, and issuing the command to the physical layer according to the generated issuance timing information.
  • the data receiving unit is capable of acquiring read data obtained from the physical layer in response to the issuance of a command to the physical layer, and outputting the acquired read data.
  • a first memory control method is a method capable of controlling access to a DRAM configured with a plurality of banks.
  • the first memory control method includes the following seven methods. ( ⁇ 1) arbitrating the output order of multiple memory access requests related to the accepted memory access; ( ⁇ 2) generating a command for the DRAM based on the memory access request after output order arbitration; ( ⁇ 3) generating issuance timing information for the generated command and issuing the command to the physical layer according to the generated issuance timing information; ( ⁇ 4) outputting write data corresponding to the generated command to the physical layer in synchronization with the issuance of the command; ( ⁇ 5) when a CAS command is generated, rewriting the write data so as to reduce data toggle, and outputting the rewritten data obtained thereby to the physical layer; ( ⁇ 6) when a CAS command is generated and two commands collide between two banks due to the generation of the CAS command, determining the priority of the two colliding commands so that the write command corresponding to the two colliding commands can be issued as quickly as possible; ( ⁇ 7) cancel
  • a second memory control method is a method capable of controlling access to a DRAM configured with a plurality of banks.
  • FIG. 1 is a diagram showing an example of a truth table for a CAS command during writing.
  • Figure 2 shows an example of a timing diagram of the Data Pin when a write command with a CAS command is issued.
  • FIG. 3 is a diagram showing an example of a burst sequence during reading.
  • FIG. 4 is a diagram illustrating an example of functional blocks of a SoC including a memory controller according to an embodiment of the present disclosure.
  • FIG. 5 is a diagram for explaining condition 1 for canceling the issuance of a CAS command.
  • FIG. 6 is a diagram for explaining condition 2 for canceling the issuance of a CAS command.
  • FIG. 7 is a diagram showing an example of a procedure for canceling the issuance of a CAS command during writing.
  • FIG. 8 is a diagram showing an example of a procedure for rewriting read data during reading.
  • FIG. 9 is a diagram illustrating a modification of the functional blocks of the memory controller of FIG.
  • SDRAMs synchronous dynamic random access memories
  • DRAMs DRAMs that operate in synchronization with a clock signal, and are often composed of multiple banks.
  • LPDDR5 and LPDDR5X provide a CAS command that utilizes the properties of the data being transferred to suppress the toggling of the Data Pin or to change the order in which data is transferred, as a means of reducing power consumption.
  • Figure 1 shows an example of a truth table for a CAS command.
  • the command is a CAS command.
  • “CA0, CA1, CA2, CA3” in the DDR command PIN at the falling edge of the clock are “DC0, DC1, DC2, DC3” (data copy) ( ⁇ 1 in Figure 1).
  • “CA6” in the DDR command PIN at the falling edge of the clock is "B3” (the third bit of the burst address) ( ⁇ 2 in Figure 1).
  • DC0 is applied to the first 8 beats in BL16 or BL32.
  • DC1 is applied to the second 8 beats in BL16 or BL32.
  • DC2 is applied to the third 8 beats in BL32.
  • DC3 is applied to the fourth 8 beats in BL32.
  • Figure 2 shows an example of a timing diagram of the Data Pin when a write command with a CAS command is issued.
  • two ⁇ CAS>s are lined up because one corresponds to the rising edge of the clock and the other corresponds to the falling edge of the clock.
  • the two ⁇ CAS>s are collectively represented as a single ⁇ CAS>.
  • two ⁇ WR>s are lined up because one corresponds to the rising edge of the clock and the other corresponds to the falling edge of the clock.
  • the two ⁇ WR>s are collectively represented as a single ⁇ WR>.
  • Figure 3 shows an example of a burst sequence during a read.
  • data read from the DRAM in the normal order (first read data) is output from the physical layer.
  • the CAS command which is used to suppress the toggling of the Data Pin or to change the data transfer order, is restricted to be issued one clock before the WRITE or READ command.
  • the issuance of a CAS command may cause a collision of command issuance requests between different banks, resulting in a decrease in data transfer efficiency. Therefore, the inventor of the present application will explain below possible measures to suppress the decrease in data transfer efficiency caused by the use of CAS commands.
  • FIG. 4 illustrates an example of a schematic configuration of an information processing system including a SoC (System on a chip) 1 including a memory controller 20 according to an embodiment of the present disclosure.
  • the information processing system includes, for example, a SoC 1 including the memory controller 20 and a PHY 30, a plurality of initiators 10, and a DRAM 40.
  • the memory controller 20 corresponds to a specific example of a "memory controller" in the present disclosure.
  • PHY 30 is a PHY that complies with LPDDR5 or LPDDR5X.
  • DRAM 40 is a DRAM that complies with LPDDR5 or LPDDR5X.
  • DRAM 40 for example, has multiple bank groups defined. Each bank group, for example, has multiple banks defined.
  • the multiple initiators 10 are capable of writing and reading data to and from the DRAM 40 via the SoC 1.
  • Each initiator 10 is, for example, a central processing unit (CPU) or a functional block.
  • Each initiator 10 is capable of issuing a memory access request to write or read data to the DRAM 40 and outputting it to the memory controller 20.
  • This memory access request includes, for example, a logical address in a virtual memory area assigned to each initiator 10, a BL length which is the length of the data to be accessed, identification information for identifying the initiator 10, and a transfer direction.
  • the transfer direction here indicates whether it is a write request to write data or a read request to read data.
  • Each initiator 10 is capable of outputting write data to be written to the DRAM 40 to the memory controller 20 in accordance with a data output instruction from the memory controller 20.
  • Each initiator 10 is capable of communicating with the memory controller 20 using, for example, a protocol defined in AMBA (Advanced Microcontroller Bus Architecture) (for example, the AXI (Advanced eXtensible Interface) protocol).
  • AMBA Advanced Microcontroller Bus Architecture
  • AXI Advanced eXtensible Interface
  • the memory controller 20 includes a command arbitration unit 21, as shown in FIG. 1, for example.
  • the command arbitration unit 21 corresponds to a specific example of the "arbitration unit" of this disclosure.
  • the memory controller 20 communicates with each initiator 10 and is capable of receiving a memory access request from each initiator 10.
  • the memory access request is, for example, a write request or a read request.
  • the memory controller 20 controls a write operation to the DRAM 40 or a read operation from the DRAM 40 based on the received memory access request.
  • the memory controller 20 When the memory controller 20 receives a write request from the initiator 10, it is capable of receiving further data to be written from the initiator 10.
  • the memory controller 20 is capable of issuing a write command to the DRAM 40 and transmitting the data received from the initiator 10 to the DRAM 40.
  • the DRAM 40 is capable of writing the data received from the memory controller 20 to its internal memory cell array.
  • the memory controller 20 When the memory controller 20 receives a read request from the initiator 10, it is capable of issuing a read command and sending it to the DRAM 40.
  • the DRAM 40 is capable of reading data from the memory cell array in response to the read command and sending the read data to the memory controller 20.
  • the memory controller 20 is capable of sending the data received from the DRAM 40 to the initiator 10.
  • the memory controller 20 converts the logical address included in the memory access request output from the initiator 10 into a physical address corresponding to the DRAM 40.
  • the physical address here refers to an address that indicates the bank, row, and column that make up the DRAM 40, and refers to a bank address, row address, and column address.
  • the command arbitration unit 21 is capable of arbitrating the output order of multiple memory access requests obtained from multiple initiators 10.
  • the command arbitration unit 21 performs arbitration based on the physical addresses indicated in the multiple memory access requests obtained from the multiple initiators 10.
  • the command arbitration unit 21 is capable of outputting the multiple memory access requests to the FIFO 22 after arbitration based on the arbitration results.
  • the command arbitration unit 21 obtains read data from the data FIFO 22C, it is capable of outputting the obtained read data to the initiator 10 that originated the read request.
  • the memory controller 20 further includes a FIFO (First-In First-Out) 22, a command generation unit 23, a DQ[7-1, 15-9] generation unit 24, a command scheduler 25, and a data transmission/reception unit 26.
  • the command generation unit 23 corresponds to a specific example of a "command generation unit” in the present disclosure.
  • the DQ[7-1, 15-9] generation unit 24 corresponds to a specific example of a "rewrite data generation unit” in the present disclosure.
  • the command scheduler 25 corresponds to a specific example of a "command scheduler” in the present disclosure.
  • the data transmission/reception unit 26 corresponds to a specific example of a "data transmission/reception unit” in the present disclosure.
  • the post-arbitration FIFO 22 has, for example, a request FIFO 22A, a data FIFO 22B, and a data FIFO 22C, as shown in FIG. 4.
  • the request FIFO 22A is a memory element that stores memory access requests received from the initiator 10 via the command arbitration unit 21.
  • the request FIFO 22A stores multiple memory access requests in the order in which they are received, and when a new memory access request is stored in the request FIFO 22A, it is possible to output the memory access request that was stored the oldest to the command generation unit 23.
  • the data FIFO 22B is a memory element that stores write data received from the initiator 10 via the command arbitration unit 21.
  • the data FIFO 22B stores multiple pieces of write data in the order in which they are received, and when new write data is stored in the data FIFO 22B, it is possible to output the oldest stored write data to the command generation unit 23, the DQ1-7 generation unit 24, and the data transmission unit 26A.
  • the data FIFO 22C is a memory element in which read data received from the DRAM 40 via the data receiving unit 26B described below is stored.
  • the data FIFO 22C stores multiple read data in the order in which they are received, and when new read data is stored in the data FIFO 22C, it is possible to output the oldest read data stored to the command arbitration unit 21.
  • the command generation unit 23 includes, for example, an ACT/PRE command generation unit 23A, a W/R command generation unit 23B, and a CAS command generation unit 23C.
  • the ACT/PRE command generation unit 23A is capable of generating an ACT command (Active command) and a PRE command (Precharge command) based on the memory access request received from the request FIFO 22A, and outputting them to the command scheduler 25.
  • the W/R command generation unit 23B is capable of generating a WR command (Write command) or an RD command (Read command) based on the memory access request received from the request FIFO 22A, and outputting them to the command scheduler 25.
  • CAS command generation unit 23C When write data is input from data FIFO 22B, CAS command generation unit 23C is capable of generating a CAS command based on the memory access request input from request FIFO 22A and the write data input from data FIFO 22B, and outputting the CAS command to command scheduler 25. When write data is not input from data FIFO 22B, CAS command generation unit 23C is capable of generating a CAS command based on the memory access request input from request FIFO 22A, and outputting the CAS command to command scheduler 25.
  • the DQ[7-1,15-9] generation unit 24 is capable of generating rewrite data for a portion of the write data that is to be rewritten to reduce data toggle.
  • the DQ[7-1,15-9] generation unit 24 is capable of generating data of "0" as data for rewriting the data in DQ[7-1] and outputting this to the data transmission unit 26A.
  • the DQ[7-1,15-9] generation unit 24 is capable of generating data of "0" as data for rewriting the data in DQ[15-9] and outputting this to the data transmission unit 26A.
  • the command scheduler 25 is capable of controlling the timing of issuing various commands to the DRAM 50 based on the various commands input from the command generation unit 23.
  • the command scheduler 25 is capable of generating issuance timing information for the various commands input from the command generation unit 23, and issuing the various commands to the PHY 30 according to the generated issuance timing information.
  • the command scheduler 25 is capable of canceling the issuance of the CAS command generated by the CAS command generation unit 23C to the PHY 30. In other words, even if a CAS command is generated by the CAS command generation unit 23C, the command scheduler 25 is capable of canceling the issuance of the CAS command to the PHY 30.
  • Condition A A CAS command is generated in the command generating unit 23C, and two commands collide between two banks due to the generation of the CAS command.
  • Condition B When condition A is satisfied, the priorities of the two colliding commands are determined so that a write command corresponding to the two colliding commands can be issued as quickly as possible, and the two colliding commands are issued at a timing determined according to the determined priorities, causing a penalty to occur to the write commands corresponding to the two colliding commands.
  • the command scheduler 25 is capable of generating a flag capable of identifying whether or not the CAS command generated in the CAS command generating unit 23C has been issued to the PHY 30, and outputting the flag to the data transmitting/receiving unit 26.
  • the conditions (conditions A and B) for determining whether or not to cancel the issuance of the CAS command generated in the CAS command generating unit 23C to the PHY 30 will be explained using Figures 5(A), 5(B), 5(C), 6(A), 6(B), 6(C), and 6(D).
  • FIG. 5A, 5B, and 5C are diagrams for explaining condition A for canceling the issuance of a CAS command.
  • Condition A is illustrated in FIG. 5A.
  • FIG. 5A illustrates a state in which two commands (CAS command, ACT2 command (Active command)) collide between two banks due to the generation of a CAS command.
  • FIG. 5B illustrates a state in which the ACT2 command of bank1 is delayed by one clock immediately after the WR command of bank0 in order to avoid the satisfaction of condition A.
  • FIG. 5C illustrates a state in which the CAS command, WR command (write command), CAS command, and WR command of bank0 are delayed by one clock in order to avoid the satisfaction of condition A.
  • the command scheduler 25 is capable of determining the priority of two conflicting commands so that the write commands corresponding to the two conflicting commands (WR1 and WR2 in FIG. 5(A)) can be issued as quickly as possible.
  • the command scheduler 25 is capable of prioritizing ACT2 of bank1 and delaying the CAS command, WR command, CAS command, and WR command of bank0 by one clock as shown in FIG. 5(C).
  • FIG. 6A, 6B, 6C, and 6D are diagrams for explaining condition B for canceling the issuance of a CAS command.
  • Condition A is illustrated in FIG. 6A.
  • FIG. 6A illustrates a state in which two commands (CAS command, ACT2 command) collide between two banks due to the generation of a CAS command.
  • FIG. 6B illustrates a state in which a penalty occurs as a result of delaying ACT2 of bank1 to immediately after the WR command of bank0 by one clock in order to avoid satisfying condition A.
  • FIG. 6C illustrates a state in which a penalty occurs as a result of delaying the CAS command, WR command, CAS command, WR command, CAS command, and WR command of bank0 by one clock in order to avoid satisfying condition A. It can be seen from Fig. 6(B) and Fig. 6(C) that a penalty occurs when the collision avoidance shown in Fig. 6(C) is performed and when the collision avoidance shown in Fig. 6(B) is performed.
  • Fig. 6(C) illustrates an example in which a penalty occurs in the write commands corresponding to two conflicting commands when ACT2 in bank1 is prioritized and the CAS command in bank0 is delayed (when two conflicting commands are issued at a timing determined according to the priority). That is, Fig. 6(C) illustrates condition B.
  • FIG. 6(D) illustrates an example in which a penalty no longer occurs as a result of the issuance of a CAS command being canceled. Note that when the issuance of a CAS command is canceled, the write data obtained from data FIFO 22B is output to PHY 30 as is. In other words, suppressing the occurrence of a penalty takes priority over suppressing the toggling of the Data Pin.
  • the data receiver/transmitter 26 has, for example, a data transmitter 26A and a data receiver 26B, as shown in FIG. 2.
  • the data transmission unit 26A is capable of outputting write data corresponding to a command accepted by the memory controller 20 to the PHY 30 in synchronization with the issuance of the command.
  • the data transmission unit 26A is capable of rewriting the write data so as to reduce data toggling, and outputting the rewritten data thus obtained to the PHY 30.
  • the data transmission unit 26A is capable of outputting the original write data to the PHY 30.
  • the data transmission unit 26A When a CAS command is issued in the command scheduler 25, the data transmission unit 26A is capable of rewriting the portion of the write data to be rewritten with the rewrite data and outputting the rewritten write data to the PHY 30. For example, when a CAS command is issued in the command scheduler 25, the data transmission unit 26A is capable of replacing the data DQ[7-1] and DQ[15-9] of the write data obtained from the data FIFO 22B with data of "0" generated by the DQ[7-1, 15-9] generation unit 24.
  • the data transmission unit 26A is capable of outputting the write data as is to the PHY 30.
  • the data transmission unit 26A is capable of outputting the write data obtained from the data FIFO 22B as is to the PHY 30.
  • the data receiving unit 26B is capable of acquiring read data from the PHY 30 in response to the issuance of a command to the PHY 30, and outputting the acquired read data to the data FIFO 22C.
  • the data receiving unit 26B is capable of reading read data from the DRAM 50 in synchronization with the issuance of a command.
  • the data receiving unit 26B may be capable of, for example, generating new read data including the necessary data at the time when the necessary data of the second read data is obtained from the PHY 30, without waiting for the remaining data of the second read data to be obtained from the PHY 30, and outputting the new read data to the data FIFO 22C.
  • the data receiving unit 26B may be capable of, for example, preparing dummy data in advance, and outputting the generated read data by adding the necessary data after the dummy data to the data FIFO 22C.
  • the data receiving unit 26B may be capable of, for example, outputting only the necessary data to the data FIFO 22C.
  • PHY 30 is a physical layer. PHY 30 is capable of outputting commands supplied in synchronization with the operating clock of memory controller 20 and write data input from data transmission unit 26A of memory controller 20 based on the memory clock of DRAM 40. PHY 30 is also capable of outputting data read in synchronization with the memory clock of DRAM 40 to data reception unit 26B in synchronization with the operating clock of memory controller 20.
  • Fig. 7 shows an example of a procedure for canceling the issuance of a CAS command during a write.
  • the memory controller 20 receives memory access requests from multiple initiators 10. At this time, the memory controller 20 arbitrates the multiple memory access requests it receives (step S101). The memory controller 20 stores the multiple memory access requests in the request FIFO 22A in the arbitrated order, and stores the write data in the data FIFO 22B in the arbitrated order. The memory controller 20 generates various commands based on the memory access requests received from the request FIFO 22A (step S102). At this time, the memory controller 20 determines whether or not it is necessary to generate a CAS command (step S103).
  • the memory controller 20 controls the timing of issuing various commands to the DRAM 50 based on the various commands including the CAS command. At this time, the memory controller 20 determines whether the timing of issuing two commands between different banks satisfies condition A (step S104). If the timing of issuing two commands between different banks satisfies condition A (step S104; Y), the memory controller 20 determines the priority of the two commands that satisfy condition A (step S105). The memory controller 20 further determines whether the timing of issuing various commands satisfies condition B (step S106). If the timing of issuing various commands satisfies condition B (step S106; Y), the memory controller 20 cancels the issuance of the CAS command (step S107).
  • step S103 if it is not necessary to generate a CAS command (step S103; N) (2)
  • step S104 the timing of issuing two commands between different banks does not satisfy condition A (step S104; N)
  • step S106 the timing of issuing various commands does not satisfy condition B (step S104; N) (4)
  • step S107 When the issuance of the CAS command is canceled in step S107.
  • Fig. 8 shows an example of a procedure for rewriting read data during reading.
  • the memory controller 20 receives memory access requests from multiple initiators 10. At this time, the memory controller 20 arbitrates the multiple memory access requests it receives (step S201). The memory controller 20 stores the multiple memory access requests in the request FIFO 22A in the order in which they were arbitrated. The memory controller 20 generates various commands based on the memory access requests received from the request FIFO 22A (step S202). At this time, the memory controller 20 determines whether or not it is necessary to generate a CAS command (step S203).
  • a CAS command is provided as a means of reducing power consumption, taking advantage of the properties of the data being transferred to suppress the toggling of the Data Pin or to change the order of data transfer.
  • the CAS command for suppressing the toggling of the Data Pin or to change the order of data transfer is restricted to being issued one clock before a WRITE or READ command.
  • the issuance of a CAS command can cause a collision of command issuance requests between different banks, reducing data transfer efficiency.
  • the portion of the write data to be rewritten in order to reduce data toggling is rewritten with rewrite data, and the rewritten write data is output to the PHY 30.
  • the write data is output to the PHY 30 as is. This makes it possible to suppress a decrease in data transfer efficiency caused by the use of a CAS command.
  • Modifications 9 shows a modified example of the schematic configuration of the information processing system according to the above embodiment.
  • the information processing system further includes a flag register 27 in addition to the information processing system according to the above embodiment, as shown in FIG.
  • the flag register 27 is a memory element that stores a flag that externally instructs the command scheduler 25 whether or not to execute a series of procedures for determining whether the above-mentioned conditions A and B are met. The above-mentioned flags are set externally in the flag register 27.
  • the command scheduler 25 for example, after executing step S103 in FIG. 7, checks the flag stored in the flag register 27, and is thereby able to determine whether or not to determine whether the above-mentioned conditions A and B are met. In this way, it becomes possible to execute the CAS command regardless of whether the above-mentioned conditions A and B are met.
  • a memory controller capable of controlling access to a dynamic random access memory (DRAM) composed of a plurality of banks, comprising: an arbitration unit capable of arbitrating an output order of a plurality of memory access requests regarding the received memory access; a command generating unit capable of generating a command for the DRAM based on the memory access request output from the arbitration unit; a command scheduler that generates issuance timing information for the command generated by the command generation unit and issues the command to a physical layer in accordance with the generated issuance timing information; a data transmission unit capable of outputting the generated write data corresponding to the command to the physical layer in synchronization with issuance of the command; the data transmission unit is capable of rewriting the write data so as to reduce data toggle when a CAS command is generated by the command generation unit, and outputting the rewritten data obtained thereby to the physical layer; the command scheduler is capable of determining priorities of the two conflicting commands so that, when the CAS command is generated in the command generating unit
  • a rewrite data generating unit capable of generating rewrite data for a portion of the write data to be rewritten in order to reduce data toggle; when the CAS command is issued by the command scheduler, the data transmission unit is capable of rewriting the portion of the write data to be rewritten with the rewrite data and outputting the rewritten write data to the physical layer;
  • the memory controller according to claim 2 wherein the data transmission unit is capable of outputting the write data as is to the physical layer when the issuance of the CAS command is canceled in the command scheduler.
  • a memory control method in a memory controller capable of controlling access to a DRAM (Dynamic Random Access Memory) composed of a plurality of banks comprising: Arbitrating an output order of a plurality of memory access requests related to the accepted memory access; generating a command for the DRAM based on the memory access request after output order arbitration; generating issuance timing information for the generated command, and issuing the command to a physical layer in accordance with the generated issuance timing information; outputting the generated write data corresponding to the command to the physical layer in synchronization with issuance of the command; and if a CAS command is generated, rewriting the write data so that data toggle is reduced, and outputting the rewritten data obtained thereby to the physical layer;
  • the CAS command is generated and two commands collide between the two banks due to the generation of the CAS command, determining priorities of the two colliding commands so that a write command corresponding to the two colliding commands can be issued as quickly as possible; canceling issuance of the CAS command if a penalty occurs to
  • DRAM dynamic random access memory

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Abstract

L'invention concerne un dispositif de commande de mémoire selon un mode de réalisation de la présente divulgation, lorsqu'une commande CAS est générée et deux commandes entrent en collision entre deux banques en raison de la génération de la commande CAS, un planificateur de commandes peut déterminer les priorités des deux commandes en collision de telle sorte que des commandes d'écriture correspondant aux deux commandes en collision peuvent être émises aussi rapidement que possible. Lorsque deux commandes en collision sont émises à un moment déterminé en fonction des priorités, le planificateur de commandes peut annuler l'émission d'une commande CAS si une pénalité se produit dans les commandes d'écriture correspondant aux deux commandes en collision.
PCT/JP2024/017884 2023-05-31 2024-05-15 Dispositif de commande de mémoire et procédé de commande de mémoire Pending WO2024247717A1 (fr)

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