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WO2024132658A1 - Module de puissance - Google Patents

Module de puissance Download PDF

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Publication number
WO2024132658A1
WO2024132658A1 PCT/EP2023/085241 EP2023085241W WO2024132658A1 WO 2024132658 A1 WO2024132658 A1 WO 2024132658A1 EP 2023085241 W EP2023085241 W EP 2023085241W WO 2024132658 A1 WO2024132658 A1 WO 2024132658A1
Authority
WO
WIPO (PCT)
Prior art keywords
low current
power module
axis
current connections
semiconductor switches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2023/085241
Other languages
English (en)
Inventor
Tim RETTMANN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron Danfoss GmbH
Original Assignee
Semikron Danfoss GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron Danfoss GmbH filed Critical Semikron Danfoss GmbH
Publication of WO2024132658A1 publication Critical patent/WO2024132658A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

Definitions

  • the present invention relates to a power module comprising a package constituting a housing, wherein the power module comprises at least one metallisation layer onto which a plurality of semiconductor switches are arranged, wherein the metallisation layer comprises conductive tracks forming a plurality of power tracks and low current tracks for the semiconductor switches, wherein the housing comprises a surface portion provided above the semiconductor switches, wherein one or more low current connections are electrically connected to each of the semiconductor switches.
  • Power modules are used for power conversion equipment in energy (e.g. in inverters for renewable energies as wind turbines, solar power panels, tidal power plants and electric vehicles), industrial and e- mobility applications including industrial motor drives, embedded motor drives, uninterruptible power supplies and AC-DC power supplies.
  • energy e.g. in inverters for renewable energies as wind turbines, solar power panels, tidal power plants and electric vehicles
  • industrial and e- mobility applications including industrial motor drives, embedded motor drives, uninterruptible power supplies and AC-DC power supplies.
  • the power module according to the invention is a power module comprising:
  • the metallisation layer comprises conductive tracks forming a plurality of power tracks and low current tracks for the semiconductor switches
  • the housing comprises a surface portion provided above the semiconductor switches, wherein one or more low current connections are electrically connected to each of the semiconductor switches, wherein the low current connections extend from the metallisation layer through the surface portion and protrudes therefrom, characterised in that the low current connections are grouped in connection blocks.
  • the power module comprises a package constituting a housing.
  • the package is a molded package.
  • the at least one metallisation area may be a power electronic substrate.
  • the metallisation area is formed from a copper layer of a direct bonded copper (DBC) substrate.
  • DBC direct bonded copper
  • the metallisation layer comprises conductive tracks forming a plurality of power tracks and low current tracks for the semiconductor switches.
  • the housing comprises a surface portion provided above the semiconductor switches.
  • One or more low current connections are electrically connected to each of the semiconductor switches.
  • the low current connections extend from the metallisation layer through the surface portion and protrudes therefrom.
  • connection blocks The low current connections are grouped in connection blocks. Hereby, a compact construction can be achieved.
  • two low current connections low current connections are electrically connected to each of the semiconductor switches.
  • the power module comprises a baseplate, wherein at least one metallisation layer is thermal contact with the baseplate.
  • each semiconductor switch has a first low current connection (connected to the gate pad of the semiconductor switch) and a second low current connection (a "Kelvin connection” or “sense connection”) connected to the source pad of the semiconductor switch.
  • the low current connections are connections that should be distinguished from the high current connections of the power module by the fact that they are not required to carry the high currents that are switched by the semiconductors of the power module, but only the low currents needed to activate the switching through control of the gate pads of the semiconductors or, in the case of the sense connections, allow monitoring of the voltage present at the source pad of the respective semiconductors.
  • a source pad is arranged on the top of the semiconductor switch, wherein the bottom surface of the semiconductor switch constitutes the emitter connection, through which the semiconductor switch it is connected to the power track on which it is positioned.
  • the source and emitter connections conduct the high current that is controlled via the gate connections.
  • each connection block contains two or more low current connections.
  • each connection block contains three or more low current connections.
  • each connection block contains four or more low current connections.
  • each connection block contains four low current connections arranged in a square configuration (one control connection in each corner of a square).
  • each connection block contains two parallel plateshaped low current connections.
  • the semiconductor switches are arranged along a single row extending along a first axis.
  • the parallel plate-shaped low current connections extend perpendicular to and are spaced from each other along the first axis. In an embodiment, the parallel plate-shaped low current connections of each semiconductor switch extend parallel the first axis and are spaced from each other along a second axis extending perpendicular to the first axis.
  • two adjacent semiconductor switches share the same parallel plate-shaped low current connections (see Fig. 4A).
  • the parallel plate-shaped low current connections of each semiconductor switch extend parallel the first axis and are spaced from each other along a second axis extending perpendicular to the first axis.
  • the low current connections are grouped in blocks with two connections constituting a coaxial structure comprising a hollow cylindrical member) that at least partly surrounds an inner centrally arranged rod member.
  • each low current connection is placed on a conductive track, wherein a wire bond connects each low current connection with the corresponding semiconductor switch.
  • the power module comprises:
  • phase output power terminal protruding from the opposite side of the housing.
  • the semiconductor switches are silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the semiconductor switches are silicon MOSFETs.
  • the semiconductor switches are gallium nitride (GaN) field-effect transistors (FETs)
  • the semiconductor switches are insulated-gate bipolar transistors (IGBTs).
  • the invention significantly improves the overall switching performance of the power module and increase the power density, especially for molded power modules using current lead frame technology.
  • the switching conditions for each switch are equalized and the gate voltages may be kept in the safe operating area during switching.
  • the overall space on the substrate (such as a DOB substrate) will be increased, because fewer gate tracks and gate resistors are required within the housing.
  • the invention brings each gate connection to the top side of the power module via the shortest path.
  • a plurality of semiconductor power modules may be connected in parallel via a printed circuit board (PCB).
  • the internal gate resistor (if required, although the flexibility allowed by this invention reduces the need for individual gate resistors) may be mounted on this external PCB.
  • the invention enables improved high-efficiency switching properties of power semiconductor devices (including Silicon Carbide (SiC) and Gallium Nitride (GaN) power semiconductor devices).
  • SiC Silicon Carbide
  • GaN Gallium Nitride
  • the invention enables that: the switching speed can be increased without compromising the safe operating area of the semiconductor switch; any resonant effects may be suppressed; the gate current can be increased by a factor of approximately 1.4 in order to reduce the delay time of the switching and to charge the Miller capacitance faster; the switching losses can be reduced significantly: the acceleration effects caused by magnetic effects can be suppressed; if additional gate resistors are needed, these components can be placed on the PCB as a standard chip resistor, which is cheaper, requires less tolerance and offers design freedom since a larger range of resistor values are available; the gate inductance can be reduced by factor six or more for each topology semiconductor switch; each top contact will most likely have a gate inductance of approximately 20 nH which can bring the overall gate inductance down to approximately 3.4 nH.
  • the invention makes it possible to keep the gate signals in the safe operating area in the molded power modules using the technology of today.
  • the invention makes it possible to reduce the gate inductance without adding additional parts.
  • Fig. 1 shows a power module according to the invention
  • Fig. 2 shows another view of the power module according to the invention
  • Fig. 3A shows components of a power module according to the invention
  • Fig. 3B shows components of another power module according to the invention
  • Fig. 4A shows components of a further power module according to the invention
  • Fig. 4B shows components of a power module according to the invention
  • Fig. 5 shows components of a power module according to the invention
  • Fig. 6A shows components of a power module according to the invention
  • Fig. 6B shows components of a power module according to the invention
  • Fig. 6C shows a cross-sectional view of a portion of the components shown in Fig. 6B.
  • a power module 2 of the present invention is illustrated in Fig. 1.
  • Fig. 1 is a schematic top view of a power module 2 according to the invention.
  • the power module 2 comprises a plurality of semiconductor switches 6 each being placed on a metallisation layer.
  • the metallisation layer may form part of a substrate, such as a direct copper bonded (DCB) substrate.
  • the schematic view of the power module 2 shown in Fig. 1 shows the placement of the semiconductor switches 6 on the tracks formed in the metallisation layer, and some of the connections between those switches 6 and the low current connections 4, 4', 4", 4"'.
  • the connections between the semiconductor switches 6 and the power tracks 46, 48, 50, 52 which in combination form the topology of a half bridge, are not shown.
  • Each semiconductor switch 6 is electrically connected to a connection assembly 14 by means of two wire bonds 12.
  • One of the two wire bonds 12 is electrically connected to a first conductive track 10.
  • the other wire bond is electrically connected to a second conductive track 8.
  • the semiconductor switches 6 are arranged in pairs along rows in such a manner that the semiconductor switches 6 of each pair are electrically connected to the same connection assembly 14.
  • the rows extend along the X axis that extends parallel to the longitudinal axis of the power module 2.
  • a plurality of low current connections 4, 4', 4", 4"' protrude from each connection assembly 14.
  • the low current connections 4, 4', 4", 4"' extend perpendicular to a X-Y plane of the power module 2 (spanned by the X and Y axes indicated).
  • the semiconductor switches 6 extend along the same X-Y plane.
  • the power module 2 comprises a central power track 52 that is electrically connected to a positive terminal 20 protruding from the housing.
  • the positive terminal 20 is provided with a hole 24.
  • the central power track 52 is arranged between two lateral power tracks 46, 48 that are connected to two negative DC terminals 16, 18. These terminals 16, 18 are each provided with a hole 24.
  • An intermediate power track 50 is arranged between two lateral power tracks 46, 48 and the central power track 52. The intermediate power track 50 is electrically connected to a phase terminal 22 provided with a hole 24.
  • the semiconductor switches 6 are arranged in a symmetric manner. Six semiconductor switches 6 are arranged at each lateral side of the intermediate power track 50. These semiconductor switches are electrically connected to laterally arranged connection assemblies 14 relative in a central space provided between the lateral sides of the basically U-shaped central power track 52.
  • Six semiconductor switches 6 are arranged at each lateral side of the central power track 52. These semiconductor switches are electrically connected to laterally arranged connection assemblies 14.
  • At least one of the one or more metallisation areas is in thermal contact with a baseplate.
  • Fig. 2 illustrates another view of the power module 2 according to the invention.
  • the power module 2 corresponds to the one shown in Fig. 1.
  • the power module 2 comprises a molded package constituting a housing 30.
  • the housing 30 is box shaped.
  • the housing 30 comprises a surface portion 26 provided above the semiconductor switches (see Fig. 1).
  • a plurality of low current connections 4, 4', 4", 4"' are electrically connected to each of the semiconductor switches (see Fig. 1).
  • the low current connections 4, 4', 4", 4"' extend from the metallisation layer (see Fig. 1) through the surface portion 26 and protrude therefrom.
  • the low current connections 4, 4', 4", 4"' are grouped in connection blocks 28.
  • the low current connections 4, 4', 4", 4"' are suitable for controlling the gates of the semiconductor switches 6 and for passing sensing signals.
  • Fig. 3A illustrates components 32 of a power module according to the invention.
  • the components 32 include a substrate 34 upon which a first semiconductor switch 6 and a second semiconductor switch 6' are placed.
  • the substrate 34 may be a direct copper bonding (DCB) substrate.
  • DCB direct copper bonding
  • the first semiconductor switch 6 comprises a source pad 42 and a gate pad 44.
  • a first wire bond 12 electrically connects the source pad 42 to a first conductive track 10.
  • a second wire bond electrically connects the gate pad 44 to a second conductive track 8.
  • the first conductive track 10 and the second conductive track 8 are electrically connected to a first and second low current connection 4, 4', respectively.
  • the second semiconductor switch 6' comprises a source pad 42' and a gate pad 44'.
  • a wire bond 12' electrically connects the source pad 42' to a third conductive track 10', while another wire bond electrically connects the gate pad 44' to a fourth conductive track 8'.
  • the third conductive track 10' and the fourth conductive track 8' are electrically connected to a third and fourth low current connection 4'", 4", respectively.
  • the low current connections 4, 4', 4", 4'" are kept in place by a holding member 56.
  • the low current connections 4, 4', 4", 4'" extend along the Z axis of the coordinate system indicated next to the substrate 34.
  • the substrate 34 is planar and extends along a plane spanned by the X axis and the Y axis.
  • the low current connections 4, 4', 4", 4"' comprise a foot portion that is attached to the corresponding conductive tracks 10, 8, 8', 10'.
  • This construction enables signal to go directly to the top side of the power module without any internal interconnection to other semiconductor switches which may be required for mass paralleling.
  • Fig. 3B illustrates components 32 of another power module according to the invention.
  • the components 32 include a substrate 34 and two semiconductor switches 6, 6' like the ones shown in Fig. 3A.
  • the first semiconductor switch 6 is provided with a source pad 42 and a gate pad 44 and a first wire bond 12 electrically connects the source pad 42 to a first conductive track 10.
  • a second wire bond electrically connects the gate pad 44 to a second conductive track 8.
  • the first conductive track 10 and the second conductive track 8 are electrically connected to a first and second low current connection 4', 4, respectively.
  • the second semiconductor switch 6' is provided with a source pad 42' and a gate pad 44' and a wire bond 12' electrically connects the source pad 42' to a third conductive track 10'. Another wire bond electrically connects the gate pad 44' to a fourth conductive track 8'.
  • the third conductive track 10' and the fourth conductive track 8' are electrically connected a third and fourth low current connection 4'", 4", respectively.
  • the low current connections 4, 4', 4", 4'" are shaped as plates arranged in pairs extending parallel to each other.
  • the plates are parallel to the plane spanned by the Y axis and the Z axis.
  • the substrate 34 is planar and extends along a plane spanned by the X axis and the Y axis.
  • the conductive tracks 8, 8, 10, 10' extend along the same plane as the substrate 34.
  • Fig. 4A illustrates components of a further power module according to the invention.
  • the components include a substrate 34 and two semiconductor switches 6, 6' like the ones shown in Fig. 3A and in Fig. 3B.
  • the first semiconductor switch 6 is provided with a source pad 42 and a gate pad 44 and a first wire bond 12 electrically connects the source pad 42 of the first semiconductor switch 6 to a first conductive track 10. Another wire bond electrically connects the gate pad 44 of the first semiconductor switch 6 to a second conductive track 8.
  • a third wire bond 12' electrically connects the source pad 42' of the second semiconductor switch 6' to a third conductive track 10' that is electrically connected to the first conductive track 10.
  • a fourth wire bond electrically connects the gate pad 44' of the second semiconductor switch 6' to a fourth conductive track 8' that is electrically connected to the second conductive track 8.
  • the conductive tracks 8, 8', 10, 10' are thus electrically connected to the corresponding low current connections 4', 4', 4 and 4 respectively.
  • the low current connections 4, 4' are formed as two parallel plates. Each plate is basically rectangular and comprises a cut-away portion centrally arranged at the edge of the plate.
  • Fig. 4B illustrates components of a power module according to the invention.
  • the components include a substrate 34 and two semiconductor switches 6, 6' that basically corresponds to the ones shown in Fig. 3A.
  • the first semiconductor switch 6 is provided with a source pad 42 and a gate pad 44.
  • a first low current connection 4 protrudes from and is electrically connected to the gate pad 44.
  • a second low current connection 4' extends parallel to the first low current connection 4.
  • the second low current connection 4' protrudes from and is electrically connected to the source pad 42.
  • the second semiconductor switch 6' is provided with a source pad 42' and a gate pad 44'.
  • a third low current connection 4'" protrudes from and is electrically connected to the gate pad 44'.
  • a fourth low current connection 4" extends parallel to the third low current connection 4'". The fourth low current connection 4" protrudes from and is electrically connected to the source pad 42'.
  • Fig. 5 illustrates a perspective view of components of a power module according to the invention.
  • the components include a substrate 34 and two semiconductor switches 6, 6' like the ones shown in Fig. 4A.
  • the first semiconductor switch 6 is provided with a source pad 42 and a gate pad 44.
  • a first wire bond 12 electrically connects the source pad 42 to first conductive track 8.
  • a second wire bond electrically connects the gate pad 44 to a second conductive track 10.
  • the first conductive track 8 and the second conductive track 10 are electrically connected to a first and second low current connection 4', 4, respectively.
  • the low current connections 4', 4 are plate-shaped and extend parallel to each other along a plane spanned by the Z axis and X axis indicated.
  • the substrate 34 is planar and extends along a plane spanned by the Y axis and the X axis. Accordingly, the low current connection 4, 4' extend perpendicular to the plane of the substrate 34.
  • the second semiconductor switch 6' is provided with a source pad 42' and a gate pad 44' and a wire bond 12' electrically connects the source pad 42' to third conductive track 8'. Another wire bond electrically connects the gate pad 44' to a fourth conductive track 10'.
  • the third conductive track 8' and the fourth conductive track 10' are electrically connected a third and fourth low current connection 4'", 4", respectively.
  • the low current connections 4", 4'" are plate-shaped and extend parallel to the other low current connections 4, 4' and extend perpendicular to the plane of the substrate 34.
  • the low current connections 4, 4', 4", 4'" are shaped as plates arranged in pairs extending parallel to each other.
  • the plates are parallel to the plane spanned by the Y axis and the Z axis.
  • the substrate 34 is planar and extends along a plane spanned by the X axis and the Y axis.
  • the conductive tracks 8, 8', 10, 10' extend along the same plane as the substrate 34.
  • Fig. 6A illustrates components of a power module according to the invention.
  • the components include a substrate 34 and two semiconductor switches 6, 6' like the ones shown in Fig. 4A and Fig. 4B.
  • the first semiconductor switch 6 is provided with a source pad 42 and a gate pad 44.
  • a first wire bond 12 electrically connects the source pad 42 to first conductive track 8.
  • a second wire bond electrically connects the gate pad 44 to a second conductive track 10.
  • the second conductive track 10 is basically U-shaped and surrounds the side portions of the first conductive track 8.
  • the second conductive track 10 is electrically connected to several first low current connections 4 protruding from an electrically conducting coaxial structure 36 comprising a cylindrical member 40 that is electrically connected to the second conductive track 10.
  • Four first low current connections 4 are evenly distributed along the distal end of the cylindrical member 40. The number of first low current connections 4 may, however, be different from four.
  • the first conductive track 8 is electrically connected to a second low current connection 4' that is provided at the distal end of a rod member 38 extending centrally inside the cylindrical member 40 along its longitudinal axis (extending along the Z axis indicated).
  • the substrate 34 is planar and extends along a plane spanned by the Y axis and the X axis. Accordingly, the low current connection 4, 4' extend perpendicular to the plane of the substrate 34.
  • the second semiconductor switch 6' is provided with a source pad 42' and a gate pad 44' and a wire bond 12' electrically connects the source pad 42' to third conductive track 8'. Another wire bond electrically connects the gate pad 44' to a fourth conductive track 10'.
  • the third conductive track 8' and the fourth conductive track 10' are electrically connected a third and fourth low current connection 4'", 4", respectively.
  • the low current connections 4", 4'" are shaped like the low current connections 4, 4' that are electrically connected to the first semiconductor switch 6.
  • Fig. 6B illustrates components of a power module according to the invention.
  • the components include a substrate 34 and two semiconductor switches 6, 6' like the ones shown in Fig. 6A.
  • the first semiconductor switch 6 is provided with a source pad 42 and a gate pad 44.
  • a first wire bond 12 electrically connects the source pad 42 to first conductive track 8.
  • a second wire bond electrically connects the gate pad 44 to a second conductive track 10.
  • the first conductive track 8 and the second conductive track 10 are arranged on a row extending parallel to the longitudinal axis of the substrate 34.
  • the first conductive track 8 is electrically connected to a first low current connection 4 protruding from the first conductive track 8.
  • the second conductive track 10 is electrically connected to a second low current connection 4' protruding from the second conductive track 10.
  • the second semiconductor switch 6' is provided with a source pad 42' and a gate pad 44'.
  • a wire bond 12' electrically connects the source pad 42' to a third conductive track 8'.
  • Another wire bond electrically connects the gate pad 44' to a fourth conductive track 10'.
  • the third conductive track 8' and the fourth conductive track 10' are arranged on a row extending parallel to the longitudinal axis of the substrate 34.
  • the third conductive track 8' is electrically connected to a third low current connection 4" protruding from the third conductive track 8'.
  • the fourth conductive track 10' is electrically connected to a fourth low current connection 4'" protruding from the fourth conductive track 10'.
  • the low current connections 4, 4', 4", 4'" comprise a cylindrical proximal portion and a thinner centrally arranged cylindrical portion protruding from the cylindrical proximal portion.
  • the substrate 34 is planar and extends along a plane spanned by the Y axis and the X axis. Accordingly, the low current connections 4, 4', 4", 4'" extend perpendicular to the plane of the substrate 34.
  • the conductive tracks 8, 8, 10, 10' extend along the same plane as the substrate 34.
  • Fig. 6C illustrates a cross-sectional view of a portion of the components shown in Fig. 6B.
  • the fourth conductive track 10' is basically U-shaped and surrounds the side portions of the third conductive track 8'.
  • a rod member 38 is connected electrically to, and rests on, the third conductive track 8'.
  • a cylindrical member 40 is connected electrically to, and rests on, the fourth conductive track 10'.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Power Conversion In General (AREA)

Abstract

Est divulgué un module de puissance (2) comprenant un boîtier constituant un logement (30). Le module de puissance (2) comprend au moins une zone de métallisation (34) sur laquelle une pluralité de commutateurs à semiconducteur (6, 6') est disposée, la couche de métallisation (34) comprenant des pistes conductrices formant une pluralité de pistes de puissance (46, 48, 50, 52) et de pistes à faible courant pour les commutateurs à semiconducteur (6, 6'). Le logement (30) comprend une partie de surface (26) disposée au-dessus des commutateurs à semiconducteur (6, 6'). Une ou plusieurs connexions à faible courant (4, 4', 4'', 4''') sont connectées électriquement à chacun des commutateurs à semiconducteur (6, 6'). Les connexions à faible courant (4, 4', 4'', 4''') s'étendent à partir de la couche de métallisation (34) à travers la partie de surface (26) et font saillie à partir de celle-ci. Les connexions à faible courant (4, 4', 4'', 4''') sont groupées dans des blocs de connexion (28).
PCT/EP2023/085241 2022-12-19 2023-12-12 Module de puissance Ceased WO2024132658A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102022133982.3 2022-12-19
DE102022133982.3A DE102022133982A1 (de) 2022-12-19 2022-12-19 Leistungsmodul

Publications (1)

Publication Number Publication Date
WO2024132658A1 true WO2024132658A1 (fr) 2024-06-27

Family

ID=89854574

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2023/085241 Ceased WO2024132658A1 (fr) 2022-12-19 2023-12-12 Module de puissance

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DE (1) DE102022133982A1 (fr)
WO (1) WO2024132658A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003046058A (ja) * 2001-07-30 2003-02-14 Mitsubishi Electric Corp 半導体装置
US20200365564A1 (en) * 2019-05-16 2020-11-19 Danfoss Silicon Power Gmbh Semiconductor module
DE212021000233U1 (de) * 2020-10-14 2022-05-17 Rohm Co., Ltd. Halbleitermodul

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4666185B2 (ja) * 2008-06-26 2011-04-06 三菱電機株式会社 半導体装置
US9147666B2 (en) * 2009-05-14 2015-09-29 Rohm Co., Ltd. Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003046058A (ja) * 2001-07-30 2003-02-14 Mitsubishi Electric Corp 半導体装置
US20200365564A1 (en) * 2019-05-16 2020-11-19 Danfoss Silicon Power Gmbh Semiconductor module
DE212021000233U1 (de) * 2020-10-14 2022-05-17 Rohm Co., Ltd. Halbleitermodul

Also Published As

Publication number Publication date
DE102022133982A1 (de) 2024-06-20

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