WO2024131068A1 - Timing closure method and apparatus, computer device, and storage medium - Google Patents

Abstract

The present application relates to the technical field of integrated circuit design, and in particular to a timing closure method and apparatus, a computer device, and a non-volatile storage medium. The method comprises: determining the maximum distance from an original Start Point to a fan-out by means of an Elmore delay model, a distributed RC delay model and a preset delay difference; determining a radius and a circle center distance according to the maximum distance; drawing a plurality of circles within a chip frame on the basis of the radius and the circle center distance so as to segment the internal area of the chip frame; screening the plurality of circles according to the fan-out position distribution to obtain a circle after the screening; and determining the number of copies and positions of the copies of the original Start Point according to the circle after the screening to copy the original Start Point. The solution of the present application greatly facilitates timing closure, saves routing resources, greatly reduces iteration time, and reduces dependence of back-end workers on an EDA tool.

Description

A timing closure method, device, computer equipment and storage medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to a Chinese patent application filed with the China Patent Office on December 21, 2022, with application number 202211647188.X, and application name “A Timing Convergence Method, Apparatus, Computer Equipment and Storage Medium”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the technical field of integrated circuit design, and in particular to a timing closure method, apparatus, computer equipment, and non-volatile readable storage medium.

Background technique

In today's deep submicron design, as the chip scale becomes increasingly complex and the process size becomes smaller, the timing convergence problem is undoubtedly becoming more and more complex and unavoidable. Timing problems (logic DRC) mainly include setup (setup time), hold (hold time), max_capacitance (maximum capacitance), max_transition (maximum jump time), max_fanout (maximum fanout), etc., among which the analysis and optimization of setup are particularly important. Throughout the front-end and back-end design of digital IC design, the most ideal solution is to obtain a netlist without timing violations before the back-end design of the chip. Moreover, as the layout and routing stages proceed, the setup violations will become more and more serious. Unlike hold, line delay will be beneficial to hold repair, so there is no problem with a small number of violations. Therefore, before starting the next stage of Setup repair, it is best to clear all the Setup violations in this stage.

Usually, there will be setup violations in the logic synthesis stage of the chip. The mainstream EDA tool solutions can be roughly divided into the following categories: Pipeline, Retiming, Logic Duplication, Addition/Multiplication Tree, Shifting Key Signals, Eliminating Priority, etc. When the fan-out of a signal is large, it will greatly increase the difficulty of layout and routing, causing the path from the signal to each destination logic node to become too long, so it leads to the problem of excessive wiring length, which in turn leads to setup violations, congestion, etc., and becomes the critical path in the design. Therefore, the fan-out can be reduced by duplicating the signal, as shown in Figures 1A and 1B.

At present, the existing EDA tools can achieve this goal, but the EDA tools cannot control the factors such as the number of times the Start Point is copied, the position of the Start Point after copying, and the fan-out of the Start Point after copying, and cannot achieve a comprehensive balance. If you want to achieve the timing convergence problem of the high fan-out Start Point through the existing EDA tools, you can only determine the number of times a Start Point is copied according to the timing QOR (timing report) through continuous iteration. However, this method is time-consuming and labor-intensive, and the error of the results of each version is relatively large, which brings unpredictable risks and iteration time to timing convergence and manufacturability.

Summary of the invention

In view of this, it is necessary to provide a timing closure method, apparatus, computer device and non-volatile readable storage medium to address the above technical issues.

According to a first aspect of the present application, a timing closure method is provided, the method comprising:

Combined with Elmore delay model, distributed RC (Resistance Capacitance, resistance capacitance The maximum distance from the original start point to the fan-out is determined by the delay model and the preset delay difference;

Determine the radius and the center spacing based on the maximum distance;

Draw multiple circles within the chip border based on the radius and the distance between the circle centers to segment the internal area of the chip border;

Screening multiple circles using fan-out position distribution to obtain screened circles;

Based on the filtered circle, determine the number of copies and the copy position of the original Start Point to copy the original Start Point.

In some embodiments, the maximum distance from the original Start Point to the fan-out is determined by combining the Elmore delay model, the distributed RC delay model, and the preset delay difference, including:

According to the Elmore delay model, the delay expression is determined as T _Di = ∑ C _k R _ik , where T _Di represents the delay, C _k represents all the capacitors in the network structure, and R _ik is the common resistance in the path from node i to node k;

Determine the resistance per unit length and the capacitance per unit length based on the distributed RC delay model;

According to the delay expression, the resistance value per unit length and the capacitance value per unit length, the delay difference expression from the original Start Point to any two points is determined as ΔT=T _Dy -T _Dx =Cp*Rp*(L _y ² -L _x ² ), where the delay from node i to node x is expressed as T _Dx =C _x *R _x , and the delay from node i to node y is expressed as T _Dy =C _y *R _y ;

Substitute the preset delay difference value into the delay difference expression to reversely solve ^the _{Ly2 -Lx2} ^value as the maximum distance.

In some embodiments, determining the radius and the center distance according to the maximum distance includes:

Use the maximum distance as the radius;

At a maximum distance Select the center spacing from times to 2 times.

In some embodiments, drawing a plurality of circles within the chip border based on the radius and the distance between the circle centers to segment the internal area of the chip border includes:

First, find the node with the original Start Point as the starting point, the distance between the centers of the circles as the length, and sixty degrees as the angle;

Then, starting from each found node, continue to find nodes in the same way until the chip border;

Finally, draw a circle with the original Start Point and all found nodes as the center according to the radius.

In some embodiments, the drawn circles are filtered using the fan-out position distribution to obtain filtered circles, including:

Determine whether there is a fan-out distribution outside all circles;

In response to the fan-out being distributed outside the circle, the center of the circle closest to the fan-out is obtained, and the circle corresponding to the center of the circle closest to the fan-out is retained.

In some embodiments, the drawn circles are filtered using the fan-out position distribution to obtain filtered circles, further comprising:

Determine whether there is fan-out inside each circle;

In response to the presence of fan-out within the circle, the circle is retained;

In response to there not being a fan-out within the circle, the circle is deleted.

In some embodiments, the drawn circles are filtered using the fan-out position distribution to obtain filtered circles, further comprising:

Determine whether there is a fan-out in the intersection area of the circle;

In response to the existence of a fan-out in the intersection area of the circles, the distance from the center of each of the intersecting circles to the fan-out is obtained;

The circle corresponding to the smallest distance among the intersecting circles is retained, and the rest are deleted.

In some embodiments, determining the number of copies and the copy position of the original Start Point according to the filtered circle to copy the original Start Point includes:

Get the total number of filtered circles and use the total number as the number of copies of the original Start Point;

Use the centers of all the filtered circles as the copy positions of the original Start Point;

The original Start Point is copied according to the number of copies, and a copy Start Point is placed at each determined copy position.

In some embodiments, the method further comprises:

Calculate the distance between each fan-out and all Start Points respectively, and assign the fan-out to the Start Point corresponding to the replication position with the minimum distance.

In some embodiments, before determining the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed resistance and capacitance delay model, and the preset delay difference, the method further includes:

When there is a high fan-out Start Point in a chip with a long strip layout, the position and fan-out value of the original Start Point are determined based on the size and shape of the chip border.

According to a second aspect of the present application, a timing closure device is provided, the device comprising:

The first determination module is configured to determine the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed RC delay model, and the preset delay difference;

A second determination module is configured to determine the radius and the center distance according to the maximum distance;

A segmentation module is configured to draw a plurality of circles within the chip border based on a radius and a distance between the circle centers to segment the internal area of the chip border;

A screening module is configured to screen the plurality of circles using the fan-out position distribution to obtain screened circles;

The third determination module is configured to determine the number of replications and replication positions of the original Start Point based on the filtered circle in order to replicate the original Start Point.

In some embodiments, the first determining module is further configured to:

According to the Elmore delay model, the delay expression is determined as T _Di = ∑ C _k R _ik , where T _Di represents the delay, C _k represents all the capacitors in the network structure, and R _ik is the common resistance in the path from node i to node k;

Determine the resistance per unit length and the capacitance per unit length based on the distributed RC delay model;

According to the delay expression, the resistance value per unit length and the capacitance value per unit length, the delay difference expression from the original Start Point to any two points is determined as ΔT=T _Dy -T _Dx =Cp*Rp*(L _y ² -L _x ² ), where the delay from node i to node x is expressed as T _Dx =C _x *R _x , and the delay from node i to node y is expressed as T _Dy =C _y *R _y ;

Substitute the preset delay difference value into the delay difference expression to reversely solve ^the _{Ly2 -Lx2} ^value as the maximum distance.

In some embodiments, the second determining module is further configured to:

Use the maximum distance as the radius;

At a maximum distance Select the center spacing from times to 2 times.

In some embodiments, the segmentation module is further configured to:

First, find the node with the original Start Point as the starting point, the distance between the centers of the circles as the length, and sixty degrees as the angle;

Then, starting from each found node, continue to find nodes in the same way until the chip border;

Finally, draw a circle with the original Start Point and all found nodes as the center according to the radius.

In some embodiments, the screening module is further configured to:

Determine whether there is a fan-out distribution outside all circles;

In response to the fan-out being distributed outside the circle, the center of the circle closest to the fan-out is obtained, and the circle corresponding to the center of the circle closest to the fan-out is retained.

In some embodiments, the screening module is further configured to:

Determine whether there is fan-out inside each circle;

In response to the presence of fan-out within the circle, the circle is retained;

In response to there not being a fan-out within the circle, the circle is deleted.

In some embodiments, the screening module is further configured to:

Determine whether there is a fan-out in the intersection area of the circle;

In response to the existence of a fan-out in the intersection area of the circles, the distance from the center of each of the intersecting circles to the fan-out is obtained;

The circle corresponding to the smallest distance among the intersecting circles is retained, and the rest are deleted.

In some embodiments, the third determination module is further configured to:

Get the total number of filtered circles and use the total number as the number of copies of the original Start Point;

Use the centers of all the filtered circles as the copy positions of the original Start Point;

The original Start Point is copied according to the number of copies, and a copy Start Point is placed at each determined copy position.

In some embodiments, the apparatus further comprises an allocation module, the allocation module being configured to:

Calculate the distance between each fan-out and all Start Points respectively, and assign the fan-out to the Start Point corresponding to the replication position with the minimum distance.

According to a third aspect of the present application, a computer device is further provided, the computer device comprising:

at least one processor; and

The memory stores a computer program that can be run on the processor, and the processor executes the aforementioned timing closure method when executing the program.

According to a fourth aspect of the present application, a computer non-volatile readable storage medium is also provided, wherein the computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the aforementioned timing closure method is executed.

The above-mentioned timing convergence method first combines the Elmore delay calculation model and the distributed RC delay model in the interconnect line calculation model commonly used in chip design to obtain the maximum distance from the original Start Point to the fan-out, and then uses the maximum distance to draw a circle with a specific center and center spacing within the chip border, thereby dividing the internal area of the chip border, and further uses the fan-out position distribution to screen multiple circles. Finally, the number of copies and the copy position are determined according to the screened circles, so as to copy the original Start Point, which can greatly help the timing convergence, save winding resources, greatly reduce the iteration time, and reduce the dependence of the back-end staff on EDA tools.

In addition, the present application also provides a timing convergence device, a computer device and a computer non-volatile readable storage medium, which can also achieve the above-mentioned technical effects and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will describe the embodiments of the present application or the prior art. The accompanying drawings required for use in the examples or descriptions of the prior art are briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

Figure 1A is a schematic diagram of the Start Point of high fan-out;

FIG1B is a schematic diagram of the replication Start Point corresponding to FIG1A ;

FIG2 is a flow chart of a timing closure method provided by an embodiment of the present application;

FIG3 is a schematic diagram of the Start Point position within the chip frame and its fan-out position provided by another embodiment of the present application;

FIG4A is a schematic diagram of using circles to divide the inner area of a chip frame according to an embodiment of the present application;

FIG4B is a partial schematic diagram of the Start Point position in FIG4A provided by an embodiment of the present application;

FIG5 is a schematic diagram of the structure of a timing closure device provided by an embodiment of the present application;

FIG. 6 is a diagram showing the internal structure of a computer device in another embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the embodiments of the present application are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present application are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present application. They will not be explained one by one in the subsequent embodiments.

In one embodiment, as shown in FIG. 2 , the present application provides a timing closure method 100, the method comprising the following steps:

Step 101, determine the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed RC delay model and the preset delay difference;

Step 102, determining the radius and the distance between the centers of the circles according to the maximum distance;

Step 103, drawing a plurality of circles within the chip frame based on the radius and the distance between the circle centers to segment the inner area of the chip frame;

Step 104, screening multiple circles using the fan-out position distribution to obtain screened circles;

Step 105, determine the number of copies and the copy position of the original Start Point based on the filtered circle to copy the original Start Point.

The above-mentioned timing convergence method first combines the Elmore delay calculation model and the distributed RC delay model in the interconnect line calculation model commonly used in chip design to obtain the maximum distance from the original Start Point to the fan-out, and then uses the maximum distance to draw a circle with a specific center and center spacing within the chip border, thereby dividing the internal area of the chip border, and further uses the fan-out position distribution to screen multiple circles. Finally, the number of copies and the copy position are determined according to the screened circles, so as to copy the original Start Point, which can greatly help the timing convergence, save winding resources, greatly reduce the iteration time, and reduce the dependence of the back-end staff on EDA tools.

In some embodiments, the aforementioned step 101, combining the Elmore delay model, the distributed RC delay model and the preset delay difference to determine the maximum distance from the original Start Point to the fan-out, includes:

According to the Elmore delay model, the delay expression is T _Di = ∑ C _k R _ik , where T _Di represents the delay When , C _k represents all the capacitors in the network structure, and R _ik is the common resistance in the path from node i to node k;

Determine the resistance per unit length and the capacitance per unit length based on the distributed RC delay model;

According to the delay expression, the resistance value per unit length and the capacitance value per unit length, the delay difference expression from the original Start Point to any two points is determined as ΔT=T _Dy -T _Dx =Cp*Rp*(L _y ² -L _x ² ), where the delay from node i to node x is expressed as T _Dx =C _x *R _x , and the delay from node i to node y is expressed as T _Dy =C _y *R _y ;

Substitute the preset delay difference value into the delay difference expression to reversely solve ^the _{Ly2 -Lx2} ^value as the maximum distance.

In some embodiments, the aforementioned step 102, determining the radius and the distance between the centers of the circles according to the maximum distance, includes:

Use the maximum distance as the radius;

At a maximum distance Select the center spacing from times to 2 times.

In some embodiments, the aforementioned step 103, drawing a plurality of circles within the chip border based on the radius and the distance between the circle centers to segment the internal area of the chip border, includes:

First, find the node with the original Start Point as the starting point, the distance between the centers of the circles as the length, and sixty degrees as the angle;

Then, starting from each found node, continue to find nodes in the same way until the chip border;

Finally, draw a circle with the original Start Point and all found nodes as the center according to the radius.

In some embodiments, the aforementioned step 104, filtering the drawn circles using the fan-out position distribution to obtain filtered circles, includes:

Determine whether there is a fan-out distribution outside all circles;

In response to the fan-out being distributed outside the circle, the center of the circle closest to the fan-out is obtained, and the circle corresponding to the center of the circle closest to the fan-out is retained.

In some embodiments, the aforementioned step 104, filtering the drawn circles using the fan-out position distribution to obtain filtered circles, further includes:

Determine whether there is fan-out inside each circle;

In response to the presence of fan-out within the circle, the circle is retained;

In response to there not being a fan-out within the circle, the circle is deleted.

In some embodiments, the aforementioned step 104, filtering the drawn circles using the fan-out position distribution to obtain filtered circles, further includes:

Determine whether there is a fan-out in the intersection area of the circle;

In response to the existence of a fan-out in the intersection area of the circles, the distance from the center of each of the intersecting circles to the fan-out is obtained;

The circle corresponding to the smallest distance among the intersecting circles is retained, and the rest are deleted.

In some embodiments, the aforementioned step 105, determining the number of copies and the copy position of the original Start Point according to the screened circle to copy the original Start Point, includes:

Get the total number of filtered circles and use the total number as the number of copies of the original Start Point;

Use the centers of all the filtered circles as the copy positions of the original Start Point;

The original Start Point is copied according to the number of copies, and a copy Start Point is placed at each determined copy position.

In some embodiments, the method further comprises:

Calculate the distance between each fan-out and all start points respectively, and assign the fan-out to the one with the smallest distance. The Start Point corresponding to the copy position.

In another embodiment, in order to facilitate understanding of the solution of the present application, please take a chip shown in FIG. 3 as an example. It may be assumed that the chip adopts a long strip layout and is a high fan-out Start Point design. This embodiment provides another timing convergence method to solve the high fan-out Start Point replication problem. The implementation principle is to improve the original EDA tool method. According to the Elmore delay calculation model and the distributed RC delay model in the interconnect line calculation model commonly used in chip design, a high fan-out Start Point positioning algorithm is proposed to determine the number of Start Point replications, reasonably plan the position of the Start Point after replication, and the fan-out of the Start Point after replication. The implementation process is as follows:

Step 1: For designs with high fan-out start points in a strip layout, determine the location and fan-out value of the high fan-out start point based on its border size and shape. The border shape of the design is a long rectangular strip, and the fan-out size of the high fan-out start point (☆) is N.

Step 2: Based on the Elmore delay calculation model in the chip design interconnection line calculation model, the Elmore delay expression is as follows:
T _Di = ∑ C _k R _ik

Where C _k represents all the capacitors in the network structure; R _ik is the common resistance of the path from node i to node k.

Consider the Start Point (☆) in Figure 3 as node i, and its fan-out as its path node k. Then we can simply calculate the delay from node i to node x, T _Dx = C _x * R _x , and the delay from node i to node y, T _Dy = C _y * R _y . Then according to the distributed RC delay calculation model in the interconnection line calculation model, the calculation formula is as follows:
R _t = R _P * L
C _t = C _P * L

Wherein, _Rp is the resistance per unit length; _Cp is the capacitance per unit length; and L is the length of the interconnection line.

From this, we can know that the delay from Start Point (☆) to node x is T _Dx = C _p *R _p *L _x ² ; similarly, the delay to node y is T _Dy = C _p *R _p *L _y ² . It can be seen that the delay from Start Point to its different fan-outs is exponentially related to the distance due to the large difference in distance. The longer the distance, the greater the delay. Since the fan-out of the Start Point node is relatively high, it is difficult to fix this type of setup violation by adjusting the Start Point position or inserting a buffer. Therefore, the best way to fix it is to copy the Start Point. However, the number of copies, the position of the Start Point after the copy, and the fan-out it controls are issues that are worth considering.

Step 3: From step 2, the delay difference from the start point (☆) to point y and point x can be expressed as: ΔT = T _Dy - T _Dx = C _p * R _p * (L _y ² - _{L x} ² )

The size of ΔT depends on ΔL＝L _y ² -L _x ² . When the back-end implements clock tree synthesis, it is expected that the clock tree is as long and flat as possible, and the skew value in the same clock domain is as small as possible and equal to t (t is the engineering experience value), which is conducive to timing convergence. The existence of ΔT will seriously affect the balance of the clock tree, and then it will be difficult to do timing convergence. Therefore, we should control ΔT≤t, and we can derive the shortest distance ΔL _t that should be maintained from the Start Point (☆) to each node.

Step 4: Use the high fan-out Start Point positioning algorithm. This algorithm uses the high fan-out Start Point in step 1 as the starting point and the ΔL _t obtained in step 3 as the radius. ΔLt is the spacing, please 4A and 4B , a plurality of circles are used to divide the area within the frame longitudinally and/or transversely.

If the fan-out of Start Point is distributed in every corner of the design, the border will be divided into countless circles. The high fan-out Start Point will be copied as many times as the number of circles. If there is no fan-out of Start Point (☆) within the range of circle M, circle M can be deleted. This algorithm is suitable for different layout shapes. It takes the position of the high fan-out Start Point in the design as the starting point and performs vertical or horizontal division to realize resource allocation and achieve resource optimization.

Step 5: Based on the positioning algorithm mentioned in step 4, we place the copied Start Point at the center of each circle and fix it. When a fan-out falls in the intersection area of two circles, for example, the dotted line (angle bisector) shown in Figures 4A and 4B divides this area in half, the fan-out that is closer to the center point belongs to the copied Start Point. This makes the fan-out distance connected to the copied Start Point controllable and the delay controllable.

A timing closure method of this embodiment uses a high fan-out Startpoint positioning algorithm to determine the number of Startpoint replications, reasonably plan the location of the Startpoint after replication, and the fan-out of the Startpoint after replication based on the Elmore delay calculation model and the distributed RC delay model in the interconnection line calculation model commonly used in chip design. This application can greatly help timing convergence, save winding resources, greatly reduce iteration time, and reduce the dependence of back-end staff on EDA tools.

In yet another embodiment, as shown in FIG. 5 , the present application further provides a timing closure device 200, the device comprising:

A first determination module 201 is configured to determine the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed RC delay model and the preset delay difference;

A second determination module 202 is configured to determine the radius and the center distance according to the maximum distance;

A segmentation module 203 is configured to draw a plurality of circles within the chip border based on the radius and the distance between the circle centers to segment the internal area of the chip border;

A screening module 204, configured to screen the multiple circles using the fan-out position distribution to obtain screened circles;

The third determination module 205 is configured to determine the number of replications and replication positions of the original Start Point based on the filtered circle in order to replicate the original Start Point.

The above-mentioned timing convergence device first combines the Elmore delay calculation model and the distributed RC delay model in the interconnect line calculation model commonly used in chip design to obtain the maximum distance from the original Start Point to the fan-out, and then uses the maximum distance to draw a circle with a specific center and center spacing within the chip border, thereby dividing the internal area of the chip border, and further uses the fan-out position distribution to screen multiple circles. Finally, the number of copies and the copy position are determined according to the screened circles, so as to copy the original Start Point, which can greatly help the timing convergence, save winding resources, and greatly reduce the iteration time, and reduce the dependence of the back-end staff on EDA tools.

In some embodiments, the first determining module 201 is further configured to:

According to the Elmore delay model, the delay expression is determined as T _Di = ∑ C _k R _ik , where T _Di represents the delay, C _k represents all the capacitors in the network structure, and R _ik is the common resistance in the path from node i to node k;

Determine the resistance per unit length and the capacitance per unit length based on the distributed RC delay model;

According to the delay expression, the resistance value per unit length and the capacitance value per unit length, the delay difference expression from the original Start Point to any two points is determined as ΔT=T _Dy -T _Dx =Cp*Rp*(L _y ² -L _x ² ), where the delay from node i to node x is expressed as T _Dx =C _x *R _x , and the delay from node i to node y is expressed as T _Dy =C _y *R _y ;

Substitute the preset delay difference value into the delay difference expression to reversely solve ^the _{Ly2 -Lx2} ^value as the maximum distance.

In some embodiments, the second determination module 202 is further configured to:

Use the maximum distance as the radius;

At a maximum distance Select the center spacing from times to 2 times.

In some embodiments, the segmentation module 203 is further configured to:

First, find the node with the original Start Point as the starting point, the distance between the centers of the circles as the length, and sixty degrees as the angle;

Then, starting from each found node, continue to find nodes in the same way until the chip border;

Finally, draw a circle with the original Start Point and all found nodes as the center according to the radius.

In some embodiments, the screening module 204 is further configured to:

Determine whether there is a fan-out distribution outside all circles;

In response to the fan-out being distributed outside the circle, the center of the circle closest to the fan-out is obtained, and the circle corresponding to the center of the circle closest to the fan-out is retained.

In some embodiments, the screening module 204 is further configured to:

Determine whether there is fan-out inside each circle;

In response to the presence of fan-out within the circle, the circle is retained;

In response to there not being a fan-out within the circle, the circle is deleted.

In some embodiments, the screening module 204 is further configured to:

Determine whether there is a fan-out in the intersection area of the circle;

In response to the existence of a fan-out in the intersection area of the circles, the distance from the center of each of the intersecting circles to the fan-out is obtained;

The circle corresponding to the smallest distance among the intersecting circles is retained, and the rest are deleted.

In some embodiments, the third determination module 205 is further configured to:

Get the total number of filtered circles and use the total number as the number of copies of the original Start Point;

Use the centers of all the filtered circles as the copy positions of the original Start Point;

The original Start Point is copied according to the number of copies, and a copy Start Point is placed at each determined copy position.

In some embodiments, the apparatus further comprises an allocation module configured to:

Calculate the distance between each fan-out and all Start Points respectively, and assign the fan-out to the Start Point corresponding to the replication position with the minimum distance.

It should be noted that the specific definition of the timing convergence device can be found in the definition of the timing convergence method above, which will not be repeated here. Each module in the above-mentioned timing convergence device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

According to another aspect of the present application, a computer device is provided, which may be a server, and its internal structure diagram is shown in FIG6. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide The computer device has computing and control capabilities. The memory of the computer device includes a non-volatile readable storage medium and an internal memory. The non-volatile readable storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile readable storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above timing convergence method is implemented, and the method includes the following steps:

Determine the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed RC delay model, and the preset delay difference;

Determine the radius and the center spacing based on the maximum distance;

Draw multiple circles within the chip border based on the radius and the distance between the circle centers to segment the internal area of the chip border;

Screening multiple circles using fan-out position distribution to obtain screened circles;

Based on the filtered circle, determine the number of copies and the copy position of the original Start Point to copy the original Start Point.

According to another aspect of the present application, a computer non-volatile readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the timing closure method described above is implemented, including performing the following steps:

Determine the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed RC delay model, and the preset delay difference;

Determine the radius and the center spacing based on the maximum distance;

Draw multiple circles within the chip border based on the radius and the distance between the circle centers to segment the internal area of the chip border;

Screening multiple circles using fan-out position distribution to obtain screened circles;

Based on the filtered circle, determine the number of copies and the copy position of the original Start Point to copy the original Start Point.

Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer non-volatile readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and/or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims (20)

A timing closure method, characterized in that the method comprises: The maximum distance from the original starting point to the fan-out is determined by combining the Elmore delay model, the distributed resistance and capacitance RC delay model, and the preset delay difference; Determine the radius and the center distance according to the maximum distance; Draw a plurality of circles within the chip frame based on the radius and the circle center distance to segment the internal area of the chip frame; Screening multiple circles using fan-out position distribution to obtain screened circles; Based on the filtered circle, determine the number of copies and the copy position of the original Start Point to copy the original Start Point. The timing closure method according to claim 1, characterized in that the step of combining the Elmore delay model, the distributed RC delay model and the preset delay difference to determine the maximum distance from the original Start Point to the fan-out comprises: According to the Elmore delay model, the delay expression is determined as T _Di = ∑ C _k R _ik , where T _Di represents the delay, C _k represents all the capacitors in the network structure, and R _ik is the common resistance in the path from node i to node k; Determine the resistance per unit length and the capacitance per unit length based on the distributed RC delay model; According to the delay expression, the resistance per unit length and the capacitance per unit length, the delay difference expression from the original Start Point to any two points is determined as ΔT=T _Dy -T _Dx =Cp*Rp*(L _y ² -L _x ² ), wherein the delay from node i to node x is expressed as T _Dx =C _x *R _x , and the delay from node i to node y is expressed as T _Dy =C _y *R _y ; The preset delay difference value is substituted into the delay difference expression to reversely solve ^the value of _{Ly2 -Lx2} ^as the maximum distance. The timing closure method according to claim 1, wherein determining the radius and the center distance according to the maximum distance comprises: Taking the maximum distance as the radius; At a distance not exceeding the maximum Select the center spacing from times to 2 times. The timing closure method according to claim 3, characterized in that the step of drawing a plurality of circles within the chip border based on the radius and the circle center distance to divide the internal area of the chip border comprises: First, find the node with the original Start Point as the starting point, the distance between the centers of the circles as the length, and sixty degrees as the angle; Then, starting from each found node, continue to find nodes in the same way until the chip border; Finally, draw a circle with the original Start Point and all found nodes as the center according to the radius. The timing closure method according to claim 1, wherein the step of filtering the drawn circles by using the fan-out position distribution to obtain the filtered circles comprises: Determine whether there is a fan-out distribution outside all circles; In response to the fan-out being distributed outside the circle, the center of the circle closest to the fan-out is obtained, and the circle corresponding to the center of the circle closest to the fan-out is retained. The timing closure method according to claim 5, characterized in that the step of filtering the drawn circles by using the fan-out position distribution to obtain filtered circles further comprises: Determine whether there is fan-out inside each circle; In response to the presence of fan-out within the circle, the circle is retained; In response to there not being a fan-out within the circle, the circle is deleted. The timing closure method according to claim 6, wherein the step of filtering the drawn circles by using the fan-out position distribution to obtain filtered circles further comprises: Determine whether there is a fan-out in the intersection area of the circle; In response to the existence of a fan-out in the intersection area of the circles, the distance from the center of each of the intersecting circles to the fan-out is obtained; The circle corresponding to the smallest distance among the intersecting circles is retained, and the rest are deleted. The timing closure method according to claim 1, characterized in that the step of determining the number of copies and the copy position of the original Start Point according to the screened circle to copy the original Start Point comprises: Get the total number of circles after filtering, and use the total number as the number of copies of the original Start Point; Use the centers of all the filtered circles as the copy positions of the original Start Point; The original Start Point is copied according to the number of copies, and a copy Start Point is placed at each determined copy position. The timing closure method according to claim 8, characterized in that the method further comprises: Calculate the distance between each fan-out and all Start Points respectively, and assign the fan-out to the Start Point corresponding to the replication position with the minimum distance. The timing closure method according to claim 1, characterized in that before determining the maximum distance from the original Start Point to the fan-out by combining the Elmore delay model, the distributed resistance and capacitance delay model, and the preset delay difference, the method further comprises: When a high fan-out Start Point exists in a chip with a strip layout, the position and fan-out value of the original Start Point are determined based on the size and shape of the chip border. A timing closure device, characterized in that the device comprises: The first determination module is configured to determine the maximum distance from the original starting point Start Point to the fan-out by combining the Elmore delay model, the distributed resistance and capacitance RC delay model and the preset delay difference; A second determination module is configured to determine a radius and a center distance according to the maximum distance; A segmentation module is configured to draw a plurality of circles within the chip border based on the radius and the circle center distance to segment the internal area of the chip border; A screening module is configured to screen the plurality of circles using the fan-out position distribution to obtain screened circles; The third determination module is configured to determine the number of replications and replication positions of the original Start Point based on the filtered circle in order to replicate the original Start Point. The timing closure device according to claim 11, characterized in that the first The module is further configured as: According to the Elmore delay model, the delay expression is determined as T _Di = ∑ C _k R _ik , where T _Di represents the delay, C _k represents all the capacitors in the network structure, and R _ik is the common resistance in the path from node i to node k; Determine the resistance per unit length and the capacitance per unit length based on the distributed RC delay model; According to the delay expression, the resistance per unit length and the capacitance per unit length, the delay difference expression from the original Start Point to any two points is determined as ΔT=T _Dy -T _Dx =Cp*Rp*(L _y ² -L _x ² ), wherein the delay from node i to node x is expressed as T _Dx =C _x *R _x , and the delay from node i to node y is expressed as T _Dy =C _y *R _y ; The preset delay difference value is substituted into the delay difference expression to reversely solve ^the value of _{Ly2 -Lx2} ^as the maximum distance. The timing closure device according to claim 11, wherein the second determination module is further configured to: Taking the maximum distance as the radius; At a distance not exceeding the maximum Select the center spacing from times to 2 times. The timing closure device according to claim 12, wherein the segmentation module is further configured to: First, find the node with the original Start Point as the starting point, the distance between the centers of the circles as the length, and sixty degrees as the angle; Then, starting from each found node, continue to find nodes in the same way until the chip border; Finally, draw a circle with the original Start Point and all found nodes as the center according to the radius. The timing closure device according to claim 11, wherein the screening module is further configured to: Determine whether there is a fan-out distribution outside all circles; In response to the fan-out being distributed outside the circle, the center of the circle closest to the fan-out is obtained, and the circle corresponding to the center of the circle closest to the fan-out is retained. The timing closure device according to claim 15, wherein the screening module is further configured to: Determine whether there is fan-out inside each circle; In response to the presence of fan-out within the circle, the circle is retained; In response to there not being a fan-out within the circle, the circle is deleted. The timing closure device according to claim 16, wherein the screening module is further configured to: Determine whether there is a fan-out in the intersection area of the circle; In response to the existence of a fan-out in the intersection area of the circles, the distance from the center of each of the intersecting circles to the fan-out is obtained; The circle with the smallest distance among the intersecting circles is retained, and the rest are deleted. The timing closure device according to claim 11, characterized in that the third determination module is further configured to: Get the total number of filtered circles and use the total number as a copy of the original Start Point frequency; Use the centers of all the filtered circles as the copy positions of the original Start Point; The original Start Point is copied according to the number of copies, and a copy Start Point is placed at each determined copy position. A computer device, comprising: at least one processor; and A memory storing a computer program executable in the processor, wherein the processor executes the method according to any one of claims 1 to 10 when executing the program. A computer non-volatile readable storage medium storing a computer program, wherein the computer program, when executed by a processor, performs the method according to any one of claims 1 to 10.