[go: up one dir, main page]

WO2024123239A1 - Hétérostructure et son procédé de formation - Google Patents

Hétérostructure et son procédé de formation Download PDF

Info

Publication number
WO2024123239A1
WO2024123239A1 PCT/SG2023/050743 SG2023050743W WO2024123239A1 WO 2024123239 A1 WO2024123239 A1 WO 2024123239A1 SG 2023050743 W SG2023050743 W SG 2023050743W WO 2024123239 A1 WO2024123239 A1 WO 2024123239A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
fully
gan
channel
channel layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SG2023/050743
Other languages
English (en)
Inventor
Ravikiran LINGAPARTHI
Dharmarasu NETHAJI
Radhakrishnan K
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanyang Technological University
Original Assignee
Nanyang Technological University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanyang Technological University filed Critical Nanyang Technological University
Priority to EP23901207.3A priority Critical patent/EP4643394A1/fr
Publication of WO2024123239A1 publication Critical patent/WO2024123239A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • Various embodiments of this disclosure may relate to a hetero structure.
  • Various embodiments of this disclosure may relate to a method of forming a heterostructure.
  • CMOS Complementary metal-oxide semiconductor
  • ICs integrated circuits
  • Si Silicon
  • gallium nitride (GaN), silicon carbide (SiC), and gallium oxide (Ga2Os)
  • GaN gallium nitride
  • GaN with a large bandgap and high saturation velocity enables not only high voltage and high power operation, but also enables high frequency operation.
  • transistor amplifier technology that can operate not just at higher frequencies but also with better output power and efficiency is required.
  • GaN based n-type high electron mobility transistors (HEMTs) have been evolved to meet the above mentioned requirements.
  • GaN n-channel transistors in electronic systems are slowed down to be compatible with the operational speed of Si CMOS technologies, which is neither an energy efficient nor a higher frequency option.
  • nitride complementary technology can be attributed to the lack of suitable p-type dopants that can result in nitride p-channel transistors with higher conductivity and higher current operation.
  • Recently, efforts to realize GaN p-type transistors have been increased, resulting in the evolution of three choices of promising technologies for GaN p- channel transistors and for developing nitride complementary technology.
  • the first of the three choices is p-type GaN transistors with an magnesium-doped (Mg-doped) GaN channel.
  • Mg-doped magnesium-doped
  • the second choice uses polarization induced doping, where heterojunction between GaN and temary/quatemary materials such as gallium nitride/ aluminum gallium nitride (GaN/AlGaN), indium gallium nitride/gallium nitride (InGaN/GaN), and gallium nitride/aluminum indium gallium nitride (GaN/AlInGaN) were explored.
  • the two-dimensional hole gas (2DHG) is generated at the interface between undoped GaN and the back barrier layer, resulting in improved conductivity compared to the choice 1 structure.
  • the conductivities achieved were still below the levels required for high performance transistors.
  • the conductivities achieved were still below the levels required for high performance transistors.
  • the third choice of technology uses undoped GaN/AlN layers with GaN pseudomorphically grown (resulting in fully strained GaN layers) over the AIN layer.
  • Such a system demonstrated high conductivity hole gas, and p- channel HEMTs were demonstrated with high current densities of 420 mA/mm and high frequency of operation of 20 GHz fr/fMAx.
  • nitride complementary technology was proposed on the AIN platform.
  • the main idea for developing complementary technology on the AIN platform is to achieve high density two-dimensional electron gas (2DEG) at the top AlN/GaN interface and hole gas at the bottom GaN /AIN interface in an AlN/strained GaN/AlN heterostructure.
  • 2DEG high density two-dimensional electron gas
  • the AIN platform provides a huge back barrier, thus reducing the spreading of the 2DHG into the buffer, resulting in improved device gain and efficiency.
  • the high thermal conductivity of AIN provides a better heat sink, improving the reliability of GaN HEMTs.
  • ICP-RIE inductively coupled plasma-reactive ion etching
  • the heterostructure may include a substrate.
  • the heterostructure may also include a buffer layer on the substrate, a first region of the buffer layer having a regrowth portion.
  • the hetero structure may further include a fully strained channel layer on a second region of the buffer layer such that two dimensional hole gas (2DHG) is formed at an interface between the fully strained channel layer and the second region of the buffer layer, wherein the second region of the buffer layer and the fully strained channel layer form a p-channel portion of the heterostructure.
  • the heterostructure may additionally include a fully relaxed channel layer on the regrowth portion of the buffer layer, the fully relaxed channel layer separated from the fully strained channel layer by a gap.
  • the heterostructure may also include a fully strained or completely lattice matched barrier layer on the fully relaxed channel layer such that two dimensional electron gas (2DEG) is formed at an interface between the fully strained or completely lattice matched barrier layer and the fully relaxed channel layer, wherein the first region of the buffer layer having the regrowth portion, the fully relaxed channel layer and the fully strained or completely lattice matched barrier layer form a n-channel portion of the hetero structure.
  • the n-channel portion of the hetero structure may be devoid of two dimensional hole gas (2DHG).
  • Various embodiments may provide a method of forming a hetero structure.
  • the method may include forming a buffer layer on a substrate, a first region of the buffer layer having a regrowth portion.
  • the method may also include forming a fully strained channel layer on a second region of the buffer layer such that two dimensional hole gas (2DHG) is formed at an interface between the fully strained channel layer and the second region of the buffer layer, wherein the second region of the buffer layer and the fully strained channel layer form a p- channel portion of the heterostructure.
  • the method may further include forming a fully relaxed channel layer on the regrowth portion of the buffer layer, the fully relaxed channel layer separated from the fully strained channel layer by a gap.
  • the method may additionally include forming a fully strained or completely lattice matched barrier layer on the fully relaxed channel layer such that two dimensional electron gas (2DEG) is formed at an interface between the fully strained or completely lattice matched barrier layer and the fully relaxed channel layer, wherein the first region of the buffer layer having the regrowth portion, the fully relaxed channel layer and the fully strained or completely lattice matched barrier layer form a n-channel portion of the hetero structure.
  • the n-channel portion of the hetero structure may be devoid of two dimensional hole gas (2DHG).
  • FIG. 1 is a general illustration of a heterostructure according to various embodiments.
  • FIG. 2 is a general illustration of a method of forming a hetero structure according to various embodiments.
  • FIG. 3A is a schematic of a hetero structure according to various embodiments.
  • FIG. 3B is a schematic of the heterostructure shown in FIG. 3A after reactive ion etching (RIE) or inductive coupled plasma-reactive ion etching (ICP-RIE) according to various embodiments.
  • RIE reactive ion etching
  • ICP-RIE inductive coupled plasma-reactive ion etching
  • FIG. 4A is a schematic of another heterostructure according to various embodiments.
  • FIG. 4B is a schematic of the hetero structure shown in FIG. 4A according to various embodiments, but in which the interface between the fully relaxed channel layer and the regrowth portion of the buffer layer is at a same level as the interface between the fully strained channel layer and the second region of the buffer layer.
  • FIG. 5 is a schematic of yet another hetero structure according to various embodiments.
  • FIG. 6 shows the schematic of a cross-section of the unintentionally doped (UID) gallium nitride/aluminum nitride (GaN/AlN) heterostructure according to various embodiments.
  • UID unintentionally doped gallium nitride/aluminum nitride
  • FIG. 7 shows (a) a plot of z-axis Q z (* 10 7 , in relative lattice units or rlu) as a function of x- axis Q x (* 10 7 , in relative lattice units or rlu) illustrating the X-ray diffraction reciprocal space mapping (XRD RSM) along the gallium nitride GaN (105) plane of sample (a) according to various embodiments; (b) a plot of z-axis Q z (* 10 7 , in relative lattice units or rlu) as a function of x-axis Q x (* 10 7 , in relative lattice units or rlu) illustrating the X-ray diffraction reciprocal space mapping (XRD RSM) along the gallium nitride GaN (105) plane of sample (b) according to various embodiments; a plot of z-axis Q z (* 10 7 , in relative lattice units
  • FIG. 8 shows a table summarizing the sheet resistance, mobility, sheet carrier concentration, and type of charge carriers for all samples (a) - (d) according to various embodiments.
  • FIG. 9 shows a plot of capacitance (x IO 10 Farads or F) as a function of applied bias (in volts or V) illustrating the capacitance-voltage (C-V) measurements on samples (a) and (c) according to various embodiments, with the inset showing an optical microscopy image of the contact.
  • FIG. 10 shows a plot of two-dimensional hole gas (2DHG) concentration (x 10 13 per square centimeters or cm -2 ) as a function of gallium nitride (GaN) thickness (in nanometers or nm) illustrating the variation of 2DHG concentration with channel thickness for different GaN surface potentials ((
  • 2DHG two-dimensional hole gas
  • FIG. 11 shows a schematic of a gallium nitride/aluminum nitride/ gallium nitride/aluminum nitride (GaN/AlN/GaN/AlN) heterostructure on the silicon carbide (SiC) substrate according to various embodiments.
  • FIG. 12 shows (a) a plot of z-axis Q z (* 10 7 , in relative lattice units or rlu) as a function of x- axis Q x (* 10 7 , in relative lattice units or rlu) illustrating the X-ray diffraction reciprocal space mapping (XRD RSM) along the gallium nitride GaN (105) plane of sample (e) according to various embodiments; and (b) a plot of z-axis Q z (* 10 7 , in relative lattice units or rlu) as a function of x-axis Q x (* 10 7 , in relative lattice units or rlu) illustrating the X-ray diffraction reciprocal space mapping (XRD RSM) along the gallium nitride GaN (105) plane of sample (f) according to various embodiments.
  • XRD RSM X-ray diffraction reciprocal space mapping
  • FIG. 13 shows a table summarizing the results of Hall effect measurements performed on sample (e) and sample (f) according to various embodiments.
  • FIG. 14 shows (a) a plot of energy bands Ec, EF, EV (in electron-volts or eV) / carrier concentration (x IO 20 per cubic centimeter or cm -3 ) as a function of depth (in nanometers or nm) illustrating the calculated energy band profiles as well as the calculated two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) of sample (e) according to various embodiments; and (b) a plot of energy bands Ec, EF, EV (in electron-volts or eV) / carrier concentration (x IO 20 per cubic centimeter or cm -3 ) as a function of depth (in nanometers or nm) illustrating the calculated energy band profiles as well as the calculated two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) of sample (f) according to various embodiments.
  • FIG. 15 shows (a) a plot of capacitance (x IO 10 Farads or F) / integrated charge (x 10 13 cm -2 ) as a function of applied bias (in Volts or V) illustrating capacitance and integrated charge as a function of applied bias according to various embodiments; and (b) a plot of carrier concentration (per cubic centimeter or cm -3 ) as a function of thickness (in nanometer or nm) illustrating the estimated carrier concentration from capacitance-voltage (C-V) measurements as a function of sample thickness according to various embodiments.
  • FIG. 16A shows a schematic of a N-polar high-electron-mobility transistor (HEMT) heterostructure according to various embodiments.
  • HEMT high-electron-mobility transistor
  • FIG. 16B shows a plot of energy bands Ec, EF, EV (in electron-volts or eV) / carrier concentration n s (x IO 20 per cubic centimeter or cm -3 ) as a function of thickness/depth from surface (in nanometers or nm) illustrating the simulated energy band profiles as well as the simulated two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) distribution as a function of thickness/depth according to various embodiments.
  • 2DEG two-dimensional electron gas
  • 2DHG two-dimensional hole gas
  • FIG. 16C shows a plot of capacitance (x IO 10 Farads or F) / integrated charge (x 10 12 per square centimeter or cm -2 ) as a function of applied bias (in Volts or V) illustrating capacitance and integrated charge as a function of applied bias obtained using a Schottky contact of 100 pm diameter according to various embodiments.
  • FIG. 16D shows a plot of carrier concentration (per cubic centimeter or cm -3 ) as a function of thickness/depth illustrating the estimated carrier concentration from capacitance-voltage (C- V) measurements as a function of sample depth/thickness (in nanometers or nm).
  • FIG. 17 shows a table summarizing the Hall measurements on N-polar high-electron-mobility transistor (HEMT) heterostructure.
  • HEMT high-electron-mobility transistor
  • the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance, e.g. within 10% of the specified value.
  • Embodiments described in the context of one of the heterostructures are analogously valid for the other heterostructure.
  • embodiments described in the context of a method are analogously valid for a heterostructure, and vice versa.
  • buried-2DHG as described herein may refer to the 2DHG present under the 2DEG.
  • a direct proof of the coexistence of 2DEG and buried-2DHG in the same AlN/GaN/AlN heterostructure has not been demonstrated to date.
  • the coexistence of 2DHG on top of 2DEG was demonstrated in GaN/AlNGaN/GaN heterostructure, where the top 2DHG was stabilized by the Mg-doped p-type GaN layer.
  • Various embodiments may relate to a heterostructure suitable for CMOS technology.
  • Various embodiments may relate to a hetero structure including a p-channel portion and a n- channel portion, but in which the two dimensional hole gas (2DHG) and the two dimensional electron gas (2DEG) are not interdependent on each other.
  • Various embodiments may relate to a hetero structure devoid of a buried 2DHG under a 2DEG.
  • FIG. 1 is a general illustration of a heterostructure according to various embodiments.
  • the heterostructure may include a substrate 102.
  • the hetero structure may also include a buffer layer 104 on the substrate 102, a first region of the buffer layer 104 having a regrowth portion 104a.
  • the heterostructure may further include a fully strained channel layer 106 on a second region of the buffer layer 104 such that two dimensional hole gas (2DHG) is formed at an interface between the fully strained channel layer 106 and the second region of the buffer layer 104, wherein the second region of the buffer layer 104 and the fully strained channel layer 106 form a p-channel portion of the heterostructure.
  • 2DHG two dimensional hole gas
  • the heterostructure may additionally include a fully relaxed channel layer 108 on the regrowth portion 104a of the buffer layer 104, the fully relaxed channel layer 108 separated from the fully strained channel layer 106 by a gap.
  • the hetero structure may also include a fully strained or completely lattice matched barrier layer 110 on the fully relaxed channel layer 108 such that two dimensional electron gas (2DEG) is formed at an interface between the fully strained or completely lattice matched barrier layer 110 and the fully relaxed channel layer 108, wherein the first region of the buffer layer 104 having the regrowth portion 104a, the fully relaxed channel layer 108 and the fully strained or completely lattice matched barrier layer 110 form a n-channel portion of the heterostructure.
  • the n-channel portion of the heterostructure may be devoid of two dimensional hole gas (2DHG).
  • various embodiments may include a hetero structure including a n- channel portion and a p-channel portion.
  • the n-channel portion may include a first region of a buffer layer 104 including a regrowth portion 104a, a fully relaxed channel layer 108 and a fully strained or completely lattice matched barrier layer 110.
  • the p-channel portion may include a second region of the buffer layer 104 and a fully strained channel layer 106.
  • the n- channel portion and the p-channel portion may be lateral to each other and may both be over a substrate.
  • the dashed lines used to denote the 2DHG and 2DEG in FIG. 1 are spaced from the interfaces of layer 106/layer 104 and layer 108/layer 110, respectively, as the peaks of the 2DHG and 2DEG distributions may be away from the respective interface.
  • one or more portions of the 2DHG may overlap or almost overlap with the interface between fully strained channel layer 106 and buffer layer 104.
  • one or more portions of the 2DEG may overlap or almost overlap with the interface between fully relaxed channel layer 108 and fully strained or completely lattice matched barrier layer 110.
  • the 2DHG may have any suitable sheet hole concentration, any value e.g. above 10 13 cm' 2 .
  • the 2DEG may have any suitable sheet electron concentration, any value e.g. above 10 12 cm' 2 .
  • the channel layer 108 may be fully relaxed when the strain arising due to lattice mismatch with the underlying buffer layer 104 (i.e. regrowth portion 104a) is relaxed due to the formation of misfit dislocations at the interface between the channel layer 108 and the buffer layer 104 (i.e. regrowth portion 104a), such that there is no residual strain in the channel layer 108.
  • the fully relaxed channel layer 108 may have a thickness of any suitable dimensions, e.g. 60 nm or more.
  • a thicker fully relaxed channel layer 108 may lead to a higher sheet electron concentration in the 2DEG.
  • a thicker fully relaxed channel layer 108 may also lead to improved mobility. The above mentioned may be due to the reduced back polarization effects on the 2DEG as thickness of the channel layer 108 increases.
  • the channel layer 106 may be fully strained due to lattice mismatch with the underlying buffer layer 304, and there is no strain relaxation mechanism present in the channel layer 106.
  • the fully strained channel layer 106 may have a thickness of any suitable dimensions, e.g. 11 nm or less, e.g. 7.5 nm, 8 nm or 10 nm. Generally, the thickness of the fully strained channel layer 106 may be dependent on the growth conditions and the substrate 102 as described herein.
  • the fully strained channel layer 106 may also be referred to as a coherently grown channel layer or a pseudomorphically grown channel.
  • the surface potential of the fully strained channel layer 106 may lie between 1.5 eV and 2.0 eV above the valence band (inclusive of both end values).
  • the fully strained channel layer 106 may be a fully strained gallium nitride (GaN) layer.
  • the fully relaxed channel layer 108 may be a fully relaxed gallium nitride (GaN) layer.
  • the buffer layer 104 may include aluminum nitride (AIN).
  • the substrate 102 may include silicon carbide (SiC), sapphire (AI2O3), aluminum nitride (AIN), or silicon (Si).
  • SiC silicon carbide
  • AI2O3 aluminum nitride
  • AIN aluminum nitride
  • Si silicon
  • the buffer layer 104 and the substrate 102 may form a monolithic, continuous AIN structure.
  • the buffer layer 104 may be a buffer region, i.e. a top region of the AIN structure, while the substrate 102 may be a substrate region of the AIN structure under the buffer region.
  • the fully strained or completely lattice matched barrier layer 110 may include aluminum nitride (AIN) or scandium aluminum nitride (Sc x Ali- x N, where 0 ⁇ x ⁇ 1).
  • the fully strained or completely lattice matched barrier layer 110 may include a ternary material or a quaternary material.
  • the heterostructure may further include a cap layer on the fully strained or completely lattice matched barrier layer 110.
  • the hetero structure may also include a further cap layer on the fully strained channel layer 106.
  • the cap layer on the fully strained or completely lattice matched barrier layer 110 may be doped with dopants of n-type, while the further cap layer on the fully strained channel layer 106 may be doped with dopants of p-type.
  • the cap layer on the fully strained or completely lattice matched barrier layer 110 may be a gallium nitride (GaN) layer doped with silicon or germanium
  • the further cap layer on the fully strained channel layer 106 may be a gallium nitride (GaN) or indium gallium nitride (InGaN) layer doped with magnesium.
  • the cap layer may be selectively etched.
  • the unetched portions of the cap layer may form a source electrode and a drain electrode on the fully strained or completely lattice-matched barrier layer 110, thereby forming a n-channel transistor.
  • the further cap layer may be selectively etched.
  • the unetched portions of the further cap layer may form a further source electrode and a further drain electrode on the fully strained channel layer 106, thereby forming a p-channel transistor.
  • the cap layer on the fully strained or completely lattice matched barrier layer 110 may be undoped.
  • An interface between the fully relaxed channel layer 108 and the regrowth portion 104a of the buffer layer 104 may be at a same or lower level than the interface between the fully strained channel layer 106 and the second region of the buffer layer 102.
  • the cap layer may be an undoped gallium nitride (GaN) layer.
  • Portions of the fully relaxed channel layer 108 may be doped with n-type dopants to form a source region and a drain region, thereby forming a n-channel transistor, while portions of the fully strained channel layer 106 may be doped with p-type dopants to form a further source region and a further drain region, thereby forming a p-channel transistor.
  • the hetero structure may include first contacts including n-type dopants, the first contacts in contact with the fully relaxed channel layer 108 and the fully strained or completely lattice matched barrier layer 110.
  • the heterostructure may also include second contacts including p-type dopants, the second contacts in contact with the fully strained channel layer 106 and the second region of the buffer layer 104.
  • the first contacts may include gallium nitride (GaN) or indium gallium nitride (InGaN)
  • the second contacts may include gallium nitride (GaN) or indium gallium nitride (InGaN)
  • the cap layer may be an undoped gallium nitride (GaN) layer.
  • the n-channel portion of the hetero structure may be devoid of 2DHG. In other words, there may not be parallel conduction in the n-channel portion. Instead, the n-channel portion of the heterostructure may include hole or hole-like trap states.
  • the thicker fully relaxed channel layer 108 may greatly reduce the back polarization on the 2DEG.
  • the gap separating the fully relaxed channel layer 108 from the fully strained channel layer 106 may be greater than the thickness of the fully strained channel layer 106 as well as the thickness of the fully relaxed channel layer 108. For instance, the gap may be at least 1000 nm wide for a 60 nm fully relaxed channel layer 108.
  • the barrier layer 110 may be fully strained or lattice matched.
  • the barrier layer 110 may be fully strained due to lattice mismatch with the underlying fully relaxed channel layer 108, and there is no strain relaxation mechanism present in the barrier layer 110.
  • the lattice constant of the barrier layer 110 may match (i.e. equal to) that of the underlying fully relaxed channel layer 108.
  • FIG. 2 is a general illustration of a method of forming a hetero structure according to various embodiments.
  • the method may include, in 202, forming a buffer layer on a substrate, a first region of the buffer layer having a regrowth portion.
  • the method may also include, in 204, forming a fully strained channel layer on a second region of the buffer layer such that two dimensional hole gas (2DHG) is formed at an interface between the fully strained channel layer and the second region of the buffer layer, wherein the second region of the buffer layer and the fully strained channel layer form a p-channel portion of the heterostructure.
  • 2DHG two dimensional hole gas
  • the method may further include, in 206, forming a fully relaxed channel layer on the regrowth portion of the buffer layer, the fully relaxed channel layer separated from the fully strained channel layer by a gap.
  • the method may additionally include, in 208, forming a fully strained or completely lattice matched barrier layer on the fully relaxed channel layer such that two dimensional electron gas (2DEG) is formed at an interface between the fully strained or completely lattice matched barrier layer and the fully relaxed channel layer, wherein the first region of the buffer layer having the regrowth portion, the fully relaxed channel layer and the fully strained or completely lattice matched barrier layer form a n-channel portion of the hetero structure.
  • the n-channel portion of the heterostructure may be devoid of two dimensional hole gas (2DHG).
  • the method may include forming a n-channel portion including a first region of a buffer layer including a regrowth portion, a fully relaxed channel layer and a fully strained or completely lattice matched barrier layer, as well as a p-channel portion including a second region of the buffer layer and a fully strained channel layer.
  • FIG. 2 is intended to illustrate some of the steps of forming a hetero structure according to various embodiments, and is not intended to limit the sequence of the various steps.
  • step 204 may occur before step 206.
  • the p-channel portion may be formed before forming the n-channel portion.
  • a portion of the fully strained channel layer may be selectively etched together with a portion of the buffer layer, before a region of the buffer layer (i.e. the first region of the buffer layer) is regrown to form the regrowth portion, and the fully relaxed channel layer is formed on the regrowth portion.
  • the fully relaxed channel layer may have a thickness of any suitable dimensions, e.g. 60 nm or more.
  • the fully strained channel layer may have a thickness of any suitable dimensions, e.g. 11 nm or less.
  • the fully strained channel layer may be a fully strained gallium nitride (GaN) layer.
  • the fully relaxed channel layer may be a fully relaxed gallium nitride (GaN) layer.
  • the buffer layer may include aluminum nitride (AIN).
  • the substrate may include silicon carbide (SiC), sapphire (A12O3), aluminum nitride (AIN), or silicon (Si).
  • the fully strained or completely lattice matched barrier layer may include aluminum nitride (AIN) or scandium aluminum nitride (Sc x Ali- x N, where 0 ⁇ x ⁇ 1).
  • the fully strained or completely lattice matched barrier layer 110 may include a ternary material or a quaternary material.
  • the heterostructure may further include a cap layer on the fully strained or completely lattice matched barrier layer.
  • the hetero structure may also include a further cap layer on the fully strained channel layer.
  • the cap layer on the fully strained or completely lattice matched barrier layer may be doped with dopants of n-type, while the further cap layer on the fully strained channel layer may be doped with dopants of p-type.
  • the cap layer on the fully strained or completely lattice matched barrier layer may be a gallium nitride (GaN) layer doped with silicon or germanium
  • the further cap layer on the fully strained channel layer may be a gallium nitride (GaN) or indium gallium nitride (InGaN) layer doped with magnesium.
  • the method may include selectively etching the cap layer such that unetched portions of the cap layer form a source electrode and a drain electrode on the fully strained or completely lattice-matched barrier layer, thereby forming a n-channel transistor.
  • the method may also include selectively etching the further cap layer such that unetched portions of the further cap layer form a further source electrode and a further drain electrode on the fully strained channel layer, thereby forming a p-channel transistor.
  • the cap layer on the fully strained or completely lattice matched barrier layer may be undoped.
  • An interface between the fully relaxed channel layer and the regrowth portion of the buffer layer may be at a same or lower level than the interface between the fully strained channel layer and the second region of the buffer layer.
  • the cap layer may be an undoped gallium nitride (GaN) layer.
  • Portions of the fully relaxed channel layer may be doped with n-type dopants to form a source region and a drain region, thereby forming a n-channel transistor, while portions of the fully strained channel layer may be doped with p-type dopants to form a further source region and a further drain region, thereby forming a p-channel transistor.
  • the method may include forming first contacts including n-type dopants, the first contacts in contact with the fully relaxed channel layer and the fully strained or completely lattice matched barrier layer.
  • the method may also include forming second contacts including p-type dopants, the second contacts in contact with the fully strained channel layer and the second region of the buffer layer.
  • the first contacts may include gallium nitride (GaN) or indium gallium nitride (InGaN)
  • the second contacts may include gallium nitride (GaN) or indium gallium nitride (InGaN)
  • the cap layer may be an undoped gallium nitride (GaN) layer.
  • Various embodiments may relate to a nitride based complementary technology heterostructure with n-channel and p-channel transistors, which may include 2DEG and 2DHG respectively.
  • the p-channel transistor may contain GaN epilayer pseudomorphically grown on AIN buffer/substrate layer.
  • the n-channel transistor may contain GaN/top barrier/relaxed GaN/AlN buffer regrown alongside of the p-channel transistor in the selected areas, after etching the pseudomorphic GaN layer and some AIN buffer layer.
  • FIG. 3 A is a schematic of a heterostructure according to various embodiments.
  • the heterostructure may include an AIN buffer layer 304 epitaxially grown over a substrate 302.
  • the substrate 302 may include AIN.
  • the AIN buffer layer 304 and the AIN substrate 302 may form a monolithic structure.
  • a GaN-1 channel layer 306 (fully strained) may be coherently grown over the AIN buffer layer 304 to achieve 2DHG at GaN/AlN interface. As there is no other barrier layer on top of the coherently grown GaN channel layer 306, the 2DHG may be achieved unambiguously.
  • a P++ GaN or InGaN cap layer 312 (e.g. doped with a dopant such as magnesium (Mg)) may be grown on the top of the GaN channel layer 306.
  • the cap layer 312 may be used for ohmic contact purposes.
  • the total layer thickness of the p++ GaN or InGaN cap layer 312 may be maintained such that there is no relaxation of the underlying GaN-1 channel layer 306.
  • the concentration of the dopant in the cap layer 312 may be of any suitable value, e.g. any value greater than 10 19 cm' 3 .
  • the cap layer 312, the channel layer 306 and the region of the buffer layer 304 in which the cap layer 312 and the channel layer 306 are over may form a p- channel portion of the hetero structure.
  • the as-grown wafer may be patterned and masked using dielectric materials such as silicon dioxide (SiCh) or silicon nitride (SiN) in the areas where 2DHG needs to be preserved.
  • dielectric materials such as silicon dioxide (SiCh) or silicon nitride (SiN)
  • ICP-RIE inductive coupled plasma-reactive ion etching
  • RIE reactive ion etching
  • An AlN/relaxed GaN channel layer/barrier layer (AIN, ScAlN or ternary or quaternary )/GaN cap layer hetero structure may be grown in the unmasked areas.
  • a thin AIN portion 304a may be regrown from the AIN buffer layer 304 using epitaxial growth methods such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) techniques. Regrowth of AIN may help avoid parallel conduction due to the regrowth interface.
  • the thickness of the GaN-2 channel layer 308 may be selected such that the GaN layer 308 is fully relaxed.
  • the thicker relaxed GaN-2 channel layer 308 may not provide any 2DHG at the interface between the GaN-2 channel layer 308 and the AIN buffer layer 304 (or the regrowth portion 304a). Moreover, a thick GaN-2 channel layer 308 may also reduce the back polarization effect on 2DEG concentration at the interface between the barrier layer 310 and the GaN-2 channel layer 308. The reduced back polarization may offer freedom to design the barrier layer 310 to achieve the required 2DEG and mobility.
  • the barrier layer 310 may be fully strained or lattice matched to the GaN-2 channel layer 308.
  • the concentration of the dopant in the cap layer 314 may be of any suitable value, e.g. any value greater than 10 18 cm' 3 .
  • the cap layer 314, the barrier layer 310, the channel layer 308 and the regrowth portion 304a may form a n- channel portion of the hetero structure.
  • FIG. 3B is a schematic of the hetero structure shown in FIG. 3 A after reactive ion etching (RIE) or inductive coupled plasma-reactive ion etching (ICP-RIE) according to various embodiments.
  • the GaN cap layer 314 may be etched such that the remaining unetched portions form source electrode 314a and drain electrode 314b.
  • the cap layer 312 may be etched such that the remaining unetched portions form source electrode 312a and drain electrode 312b. Accordingly, the p-channel portion of the hetero structure may form a p-channel transistor, while the n-channel portion of the heterostructure may form a n-channel transistor.
  • FIG. 4A is a schematic of another hetero structure according to various embodiments.
  • the heterostructure may include an AIN buffer layer 404 epitaxially grown over a substrate 402.
  • the substrate 402 may include AIN.
  • the AIN buffer layer 404 and the AIN substrate 402 may form a monolithic structure.
  • a GaN-1 channel layer 406 (fully strained) may be coherently grown over the AIN buffer layer 404 (or substrate 402) to achieve 2DHG at GaN/AlN interface. As there is no other barrier layer on top of the coherently grown GaN channel layer 406, the 2DHG may be achieved unambiguously.
  • the channel layer 406 and the region of the buffer layer 404 in which the channel layer 406 is over may form a p-channel portion of the hetero structure.
  • the as-grown wafer may be patterned and masked using dielectric materials such as silicon dioxide (SiO2) or silicon nitride (SiN) in the areas where 2DHG needs to be preserved.
  • dielectric materials such as silicon dioxide (SiO2) or silicon nitride (SiN)
  • ICP-RIE inductive coupled plasma-reactive ion etching
  • RIE reactive ion etching
  • An AlN/relaxed GaN channel layer/barrier layer (AIN, ScAlN or ternary or quaternary )/GaN cap layer heterostructure may be grown in the unmasked areas.
  • An AlN/relaxed GaN channel layer/barrier layer (AIN, ScAlN or ternary or quaternary )/GaN cap layer heterostructure may be grown in the unmasked areas.
  • a thin AIN portion 404a may be regrown from the AIN buffer layer 404 using epitaxial growth methods such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) techniques. Regrowth of AIN may help avoid parallel conduction due to the regrowth interface.
  • the thickness of the GaN-2 channel layer 408 may be selected such that the GaN layer 408 is fully relaxed.
  • the thicker relaxed GaN-2 channel layer 408 may not provide any 2DHG at the interface between the GaN-2 channel layer 408 and the AIN buffer layer 404 (or the regrowth portion 404a). Moreover, a thick GaN-2 channel layer 408 may also reduce the back polarization effect on 2DEG concentration at the interface between the barrier layer 410 and the GaN-2 channel layer 408. The reduced back polarization may offer freedom to design the barrier layer 410 to achieve the required 2DEG and mobility.
  • the barrier layer 410 may be fully strained or lattice matched to the GaN-2 channel layer 408.
  • a GaN cap layer 414 may be deposited on the barrier layer 410.
  • the cap layer 414, the barrier layer 410, the channel layer 408 and the regrowth portion 404a may form a n-channel portion of the hetero structure.
  • portions of the fully relaxed channel layer 408 may be doped with n- type dopants to form a source region and a drain region, such that the n-channel portion forms a n-channel transistor.
  • portions of the fully strained channel layer 406 may be doped with p-type dopants to form a further source region and a further drain region, such that the p- channel portion forms a p-channel transistor.
  • FIG. 4B is a schematic of the heterostructure shown in FIG. 4A according to various embodiments, but in which the interface between the fully relaxed channel layer 408 and the regrowth portion 404a of the buffer layer 404 is at a same level as the interface between the fully strained channel layer 406 and the second region of the buffer layer 404.
  • the heterostructure may also include the substrate 402, the barrier layer 410 and the cap layer 414.
  • FIG. 4A shows the hetero structure in which the interface between the fully relaxed channel layer 408 and the regrowth portion 404a of the buffer layer 404 is at a lower level compared to the interface between the fully strained channel layer 406 and the second region of the buffer layer 404.
  • the structures in FIG. 4A or 4B may result primarily depending on the amount of AIN that is etched prior to regrowth.
  • FIG. 5 is a schematic of yet another hetero structure according to various embodiments.
  • the hetero structure may include an AIN buffer layer 504 epitaxially grown over a substrate 502.
  • the substrate 502 may include AIN.
  • the AIN buffer layer 504 and the AIN substrate 502 may form a monolithic structure.
  • a GaN- 1 channel layer 506 (fully strained) may be coherently grown over the AIN buffer layer 504 (or substrate 502) to achieve 2DHG at GaN/AlN interface. As there is no other barrier layer on top of the coherently grown GaN channel layer 506, the 2DHG may be achieved unambiguously.
  • the channel layer 506 and the region of the buffer layer 504 in which the channel layer 506 is over may form a p-channel portion of the heterostructure.
  • the as-grown wafer may be patterned and masked using dielectric materials such as silicon dioxide (SiO2) or silicon nitride (SiN) in the areas where 2DHG needs to be preserved.
  • dielectric materials such as silicon dioxide (SiO2) or silicon nitride (SiN)
  • ICP-RIE inductive coupled plasma-reactive ion etching
  • RIE reactive ion etching
  • An AlN/relaxed GaN channel layer/barrier layer (AIN, ScAlN or ternary or quaternary )/GaN cap layer heterostructure may be grown in the unmasked areas.
  • a thin AIN portion 504a may be regrown from the AIN buffer layer 504 using epitaxial growth methods such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) techniques. Regrowth of AIN may help avoid parallel conduction due to the regrowth interface.
  • the thickness of the GaN-2 channel layer 508 may be selected such that the GaN layer 508 is fully relaxed. The thicker relaxed GaN-2 channel layer 508 may not provide any 2DHG at the interface between the GaN-2 channel layer 508 and the AIN buffer layer 504 (or the regrowth portion 504a).
  • a thick GaN-2 channel layer 508 may also reduce the back polarization effect on 2DEG concentration at the interface between the barrier layer 510 and the GaN-2 channel layer 508.
  • the reduced back polarization may offer freedom to design the barrier layer 510 to achieve the required 2DEG and mobility.
  • the barrier layer 510 may be fully strained or lattice matched to the GaN-2 channel layer 508.
  • a cap layer 514 may be deposited on the barrier layer 510. The cap layer 514, the barrier layer 510, the channel layer 508 and the regrowth portion 504a may form a n-channel portion of the hetero structure.
  • n++ regrown contacts 516a, 516b may be present on the 2DEG portion of the heterostructure while p++ regrown contacts 518a, 518b may be present on the 2DHG portion of the heterostructure.
  • the n++ regrown contacts 516a, 516b may act as the source electrode and the drain electrode of the n-channel transistor based on the n-channel portion, while the P++ regrown contacts 518a, 518 may act as the source electrode and the drain electrode of the p-channel transistor based on the p-channel portion.
  • the contacts 516a, 516b may be doped with a n-type dopant such as silicon (Si) or germanium (Ge).
  • the concentration of the n-type dopant may be of any suitable value, e.g. any value greater than 10 19 cm' 3 .
  • the contacts 518a, 518b may be doped with a p-type dopant such as magnesium.
  • the concentration of the p-type dopant may be of any suitable value, e.g. any value greater than 5 x 10 19 cm' 3 .
  • p-type doping and p-channel transistors were achieved through three methods: (1) Mg-doped GaN channel; (2) Polarization induced 2DHG at the hetero-interface of GaN and ternary or quaternary barrier layers; and (3) Polarization induced 2DHG at GaN and AIN hetero -interface.
  • Methods (1) and (2) result in poor conductivity and hence limiting their suitability for high performance p-channel transistors and complementary technology.
  • method 3 demonstrated high conductivity hole gas at the interface of fully strained GaN on AIN, and hence it is more suitable for the development of p-channel transistors and complementary technology.
  • the previously proposed method and the hetero structure has the following limitations to implementing nitride’s complementary technology.
  • nitride complementary technology
  • to access the buried-2DHG it is necessary to eliminate the 2DEG at the top AlN/GaN interface by etching the top AIN barrier layer.
  • Such recess etching leads to recess etch control and reproducibility complications.
  • the recess etch exposed area may lead to the alteration of surface states of the p-channel GaN layer, which may affect the formation or reduction of high concentration 2DHG.
  • the n-channel transistor always has an active 2DHG at the bottom GaN/AlN interface.
  • the 2DHG may limit the n-type transistor operation due to parallel conduction.
  • the GaN thickness should be relatively thinner for maintaining coherent growth over the AIN buffer and to achieve a high conductance p-channel layer.
  • the proximity of negative polarization of the bottom GaN/AlN interface may affect the formation and concentration of 2DEG present at the top AlN/GaN interface.
  • the concentration of 2DEG and 2DHG are interdependent, as the polarization charges at the corresponding interfaces are close to each other. This interdependence may severely limit the design of the individual n-type and p-channel transistors.
  • the 2DHG may need not be accessed or achieved by the removal of the 2DEG or by etching the top-barrier layer.
  • recess etch control of the AIN layer and reproducibility complications with recess etching may be eliminated.
  • various embodiments may provide unambiguous formation of 2DHG if the GaN channel is grown coherently over the AIN buffer layer.
  • the thicker GaN channel in the n-channel transistor heterostructure may reduce the negative polarization effect of the bottom GaN/AlN interface on the top 2DEG, resulting in not only a higher concentration of 2DEG, but also a better control over the design of the top barrier for n- channel transistors.
  • the interdependency of 2DEG and 2DHG on each other may have been reduced or eliminated, thus providing independent control over the design of n-channel transistors and p-channel transistors for developing complementary technology on AIN buffer/ substrate.
  • FIG. 6 shows the schematic of a cross-section of the unintentionally doped (UID) gallium nitride/aluminum nitride (GaN/AlN) heterostructure according to various embodiments.
  • the studied GaN/AlN HEMT heterostructures were grown using the plasma assisted-molecular beam epitaxy (PA-MBE) growth technique on 1” x 1” Si- face 4H-SiC substrate. It should be noted that Si-face SiC substrates result in metal-polar heterostructures.
  • PA-MBE plasma assisted-molecular beam epitaxy
  • the epi-structure growth started with a 200 nm thick AIN buffer layer, grown in extremely nitrogen-rich (N-rich) growth conditions (IIVV « 1) to avoid Si carryover from the SiC substrate to the GaN/AlN interface.
  • N-rich extremely nitrogen-rich
  • Reflection high energy electron diffraction (RHEED) showed a bright spotty pattern during N-rich AIN layer growth.
  • N-rich nitrogen-rich
  • a 100 nm thick AIN layer was grown in slightly metal-rich growth conditions to achieve 2D growth mode. RHEED patterns become streaky for the 2D AIN growth.
  • any excess Al metal on the surface of the AIN layers was consumed by opening the plasma source to the substrate for 1 min.
  • Capacitance-voltage (C-V) measurements were performed to further confirm the presence and absence of 2DHG in the sample with coherently grown (sample (c)) and relaxed GaN layer (sample (a)), respectively.
  • FIG. 9 shows a plot of capacitance (x IO 10 Farads or F) as a function of applied bias (in volts or V) illustrating the capacitance-voltage (C-V) measurements on samples (a) and (c) according to various embodiments, with the inset showing an optical microscopy image of the contact.
  • C-V measurements were performed on a circular titanium Ti (40 nm)/gold Au (250 nm) Schottky contact of 300 pm diameter with surrounded ohmic contact of nickel Ni (50 nm)/gold Au (100 nm), as shown in the inset of FIG. 9.
  • the Ni/Au ohmic contact was annealed in the oxygen atmosphere at 450 °C.
  • C-V measurements were performed from -1 to 5 V at the frequency of 5 KHz. As shown in FIG.
  • the coherently grown GaN layer shows the presence of charge with a large capacitance value, while the sample grown with the relaxed GaN layer (sample (a)) results in almost constant and very low capacitance, an indication of the absence of the charge in the heterostructure.
  • the capacitance obtained for sample (c) at 0 V is only half of the value expected for a sample with a Schottky contact with 300 pm and a GaN channel thickness of 11 nm.
  • the lower capacitance could be due to the high contact resistance of Ni/Au ohmic contact.
  • a p++ GaN layer may be useful under the Ni/Au ohmic contact.
  • the 2DHG concentration in GaN/AlN hetero structure is simulated as a function of GaN layer thickness and GaN surface potentials (((>) of 0.5, 1.0, 1.5, 2.0, and 2.5 eV using the 1-dimensional Poisson-Schrodinger solver.
  • the simulated 2DHG data closely matches with the simulated data from a previous study.
  • the 2DHG measurements of samples (c) and (d) are also plotted on the same plot to extract the GaN surface potential for samples (c) and (d).
  • FIG. 10 shows a plot of two-dimensional hole gas (2DHG) concentration (x 10 13 per square centimeters or cm -2 ) as a function of gallium nitride (GaN) thickness (in nanometers or nm) illustrating the variation of 2DHG concentration with channel thickness for different GaN surface potentials (([)) of 0.5, 1.0, 1.5, 2.0, and 2.5 eV according to various embodiments.
  • Experimentally obtained hole gas concentrations are also plotted as scattered points.
  • the surface potential of the GaN channel layer in the GaN/AlN hetero structure lies between 1.5 eV and 2.0 eV. This value is closely matched with the surface potential obtained for similar heterostructures with 2DHG at GaN/AlN interface.
  • the surface potential may be closer to the middle of the GaN band gap-
  • FIG. 11 shows a schematic of a gallium nitride/aluminum nitride/ gallium nitride/aluminum nitride (GaN/AlN/GaN/AlN) heterostructure on the silicon carbide (SiC) substrate according to various embodiments.
  • the formation of 2DEG in GaN-cap/AlN barrier/fully relaxed GaN/AlN heterostructure and GaN-cap/AlN barrier/coherently grown GaN/AlN hetero structure may be investigated. Hence, two heterostructures were grown, samples (e) and (f).
  • the epilayer structure of sample (e) is GaN (1 nm)/ AIN (5.9 nm)/GaN (62 nm)/ AIN (300 nm).
  • the epilayer structure of the sample (f) is GaN (2.6 nm)/ AIN (6 nm)/GaN (10 nm)/ AIN (300 nm).
  • XRD RSM mapping of the samples (e) and (f) are presented in FIG. 12.
  • FIG. 12 shows (a) a plot of z-axis Q z (* 10 7 , in relative lattice units or rlu) as a function of x-axis Q x (* 10 7 , in relative lattice units or rlu) illustrating the X-ray diffraction reciprocal space mapping (XRD RSM) along the gallium nitride GaN (105) plane of sample (e) according to various embodiments; and (b) a plot of z-axis Q z (* 10 7 , in relative lattice units or rlu) as a function of x-axis Q x (* 10 7 , in relative lattice units or rlu) illustrating the X-ray diffraction reciprocal space mapping (XRD RSM) along the gallium nitride GaN (105) plane of sample (f) according to various embodiments.
  • Sample (e) showed a relaxed GaN channel layer, while sample (f) showed a coherently
  • FIG. 13 shows a table summarizing the results of Hall effect measurements performed on sample (e) and sample (f) according to various embodiments.
  • sample (e) with a relaxed GaN channel layer showed a higher 2DEG concentration of 3.94 x 10 13 cm’ 2 .
  • sample (f) with a coherently grown GaN layer showed a lower 2DEG concentration of only 0.5 x 10 13 cm’ 2 .
  • Poisson-Schrodinger (PS) simulations were performed.
  • a GaN cap surface potential of 0.6 eV was assumed based on the calibration of the PS simulator using the 2DEG density obtained from a baseline GaN cap/AlGaN/GaN HEMT heterostructure, grown using PA-MBE growth system.
  • Ec, EF and Ev represent the conduction band, Fermi level and valence band respectively.
  • simulation results also showed a higher 2DEG sheet carrier concentration of 4.46 x 10 13 cm’ 2 for sample (e), while sample (f) showed a lower 2DEG sheet carrier concentration of 0.76 x 10 13 cm’ 2 .
  • the PS simulations confirmed that the observed difference in the 2DEG concentration between samples (e) and (f) is expected for these heterostructures.
  • the simulated values are slightly different when compared with the obtained 2DEG concentration.
  • the surface potential is fixed in these simulations. Hence, to accurately get the 2DEG concentration, it is necessary to change the surface potential. However, the change of surface potential is not discussed here.
  • sample (e) and sample (f) can be mainly attributed to the effect of negative polarization due to the back GaN/AlN interface. It should be noted that a similar net negative polarization charge exists at the bottom GaN/AlN interface of both samples (e) and (f). However, for sample (e), its thicker GaN channel reduces the negative polarization effect on the 2DEG, resulting in lesser depletion and hence, a higher 2DEG concentration of 3.94 x 10 13 cm’ 2 as shown in FIG. 13.
  • the lower 2DEG concentration in sample (f) can be attributed to the greater depletion of the 2DEG in sample (f), where thin GaN channel brings negative polarization charge much closer to the 2DEG, resulting in its greater depletion.
  • both heterostructures of samples (e) and (f) should result in a high concentration of 2DHG at the back GaN/AlN interface.
  • the GaN channel layer in the sample (e) is relaxed.
  • no 2DHG may exist at this interface.
  • the heterostructure with GaN cap/ AIN barrier/fully strained GaN/AlN buffer of sample (f) should have high 2DHG at the bottom GaN/AlN interface.
  • the previously proposed method suggested that this high concentration of buried-2DHG provides the necessary charge for p-channel GaN HEMT heterostructure.
  • the presence of buried-2DHG results in parallel conduction and uncertainty over the measured carrier concentration and mobility in the Hall measurements of these heterostructures.
  • the total integrated carrier concentration is approximately 0.41 x 10 13 cm' 2 , which is of similar order as that of the measured carrier concentration of 0.5 x 10 13 cm’ 2 .
  • the 2DEG concentration obtained using Hall measurements on this sample is indeed reasonable, and there is no parallel conduction effect of 2DHG in the Hall measurements.
  • FIG. 16A shows a schematic of a N-polar high-electron-mobility transistor (HEMT) heterostructure according to various embodiments.
  • FIG. 16B shows a plot of energy bands Ec, 1 EF, EV (in electron-volts or eV) / carrier concentration n s (x IO 20 per cubic centimeter or cm -3 ) as a function of thickness/depth from surface (in nanometers or nm) illustrating the simulated energy band profiles as well as the simulated two-dimensional electron gas (2DEG) and two- dimensional hole gas (2DHG) distribution as a function of thickness/depth according to various embodiments.
  • the energy band diagrams as well as 2DEG and 2DHG distributions are obtained from the PS simulation.
  • FIG. 16C shows a plot of capacitance (x IO 10 Farads or F) / integrated charge (x 10 12 per square centimeter or cm -2 ) as a function of applied bias (in Volts or V) illustrating capacitance and integrated charge as a function of applied bias obtained using a Schottky contact of 100 pm diameter according to various embodiments.
  • FIG. 16D shows a plot of carrier concentration (per cubic centimeter or cm -3 ) as a function of thickness/depth (in nanometers or nm) illustrating the estimated carrier concentration from capacitance-voltage (C-V) measurements as a function of sample depth/thickness.
  • FIG. 17 shows a table summarizing the Hall measurements on N-polar high-electron-mobility transistor (HEMT) heterostructure.
  • HEMT high-electron-mobility transistor
  • the integrated carrier concentration is approximately 0.9 x 10 13 cm -2 , which is close to that of the Hall measurement carrier concentration of 0.93 x 10 13 cm' 2 .
  • the matching of carrier concentration from Hall and C-V measurements indicates that there is no parallel conduction effect of 2DHG in the Hall measurements.
  • FIG. 16D of the carrier concentration profile as a function of thickness it can also be noted that there is no buried- 2DHG at the negatively polarized AlGaN/GaN interface. As suggested previously, presence of 2DHG will not allow the depletion to continue into the GaN buffer layer.
  • N-vacancies with deep-donor character may act as efficient hole traps.
  • the presence of hole trap states at the negative polarization interface of a Ga-polar dualchannel AlGaN/GaN HEMT heterostructure has been demonstrated through deep-level transient spectroscopy measurements. In this heterostructure, hole gas is supposed to exist at this negative polarization interface according to conventional thinking. However, the direct evidence of the presence of hole traps may be proof for the absence of buried-2DHG underneath 2DEG at the negative polarization interface in Ga-polar heterostructures.
  • the buried 2DHG may not be present, and to replenish the 2DHG, reactive ion etching of the top GaN/AlN epilayers may be necessary.
  • the pseudomorphic GaN channel on the AIN platform may provide unambiguous 2DHG
  • regrown GaN-cap/top-barrier/relaxed GaN/AlN hetero structure may provide 2DEG.
  • this may provide independent design and control of high conductivity 2DEG and 2DHG over the AIN buffer layer/substrate, which is not provided by the earlier proposed technologies.
  • this methodology may establish unambiguous and reproducible 2DHG without the need for removing 2DEG on the top of the heterostructure.
  • the proposed methodology may provide a better way of achieving complementary technology with high-conductivity p-channel transistors.
  • Complementary transistor technology using wide bandgap semiconductor materials like the one described in this work, enables electronic circuit’s operation at higher voltages- reducing the necessity of voltage step-down stages in power electronics and logic circuits.
  • Electronic circuits with fewer stepping-down stages are both compact and an environmental- friendly energy-saving approach.
  • the ever-expanding digital technology-based industries, such as the mobile phone industry, laptops, chargers, and display technologies, can be directly impacted by the proposed technology developed in this investigation. For example, owing to the effective power conversion, mobile phones and laptops will have longer-lasting batteries and will be much smaller. Additionally, implementing the suggested nitride complementary technology in lieu of current generation CMOS technology in the data centers will reduce the enormous amounts of electricity consumption.
  • Nitride based complementary technology is also advantageous to be used in mobile communication sectors with frequency of operation in the 5G and beyond-5G spectrum. This technology not only enables faster operations of the mobile base stations but also makes them energy efficient and compact. The proposed technology may also play a vital role in electric vehicles, where power management applications are necessary. [0098] In addition to civil applications, various embodiments may have a major impact on defense and space industries, where integrated electronics may require operations in harsh environments. The developed nitride complementary technology may be operated at higher temperatures and in harsh environments. Hence, various embodiments involving nitride complementary technology based on AIN buffer layer/ AIN substrate may have a significant influence on the electronic sector and may be able to meet the demands of future civil and defense applications.

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

Divers modes de réalisation peuvent concerner une hétérostructure comprenant un substrat et une couche tampon sur le substrat, une première région de la couche tampon ayant une partie de recroissance. L'hétérostructure peut en outre comprendre une couche de canaux entièrement contrainte sur une seconde région de la couche tampon de telle sorte qu'un gaz de trous bidimensionnels est formé au niveau d'une interface entre la couche de canaux complètement contrainte et la seconde région de la couche tampon. L'hétérostructure peut en outre comprendre une couche de canaux entièrement relâchée sur la partie de recroissance de la couche tampon. L'hétérostructure peut également comprendre une couche barrière entièrement contrainte ou correspondant complètement en réseau sur la couche de canaux entièrement relâchée de telle sorte qu'un gaz d'électrons bidimensionnels est formé au niveau d'une interface entre la couche barrière entièrement contrainte ou correspondant complètement en réseau et la couche de canaux entièrement relâchée, la première région de la couche tampon comprenant la partie de recroissance.
PCT/SG2023/050743 2022-12-08 2023-11-09 Hétérostructure et son procédé de formation Ceased WO2024123239A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP23901207.3A EP4643394A1 (fr) 2022-12-08 2023-11-09 Hétérostructure et son procédé de formation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10202260366P 2022-12-08
SG10202260366P 2022-12-08

Publications (1)

Publication Number Publication Date
WO2024123239A1 true WO2024123239A1 (fr) 2024-06-13

Family

ID=91380393

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2023/050743 Ceased WO2024123239A1 (fr) 2022-12-08 2023-11-09 Hétérostructure et son procédé de formation

Country Status (2)

Country Link
EP (1) EP4643394A1 (fr)
WO (1) WO2024123239A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030102482A1 (en) * 2001-12-03 2003-06-05 Saxler Adam William Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors
US20180138303A1 (en) * 2016-11-11 2018-05-17 Robert L. Coffie Transistor structure including a scandium gallium nitride back-barrier layer
US20210098615A1 (en) * 2019-10-01 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integration of p-channel and n-channel e-fet iii-v devices without parasitic channels
US20210249513A1 (en) * 2018-07-20 2021-08-12 Cornell University Polarization-induced 2d hole gases for high-voltage p-channel transistors
US20210343703A1 (en) * 2020-05-04 2021-11-04 Massachusetts Institute Of Technology Semiconductor device with linear parasitic capacitance
US20220199782A1 (en) * 2020-12-19 2022-06-23 Cornell University Integrated electronics on the aluminum nitride platform

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030102482A1 (en) * 2001-12-03 2003-06-05 Saxler Adam William Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors
US20180138303A1 (en) * 2016-11-11 2018-05-17 Robert L. Coffie Transistor structure including a scandium gallium nitride back-barrier layer
US20210249513A1 (en) * 2018-07-20 2021-08-12 Cornell University Polarization-induced 2d hole gases for high-voltage p-channel transistors
US20210098615A1 (en) * 2019-10-01 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integration of p-channel and n-channel e-fet iii-v devices without parasitic channels
US20210343703A1 (en) * 2020-05-04 2021-11-04 Massachusetts Institute Of Technology Semiconductor device with linear parasitic capacitance
US20220199782A1 (en) * 2020-12-19 2022-06-23 Cornell University Integrated electronics on the aluminum nitride platform

Also Published As

Publication number Publication date
EP4643394A1 (fr) 2025-11-05

Similar Documents

Publication Publication Date Title
Choi et al. The effect of an Fe-doped GaN buffer on off-state breakdown characteristics in AlGaN/GaN HEMTs on Si substrate
Egawa et al. Characterizations of recessed gate AlGaN/GaN HEMTs on sapphire
Medjdoub et al. Barrier-layer scaling of InAlN/GaN HEMTs
Dang et al. Measurement of drift mobility in AlGaN/GaN heterostructure field-effect transistor
Roul et al. Binary group III-nitride based heterostructures: band offsets and transport properties
US9780181B1 (en) Semiconductor device with multi-function P-type diamond gate
Kaun et al. Molecular beam epitaxy for high-performance Ga-face GaN electron devices
WO2013147710A1 (fr) Structures de transistor à grande mobilité d'électrons à base de nitrure du groupe iii et leur procédé de fabrication
Hao et al. Nitride wide bandgap semiconductor material and electronic devices
Jiang et al. Exploring an approach toward the intrinsic limits of GaN electronics
Hahn et al. Charge balancing in GaN-based 2-D electron gas devices employing an additional 2-D hole gas and its influence on dynamic behaviour of GaN-based heterostructure field effect transistors
He et al. Correlating device behaviors with semiconductor lattice damage at MOS interface by comparing plasma-etching and regrown recessed-gate Al2O3/GaN MOS-FETs
Ravikiran et al. Growth and characterization of AlGaN/GaN/AlGaN double-heterojunction high-electron-mobility transistors on 100-mm Si (111) using ammonia-molecular beam epitaxy
Wang et al. Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors
Xing et al. Normally-OFF AlGaN/GaN-based HEMTs with decreasingly graded AlGaN cap layer
Varghese et al. Impact of AlN interlayer's in epitaxial and passivation scheme on the DC and microwave performance of doping-less GaN HEMT
Chettri et al. Demonstration of aluminum nitride metal oxide semiconductor field effect transistor on sapphire substrate
Kurt et al. Investigation of a hybrid approach for normally-off GaN HEMTs using fluorine treatment and recess etch techniques
WO2024123239A1 (fr) Hétérostructure et son procédé de formation
JP6941903B1 (ja) ノーマリーオフ型分極超接合ＧａＮ系電界効果トランジスタおよび電気機器
Edwin Characterization and Numerical Simulation of Gallium Nitride-Based Metal-Oxide-Semiconductor High Electron Mobility Transistor with High-K Gate Stack
Shivam et al. High-Performance Analysis of Recessed Gate AlN/β-Ga 2 O 3 HEMT
Gülseren Design, Fabrication, and Characterization of Normally-off Gan Hemts
Gatabi Tunnel MOS Heterostructure Field Effect Transistor for RF Switching Applications
Yang Advanced Electronic Devices based on Wide/Ultra-Wide Bandgap Semiconductor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23901207

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 2023901207

Country of ref document: EP