WO2024117713A1 - Memory device for efficiently performing dram internal row shuffle - Google Patents

Abstract

A memory device for efficiently performing a DRAM internal row shuffle of the present invention is a technology that proposes a DRAM internal structure that supports quickly performing a DRAM internal row shuffle operation. A DRAM structure proposed in the present invention uses an isolation transistor to allow fast access to one specific row for each subarray, and pairs two subarrays such that fast-accessible row data from each subarray can be accessed from the other paired subarrays. The present invention may optimize a row hammer prevention technology through the DRAM internal row shuffle. The present invention is implemented inside a DRAM and may be further optimized for specific characteristics of each DRAM device.

Description

Memory device to efficiently perform DRAM internal row shuffle

The present invention is a technology that proposes a DRAM internal structure that supports quickly performing a DRAM internal row shuffle operation. The DRAM structure proposed in the present invention uses an isolation transistor to quickly access one specific row for each subarray, and pairs two subarrays to pair data in rows that can be accessed quickly in each subarray. Allows quick access from other built subarrays. Using the present invention, row hammer prevention technology through DRAM internal row shuffle can be optimized. The present invention can be implemented inside DRAM and further optimized to suit the specific characteristics of each DRAM device.

The present invention optimizes the DRAM internal row shuffle operation and accelerates the mapping process between the physical address of the host machine and the DRAM internal device address. In addition, the present invention is applicable to all types of DRAM, and can be applied not only to the RFM interface but also to DRAM using a next-generation memory interface such as CXL (Compute eXpress Link). In terms of security regarding mapping information, storage It can be applied to all storage media such as .

Recently, as the DRAM process has become more refined, the row hammer problem has become more severe, and DRAM manufacturers must solve the row hammer problem more efficiently. In addition, solving the row hammer problem in a memory controller is costly because it cannot take into account the different characteristics of each DRAM device and must be approached conservatively, and additional information about adjacent rows is required because the internal mapping and structure of the DRAM is not known. Therefore, the need to solve the row hammer problem inside DRAM is emerging, and the present invention can be fully utilized by DRAM manufacturers as it can solve the row hammer problem with low performance degradation and high energy efficiency inside DRAM.

Figure 1 is a diagram showing a DRAM-based main memory architecture.

Referring to FIG. 1, the DRAM-based main memory system is hierarchically structured with multiple memory channels, ranks, and banks, and is connected to a memory controller. Each bank is a two-dimensional array of DRAM cells and is composed of multiple subarrays to efficiently manage the cells. Each cell is indexed by row and column address by wordline and bitline. A subarray is a set of rows that share a bit line. In each subarray, there is a bitline sense amplifier that amplifies and temporarily stores the cell data of the selected row. The bit line sense amplifier of each subarray is connected to the global data line (global IO, GIO) through the local data line (local IO, LIO). The DRAM device first performs row activation to process memory requests. Row activation selects a subarray within a bank through a global row decoder and selects a specific row within the subarray through a local row decoder. In the column decoder, a specific column is finally selected by activating a specific column select line.

DRAM address mapping

The physical address in the host processor passes through the memory controller and the DRAM device and is finally converted into a specific DRAM device address. The host processor divides the physical address into channel, rank, bank, row, and column addresses through a unique method, and through this, utilizes parallelism to efficiently access DRAM memory. When a physical address reaches a DRAM device, the DRAM row decoder maps the given physical address to a specific device address, and this mapping method may vary depending on the DRAM manufacturer or device. Additionally, the mapping of physical addresses to device addresses is more complex because DRAM manufacturers use spare rows and columns to provide resiliency by remapping defective cells. However, the mapping of these physical addresses to device addresses is generally static.

low hammer attack

Modern DRAM devices are vulnerable to raw hammer attacks that corrupt data in DRAM cells. A row hammer attack utilizes the electrical interference phenomenon between adjacent rows, repeatedly activating a specific row (aggressor row) to cause a bit flip in an adjacent row (victim row). . Row hammer attacks are a powerful threat to computer systems because they arbitrarily change data values stored in memory and can cause data corruption and system errors. The minimum number of activations that cause the low hammer phenomenon is called the hammer count. According to a recent study [TRRespass], the activation of one row not only affects adjacent rows, but also non-adjacent but nearby rows. This effect on non-adjacent rows is called a blast attack, and the attack radius is called the blast radius.

Low hammer prevention technology

Industry and academia are proposing many solutions to prevent row hammer. Solutions to prevent row hammer primarily use one of three technologies: The first technique is target row refresh (TRR). TRR is a technology that additionally refreshes specific rows to prevent bit flips due to row hammering. In general, there is a counter that counts the number of ACTs on the rows, and TRR is performed when a certain value (threshold) is reached [CBT, TWiCe, Graphene], or TRR is performed with a certain probability for each row activation [PARA]. The second technology is throttling, which modifies the scheduler of the memory controller to select threads with a lot of memory access and prevents the thread from accessing memory to a specific row [BlockHammer]. The third technology is row-shuffle, which selects attack rows with high activation and swaps them with other rows [RRS]. Using row shuffle, the mapping between physical addresses and device addresses can be continuously changed, making it impossible for a row hammer attacker to attack the desired row. However, in the case of [RRS], due to the limited size of the remapping table, the mapping information is restored after a certain row shuffle, allowing the attacker to attack the desired row again.

Solutions to prevent row hammer can be implemented on the memory controller side or DRAM side using the above technologies. When implemented on the memory controller side, it has the advantage of being able to be implemented through a logic process that is faster than the DRAM process and easier in terms of area, and can receive help from the system. However, since one memory controller is generally responsible for multiple DRAM devices, activation counters for all DRAM devices handled by the memory controller are required, resulting in a large area burden. In addition, since different hammer counts and blast radii cannot be applied differently for each DRAM device, conservative characteristic values must be considered for defense, resulting in large area and performance overhead. When implemented on the DRAM side, row hammer attacks can be prevented more efficiently by considering the internal characteristics of each DRAM device. Additionally, a row hammer prevention solution can be built using only the device address, without considering the mapping between the physical address and the device address. However, in the existing interface between the processor and memory where the memory is passive, the implementation on the DRAM side is limited due to timing constraints.

R.F.M.

Recently, an interface called RFM (ReFresh Management) was added to DDR5, LPDDR5, and HBM3. In this interface, the memory controller periodically sends RFM commands to DRAM according to the set activation number (RAAIMT) of each bank and provides a certain timing margin to the DRAM device. When DRAM receives an RFM command, it can automatically perform operations to prevent row hammer at a given timing. This RFM interface enables cooperation between the memory controller and DRAM in row hammer prevention and facilitates memory-side implementation of row hammer prevention solutions.

[Prior Art Document] Republic of Korea Patent Publication No. 2385443 “Selective row hammer refresh device and method for preventing counter-based row hammer” (registered on April 6, 2022)

The memory device for efficiently performing internal DRAM row shuffling, which was developed to solve the above-described problems, prevents row hammering by implementing row shuffling inside DRAM, and at the same time overcomes the disadvantages of implementing row shuffle on the memory controller side. The purpose is to avoid being influenced by .

In addition, the memory device for efficiently performing DRAM internal row shuffling of the present invention aims to prevent row hammering by preventing row hammer attackers from knowing the mapping information of DRAM rows through effective DRAM internal row shuffling.

In addition, the memory device for efficiently performing DRAM internal row shuffle of the present invention optimizes the DRAM internal row shuffle operation, accelerates the mapping process between the physical address of the host machine and the DRAM internal device address, and is applicable to all types of DRAM. The purpose is to make it possible.

A memory device for efficiently performing DRAM internal row shuffling according to the present invention to achieve the above-described object includes: a memory controller; and a plurality of pairs of subarrays to which subarray pairing is applied, in which the remapping rows of the target subarray are placed in a pair subarray paired with the target subarray, and the remapping rows include the physical addresses of the rows and the DRAM device address. A DRAM device storing mapping information, wherein when receiving an activation (ACT) command from a memory controller, the DRAM device first activates a remapping row to read the mapping information of the target row, and then reads the mapping information of the target row. The target row is activated using the device address of the information, and activation (ACT) instructions are continuously generated. When a row hammer prevention instruction is received from the memory controller, the remapping row of the pair subarray is searched and many activations (ACT) are generated. Find out the DRAM device address of the target aggressor row that is determined to have occurred, perform row shuffling of the target aggressor row in the target subarray, and remap rows in the pair subarray while row shuffling is being performed or when it is completed. It is characterized by updating the information.

Preferably, each of the pair of sub-arrays includes an isolation transistor located between the remapping row and other rows.

In the pair of sub-arrays, the bit line sense amplifier of one sub-array can transmit data because the local row decoder and the data line of the other sub-array are connected to each other.

The remapping row is preferably located closest to the bitline sense amplifier for fast activation.

In the row shuffle, when a DRAM device receives a row hammer prevention command, it selects the row with the largest ACT counter value as the target attack row, or rows in which ACT occurred from the previous row hammer prevention command to the current row hammer prevention command. A randomly selected row is selected as the target attack row, a random row is selected using a random number generator, and the data of the row selected as a random row is copied to an empty row. When copying is completed, the data of the target attack row is randomly selected. It is desirable to copy the rows and then update the changed positions in a remapping row that has mapping information for the rows according to the positions of the changed rows.

According to the present invention as described above, the row shuffle is implemented inside the DRAM to prevent row hammering, and at the same time, it is not affected by the disadvantages of implementing the row shuffle on the memory controller side. To efficiently perform the row shuffle inside the DRAM. A memory device may be provided.

In addition, according to the present invention, it is possible to provide a memory device for efficiently performing internal DRAM row shuffling, which prevents row hammering by preventing row hammer attackers from knowing the mapping information of DRAM rows through effective internal DRAM row shuffling. there is.

In addition, according to the present invention, a method for efficiently performing intra-DRAM row shuffling optimizes the DRAM internal row shuffle operation, accelerates the mapping process between the physical address of the host machine and the DRAM internal device address, and is applicable to all types of DRAM. A memory device may be provided.

To describe the effects of the present invention described above in more detail, the present invention reduces performance degradation and increases energy efficiency by accelerating DRAM internal row shuffling and access to remapped DRAM rows, thereby reducing costs. Unlike existing row hammer prevention technologies, DRAM internal row shuffle dynamically randomizes the mapping between the physical address of DRAM rows from the host processor and the DRAM internal device address, preventing row hammer attackers from creating sophisticated attack patterns. there is. However, each time row shuffling is performed, copying and shuffling a DRAM row of about 8 KB in size to another DRAM row may take a lot of time and energy. Additionally, because the mapping between the physical addresses of DRAM rows and the DRAM internal device address changes, additional time (delay) is required each time DRAM rows are accessed. The present invention effectively reduces the overhead of DRAM row shuffling.

Since the present invention can perform row shuffle, a row hammer prevention technology, inside DRAM, it is not affected by the shortcomings of existing row hammer prevention technologies implemented in a memory controller. Since the hammer count and blast radius of the DRAM device used can be known inside the DRAM, the present invention can be implemented with minimal area and performance overhead accordingly.

Figure 1 is a diagram showing a DRAM-based main memory architecture.

Figure 2 is a diagram showing the remapping row and isolation transistor in the sub-array of the present invention.

Figure 3 is an internal structure diagram of the DRAM of the present invention with isolation transistor and subarray pairing applied.

Figure 4 is a detailed diagram of the internal structure of the DRAM of the present invention in which the access time of the remapping row is reduced through pairing of an isolation transistor and a subarray.

Figure 5 is an operation flow chart of the row hammer prevention technology based on DRAM internal row shuffle in the DRAM internal structure of the present invention.

Figure 6 is an example of a row shuffle that operates during the row hammer prevention instruction of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings.

However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are merely provided to ensure that the disclosure of the present invention is complete and to be understood by those skilled in the art in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, a memory device for efficiently performing DRAM internal row shuffle according to an embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1 , the memory device 100 for efficiently performing DRAM internal row shuffle according to an embodiment of the present invention includes a memory controller 120 and a DRAM device 140.

Figure 2 is a diagram showing the remapping row and isolation transistor in the sub-array of the present invention.

Referring to FIG. 2, in the present invention, a remapping row is placed inside the DRAM to store mapping information of addresses that change due to row shuffling, through which the mapping information can be quickly accessed. In addition, it allows quick access to remapping rows through an isolation transistor, and uses subarray pairing to quickly read remapping information to activate changed DRAM rows. Through this, the DRAM internal structure proposed in the present invention can perform row shuffling within the DRAM quickly and energy efficiently.

Remapping Row

The remapping row stores mapping information between the physical addresses of DRAM rows and the DRAM device address. When the DRAM device receives the ACT command, it first activates the remapping row and reads the mapping information of the target row. Afterwards, the target row can be activated using the device address of the mapping information. Remapping rows cannot be accessed from the memory controller because they do not have a corresponding physical address in the host processor.

Isolation Transistor

To quickly activate the remapping row, place the remapping row closest to the bitline sense amplifier as shown in Figure 2 and place an isolation transistor between the remapping row and other rows. The biggest part of the latency of row activation is changing the voltage of a bitline with a long capacitance. Therefore, by using an isolation transistor, the length of the bit line that shares charge with the remapping row can be shortened, and through this, the time to activate the remapping row can be shortened.

Subarray Pairing

To speed up the search for remapping rows performed at each ACT command, the present invention utilizes subarray pairing. Subarray pairing involves pairing two subarrays and placing the remapping rows of one subarray in another subarray. Since each subarray has its own row buffer, rows can be independently activated or precharged for each subarray through slight changes inside the DRAM. Through this, in the target row activation process, which previously consisted of four steps: 1) remapping row activation, 2) remapping row read, 3) remapping row precharge, and 4) target row activation, using subarray pairing allows 3) remapping row Precharge can be performed simultaneously with 4) target row activation. Through this, the access time of remapping rows can be reduced.

Figure 3 is a diagram showing the internal structure of a DRAM of the present invention to which an isolation transistor and subarray pairing are applied. Referring to FIG. 3, in a subarray pair, the bitline sense amplifier of one subarray can transmit data because the data line is connected to the local row decoder of the other subarray.

Figure 4 is a detailed diagram of the internal structure of a DRAM according to the present invention in which the access time of a remapping row is reduced through pairing of an isolation transistor and a subarray.

Referring to FIG. 4, when searching for a remapping row, the bank controller inputs the corresponding column address from the remapping row to the column decoder based on the row address received. The mapping information in the remapping row can be input to the local row decoder of the paired subarray through the DEMUX (Demultiplexer) in each subarray. The controller manages remapping row searches, row copying, and general DRAM operations.

Figure 5 is an operation flow chart of the row hammer prevention technology based on DRAM internal row shuffle in the DRAM internal structure of the present invention.

The subarray in which the row to be activated by the activation (ACT) command sent from the memory controller 120 to the DRAM device 140 exists is defined as the target subarray, and the subarray paired with the target subarray is defined as a pair subarray.

Referring to FIG. 5, each time the memory controller 120 sends an ACT command to the DRAM device 140 (step S110), the DRAM device 140 searches for a remapping row in the pair subarray and stores it in the received target row physical address. Find the corresponding DRAM device address (step S120). Then, the corresponding target row is activated in the target subarray (step S130).

If ACT continues to occur and the memory controller 120 determines that a row hammer prevention operation is necessary, it sends a row hammer prevention command to the DRAM device 140. This row hammer prevention command may be an RFM command or a special command added to prevent row hammer.

That is, the memory controller 120 transmits an activation command (ACT command) that causes a specific DRAM bank to be activated to the DRAM device 140, and selects one of the plurality of ACT counters issued for each DRAM bank present in the memory controller. The ACT counter value of the specific DRAM bank is increased by 1 (step S140).

Next, when the ACT counter value reaches the refresh management threshold (RAAIMT) previously received from DRAM (step S150), RFM causes the memory controller 200 to perform a row hammer refresh (RH refresh) on the corresponding DRAM bank. A command is sent to the DRAM device (step S160).

When receiving the row hammer prevention command, the DRAM device 140 searches the remapping rows of the pair subarray to find the DRAM device address of the target aggressor row where it is determined that many ACTs have occurred (step S170). Then, row shuffling of target attack rows is performed in the target subarray. The target attack row may be selected based on a table counting the number of ACTs, or may be selected randomly (step S180). While row shuffling is being performed or when it is completed, the remapping row information is updated in the pair subarray (step S190).

Figure 6 is an example diagram of row shuffle that operates during the row hammer prevention instruction of the present invention.

Referring to FIG. 6, in this example, two row copies are performed for three rows each time a row hammer prevention instruction is issued. The three rows consist of a target aggressor row, a random row, and an empty row. Target attack rows are rows that are considered to have a lot of ACT, and are the main target of the row shuffle. Since the random row is randomly selected and shuffled with the target attack row, randomness is given to the DRAM mapping of the target attack row to prevent the row hammer attacker from attacking the target attack row again. An empty row is an additional row that is placed as a temporary buffer for row shuffling. Since empty rows do not have separate physical addresses, they cannot be accessed from the memory controller.

In the example above, when using the row hammer prevention command, row shuffle operates in the following order. First, when the DRAM device receives a row hammer prevention command, it selects a target attack row based on the ACT count of previous commands. At this time, the row with the largest ACT counter value can be selected, or one of the rows in which ACT has occurred from the previous row hammer prevention instruction to the current row hammer prevention instruction can be randomly selected. When selecting randomly, a random number generator is used. Additionally, the random row is selected using a random number generator. Afterwards, the data of the row selected as a random row is copied to an empty row. When copying is complete, the data of the row selected as the target attack row is copied to a random row. After two row copies are completed, the changed positions are updated in the remapping rows with mapping information of the corresponding rows according to the positions of the changed rows.

Accordingly, in the present invention, the target attack row where a lot of activation occurs is replaced with a row that the attacker does not know, making it difficult for the attacker to attack anymore. Additionally, if enough row shuffling occurs, it becomes difficult to use attack patterns using blast attacks because it becomes impossible to know how close the rows are.

As mentioned earlier, the time taken for the ACT command is reduced because the precharge time of the remapping row is covered by the target row activation time. In the case of the RFM command, search and update of remapping rows are performed in the pair subarray, and row shuffling is performed in the target subarray. The time used to search and update remapping rows may be obscured by the row shuffle execution time.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of the present invention is indicated by the scope of the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. must be interpreted.

[Explanation of symbols]

100: Memory device of the present invention 120: Memory controller

140: DRAM device 142: a pair of subarrays

Claims (5)

memory controller; and It includes a plurality of pairs of subarrays to which subarray pairing is applied, in which the remapping rows of the target subarray are placed in a pair subarray paired with the target subarray, and the remapping rows include mapping of physical addresses of the rows and DRAM device addresses. Includes a DRAM device in which information is stored, The DRAM device, When an activation (ACT) command is received from the memory controller, the remapping row is first activated to read the mapping information of the target row, and then the target row is activated using the device address of the mapping information. When activation (ACT) commands are continuously issued and a row hammer prevention command is received from the memory controller, the remapping rows of the pair subarray are searched and the DRAM device in the target aggressor row where it is determined that a lot of activation (ACT) has occurred Efficiently inside DRAM, characterized by finding the address, performing row shuffling of the target attack row in the target subarray, and updating information of the remapping row in the pair subarray while row shuffling is performed or when the performance is completed. A memory device for performing row shuffle. The method of claim 1, wherein the pair of subarrays is: A memory device for efficiently performing internal DRAM row shuffling, including an isolation transistor located between each remapping row and other rows. The method of claim 1, wherein in the pair of subarrays, A memory device for efficiently performing internal DRAM row shuffling, characterized in that the bit line sense amplifier of one sub-array is connected to the local row decoder of another sub-array and the data line to transmit data. The method of claim 1, wherein the remapping row is: A memory device for efficiently performing internal DRAM row shuffle, characterized by being located closest to the bitline sense amplifier for fast activation. The method of claim 1, wherein the row shuffle is: When the DRAM device receives a row hammer prevention command, it selects the row with the largest ACT counter value as the target attack row, or selects a randomly selected row among the rows in which ACT occurred from the previous row hammer prevention command to the current row hammer prevention command. Select a target attack row, select a random row using a random number generator, copy the data of the row selected as a random row to an empty row, and when copying is complete, copy the data of the target attack row to the random row. A memory device for efficiently performing internal DRAM row shuffling, characterized in that the changed positions are updated in remapping rows having mapping information of the corresponding rows according to the positions of the changed rows.

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