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WO2024189573A1 - Tranche de stripline pour système de connecteur à base de tranche - Google Patents

Tranche de stripline pour système de connecteur à base de tranche Download PDF

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Publication number
WO2024189573A1
WO2024189573A1 PCT/IB2024/052490 IB2024052490W WO2024189573A1 WO 2024189573 A1 WO2024189573 A1 WO 2024189573A1 IB 2024052490 W IB2024052490 W IB 2024052490W WO 2024189573 A1 WO2024189573 A1 WO 2024189573A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
stripline
recited
multilayer stripline
signal transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/IB2024/052490
Other languages
English (en)
Inventor
Charles Raymond Gingrich III
Scott Eric Walton
Keith Edwin Miller
Bruce Allen Champion
Michael Frank Cina
Joshua Allen ROSENAU
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Solutions GmbH
Original Assignee
TE Connectivity Solutions GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/589,470 external-priority patent/US20240313480A1/en
Application filed by TE Connectivity Solutions GmbH filed Critical TE Connectivity Solutions GmbH
Priority to CN202480018442.0A priority Critical patent/CN120826984A/zh
Publication of WO2024189573A1 publication Critical patent/WO2024189573A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/648—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding  
    • H01R13/658—High frequency shielding arrangements, e.g. against EMI [Electro-Magnetic Interference] or EMP [Electro-Magnetic Pulse]
    • H01R13/6581—Shield structure
    • H01R13/6585—Shielding material individually surrounding or interposed between mutually spaced contacts
    • H01R13/6586—Shielding material individually surrounding or interposed between mutually spaced contacts for separating multiple connector modules
    • H01R13/6587—Shielding material individually surrounding or interposed between mutually spaced contacts for separating multiple connector modules for mounting on PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09263—Meander
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components

Definitions

  • the invention relates generally to electrical connectors and connector systems.
  • the invention is directed to a wafer based electrical connector with stripline based wafers.
  • Electrical connectors for interconnecting a circuit board backplane to a daughterboard generally comprise two mating connector halves.
  • One of the mating halves commonly includes a plurality of wafers or circuit boards which include signal carrying traces and ground traces.
  • These connectors have a high contact density and are required to operate at relatively high electrical speeds. Due to continuing trends toward miniaturization and improved electrical performance by the electronics industry, requirements for greater contact density and higher electrical speeds are constantly being promulgated.
  • the solution is provided by a connector system that includes one or more multi- layer stripline wafers which provide a number of signal integrity benefits.
  • the signal integrity benefits include, but are not limited to, better skew, impedance, and shielding performance.
  • the one or more multi-layer stripline wafers of the connector also provide increased current capacity for power wafer applications.
  • FIG.1 is a top view of an illustrative circuit board or wafer according the prior art, the wafer has grounded coplanar waveguide transmission lines.
  • FIG.2 is a perspective view of an illustrative circuit board or wafer according the prior art.
  • FIG. 3 is a perspective view of an illustrative embodiment of a multilayer circuit board or wafer according to the present invention. [0009] FIG.
  • FIG. 4 is a view of an illustrative embodiment of a representative layer of the multilayer circuit board or wafer of FIG.3.
  • FIG. 5 is a view of another illustrative layer of a representative layer of the multilayer circuit board or wafer of FIG.3.
  • FIG.6 is a cross-sectional view of the multilayer circuit board or wafer taken along line 6-6 of FIG.3.
  • FIG.7 is a partial perspective view of a mating area of the multilayer circuit board or wafer of FIG.3.
  • FIG.8 is a side view of the multilayer circuit board or wafer of FIG.3, illustrating the different layers.
  • FIG.9 is a perspective view of an illustrative electrical connector assembly with multiple wafers according to the present invention, the wafers having slots that engage with backplane connector housing keys to assure accurate contact to pad alignment and provide robust backplane housing.
  • FIG.10 is a graph illustrating the comparison between two simulated wafers with five signal pairs, the plot shows that the far end crosstalk (FEXT) is significantly lower in the stripline wafer of the present invention when compared to the grounded coplanar waveguide wafer of the prior art.
  • FEXT far end crosstalk
  • FIG.11 is a diagrammatic view of first illustrative layers of a four layer circuit board or wafer configured to accommodate high-speed signal integrity, layers (a) and (d) are ground planes and layers (b) and (c) are routed layers.
  • FIG.12 is a diagrammatic view of second illustrative layers of a four layer circuit board or wafer configured to accommodate high current/power, layers (a), (b), (c) and (d) are conductive plane layers.
  • FIG.13 is a view of an illustrative alternate embodiment of a representative layer of the multilayer circuit board or wafer with the layer above shown as translucent, the view illustrates vias which follow the trace routing of the representative layer.
  • FIG 14 is a cross-section view of the representative views of FIG.13.
  • the connector system includes one or more multi-layer stripline wafers which provide a number of signal integrity benefits.
  • the signal integrity benefits include, but are not limited to, better skew, impedance, and shielding performance.
  • the one or more multi- layer stripline wafers of the connector also provide increased current capacity for power wafer applications.
  • the one or more multi-layer stripline wafers are typically thicker than known wafers, providing mechanical benefits to the electrical connector.
  • An embodiment is directed to a multilayer stripline wafer for use in an electrical connector.
  • the multilayer stripline wafer includes multiple layers. Single ended signal transmission pathways are positioned on at least one internal layer of the multiple layers.
  • the single ended signal transmission pathways are spaced apart to remain uncoupled.
  • Conductive planar members are positioned in one or more layers of the multiple layers, The conductive planar members are spaced from the single ended signal transmission pathways.
  • One or more of the internal conductive planar members controls the impedance of the single ended signal transmission pathways.
  • An embodiment is directed to a multilayer stripline wafer for use in an electrical connector.
  • the multilayer stripline wafer includes multiple layers. Differentially coupled signal transmission pathways are positioned on at least one internal layer of the multiple Attorney Docket No. TE-05431-WO-01 layers.
  • Conductive planar members are positioned in one or more layers of the multiple layers. The conductive planar members are spaced from the differentially coupled signal transmission pathways.
  • One or more conductive planar members controls the impedance of the differentially coupled signal transmission pathways.
  • An embodiment is directed to a multilayer stripline wafer for use in an electrical connector.
  • the multilayer stripline wafer includes multiple layers of conductive material which are spaced apart. The multiple layers of conductive material are configured to allow for high current transmission across the multilayer stripline wafer.
  • Known wafer based connector systems 10 use grounded coplanar waveguide signal transmission lines, traces or pathways 12, as shown in FIG.1.
  • the wafer based connector systems 10 use skew compensation techniques that lengthen the trace 14 close to the pincer and/or mating regions 16. These are complex, cumbersome to design, and difficult to tune from an impedance perspective.
  • the grounded coplanar waveguide transmission lines, traces or pathways 12 is constructed on a two layer wafer 18.
  • the impedance in the beam area 22 of a two layer wafer-based connector system 10 is high, which is undesirable.
  • the impedance of the beam area 22 is high because, on a two layer wafer 18, the beam area 22 of a mating signal contacts 20 is positioned over a section of the wafter 18 which has no copper or ground layer provided therein. Consequently, the beam area 22 is far from the ground plane 24.
  • the thickness of the wafer 18 could be reduced; however, the wafer 18 cannot be too thin because of durability considerations.
  • the illustrative multilayer stripline wafer 30 of the present invention allows for signals to be routed single ended.
  • the signals may be routed with differential signal transmission lines, traces or pathways.
  • the single ended signal transmission lines, traces or pathways 32 can be spaced apart such that they remain uncoupled or loosely coupled. When a signal transmission lines, traces or pathways 32 are uncoupled there is no mode conversion; thus, the signal Attorney Docket No. TE-05431-WO-01 transmission lines, traces or pathways 32 must only be length matched for skew compensation to be successful.
  • FIGS.3-9 illustrate an electrical connector system 40 formed in accordance with an illustrative embodiment.
  • the electrical connector system 40 includes a backplane connector 42 and a daughtercard connector 44 that are used to electrically connect a backplane circuit board (not shown) and a daughtercard circuit board (not shown).
  • electrical connector system 40 is described herein with reference to backplane connectors 42 and daughtercard connectors 44, it is realized that the subject matter herein may be utilized with different types of electrical connectors other than a backplane connector or a daughtercard connector, such as, but not limited to, a mezzanine type connector system where the wafers are essentially an interposer.
  • the backplane connector 42 and the daughtercard connector 44 are merely illustrative of an illustrative embodiment of an electrical connector system 40 that interconnects a particular type of circuit board, namely a backplane circuit board, with a daughtercard circuit board.
  • the daughtercard connector 44 constitutes a right angle connector wherein a mating interface 46 and mounting interface 48 are oriented perpendicular to one another.
  • the daughtercard connector 44 may be mounted to the daughtercard circuit board at the mounting interface 48 and mated to the backplane connector 42 at the mating interface 46.
  • Other orientations of the interfaces 46, 48 are possible in alternative embodiments.
  • the daughtercard connector 44 includes a housing 50 holding a plurality of the stripline wafers 30.
  • the housing 50 may be made from one or more components without departing from the scope of the invention.
  • Each of the stripline wafers 30 has individual signal transmission lines, traces or pathways 32 that extend between conductive pads 52 provided proximate the mating interface 46 and conductive pads 54 provided proximate the mounting interface 48, Attorney Docket No. TE-05431-WO-01 although the particular configuration of the individual signal transmission lines, traces or pathways 32 may vary from wafer 30 to wafer 30.
  • the signal conductive pads 52 are configured to make an electrical connection to the signal transmission lines, traces or pathways 32 by known methods, such as, but not limited to vias or through holes.
  • the signal conductive pads 52 are configured to be mated with and electrically connected to the signal contacts 20 of the backplane connector 42.
  • Floating pads 53 are provided proximate the mating interface 46.
  • the floating pads 53 extend between the mating interface 46 and the conductive pads 52.
  • the floating pads 53 do not physically engage the conductive pads 52.
  • the floating pads 53 are positioned proximate to, but spaced from a second internal ground layer 72 which are positioned in an adjacent layer of the wafer 30.
  • the floating pads 53 may be spaced further from any grounding members.
  • the floating pads 53 are capacitively coupled to the second internal ground layer 72 and the beam area 22 of the contact 20.
  • the floating pads 53 may be capacitively coupled to other layers.
  • the illustrative wafer 30 has a first conductive layer 70, a second internal conductive layer 72, a third internal conductive layer 74 and a fourth conductive layer 76.
  • the first conductive layer 70 is a top ground layer.
  • the fourth conductive layer 76 is a bottom ground layer.
  • the second layer 72 includes the signal transmission lines, traces or pathways 32.
  • the third conductive layer 74 includes some ground copper or paths.
  • the purpose and use of each conductive layer may vary according to the particular configuration needed.
  • the signal transmission lines, traces or pathways 32 may be routed on the third internal conductive layer 74.
  • stitched ground vias 75 may also be provided on the ground layers.
  • the vias 75 follow the routing of the signal transmission lines, traces or pathways 32 to further facilitate noise reduction. Additionally, in various Attorney Docket No. TE-05431-WO-01 embodiments ground and power can be shared on any given layer. Although the embodiment illustrates four layers, any number of layers may be used. [0033] Openings 62 are provided in the first layer 70 to expose the conductive pads 52 and the floating pads 53. An opening 63 (FIG.3) is also provided to expose conductive pads 54. The fourth conductive ground plane layer 76 is positioned on the opposed side of the wafer 30. The ground layers 70 and 76 are configured to be mated with, and electrically connected to, ground contacts or ground plates of the backplane connector 42.
  • the stripline signal transmission lines, traces or pathways 32 greatly reduces the complexity associated with skew compensation as compared to known wafer connectors.
  • the stripline wafers 30 allow for signals to be routed single ended over the stripline signal transmission lines, traces or pathways 32.
  • the single ended stripline signal transmission lines, traces or pathways 32 can be spaced apart such that they remain uncoupled. As the stripline signal transmission lines, traces or pathways 32 are uncoupled, there is no mode conversion; thus, the stripline signal transmission lines, traces or pathways 32 must only be length matched for skew compensation to be successful.
  • the stripline wafers 30 also allow for an increased routing density.
  • the stripline signal transmission lines, traces or pathways 32 can be significantly narrower as compared to the grounded coplanar waveguide while meeting the same impedance target.
  • An increased routing density allows for a denser electrical connector system 40.
  • the stripline wafers 30 better allow printed circuit board manufacturers to consistently meet required impedance targets which will lead to fewer discarded printed circuit boards.
  • the grounded coplanar waveguide of the prior art is susceptible to under/over etching which can negatively impact impedance.
  • the multilayer stripline wafer 30 has the second internal conductive planar member 72 and the third internal conductive planar member 74 positioned in the beam area 22.
  • the second internal conductive planar member 72 is a ground member.
  • the second internal conductive planar member 72 is used as a reference and is capacitively coupled to the floating pads 53 in the beam areas 22 of the contacts 20 to allow the floating pads 53 to cooperate with the beams areas 22 to reduce the impedance of the beam areas 22.
  • the ground planar member 72 may be spaced approximately 0.004 inches from the floating pads 53.
  • the stripline wafers 30 of the present invention allow for finer control of the impedance in the signal transmission lines, traces or pathways 32.
  • the internal planar members 72, 74 can be used to reduce impedance in the signal transmission lines, traces or pathways 32, to minimize noise resonance, and improve connector performance.
  • the internal conductive planar members 72, 74 may be positioned in other locations and may be used for different purposes, such as, but not limited to, multiple voltage planes.
  • the multilayer stripline wafer 30 has a higher volume of copper than known grounded coplanar waveguide.
  • the multilayer stripline wafer 30 can have various configurations.
  • the multilayer stripline wafer 30 can have top and bottom ground planes 70’, 76’ with routed layers 72’, 74’ positioned therebetween for high speed signal integrity, as shown in FIG. 11.
  • FIG.12 shows the multilayer stripline wafer 30 having conductive plane layers, such as, but not limited to, copper plane layers, for all layers 70”, Attorney Docket No.
  • the signal transmission lines, traces or pathways 32 in any of the layers can be single ended transmission lines, traces or pathways or coupled differential transmission lines, traces or pathways.
  • the stripline signal transmission lines, traces or pathways 32 are also significantly less susceptible to noise than the grounded coplanar waveguide wafers of the prior art. In very high-speed applications, noise is one of the main factors that degrade performance. Because the stripline signal transmission lines, traces or pathways 32 can be designed to be narrow, the stripline signal transmission lines, traces or pathways 32 can be spaced far enough apart from each other to practically eliminate electromagnetic coupling.
  • the stripline signal transmission lines, traces or pathways 32 is also highly immune to FEXT.
  • the equation for FEXT can be seen below. In a stripline configuration, the mutual inductance and the inductance per unit length are the same and the mutual capacitance and capacitance per unit length are the same. This mean that, in the stripline configuration, the term in the parentheses will be zero. Therefore, in regions where the stripline signal transmission lines, traces or pathways 32 are coupled, there should be no FEXT.
  • a comparison between two simulated wafers with five pairs is shown in FIG.10.
  • the multilayer stripline wafer 30 allows for versatility and different routing options to isolate the stripline signal transmission lines, traces or pathways 32 from each other.
  • signals transmitted could be routed on one layer and signals received on another layer.
  • a ground plane could be placed in between layers to isolate them from each other.
  • multiple voltage planes could also be used within the same wafer, as shown in FIG.8.
  • the first internal planar member 70 could be used for, but not limited to, 12 volts and the second internal planar member 72 could be used for, but not limited to, 24 volts.
  • the ground and power return could be designed on the same wafer.
  • three different voltage planes and three ground return planes may be provided on a six-layer wafer.
  • stripline signal transmission lines, traces or pathways may be routed on layer two and layers one and four could be used as a ground reference, allowing the stripline signal transmission lines, traces or pathways to be wider allowing the stripline signal transmission lines, traces or pathways to have less loss.
  • Many other configurations of the wafers may be used. These are a few of the many applications the stripline wafer could be used in where none of these applications would be achievable with the grounded coplanar waveguide wafer.
  • the stripline wafer is thicker than the known grounded coplanar waveguide wafer, making the stripline wafer more durable.
  • the slot 80 extends from the mating interface 46, as shown in FIG.9.
  • the slot 80 is positioned in line and cooperates with a strength member or rib 82 provided in the backplane connector 42.
  • the strength member 82 reinforces the backplane connector 42, allowing the backplane connector 42 to be more robust.
  • the strength member 82 is inserted into the slot 80.
  • the strength member 82 cooperates with the slot 80 to proper position and align the daughtercard connector 44 with the backplane connector 42.
  • the slot 80 and strength member 82 act as a key to ensure there is accurate alignment between the conductive pads 52 of the stripline wafer 30 of the daughtercard connector 44 and the signal contacts 20 in the backplane connector 42.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)

Abstract

L'invention concerne une tranche de stripline multicouche destinée à être utilisée dans un connecteur électrique. La tranche de stripline multicouche comprend de multiples couches. Des voies de transmission de signal sont positionnées sur au moins une couche interne des multiples couches. Les voies de transmission de signal peuvent être désaccouplées ou couplées de manière lâche des voies de transmission de signal asymétrique à extrémité unique ou des voies de transmission de signal couplées de manière différentielle. Des éléments plans conducteurs sont positionnés dans une ou plusieurs couches des multiples couches. Les éléments plans conducteurs sont espacés des voies de transmission de signal. Un ou plusieurs éléments plans conducteurs commandent l'impédance des voies de transmission de signal.
PCT/IB2024/052490 2023-03-14 2024-03-14 Tranche de stripline pour système de connecteur à base de tranche Pending WO2024189573A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202480018442.0A CN120826984A (zh) 2023-03-14 2024-03-14 用于基于晶片连接器系统的带状线晶片

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202363490014P 2023-03-14 2023-03-14
US63/490,014 2023-03-14
US18/589,470 2024-02-28
US18/589,470 US20240313480A1 (en) 2023-03-14 2024-02-28 Stripline Wafer for Wafer Based Connector System

Publications (1)

Publication Number Publication Date
WO2024189573A1 true WO2024189573A1 (fr) 2024-09-19

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Application Number Title Priority Date Filing Date
PCT/IB2024/052490 Pending WO2024189573A1 (fr) 2023-03-14 2024-03-14 Tranche de stripline pour système de connecteur à base de tranche

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010011753A1 (fr) * 2008-07-22 2010-01-28 Molex Incorporated Borne de terre à résonance amortie
US20150228706A1 (en) * 2014-02-10 2015-08-13 Samsung Display Co., Ltd. Display device
US20170018881A1 (en) * 2015-07-14 2017-01-19 Tyco Electronics Corporation Pluggable connector and interconnection system configured for resonance control
US20190162768A1 (en) * 2017-11-30 2019-05-30 Dell Products, L.P. Test apparatus for signal integrity testing of connectors
US20200296822A1 (en) * 2019-03-12 2020-09-17 SK Hynix Inc. Semiconductor module including a printed circuit board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010011753A1 (fr) * 2008-07-22 2010-01-28 Molex Incorporated Borne de terre à résonance amortie
US20150228706A1 (en) * 2014-02-10 2015-08-13 Samsung Display Co., Ltd. Display device
US20170018881A1 (en) * 2015-07-14 2017-01-19 Tyco Electronics Corporation Pluggable connector and interconnection system configured for resonance control
US20190162768A1 (en) * 2017-11-30 2019-05-30 Dell Products, L.P. Test apparatus for signal integrity testing of connectors
US20200296822A1 (en) * 2019-03-12 2020-09-17 SK Hynix Inc. Semiconductor module including a printed circuit board

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