WO2024183177A1 - Control circuit and memory - Google Patents

Abstract

A control circuit (200) and a memory (300). The control circuit (200) comprises a reset signal generation circuit (220) and a test mode circuit (230). The reset signal generation circuit (220) is used for receiving a control signal and a test mode entry signal, and generating and outputting a test mode reset signal according to the control signal and the test mode entry signal. The test mode circuit (230) is used for resetting and outputting a test mode signal according to the test mode reset signal, wherein the test mode signal indicates duty cycle adjustment of a clock signal.

Description

Control circuit and memory

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is based on and claims the priority of Chinese patent application with application number 202310219465.5 and application date March 3, 2023. The entire contents of the Chinese patent application are hereby introduced into the present disclosure as a reference.

Technical Field

The present disclosure relates to, but is not limited to, a control circuit and a memory.

Background Art

With the continuous development of science and technology, high data reliability and high access speed have become important trends in the development of semiconductor memory. Among them, dynamic random access memory (DRAM) is a volatile memory and is widely used in computers and various electronic devices.

Generally, the memory uses a delay locked loop (DLL) circuit to adjust the delay of the clock signal so that the phases of the two signals are consistent, that is, the edges are aligned. The DLL circuit uses a duty cycle corrector (DCC) to adjust the duty cycle of the clock signal to optimize the data window. Therefore, how to shorten the time required to adjust the duty cycle of the clock signal in the memory has become an urgent problem to be solved in the industry.

Summary of the invention

In view of this, an embodiment of the present disclosure provides a control circuit and a memory.

In a first aspect, an embodiment of the present disclosure provides a control circuit, comprising: a reset signal generating circuit, for receiving a control signal and a test mode entry signal, and generating and outputting a test mode reset signal according to the control signal and the test mode entry signal; a test mode circuit, connected to the reset signal generating circuit, the test mode circuit being used to reset and output a test mode signal according to the test mode reset signal; wherein the test mode signal indicates a duty cycle adjustment of a clock signal.

In some embodiments, the control signal includes a first control signal and a second control signal; the reset signal generating circuit includes a first control circuit for receiving the first control signal, and a second control circuit for receiving the second control signal; the first control circuit is also used to receive the test mode entry signal, and output a first input signal according to the test mode entry signal, and output a first internal signal according to the first control signal and the test mode entry signal; the second control circuit is connected to the first control circuit, for receiving the first input signal and the first internal signal, and outputting the test mode reset signal according to the second control signal, the first internal signal and the first input signal.

In some embodiments, when the level of the first control signal is the first level, the first control circuit is used to output the first internal signal at the second level; When the level of the control signal is the second level, the first control circuit is used to output the first internal signal having the same level as the test mode entry signal. The first control circuit is also used to output the first input signal having the same level as the test mode entry signal.

In some embodiments, the first control circuit includes: a first input unit, used to receive the test mode entry signal, and generate and output the first input signal of the same level as the test mode entry signal according to the test mode entry signal; a second input unit, used to receive the first control signal, and generate and output a second input signal of opposite level to the first control signal according to the first control signal; a first operation unit, connected to the first input unit and the second input unit, used to receive the first input signal and the second input signal, and generate and output the first internal signal according to the first input signal and the second input signal.

In some embodiments, the first operation unit includes: a NAND gate, the input end of the NAND gate is used to receive the first input signal and the second input signal; a first inverter, the input end of the first inverter is connected to the output end of the NAND gate; the output end of the first inverter is used to output the first internal signal.

In some embodiments, the first input unit includes a buffer, the input end of the buffer is used to receive the test mode entry signal, and the output end of the buffer is used to output the first input signal; the second input unit includes a second inverter, the input end of the second inverter is used to receive the first control signal, and the output end of the second inverter is used to output the second input signal.

In some embodiments, the buffer comprises: an even number of cascaded inverters.

In some embodiments, the second control circuit includes: a second operation unit, connected to the first input unit and the first operation unit, used to receive the first input signal and the first internal signal, and in response to the received second control signal, generate and output the test mode reset signal according to the first input signal and the first internal signal; when the level of the second control signal is the first level, the second control circuit is used to output the test mode reset signal with the same level as the first input signal; when the level of the second control signal is the second level, the second control circuit is used to output the test mode reset signal with the same level as the first internal signal.

In some embodiments, the second operation unit includes: a data selector, the input end of the data selector is used to receive the first input signal and the first internal signal, and the control end of the data selector is used to receive the second control signal; wherein, when the level of the second control signal is the second level, the data selector is used to output a second internal signal opposite to the level of the first internal signal, and when the level of the second control signal is the first level, the data selector is used to output a second internal signal opposite to the level of the first input signal; a third inverter, the input end of the third inverter is connected to the output end of the data selector, for receiving the second internal signal, and the output end of the third inverter is used to output the test mode reset signal.

In some embodiments, the control circuit further comprises: a command and address decoder for receiving a mode register configuration command and decoding and generating a corresponding mode register configuration command according to the mode register configuration command. A configuration value of a register; a mode register circuit connected to the command and address decoder, and used to generate the test mode entry signal according to the configuration value of the mode register; a delay locked loop circuit connected to the test mode circuit, and used to adjust the duty cycle of the clock signal according to the test mode signal.

In some embodiments, the delay locked loop circuit includes: a clock division circuit, used to generate multiple divided clock signals with different phases according to the clock signal; a duty cycle correction circuit, connected to the test mode circuit and the clock division circuit, the duty cycle correction circuit includes multiple duty cycle correction sub-circuits; each of the duty cycle correction sub-circuits is used to adjust the duty cycle of one of the divided clock signals according to the test mode signal to output a corrected clock signal.

In some embodiments, the test mode signal includes multiple test mode sub-signals, and the duty cycle correction sub-circuit includes: a multi-stage adjustment unit connected in series, each stage of the adjustment unit is used to receive at least one of the test mode sub-signals to gradually adjust the duty cycle of the divided clock signal; the input end of the first stage of the adjustment unit is used to receive the divided clock signal, and the input end of each of the remaining stages of the adjustment unit is connected to the output end of the previous stage of the adjustment unit, and the output end of the last stage of the adjustment unit is used to output the corrected clock signal.

In some embodiments, the regulating unit includes: a fourth inverter and at least one pulse regulating unit; the input end of the fourth inverter is connected to the input end of the pulse regulating unit, and they are used together as the input end of the regulating unit; the output end of the fourth inverter is connected to the output end of the pulse regulating unit, and they are used together as the output end of the regulating unit; the control end of the pulse regulating unit is connected to the test mode circuit, and is used to receive the corresponding test mode sub-signal; the fourth inverter and the input end of the pulse regulating unit in the first stage of the regulating unit are used to receive the divided clock signal; the fourth inverter and the input end of the pulse regulating unit in each of the remaining stages of the regulating unit are used to receive the intermediate clock signal output by the previous stage of the regulating unit; the output end of the fourth inverter and the pulse regulating unit in the last stage of the regulating unit is used to output the correction clock signal; the output end of the fourth inverter and the pulse regulating unit in each of the remaining stages of the regulating unit is used to output the intermediate clock signal; the pulse regulating unit is used to adjust the width of the high level pulse and the low level pulse in the intermediate clock signal according to the test mode sub-signal.

In some embodiments, the pulse adjustment unit includes: a first switching transistor, the source of which is connected to a first voltage terminal; a gate of which is connected to an input terminal of the fourth inverter for receiving the intermediate clock signal or the divided clock signal; a second switching transistor, the source of which is connected to a second voltage terminal; a gate of which is connected to an input terminal of the fourth inverter for receiving the intermediate clock signal or the divided clock signal; a pull-up transistor, the source of which is connected to a drain of the first switching transistor; a gate of which is used to receive a corresponding test mode sub-signal; a drain of which is connected to the output terminal of the fourth inverter; a pull-down transistor, the source of which is connected to a drain of the second switching transistor; a gate of which is used to receive a corresponding test mode sub-signal; and a drain of which is connected to the output terminal of the fourth inverter.

In a second aspect, an embodiment of the present disclosure provides a memory, comprising: a memory cell array; and a peripheral circuit, comprising the control circuit described in any one of the above embodiments.

In the control circuit provided in the embodiment of the present disclosure, the reset signal generating circuit is used to output a test mode reset signal according to at least one control signal and a test mode entry signal. In this way, by adjusting the level of the control signal, the reset signal generating circuit can output a test mode reset signal of a different level from the test mode entry signal. Therefore, the test mode circuit can reset the test mode signal according to the test mode reset signal, rather than directly resetting the test mode signal according to the test mode entry signal, thereby reducing the situation where the delay locked loop circuit readjusts the clock signal duty cycle according to the reset test mode signal, saving the time required to adjust the clock signal duty cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram 1 of a control circuit provided in an embodiment of the present disclosure;

FIG2 is a schematic diagram of a duty cycle correction subcircuit provided in an embodiment of the present disclosure;

FIG3 is a second schematic diagram of a control circuit provided in an embodiment of the present disclosure;

FIG4 is a third schematic diagram of a control circuit provided in an embodiment of the present disclosure;

FIG5 is a schematic diagram 1 of a reset signal generating circuit in a control circuit provided in an embodiment of the present disclosure;

FIG6 is a second schematic diagram of a reset signal generating circuit in a control circuit provided in an embodiment of the present disclosure;

FIG7 is a schematic diagram of a delay locked loop circuit in a control circuit provided in an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a memory provided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an", and "the" are used herein. It is also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

In some embodiments, the dynamic random access memory uses a delay locked loop circuit to align the clock signal with the data strobe signal (DQS). In the fourth generation double data rate memory (Double Data Rate 4, DDR4), data can be transmitted on both the rising and falling edges of the system clock, so it is necessary to make the duty cycle of the clock signal as close to 50% as possible to optimize the data window, and DDR4 samples data through a two-phase clock signal. Specifically, the delay locked loop circuit splits the clock signal into an odd clock signal and an even clock signal, and adjusts the duty cycle of the odd clock signal and the even clock signal respectively, thereby balancing the odd clock signal and the even clock signal to ensure data consistency. It is understandable that the odd clock signal and the even clock signal here can have a phase difference of 180 degrees. In addition, the fifth-generation double data rate memory (Double Data Rate 5, DDR5) and the sixth-generation double data rate memory (Double Data Rate 6, DDR6) both sample data through a four-phase clock signal. Therefore, the clock signal of each phase needs to be duty cycle adjusted.

In some embodiments, as shown in FIG. 1 , a control circuit 100 is provided for adjusting the clock duty cycle, specifically comprising: a command and address decoder 150, for receiving a mode register configuration command, and decoding and generating a corresponding mode register configuration value according to the mode register configuration command; a mode register circuit 110, connected to the command and address decoder 150, for generating the test mode entry signal MR0_EN according to the mode register configuration value; a test mode circuit 130, connected to the mode register circuit 110, the test mode circuit 130 is used to reset and output a plurality of test mode signals TM according to the test mode entry signal MR0_EN; and a delay locked loop circuit 140, connected to the test mode circuit 130, the delay locked loop circuit 140 is used to adjust the duty cycle of the clock signal CLK according to the test mode signal TM.

Specifically, the command and address decoder 150 can receive a mode register configuration command issued by the memory controller, and decode the mode register configuration command to generate a corresponding mode register configuration value. Exemplarily, in DDR4, the mode register configuration command can be a mode register setting command (Mode Register Setting, MRS), and in DDR5, the mode register configuration command can be a mode register write command (Mode Register Write, MRW). The mode register circuit 110 is used to define the operating modes corresponding to various functions of the memory. The mode register circuit 110 is connected to the command and address decoder 150, and generates a test mode entry signal MR0_EN according to the mode register configuration value. Exemplarily, after the mode register configuration command issued by the memory controller is decoded by the command and address decoder 150, a mode register configuration value can be generated to set a specified bit in a mode register (such as MR0) to a specified value (such as setting the A7 bit to 0 or 1). The specific value is also set by the memory controller. In addition, in the test, the corresponding value can also be set manually to control the execution. The corresponding functions are performed, for example, the A7 bit of MR0 is manually set to 1, that is, the test mode is entered. At this time, the test mode circuit 130 generates multiple test mode signals TM and adjusts the parameters of the test mode signal TM to adjust the duty cycle of the clock signal. After the duty cycle adjustment is completed, the values of the relevant parameters of the test mode signal can be fixed in the memory by burning the fuse circuit and will not be changed.

The delay locked loop circuit includes a clock frequency division circuit and a duty cycle correction circuit. The clock frequency division circuit is used to generate a plurality of frequency division clock signals with different phases according to the clock signal. The duty cycle correction circuit includes a plurality of duty cycle correction subcircuits, each of which is used to adjust the duty cycle of a frequency division clock signal according to the test mode signal. The test mode signal TM may include a plurality of test mode sub-signals TM<0> to TM<n>, where n is a positive integer. As shown in FIG2 , a duty cycle correction subcircuit 141 in the delay locked loop circuit is shown, and the duty cycle correction subcircuit 141 includes three stages of adjustment units 142 connected in series, and each stage of adjustment unit 142 is used to receive at least one test sub-mode signal to adjust the duty cycle of the frequency division clock signal CLK_F step by step. In some embodiments, the duty cycle correction subcircuit may also include a plurality of stages of adjustment units connected in series, and the specific number of stages of the adjustment units is determined according to the load of the clock signal. The greater the load, the more stages of adjustment units are required in the duty cycle correction subcircuit to enhance the driving capability, so there is no restriction on the number of stages here. In addition, the number of test mode sub-signals received by each level of adjustment unit can be the same or different. As shown in FIG2 , the first level of adjustment unit receives one test mode sub-signal TM<0>, the second level of adjustment unit receives one test mode sub-signal TM<1>, and the third level of adjustment unit receives three test mode sub-signals TM<2>, TM<3>, and TM<4>.

Specifically, each level of the regulating unit 142 may include: an inverter 143 and at least one pulse regulating unit 144. The input end of the inverter 143 is connected to the input end of the pulse regulating unit 144 to serve as the input end of the regulating unit 142, and the output end of the inverter 143 is connected to the output end of the pulse regulating unit 144 to serve as the output end of the regulating unit 142; in addition, the control end of the pulse regulating unit 144 is also connected to the test mode circuit and is used to receive the corresponding test mode sub-signal. It is worth noting that the input end of the inverter 143 and the pulse regulating unit 144 in the first level regulating unit 142 is used to receive the divided clock signal CLK_F, and the input end of the inverter 143 and the pulse regulating unit 144 in each of the remaining level regulating units 142 is used to receive the intermediate clock signal CLK_M output by the previous level regulating unit 142. The output ends of the inverter 143 and the pulse adjustment unit 144 in the last stage of the adjustment unit 142 are used to output the final correction clock signal CLK_C, and the output ends of the inverter 143 and the pulse adjustment unit 144 in each of the remaining stages of the adjustment unit 142 are used to output the intermediate clock signal CLK_M. The pulse adjustment unit 144 is used to adjust the width of the high level pulse and the low level pulse in the intermediate clock signal CLK_M according to the test mode sub-signal. In this way, the multi-stage adjustment unit 142 can complete the duty cycle adjustment of the divided clock signal CLK_F step by step to output the correction clock signal CLK_C.

As shown in FIG2 , the pulse adjustment unit 144 includes a pull-up transistor 145, a pull-down transistor 146, a first switch transistor 147, and a second switch transistor 148. Among them, the source of the first switch transistor 147 is connected to the first voltage terminal, and the gate of the first switch transistor 147 is connected to the input terminal of the inverter 143, for receiving the intermediate clock signal CLK_M or the divided clock signal; the source of the second switch transistor 148 is connected to the second voltage terminal; the gate of the second switch transistor 148 is connected to the input terminal of the inverter 143, for receiving the intermediate clock signal CLK_M or the divided clock signal; the source of the pull-up transistor 145 is connected to the drain of the first switch transistor 147, and the gate of the pull-up transistor 145 is used to receive the corresponding test mode sub-signal, the drain of the pull-up transistor 145 is connected to the output end of the inverter 143; the source of the pull-down transistor 146 is connected to the drain of the second switch transistor 148, the gate of the pull-down transistor 146 is used to receive the corresponding test mode sub-signal, and the drain of the pull-down transistor 146 is connected to the output end of the inverter 143. Here, the first switch transistor 147 and the pull-up transistor 145 can be PMOS transistors, the second switch transistor 148 and the pull-down transistor 146 can be NMOS transistors, the first voltage terminal can be the power supply voltage terminal VDD, and the second voltage terminal can be the ground voltage terminal VSS. Therefore, the test mode circuit can control the conduction or cut-off of multiple pull-up transistors 145 or pull-down transistors 146 in the duty cycle correction sub-circuit 141 through the combination of multiple test mode sub-signals TM<1>~TM<n>, thereby adjusting the duty cycle of the divided clock signal. Exemplarily, when the level of the test mode signal TM<0> is low, a corresponding pull-up transistor 145 in the duty cycle correction subcircuit 141 is turned on, and a corresponding pull-down transistor 146 is turned off. At this time, the rising edge time of the divided clock signal becomes shorter, and the pulse width of the high level in the divided clock signal becomes longer, thereby increasing the duty cycle; when the level of the test mode signal TM<0> is high, a corresponding pull-up transistor 145 in the duty cycle correction subcircuit 141 is turned off, and a corresponding pull-down transistor 146 is turned on. At this time, the falling edge time of the divided clock signal becomes shorter, and the pulse width of the low level in the divided clock signal becomes longer, thereby reducing the duty cycle. It is worth noting that, since each level adjustment unit 142 includes an inverter 143, for the duty cycle correction subcircuit in FIG. 2, in the first and third level adjustment units, the pull-up transistor 145 is turned on to adjust the pulse width of the low level in the divided clock signal, and the pull-down transistor 146 is turned on to adjust the pulse width of the high level in the divided clock signal; and in the second level adjustment unit, the pull-up transistor 145 is turned on to adjust the pulse width of the high level in the divided clock signal, and the pull-down transistor 146 is turned on to adjust the pulse width of the low level in the divided clock signal. That is to say, under the premise that the levels of multiple test mode signals are the same, the odd-numbered adjustment units and the even-numbered adjustment units have opposite regulating effects on the divided clock signal.

It is worth noting that the memory may have a variety of programmable circuit modules, the programmable circuit modules have fuses or anti-fuse units, and the duty cycle correction circuit is one of the functional circuits. When the level of the test mode entry signal MR0_EN is high, all test mode signals in the memory will be reset. However, during the clock signal duty cycle correction process, we do not want some test mode signals acting on the duty cycle correction circuit to be reset, because resetting the test mode signal will cause the duty cycle adjustment process to restart, thereby increasing the time of the duty cycle adjustment process.

It is understandable that, when the duty cycle correction subcircuit 141 adjusts the duty cycle of the divided clock signal, and other circuits in the memory need to be reset, the mode register circuit 110 will output a high level test mode entry signal MR0_EN. This causes the test mode signal TM output by the test mode circuit 130 corresponding to the delay locked loop circuit 140 to be reset, that is, each transistor in the duty cycle correction subcircuit 141 is reset, resulting in the duty cycle adjustment process needing to be restarted, and the value of each test mode signal TM is re-determined, which increases the time required for adjusting the duty cycle of the clock signal in the memory.

As shown in FIG3 , the present disclosure provides a control circuit 200, including: a reset signal generating circuit 220, configured to receive a control signal TMF_MR0 and a test mode entry signal MR0_EN, and to generate and reset a reset signal according to the control signal TMF_MR0 and the test mode entry signal MR0_EN. Output test mode reset signal TMF_MR0_RESET_OUT; test mode circuit 230, connected to the reset signal generating circuit 220, the test mode circuit 230 is used to reset and output the test mode signal TM according to the test mode reset signal TMF_MR0_RESET_OUT; wherein the test mode signal TM indicates the duty cycle adjustment of the clock signal CLK.

In some embodiments, as shown in Figure 4, the control circuit 200 also includes: a command and address decoder 270, which is used to receive a mode register configuration command and generate a corresponding mode register configuration value according to the mode register configuration command decoding; a mode register circuit 210, connected to the command and address decoder 270, and used to generate the test mode entry signal according to the configuration value of the mode register; a delay locked loop circuit 240, connected to the test mode circuit 230, and used to adjust the duty cycle of the clock signal CLK according to the test mode signal TM.

In the embodiment of the present disclosure, the command and address decoder 270 can receive the mode register configuration command issued by the memory controller, and decode the mode register configuration command to generate a corresponding mode register configuration value. The mode register 210 can be used to define the operation mode corresponding to various functions of the memory. The mode register circuit 210 is connected to the command and address decoder 270, and generates a test mode entry signal MR0_EN according to the mode register configuration value. The test mode entry signal MR0_EN can be used to reset the test mode signal TM issued by the test mode circuit 230. It can be understood that the mode register 210 can also output a variety of signals other than the test mode entry signal MR0_EN to meet the needs of configuring different operation modes of the memory.

The reset signal generating circuit 220 is connected to the mode register 210 and can receive at least one control signal TMF_MR0. The reset signal generating circuit 220 can output a test mode reset signal TMF_MR0_RESET_OUT according to various level combinations of the control signal TMF_MR0 and the test mode entry signal MR0_EN. Exemplarily, the control signal TMF_MR0 can be used to shield the test mode entry signal MR0_EN. For example, when the level of the control signal TMF_MR0 is high, indicating that the current test mode entry signal MR0_EN does not indicate the execution of the clock signal duty cycle adjustment, the reset signal generation circuit 220 can shield the test mode entry signal MR0_EN according to the high-level control signal TMF_MR0, and output the test mode reset signal TMF_MR0_RESET_OUT whose level is always low; and when the level of the control signal TMF_MR0 is low, indicating that the current test mode entry signal MR0_EN indicates the execution of the clock signal duty cycle adjustment, the reset signal generation circuit 220 does not shield the test mode entry signal MR0_EN, and the level of the output test mode reset signal TMF_MR0_RESET_OUT is the same as the level of the test mode entry signal MR0_EN. In some embodiments, the control signal TMF_MR0 can be generated by the control logic in the memory.

It can be understood that since a reset signal generating circuit 220 is provided between the mode register circuit 210 and the test mode circuit 230, when the level of the test mode entry signal MR0_EN is high and the level of the control signal TMF_MR0 is high, the test mode entry signal MR0_EN is shielded, the level of the test mode reset signal TMF_MR0_RESET_OUT can be low, and the test mode signal TM issued by the test mode circuit 230 may not be reset, that is, the duty cycle correction circuit in the delay locked loop circuit 240 may continue to use the settings corresponding to the previous multiple test mode signals TM without restarting the duty cycle adjustment process.

It is worth noting that the reset signal generating circuit 220 can be connected only to the test mode circuit 230 and the mode register 210, that is, the test mode entry signal MR0_EN issued by the mode register 210 can still be directly output to other circuits except the test mode circuit 230, so that the functions of other circuits in the memory except the delay locked loop circuit 240 reset by the test mode entry signal MR0_EN are not affected.

In this way, by adjusting the level of the control signal TMF_MR0, the reset signal generating circuit 220 can output the test mode reset signal TMF_MR0_RESET_OUT of a different level from the test mode entry signal MR0_EN. Therefore, the test mode circuit 230 can reset the test mode signal TM according to the generated test mode reset signal TMF_MR0_RESET_OUT, rather than directly resetting the test mode signal TM according to the test mode entry signal MR0_EN, that is, when the test mode entry signal MR0_EN indicates to execute other functions of the memory instead of indicating to start the clock signal duty cycle adjustment (the logic level value of the adjustment control signal TMF_MR0 indicates whether the executed function is the clock signal duty cycle adjustment when MR0_EN is at a valid level), the delay locked loop circuit 240 is reduced to readjust the clock signal CLK duty cycle according to the reset test mode signal TM, thereby shortening the time required to adjust the clock signal CLK duty cycle.

In some embodiments, as shown in FIG. 5 , the control signal includes a first control signal TMF_MR0_RESET_DIS and a second control signal TMF_MR0_CONTROL_DIS; the reset signal generating circuit 220 includes a first control circuit 250 for receiving the first control signal TMF_MR0_RESET_DIS, and a second control circuit 260 for receiving the second control signal TMF_MR0_CONTROL_DIS; the first control circuit 250 is further used to receive the test mode entry signal MR0_EN, and output a first input signal MR0_EN_IN according to the test mode entry signal MR0_EN. 1, and outputs the first internal signal TMF_MR0_INT1 according to the first control signal TMF_MR0_RESET_DIS and the test mode entry signal MR0_EN; the second control circuit 260 is connected to the first control circuit 250, for receiving the first input signal MR0_EN_IN1 and the first internal signal TMF_MR0_INT1, and outputs the test mode reset signal TMF_MR0_RESET_OUT according to the second control signal TMF_MR0_CONTROL_DIS, the first internal signal TMF_MR0_INT1 and the first input signal MR0_EN_IN1.

In the embodiment of the present disclosure, the first control signal TMF_MR0_RESET_DIS and the second control signal TMF_MR0_CONTROL_DIS can be generated by the control logic in the memory based on the external command or the test mode, and are respectively output to the first control circuit 250 and the second control circuit 260. The first control signal TMF_MR0_RESET_DIS is used to indicate whether the test mode entry signal MR0_EN is valid, so as to further determine whether the test mode signal TM needs to be reset; and the second control signal TMF_MR0_CONTROL_DIS is used to indicate whether the first control signal TMF_MR0_RESET_DIS is valid.

The first control circuit 250 outputs the first internal signal TMF_MR0_INT1 according to the first control signal TMF_MR0_RESET_DIS and the test mode entry signal MR0_EN. Exemplarily, the first control signal TMF_MR0_RESET_DIS can be used to shield the test mode entry signal MR0_EN, that is, when the level of the first control signal TMF_MR0_RESET_DIS is high, no matter whether the level of the test mode entry signal MR0_EN is high or low, the first control circuit 250 outputs the first internal signal TMF_MR0_INT1 according to the first control signal TMF_MR0_RESET_DIS and the test mode entry signal MR0_EN. The first control circuit 250 outputs the first internal signal TMF_MR0_INT1 with a low level. The first control circuit 250 can also output the first input signal MR0_EN_IN1 according to the test mode entry signal MR0_EN, where the level of the first input signal MR0_EN_IN1 can be consistent with the level of the test mode entry signal MR0_EN.

The second control circuit 260 may output a test mode reset signal TMF_MR0_RESET_OUT according to the second control signal TMF_MR0_CONTROL_DIS, the first internal signal TMF_MR0_INT1, and the first input signal MR0_EN_IN1. Exemplarily, the second control signal TMF_MR0_CONTROL_DIS can be used to shield the first control signal TMF_MR0_RESET_DIS, that is, when the level of the second control signal TMF_MR0_CONTROL_DIS is high, regardless of whether the level of the first control signal TMF_MR0_RESET_DIS is high or low, the second control circuit 260 outputs a test mode reset signal TMF_MR0_RESET_OUT that is the same as the level of the first input signal MR0_EN_IN1, that is, the level of the test mode reset signal TMF_MR0_RESET_OUT is consistent with the level of the test mode entry signal MR0_EN; and when the level of the second control signal TMF_MR0_CONTROL_DIS is low, the second control circuit outputs a test mode reset signal TMF_MR0_RESET_OUT that is related to the level value of the first control signal TMF_MR0_RESET_DIS.

In this way, by setting the first control circuit 250 and the second control circuit 260, and configuring the level combination of the first control signal TMF_MR0_RESET_DIS and the second control signal TMF_MR0_CONTROL_DIS, the level of the test mode reset signal TMF_MR0_RESET_OUT output to the test mode circuit can be low when the level of the test mode entry signal MR0_EN is high. In other words, the current test mode entry signal MR0_EN does not indicate the execution of the clock signal duty cycle adjustment, so when the test mode entry signal MR0_EN indicates the execution of other functions of the memory instead of indicating the start of the clock signal duty cycle adjustment, multiple test mode signals will not be reset, and the duty cycle correction circuit in the delay locked loop circuit can continue to use the settings corresponding to the previous multiple test mode signals without restarting the duty cycle adjustment process, thereby avoiding repeated work caused by resetting the parameters when the adjustment is not completed, thereby shortening the time required to adjust the clock signal duty cycle.

In some embodiments, when the level of the first control signal is the first level, the first control circuit is used to output the first internal signal at the second level; when the level of the first control signal is the second level, the first control circuit is used to output the first internal signal having the same level as the test mode entry signal, and the first control circuit is also used to output the first input signal having the same level as the test mode entry signal. It is worth noting that here and below, the first level may be a logic high level, i.e., "1", and the second level may be a logic low level, i.e., "0"; in some other embodiments, the first level may be a logic low level, and the second level may be a logic high level.

In some embodiments, as shown in FIG. 6 , the first control circuit 250 includes: a first input unit 251 for receiving the test mode entry signal MR0_EN, and generating and outputting the first input signal MR0_EN_IN1 having the same level as the test mode entry signal according to the test mode entry signal MR0_EN; a second input unit 252 for receiving the first control signal TMF_MR0_RESET_DIS, and according to the first control signal TMF_MR0_RESET_DIS, generates and outputs a second input signal TMF_MR0_RESET_IN2 with a level opposite to that of the first control signal; a first operation unit 253, connected to the first input unit 251 and the second input unit 252, for receiving the first input signal and the second input signal, and generates and outputs the first internal signal TMF_MR0_INT1 according to the first input signal MR0_EN_IN1 and the second input signal TMF_MR0_RESET_IN2.

In the embodiment of the present disclosure, the first control circuit 250 includes a first input unit 251, a second input unit 252 and a first operation unit 253. The input end of the first input unit 251 is connected to the mode register, the input end of the second input unit 252 is used to receive the first control signal TMF_MR0_RESET_DIS, and the input end of the first operation unit 253 is connected to the output ends of the first input unit 251 and the second input unit 252, and is used to receive the first input signal and the second input signal.

The first input unit 251 can output the first input signal MR0_EN_IN1 according to the received test mode entry signal MR0_EN, and the first input unit 251 can be used for signal amplification, signal shaping, and enhancing the driving capability of the signal. Exemplarily, the first input unit 251 may include at least one buffer, and the level of the first input signal MR0_EN_IN1 here may be the same as the level of the test mode entry signal MR0_EN.

The second input unit 252 can output the second input signal TMF_MR0_RESET_IN2 according to the received first control signal TMF_MR0_RESET_DIS, and the second input unit 252 can play the role of signal shaping, signal inversion, etc. Exemplarily, the second input unit 252 may include an odd number of inverters connected in series, and the level of the second input signal TMF_MR0_RESET_IN2 here may be opposite to the level of the first control signal TMF_MR0_RESET_DIS.

The first operation unit 253 can output the first internal signal TMF_MR0_INT1 according to the received first input signal MR0_EN_IN1 and the second input signal TMF_MR0_RESET_IN2. Exemplarily, the first operation unit 253 may include a NAND gate and an inverter connected in series, wherein the two input ends of the NAND gate are used to receive the first input signal MR0_EN_IN1 and the second input signal TMF_MR0_RESET_IN2, and the output end of the inverter is used to output the first internal signal TMF_MR0_INT1.

Specifically, the truth table of each signal in the first control circuit 250 is shown in Table 1, where "0" represents a logic low level and "1" represents a logic high level.

Table 1

Thus, when the first control signal TMF_MR0_RESET_DIS is at a high level, the second input signal TMF_MR0_RESET_IN2 is at a low level. Therefore, no matter whether the test mode entry signal MR0_EN is at a high level or a low level, the first internal signal output by the first operation unit 253 is TMF_MR0_INT1 is low level; only when the first control signal TMF_MR0_RESET_DIS is low level and the second input signal TMF_MR0_RESET_IN2 is high level, the level of the first internal signal TMF_MR0_INT1 output by the first operation unit 253 is the same as the level of the test mode entry signal MR0_EN.

In some embodiments, as shown in Figure 6, the first input unit 251 includes a buffer 254, the input end of the buffer 254 is used to receive the test mode entry signal MR0_EN, and the output end of the buffer 254 is used to output the first input signal MR0_EN_IN1; the second input unit 252 includes a second inverter 255, the input end of the second inverter 255 is used to receive the first control signal TMF_MR0_RESET_DIS, and the output end of the second inverter 255 is used to output the second input signal TMF_MR0_RESET_IN2.

In some embodiments, the buffer 254 includes: an even number of cascaded inverters. Specifically, as shown in FIG6 , the buffer 254 may be two inverters connected in series.

In some embodiments, as shown in FIG6 , the first operation unit 253 includes: a NAND gate 258, the input end of the NAND gate 258 is used to receive the first input signal and the second input signal; a first inverter 259, the input end of the first inverter 259 is connected to the output end of the NAND gate 258; the output end of the first inverter 259 is used to output the first internal signal.

In some embodiments, as shown in FIG. 6 , the second control circuit 260 includes: a second operation unit 261, connected to the first input unit 251 and the first operation unit 253, for receiving the first input signal MR0_EN_IN1 and the first internal signal TMF_MR0_INT1, and in response to the received second control signal TMF_MR0_CONTROL_DIS, generating and outputting the test mode reset signal TMF_MR0_RESET_OUT according to the first input signal MR0_EN_IN1 and the first internal signal TMF_MR0_INT1; When the level of the second control signal TMF_MR0_CONTROL_DIS is the first level, the second control circuit 260 is used to output the test mode reset signal TMF_MR0_RESET_OUT which is the same as the level of the first input signal MR0_EN_IN1; when the level of the second control signal TMF_MR0_CONTROL_DIS is the second level, the second control circuit 260 is used to output the test mode reset signal TMF_MR0_RESET_OUT which is the same as the level of the first internal signal TMF_MR0_INT1.

In the embodiment of the present disclosure, the second control circuit 260 may include a second operation unit 261, two input ends of the second operation unit 261 are respectively connected to the output ends of the first input unit 251 and the first operation unit 253, and the output end of the second operation unit 261 may be connected to the test mode circuit. The two input ends of the second operation unit 261 are respectively used to receive the first input signal MR0_EN_IN1 and the first internal signal TMF_MR0_INT1, and the output end of the second operation unit 261 is used to output the test mode reset signal TMF_MR0_RESET_OUT.

The second operation unit 261 can select to output the test mode reset signal TMF_MR0_RESET_OUT having the same level as the first internal signal TMF_MR0_INT1 or the first input signal MR0_EN_IN1 according to the level of the second control signal TMF_MR0_CONTROL_DIS. That is, the second operation unit 261 can shield the first control signal TMF_MR0_RESET_DIS through the second control signal TMF_MR0_CONTROL_DIS.

When the level of the second control signal TMF_MR0_CONTROL_DIS is high, the second operation unit 261 ignores the first internal signal TMF_MR0_INT1, that is, no matter whether the level of the first control signal TMF_MR0_RESET_DIS is high or low, the second operation unit 261 outputs the test mode reset signal TMF_MR0_RESET_OUT which is the same as the level of the first input signal MR0_EN_IN1. At this time, the level of the test mode reset signal TMF_MR0_RESET_OUT is consistent with the level of the test mode entry signal MR0_EN, that is, the current test mode entry signal MR0_EN indicates to execute the clock signal duty cycle adjustment.

In the case where the level of the second control signal TMF_MR0_CONTROL_DIS is low, the second operation unit 261 ignores the first input signal MR0_EN_IN1 and outputs the test mode reset signal TMF_MR0_RESET_OUT having the same level as the first internal signal TMF_MR0_INT1.

In some embodiments, as shown in FIG. 6 , the second operation unit 261 includes: a data selector 262, the input end of the data selector 262 is used to receive the first input signal MR0_EN_IN1 and the first internal signal TMF_MR0_INT1, and the control end of the data selector 262 is used to receive the second control signal TMF_MR0_CONTROL_DIS; wherein, when the level of the second control signal TMF_MR0_CONTROL_DIS is the second level, the data selector 262 is used to output the first internal signal TMF_MR0_IN T1 level is opposite to the second internal signal TMF_MR0_INT2; when the level of the second control signal TMF_MR0_CONTROL_DIS is the first level, the data selector 262 is used to output the second internal signal TMF_MR0_INT2 which is opposite to the level of the first input signal MR0_EN_IN1; a third inverter 263, the input end of the third inverter 263 is connected to the output end of the data selector 262, and is used to output the test mode reset signal TMF_MR0_RESET_OUT according to the second internal signal TMF_MR0_INT2.

Specifically, the truth table of each signal in the reset signal generating circuit 220 is shown in Table 2, wherein "0" represents a logic low level, "1" represents a logic high level, and "V" represents a valid value, that is, either a logic high level or a logic low level. It can be understood that by setting the first control circuit 250 and the second control circuit 260, and configuring the level combination of the first control signal TMF_MR0_RESET_DIS and the second control signal TMF_MR0_CONTROL_DIS, when the level of the test mode entry signal MR0_EN is high but does not indicate the execution of the clock signal duty cycle adjustment, the level of the test mode reset signal TMF_MR0_RESET_OUT output to the test mode circuit can be low, that is, when the level of the test mode entry signal MR0_EN is high but does not indicate the execution of the clock signal duty cycle adjustment, the test mode signal TM will not be reset, resulting in the duty cycle adjustment process restarting.

Table 2

In some embodiments, the reset signal generating circuit 220 may include only the first control circuit 250, but not the second control circuit 260. In this case, the first internal signal output by the first control circuit 250 may be used as a test mode reset signal, and its corresponding signal truth table is shown in Table 3. It can be understood that, on the basis of the first control circuit 250, adding the second control circuit 260 and setting the second control signal TMF_MR0_CONTROL_DIS for shielding the first control signal TMF_MR0_RESET_DIS can improve the reliability of the reset signal generating circuit 220.

Table 3

In some embodiments, as shown in Figure 7, the delay locked loop circuit 240 includes: a clock division circuit 241, used to generate a plurality of divided clock signals CLK_F with different phases according to the clock signal CLK; a duty cycle correction circuit 242, connected to the test mode circuit 230 and the clock division circuit 241, the duty cycle correction circuit 242 includes a plurality of duty cycle correction sub-circuits 244; each of the duty cycle correction sub-circuits 244 is used to adjust the duty cycle of the divided clock signal CLK_F according to the test mode signal TM to output a corrected clock signal CLK_C.

In the embodiment of the present disclosure, the delay locked loop circuit 240 has a clock frequency division circuit 241 and a duty cycle correction circuit 242. It is understandable that the delay locked loop circuit 240 may also include other circuits, such as a phase detection circuit, a duty cycle detection circuit, etc. In some embodiments, the delay locked loop circuit 240 further includes: a clock recovery circuit 243, connected to the duty cycle correction circuit 242; and used to select one of the multiple corrected clock signals CLK_C as the internal clock signal CLK_O for output.

The clock frequency dividing circuit 241 can divide the clock signal CLK input to the delay locked loop circuit 240 into a plurality of frequency divided clock signals CLK_F with phase differences, such as an odd clock signal and an even clock signal. Here, the odd clock signal and the even clock signal can have a phase difference of 180 degrees.

The duty cycle correction circuit 242 includes a plurality of duty cycle correction sub-circuits 244. Each duty cycle correction sub-circuit 244 can adjust the duty cycle of a divided clock signal CLK_F according to the test mode signal TM, and output a corresponding corrected clock signal CLK_C. The clock recovery circuit 243 can select one of the plurality of corrected clock signals CLK_C output by the duty cycle correction circuit 242 to output as the internal clock signal CLK_O.

In some embodiments, the test mode signal includes multiple test mode sub-signals, and the duty cycle correction sub-circuit includes: a multi-stage adjustment unit connected in series, each stage of the adjustment unit is used to receive at least one of the test mode sub-signals to gradually adjust the duty cycle of the divided clock signal; the input end of the first stage of the adjustment unit is used to receive the divided clock signal, and the input end of each of the remaining stages of the adjustment unit is connected to the output end of the previous stage of the adjustment unit, and the output end of the last stage of the adjustment unit is used to output the corrected clock signal.

In some embodiments, the regulating unit includes: a fourth inverter and at least one pulse regulating unit; the input end of the fourth inverter is connected to the input end of the pulse regulating unit, and they are used together as the input end of the regulating unit; the output end of the fourth inverter is connected to the output end of the pulse regulating unit, and they are used together as the output end of the regulating unit; the control end of the pulse regulating unit is connected to the test mode circuit, which is used to receive the corresponding test mode sub-signal; the fourth inverter and the input end of the pulse regulating unit in the first stage of the regulating unit are used to receive the divided clock signal; the fourth inverter and the input end of the pulse regulating unit in each of the remaining stages of the regulating unit are used to receive the intermediate clock signal output by the previous stage of the regulating unit; the output end of the fourth inverter and the pulse regulating unit in the last stage of the regulating unit is used to output the correction clock signal; the output end of the fourth inverter and the pulse regulating unit in each of the remaining stages of the regulating unit is used to output the intermediate clock signal; the pulse regulating unit is used to adjust the width of the high level pulse and the low level pulse in the intermediate clock signal according to the test mode sub-signal.

In some embodiments, the pulse adjustment unit includes: a first switching transistor, the source of which is connected to a first voltage terminal; a gate of which is connected to an input terminal of the fourth inverter for receiving the intermediate clock signal or the divided clock signal; a second switching transistor, the source of which is connected to a second voltage terminal; a gate of which is connected to an input terminal of the fourth inverter for receiving the intermediate clock signal or the divided clock signal; a pull-up transistor, the source of which is connected to a drain of the first switching transistor; a gate of which is used to receive a corresponding test mode sub-signal; a drain of which is connected to the output terminal of the fourth inverter; a pull-down transistor, the source of which is connected to a drain of the second switching transistor; a gate of which is used to receive a corresponding test mode sub-signal; and a drain of which is connected to the output terminal of the fourth inverter.

In the embodiment of the present disclosure, the duty cycle correction subcircuit can be understood with reference to FIG. 2 , which will not be described in detail here. It is worth noting that the fourth inverter here can correspond to the inverter 143 in FIG. 2 .

In a second aspect, as shown in FIG. 8 , an embodiment of the present disclosure provides a memory 300 , including: a memory cell array 310 ; and a peripheral circuit 320 , including the control circuit 200 described in any one of the above embodiments.

In the disclosed embodiment, the memory 300 includes but is not limited to DRAM, static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc. The peripheral circuit 320 is connected to the memory cell array 310, and the control circuit 200 is located in the peripheral circuit 320. In this way, by adjusting the level of the control signal, the reset signal generating circuit can output a test mode reset signal of a different level from the test mode entry signal. Therefore, the test mode circuit can reset the test mode signal according to the test mode reset signal, rather than directly resetting the test mode signal according to the test mode entry signal, so that when the current test mode entry signal is reset and In the case of non-instruction execution of clock signal duty cycle adjustment, the delay locked loop circuit is reduced to readjust the clock signal duty cycle according to the reset test mode signal, thereby saving the time required for adjusting the clock signal duty cycle.

It should be noted that the features disclosed in several method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Industrial Applicability

In the control circuit provided in the embodiment of the present disclosure, the reset signal generating circuit is used to output a test mode reset signal according to at least one control signal and a test mode entry signal. In this way, by adjusting the level of the control signal, the reset signal generating circuit can output a test mode reset signal of a different level from the test mode entry signal. Therefore, the test mode circuit can reset the test mode signal according to the test mode reset signal, rather than directly resetting the test mode signal according to the test mode entry signal, thereby reducing the situation where the delay locked loop circuit readjusts the clock signal duty cycle according to the reset test mode signal, saving the time required to adjust the clock signal duty cycle.

Claims (15)

A control circuit (200), comprising: A reset signal generating circuit (220) is used to receive a control signal and a test mode entry signal, and generate and output a test mode reset signal according to the control signal and the test mode entry signal; A test mode circuit (230) is connected to the reset signal generating circuit (220), and the test mode circuit (230) is used to reset and output a test mode signal according to the test mode reset signal; wherein the test mode signal indicates a duty cycle adjustment of a clock signal. The control circuit (200) according to claim 1, wherein the control signal comprises a first control signal and a second control signal; the reset signal generating circuit (220) comprises a first control circuit (250) for receiving the first control signal, and a second control circuit (260) for receiving the second control signal; The first control circuit (250) is further used to receive the test mode entry signal, and output a first input signal according to the test mode entry signal, and output a first internal signal according to the first control signal and the test mode entry signal; The second control circuit (260) is connected to the first control circuit (250), and is used to receive the first input signal and the first internal signal, and output the test mode reset signal according to the second control signal, the first internal signal and the first input signal. The control circuit (200) according to claim 2, wherein: When the level of the first control signal is a first level, the first control circuit (250) is used to output the first internal signal at a second level; When the level of the first control signal is the second level, the first control circuit (250) is used to output the first internal signal having the same level as the test mode entry signal; The first control circuit (250) is further used for outputting the first input signal having the same level as the test mode entry signal. The control circuit (200) according to claim 3, wherein the first control circuit (250) include: A first input unit (251) is used to receive the test mode entry signal and, based on the test mode entry signal, generate and output the first input signal having the same level as the test mode entry signal; A second input unit (252) is used to receive the first control signal, and generate and output a second input signal having a level opposite to that of the first control signal according to the first control signal; The first operation unit (253) is connected to the first input unit (251) and the second input unit (252), and is used to receive the first input signal and the second input signal, and generate and output the first internal signal according to the first input signal and the second input signal. The control circuit (200) according to claim 4, wherein the first operation unit (253) comprises: A NAND gate (258), wherein an input end of the NAND gate (258) is used to receive the first input signal and the second input signal; A first inverter (259), wherein the input end of the first inverter (259) is connected to the output end of the NAND gate (258); and the output end of the first inverter (259) is used to output the first internal signal. The control circuit (200) according to claim 4 or 5, wherein: The first input unit (251) comprises a buffer (254), the input end of the buffer (254) is used to receive the test mode entry signal, and the output end of the buffer (254) is used to output the first input signal; The second input unit (252) comprises a second inverter (255), the input end of the second inverter (255) is used to receive the first control signal, and the output end of the second inverter (255) is used to output the second input signal. The control circuit (200) according to claim 6, wherein the buffer (254) comprises: an even number of cascaded inverters. The control circuit (200) according to any one of claims 4 to 7, wherein the second control circuit (260) comprises: A second operation unit (261), connected to the first input unit (251) and the first operation unit (253), configured to receive the first input signal and the first internal signal, and in response to the received second control signal, generate and output the test mode reset signal according to the first input signal and the first internal signal; When the level of the second control signal is the first level, the second control circuit (260) is used to output the test mode reset signal having the same level as the first input signal; When the level of the second control signal is the second level, the second control circuit (260) is used to output the test mode reset signal having the same level as that of the first internal signal. The control circuit (200) according to claim 8, wherein the second operation unit (261) comprises: A data selector (262), wherein an input end of the data selector (262) is used to receive the first input signal and the first internal signal, and a control end of the data selector (262) is used to receive the second control signal; wherein, when the level of the second control signal is the second level, the data selector (262) is used to output a second internal signal having a level opposite to that of the first internal signal, and when the level of the second control signal is the first level, the data selector (262) is used to output a second internal signal having a level opposite to that of the first input signal; A third inverter (263), wherein an input end of the third inverter (263) is connected to an output end of the data selector (262) and is used to receive the second internal signal, and an output end of the third inverter (263) is used to output the test mode reset signal. The control circuit (200) according to any one of claims 1 to 9, wherein the control circuit (200) further comprises: A command and address decoder (150), configured to receive a mode register configuration command and generate a corresponding mode register configuration value according to the mode register configuration command by decoding; A mode register circuit (110), connected to the command and address decoder (150), for generating the test mode entry signal according to the configuration value of the mode register; A delay locked loop circuit (240) is connected to the test mode circuit (230) and is used to The test mode signal adjusts the duty cycle of the clock signal. The control circuit (200) according to claim 10, wherein the delay locked loop circuit (240) comprises: A clock frequency division circuit (241), used for generating a plurality of frequency-divided clock signals with different phases according to the clock signal; A duty cycle correction circuit (242) is connected to the test mode circuit (230) and the clock frequency division circuit (241), wherein the duty cycle correction circuit (242) comprises a plurality of duty cycle correction subcircuits (244); each of the duty cycle correction subcircuits (244) is used to adjust the duty cycle of a frequency-divided clock signal according to the test mode signal to output a corrected clock signal. The control circuit (200) according to claim 11, wherein the test mode signal comprises a plurality of test mode sub-signals, and the duty cycle correction sub-circuit (244) comprises: A plurality of adjustment units connected in series, each of which is used to receive at least one of the test mode sub-signals to adjust the duty cycle of the divided clock signal step by step; The input end of the first-stage regulating unit is used to receive the divided clock signal, the input end of each of the remaining stages of regulating units is connected to the output end of the previous stage of regulating unit, and the output end of the last stage of regulating unit is used to output the corrected clock signal. The control circuit (200) according to claim 12, wherein the adjustment unit comprises: A fourth inverter and at least one pulse adjustment unit; the input end of the fourth inverter is connected to the input end of the pulse adjustment unit and serves as the input end of the adjustment unit; the output end of the fourth inverter is connected to the output end of the pulse adjustment unit and serves as the output end of the adjustment unit; The control end of the pulse adjustment unit is connected to the test mode circuit (230) and is used to receive the corresponding test mode sub-signal; The fourth inverter in the first-stage regulating unit and the input end of the pulse regulating unit are used to receive the divided clock signal; the fourth inverter in each of the remaining stages and the input end of the pulse regulating unit are used to receive the intermediate clock signal output by the previous stage regulating unit. Signal; The output end of the fourth inverter and the pulse adjustment unit in the last stage of the adjustment unit is used to output the correction clock signal; the output end of the fourth inverter and the pulse adjustment unit in each of the remaining stages of the adjustment unit is used to output the intermediate clock signal; The pulse adjustment unit is used to adjust the width of the high level pulse and the low level pulse in the intermediate clock signal according to the test mode sub-signal. The control circuit (200) according to claim 13, wherein the pulse adjustment unit comprises: a first switch transistor, wherein a source of the first switch transistor is connected to a first voltage terminal; a gate of the first switch transistor is connected to an input terminal of the fourth inverter, and is used to receive the intermediate clock signal or the divided clock signal; a second switch transistor, wherein the source of the second switch transistor is connected to the second voltage terminal; and the gate of the second switch transistor is connected to the input terminal of the fourth inverter, and is used to receive the intermediate clock signal or the divided clock signal; a pull-up transistor, wherein the source of the pull-up transistor is connected to the drain of the first switch transistor; the gate of the pull-up transistor is used to receive the corresponding test mode sub-signal; the drain of the pull-up transistor is connected to the output end of the fourth inverter; A pull-down transistor, the source of which is connected to the drain of the second switch transistor; the gate of which is used to receive the corresponding test mode sub-signal; and the drain of which is connected to the output end of the fourth inverter. A memory (300), comprising: A memory cell array (310); A peripheral circuit (320) comprising the control circuit (200) according to any one of claims 1 to 14.