WO2024174396A1 - Register - Google Patents

Abstract

A register, comprising a state latch circuit, an output circuit and a state transition circuit. The output circuit is connected to the state latch circuit; the state latch circuit latches, at an output end, a plurality of pieces of current state data of an input end under triggering of one clock pulse signal; the state transition circuit is connected to the state latch circuit; the state transition circuit performs a logic operation on a multi-bit current state output and then outputs multi-bit next state data; and the output circuit performs a logic operation on the multi-bit current state output and then outputs multi-bit output data.

Description

register

This disclosure claims the priority of the Chinese patent application filed with the China Patent Office on February 23, 2023, with application number 202310174752.9 and application name “Register”, the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure is related to but not limited to a register.

Background Art

A linear feedback shift register (LFSR) is a shift register that, given the output of the previous state, uses a linear function of the output as its input.

However, if all the data in the LRSR are to be read out, multiple shifts are required, which takes a long time.

Summary of the invention

An embodiment of the present disclosure provides a register, including:

The state latch circuit receives a clock pulse signal at the clock end, and latches the multi-bit current state data at the input end at the output end under the triggering of a clock pulse signal;

An output circuit connected to the output end of the state latch circuit and used for performing a logic operation on the multi-bit current state data output by the state latch circuit and then outputting a multi-bit output data;

The state transfer circuit has an input end connected to the output end of the state latch circuit and an output end connected to the input end of the state latch circuit, and is used to perform a logic operation on the multi-bit current state data output by the state latch circuit as the next state data output.

In some embodiments, the state latch circuit includes: multiple latches; the input end of each latch is connected to the output end of the state transfer circuit, the clock end of each latch receives a clock pulse signal, the output end of each latch is connected to the input end of the output circuit, and the output end of each latch is connected to the input end of the state transfer circuit.

In some embodiments, the state transfer circuit includes: a plurality of transfer modules; each transfer module receives at least two current state data, performs a logic operation on the at least two current state data, and outputs a next state data.

In some embodiments, the output circuit includes: a plurality of output modules; each output module receives at least two current state data, performs a logic operation on the at least two current state data, and outputs an output data.

In some embodiments, the number of latches and the number of transfer modules are both 8, the current state data output by the 8 latches are recorded as the first current state data, the second current state data, ... the eighth current state data, and the 8 transfer modules are recorded as the first transfer module, the second transfer module, ... the eighth transfer module;

The first transfer module performs a logic operation on the first current state data, the second current state data, the fourth current state data and the seventh current state data to generate the first next state data;

The second transfer module performs a logic operation on the first current state data, the second current state data, the third current state data, the fifth current state data and the eighth current state data to generate the second next state data;

The third transfer module generates the third next state data according to the second current state data, the third current state data, the fourth current state data and the sixth current state data;

The fourth transfer module generates the fourth next state data according to the third current state data, the fourth current state data, the fifth current state data and the seventh current state data;

The fifth transfer module generates fifth next state data according to the first current state data, the second current state data, the fifth current state data, the sixth current state data, the seventh current state data and the eighth current state data;

The sixth transfer module generates the sixth next state data according to the third current state data, the fourth current state data, the sixth current state data and the eighth current state data;

The seventh transfer module generates seventh next state data according to the second current state data and the fifth current state data;

The eighth transfer module generates the eighth next state data based on the first current state data, the third current state data and the sixth current state data.

In some embodiments, the output terminal of the first latch outputs the first output data, the output terminal of the second latch outputs the second output data, the output terminal of the third latch outputs the third output data, and the output terminal of the fourth latch outputs the fourth output data.

In some embodiments, the number of output modules is 12, and the 12 output modules are recorded as the first output module, the second output module, ... the twelfth output module;

The first output module generates fifth output data according to the first current state data and the fifth current state data;

The second output module generates sixth output data according to the first current state data, the second current state data and the sixth current state data;

The third output module generates seventh output data according to the first current state data, the second current state data, the third current state data and the seventh current state data;

The fourth output module generates eighth output data according to the second current state data, the third current state data, the fourth current state data and the eighth current state data;

The fifth output module generates ninth output data according to the third current state data, the fourth current state data and the fifth current state data;

The sixth output module generates the tenth output data according to the fourth current state data, the fifth current state data and the sixth current state data;

The seventh output module generates the eleventh output data according to the first current state data, the fifth current state data, the sixth current state data and the seventh current state data;

The eighth output module generates the twelfth output data according to the second current state data, the sixth current state data, the seventh current state data and the eighth current state data;

The ninth output module generates the thirteenth output data according to the third current state data, the seventh current state data and the eighth current state data;

The tenth output module generates the fourteenth output data according to the first current state data, the fourth current state data and the eighth current state data;

The 11th output module generates 15th output data according to the 2nd current state data and the 5th current state data;

The twelfth output module generates sixteenth output data based on the first current state data, the third current state data, and the sixth current state data.

In some embodiments, the first transfer module includes:

An 18th XOR gate, having a first input terminal connected to the output terminal of the 4th latch, a second input terminal connected to the output terminal of the 7th latch, and an output terminal connected to the first input terminal of the 19th XOR gate;

A 19th XOR gate, a second input terminal connected to the output terminal of the 20th XOR gate, and an output terminal connected to the input terminal of the 1st latch;

A 20th XOR gate, a first input terminal connected to the output terminal of the first latch, and a second input terminal connected to the output terminal of the second latch;

The second transfer module includes:

A 21st XOR gate, having a first input terminal connected to the output terminal of the 3rd latch, a second input terminal connected to the output terminal of the 5th latch, and an output terminal connected to the first input terminal of the 22nd XOR gate;

A 22nd XOR gate, a second input terminal of which is connected to the output terminal of the 8th latch, and an output terminal of which is connected to the second input terminal of the 23rd XOR gate;

A 23rd XOR gate, a first input terminal connected to the output terminal of the 20th XOR gate, and an output terminal connected to the input terminal of the second latch;

The third transfer module includes:

A 24th XOR gate, having a first input terminal connected to the output terminal of the second latch, a second input terminal connected to the output terminal of the sixth latch, and an output terminal connected to the first input terminal of the 25th XOR gate;

A 25th XOR gate, a second input terminal of which is connected to the output terminal of the 26th XOR gate, and an output terminal of which is connected to the input terminal of the 3rd latch;

A 26th XOR gate, a first input terminal connected to the output terminal of the third latch, and a second input terminal connected to the output terminal of the fourth latch;

Transfer Module 4 includes:

A 27th XOR gate, having a first input terminal connected to the output terminal of the 26th XOR gate, a second input terminal connected to the output terminal of the 28th XOR gate, and an output terminal connected to the input terminal of the 4th latch;

A 28th XOR gate, a first input terminal connected to the output terminal of the 5th latch, and a second input terminal connected to the output terminal of the 7th latch;

Transfer Module 5 includes:

A 29th XOR gate, having a first input terminal connected to the output terminal of the 28th XOR gate, a second input terminal connected to the output terminal of the 20th XOR gate, and an output terminal connected to the first input terminal of the 30th XOR gate;

A 30th XOR gate, a second input terminal connected to the output terminal of the 31st XOR gate, and an output terminal connected to the input terminal of the 5th latch;

The first input of the 31st XOR gate is connected to the output of the 6th latch, and the second input is connected to the input of the 8th latch. Outgoing end;

Transfer Module 6 includes:

The 32nd XOR gate has a first input terminal connected to the output terminal of the 31st XOR gate, a second input terminal connected to the output terminal of the 26th XOR gate, and an output terminal connected to the input terminal of the 6th latch.

In some embodiments, the seventh transfer module includes:

A 33rd XOR gate, a first input terminal connected to the output terminal of the second latch, a second input terminal connected to the output terminal of the fifth latch, and an output terminal connected to the input terminal of the seventh latch;

Transfer Module 8 includes:

A 34th XOR gate, having a first input terminal connected to the output terminal of the first latch, a second input terminal connected to the output terminal of the third latch, and an output terminal connected to the first input terminal of a 35th XOR gate;

The 35th XOR gate has a second input terminal connected to the output terminal of the 6th latch, and an output terminal connected to the input terminal of the 8th latch.

In some embodiments, the first output module includes: a first XOR gate, a first input terminal connected to the output terminal of the first latch, a second input terminal connected to the output terminal of the fifth latch, and outputting fifth output data;

The second output module includes: a second XOR gate, a first input end of which is connected to the output end of the sixth latch, a second input end of which is connected to the output end of the 20th XOR gate, and outputs the sixth output data;

The third output module includes:

A third XOR gate, wherein the first input terminal is connected to the output terminal of the third latch, the second input terminal is connected to the output terminal of the seventh latch, and the output terminal is connected to the second input terminal of the fourth XOR gate;

The 4th XOR gate has a first input terminal connected to the output terminal of the 20th XOR gate, and an output terminal outputs the 7th output data.

In some embodiments, the fourth output module includes:

A fifth XOR gate, having a first input terminal connected to the output terminal of the second latch, a second input terminal connected to the output terminal of the eighth latch, and an output terminal connected to the first input terminal of the sixth XOR gate;

A sixth XOR gate, a second input terminal connected to the output terminal of the twenty-sixth XOR gate, and an output terminal outputting the eighth output data;

The 5th output module includes:

The 7th XOR gate has a first input terminal connected to the output terminal of the 26th latch, a second input terminal connected to the output terminal of the 5th latch, and an output terminal outputting the 9th output data.

In some embodiments, the sixth output module comprises:

An eighth XOR gate, having a first input terminal connected to the output terminal of the fifth latch, a second input terminal connected to the output terminal of the sixth latch, and an output terminal connected to the second input terminal of the ninth XOR gate;

A ninth XOR gate, a first input terminal connected to the output terminal of the fourth latch, and an output terminal outputting the tenth output data;

The 7th output module includes:

A tenth XOR gate, having a first input terminal connected to the output terminal of the first latch, a second input terminal connected to the output terminal of the seventh latch, and an output terminal connected to the second input terminal of the eleventh XOR gate;

The 11th XOR gate has a first input terminal connected to the output terminal of the 8th XOR gate, and an output terminal outputs the 11th output data.

In some embodiments, the eighth output module comprises:

A 12th XOR gate, having a first input terminal connected to the output terminal of the second latch, a second input terminal connected to the output terminal of the sixth latch, and an output terminal connected to the first input terminal of a 13th XOR gate;

A 13th XOR gate, a second input terminal of which is connected to an output terminal of a 14th XOR gate, and outputs a 12th output data;

A 14th XOR gate, a first input terminal connected to the output terminal of the 7th latch, and a second input terminal connected to the output terminal of the 8th latch;

The 9th output module includes:

The 15th XOR gate has a first input terminal connected to the output terminal of the 14th XOR gate, a second input terminal connected to the output terminal of the 3rd latch, and outputs the 13th output data.

In some embodiments, the tenth output module comprises:

A 16th XOR gate, having a first input terminal connected to the output terminal of the first latch, a second input terminal connected to the output terminal of the fourth latch, and an output terminal connected to the first input terminal of a 17th XOR gate;

The 17th XOR gate has a second input terminal connected to the output terminal of the 8th latch and outputs the 14th output data.

In some embodiments, the 33rd XOR gate outputs the 15th output data. The 35th XOR gate outputs the 16th output data.

The present application discloses a register, the register includes a state latch circuit, an output circuit and a state transfer circuit, the output circuit is connected to the output end of the state latch circuit, the state latch circuit latches multiple current state data of the input end at the output end under the triggering of a clock pulse signal, the input end of the state transfer circuit is connected to the output end of the state latch circuit, the output end of the state transfer circuit is connected to the input end of the state latch circuit, the state transfer circuit performs a logic operation on the multiple current state outputs and then outputs multiple next state data, the output circuit performs a logic operation on the multiple current state outputs and then outputs multiple output data, so that multiple output data is output after one clock pulse signal, and the input end of the state latch circuit is the next state data. In this way, the function of the LFSR is realized, and the command, data or address in the register can be output after only one shift.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

FIG1 is a schematic diagram of the structure of an exemplary memory;

FIG2 is a schematic diagram of the structure of an exemplary linear feedback shift register;

FIG3 is a schematic diagram of the structure of an example register;

FIG4 is a schematic diagram of a specific structure of an example based on the register shown in FIG3 ;

FIG. 5 is a schematic diagram of a specific structure of an example based on the register shown in FIG. 3 .

Reference numerals:

_L0n , 1st current state data; _L1n , 2nd current state data; _L2n , 3rd current state data; _L3n , 4th current state data; _L4n , 5th current state data; _L5n , 6th current state data; _L6n , 7th current state data; state data; _L7n , 8th current state data; L0, 1st latch; L1, 2nd latch; L2, 3rd latch; L3, 4th latch; L4, 5th latch; L5, 6th latch; L6, 7th latch; L7, 8th latch; 100, state latch circuit; 200, state transfer circuit; 300, output circuit; O0, 1st output data; O1, 2nd output data; O2, 3rd output data; O3, 4th output data; O4, 5th output data; O5, 6th output data; O6, 7th output data; O7, 8th output data; O8, 9th output data; O9, 10th output data; O10, 11th output data; O11, 12th output data; O12, 13th output data; O14, 15th output data; O15, 16th output data.

The above drawings have shown clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments.

DETAILED DESCRIPTION

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

In the description of this embodiment, it should be noted that if the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product is usually placed when used. It is only for the convenience of description and simplified description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this.

At present, memory technology is developing rapidly. Taking DRAM as an example, the main applications include synchronous dynamic random access memory (SDRAM), various generations of double data rate (DDRx) SDRAM, various generations of low power double data rate (LPDDRx) SDRAM and other types.

FIG1 is an example diagram of the architecture of a memory device according to an embodiment. As shown in FIG1 , a DRAM is taken as an example, and includes a command decoding circuit, an address circuit, a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a storage block. The command decoding circuit, the address circuit, and the data input/output buffer belong to the peripheral area circuit. The sense amplifier, row decoder, column decoder and storage block belong to the array area circuit. The storage block is mainly composed of word lines, bit lines and storage cells. The word lines in the storage block extend along the row direction, and the bit lines in the storage block extend along the column direction. The intersection of the word line and the bit line is the storage cell of the storage block.

In practical applications, the memory also includes a LFSR for storing addresses, data or instructions. FIG2 is a schematic diagram of the structure of an exemplary LFSR, and the working principle thereof is explained by taking the LFSR shown in FIG2 as an example. As shown in FIG2 , the LFSR includes 8 latches and 3 XOR gates, and the 8 latches are marked as the first latch L0, the second latch L1, the third latch L2, ..., the eighth latch L7 in sequence, and the 3 XOR gates are marked as XOR gate 0, XOR gate 1 and XOR gate 2 in sequence.

Among them, the clock ends of the 1st latch L0 to the 8th latch L7 receive the same clock signal CLK, the input end D of the 8th latch L7 is connected to the output end Q of the 1st latch L0, the output end Q of the 8th latch L7 is connected to the input end D of the 7th latch L6, the output end Q of the 7th latch L6 is connected to the first input end of the XOR gate 2, the second input end of the XOR gate 2 is connected to the output end Q of the 1st latch L0, the output end of the XOR gate 2 is connected to the input end D of the 6th latch L5, the output end Q of the 6th latch L5 is connected to the first input end of the XOR gate 1, and the second input end of the XOR gate 1 is connected to the The output terminal Q of the XOR gate 1 is connected to the input terminal D of the 5th latch L4, the output terminal Q of the 5th latch L4 is connected to the first input terminal of the XOR gate 0, the second input terminal of the XOR gate 0 is connected to the output terminal Q of the 1st latch L0, the output terminal of the XOR gate 0 is connected to the input terminal D of the 4th latch L3, the output terminal Q of the 4th latch L3 is connected to the input terminal D of the 3rd latch L2, the output terminal Q of the 3rd latch L2 is connected to the input terminal D of the 2nd latch L1, the output terminal Q of the 2nd latch L1 is connected to the input terminal D of the 1st latch L0, and the output terminal Q of the 1st latch L0 is the output terminal out of the LFSR.

It takes 16 clock cycles to read or write a command, data, or address from the LFSR, so that the LFSR performs 16 shifts and outputs 16 bits of data from the LFSR output terminal Out. This structure of LFSR can be supported when the memory works at a low frequency, but it cannot be supported when the memory works at a high frequency, for example, the operating frequency is higher than 3Ghz.

Based on the above considerations, the present disclosure provides a register that can realize the function of LFSR, but only needs one shift to output the command, data or address in the register. It should also be noted that the application of LFSR in a memory is taken as an example here, and the register provided by the present disclosure is not limited to being applied only in a memory.

The following uses the LFSR shown in FIG. 2 as an example to illustrate the design concept. The design concept is not limited to the LFSR shown in FIG. 2 , and other LFSR structures may also be applicable to the design concept.

The initial state data of the input terminal of the first latch L0 is marked as _L0n , the initial state data of the input terminal of the second latch L1 is marked as _L1n , and so on. The initial state data of the input terminal of the eighth latch L7 is marked as _L7n .

When the clock terminals of the first latch L0 to the eighth latch L7 receive the first clock signal, the state data of the input terminal of the first latch L0 at the first clock signal is marked as L0 _n+1 , the state data of the input terminal of the second latch L1 at the first clock signal is marked as L1 _n+1 , and so on. The state data of the input terminal of the eighth latch L7 at the first clock signal is marked as L1 n+1 . The state data at 1 clock signal is marked as L7 _n+1 . Wherein, ⊕ represents an exclusive OR logic operation, and the state data of the input terminals of the first latch L0 to the eighth latch L7 at the first clock signal satisfies the following formula:

The output of the LFSR outputs data at the first clock signal that satisfies the following formula:

_Out0n ＝ _L0n

By analogy, when the clock ends of the first latch L0 to the eighth latch L7 receive the 16th clock signal, the state data of the input end of the first latch L0 at the 16th clock signal is marked as L0 _n+16 , and the state data of the input end of the second latch L1 at the 16th clock signal is marked as L1 _n+16 . By analogy, the state data of the input end of the eighth latch L7 at the 16th clock signal is marked as L7 _n+16 . Among them, the state data of the input ends of the first latch L0 to the eighth latch L7 at the 16th clock signal satisfies the following formula:

The output of the LFSR outputs data at the 16th clock signal that satisfies the following formula:

The 16-bit data output by the LFSR are Out0 _n to Out15 _n in sequence, and the 16-bit data satisfies the following formula:

That is, after 16 shifts, the state data of the input ends of the 1st latch L0 to the 8th latch L7 are obtained by performing logical operations on the initial state data of the 1st latch L0 to the 8th latch L7, and the output data of the output end of the LFSR are obtained by performing logical operations on the initial state data of the 1st latch L0 to the 8th latch L7.

Based on the above considerations, FIG3 is a schematic diagram of the structure of a register provided by an embodiment of the present disclosure. As shown in FIG3 , the register includes a state latch circuit 100 , an output circuit 300 and a state transfer circuit 200 .

The state latch circuit 100 is provided with a clock terminal, an input terminal and an output terminal. The input terminal of the state latch circuit 100 receives a plurality of current state data, and the clock terminal of the state latch circuit 100 receives a clock pulse signal. The state latch circuit 100 latches the multi-bit current state data of the input terminal at the output terminal under the triggering of a clock pulse signal.

The input end of the output circuit 300 is connected to the output end of the state latch circuit 100. The output circuit 300 The state transfer circuit 200 performs a logic operation on the multi-bit current state data output by the state latch circuit 100 and then outputs a multi-bit output data. The input end of the state transfer circuit 200 is connected to the output end of the state latch circuit 100, and the output end of the state transfer circuit 200 is connected to the input end of the state latch circuit 100. The state transfer circuit 200 performs a logic operation on the multi-bit current state data output by the state latch circuit 100 as a multi-bit next state data output. The state transfer circuit 200 determines the logic operation mode of the multiple current state data according to the structure of the LFSR, and the output circuit 300 determines the logic operation mode of the multiple current state data according to the structure of the LFSR.

In the above technical solution, the register includes a state latch circuit 100, an output circuit 300 and a state transfer circuit 200. The input end of the output circuit 300 is connected to the output end of the state latch circuit 100, the input end of the state transfer circuit 200 is connected to the output end of the state latch circuit 100, and the output end of the state transfer circuit 200 is connected to the input end of the state latch circuit 100. The state latch circuit 100 latches the multi-bit current state data of the input end at the output end under the triggering of a clock pulse signal. The state transfer circuit 200 performs a logic operation on the multi-bit current state output and then outputs a multi-bit next state data. The output circuit 300 performs a logic operation on the multiple current state outputs and then outputs a multi-bit output data, so that the multi-bit output data is output after a clock pulse signal, and the input end of the state latch circuit 100 is the next state data. In this way, the function of the LFSR is realized, and the command, data or address in the register can be output after only one shift.

The specific structures of the state latch circuit 100, the state transfer circuit 200 and the output circuit 300 can be designed according to the specific structure of the LFSR, and the structures shown in FIG. 4 and FIG. 5 are used as examples for description.

FIG4 and FIG5 are schematic diagrams of the structure of a register provided in an embodiment of the present disclosure. As shown in FIG4 and FIG5, the state latch circuit 100 includes a plurality of latches, the input end of each latch is connected to the output end of the state transfer circuit 200, the clock end of each latch receives a clock pulse signal, the output end of each latch is connected to the input end of the output circuit 300, the output end of each latch is connected to the input end of the state transfer circuit 200, and each latch is used to latch a current state data at the output end under the triggering of the clock pulse signal. By such a setting, it is realized that multiple bits of current state data are output under the triggering of a clock pulse signal.

In some embodiments, the state transfer circuit 200 includes a plurality of transfer modules, each of which receives at least two current state data and performs a logic operation on the at least two current state data to output a next state data. Each transfer module determines the current state data for performing the logic operation and determines the logic operation mode according to the structure of the LFSR.

In some embodiments, each transfer module includes at least one logic gate circuit, and each logic gate circuit is used to perform a logic operation on two current state data to output a next state data. When the current state data processed by the two transfer modules overlap, the two transfer modules can share one logic gate circuit. By setting it in this way, the number of logic gate circuits can be reduced, and the chip area occupied by the register can be reduced.

In some embodiments, the output circuit 300 includes a plurality of output modules, each of which receives at least two current state data and performs a logic operation on the at least two current state data to output one bit of output data. Each transfer module determines the current state data to be logically operated and determines the logic operation method according to the structure of the LFSR.

In some embodiments, each output module includes at least one logic gate circuit, and each logic gate circuit is used to perform a logic operation on two current state data to output one bit of output data. When the current state data processed by the two output modules overlap, the two output modules can share one logic gate circuit. By setting it in this way, the number of logic gate circuits can be reduced, and the chip area occupied by the register can be reduced.

The specific structures of the state latch circuit 100, the output circuit 300 and the state transfer circuit 200 are designed based on the specific structure of the LFSR shown in FIG. 2.

The number of latches and the number of transfer modules are both 8. The 8 latches are marked as the first latch L0, the second latch L1, the third latch L2, ... the eighth latch L7. The 8 transfer modules are marked as the first transfer module, the second transfer module, ... the eighth transfer module. The input end of the first latch L0 receives the first current state data _L0n , the input end of the second latch L1 receives the second current state data _L1n , and so on. The input end of the eighth latch L7 receives the eighth current state data _L7n .

After the clock terminals of the eight latches receive a clock pulse signal, the output terminal of the first latch L0 outputs the first current state data _L0n , the output terminal of the second latch L1 outputs the second current state data _L1n , and so on. The output terminal of the eighth latch L7 outputs the eighth current state data _L7n .

After 16 shifts, the next state data of the input end of the first latch L0 is: L0n ₊₁₆ = _{L0n ⊕L1n ⊕L3n ⊕L6n} , so the connection relationship between the first transfer module and each latch is: the first transfer module is connected to the output ends of the first latch L0, the second latch L1, the fourth latch L3 and the seventh latch L6. The logic operation mode of the first transfer module is: the first transfer module performs a logic operation on the first current state data _L0n , the second current state data _L1n , the fourth current state data _L3n and the seventh current state data _L6n to generate the first next state data.

After 16 shifts, the state data of the input end of the second latch L1 _is : L1n ₊₁₆ = _L0n ⊕L1n _{⊕L2n ⊕L4n ⊕L7n} , so the connection relationship between the second transfer module and each latch is: the second transfer module is connected to the output ends of the first latch L0, the second latch L1, the third latch L2, the fifth latch L4 and the eighth latch L7. The logic operation mode of the second transfer module is: the second transfer module performs a logic operation on the first current state data _L0n , the second current state data _L1n , the third current state data _L2n , the fifth current state data _L4n and the eighth current state data _L7n to generate the second next state data.

After 16 shifts, the state data of the input end of the third latch L2 _is : L2n _{+16 = L1n⊕L2n⊕L3n⊕L5n} , so the connection relationship between the third transfer module and each latch is: the third transfer module is _connected to the output ends of the second latch L1, the third latch L2, the fourth latch L3 and the sixth latch L5, and the logical operation method of the third transfer module is: the third transfer module generates the third next state data according to the second current state data _L1n , the third current state data _L2n , the fourth current state data _L3n and the sixth current state data _L5n .

After 16 shifts, the state data of the input end of the 4th latch L3 is: L3n ₊₁₆ = _{L2n ⊕L3n ⊕L4n ⊕L6n} . Therefore, the connection relationship between the 4th transfer module and each latch is: the 4th transfer module is connected to the output ends of the 3rd latch L2, the 4th latch L3, the 5th latch L4 and the 7th latch L6. The logical operation mode of the 4th transfer module is: the 4th transfer module transfers the state data of the 3rd current state data L2n, the 4th current state data L3n, the 5th current state data L4 and the 7th latch L6 according to the 3rd current state data _L2n , the 4th current state data L3n, the 5th current state data _L4 and the 7th latch L6. The state data _L4n and the seventh current state data _L6n generate the fourth next state data.

After 16 shifts, the state data of the _input end _of the 5th latch L4 is: L4n ₊₁₆ = _{L0n⊕L1n⊕L4n⊕L5n⊕L6n⊕L7n} , so the connection relationship between the 5th transfer module and each _latch is: the 5th transfer module is connected to the output ends of the 1st latch L0 _, the 2nd latch L1, the 5th latch L4, the 6th latch L5, _the 7th latch L6 and the 8th latch L7, and the logical operation mode of the 5th transfer module is: the 5th transfer module generates the 5th next state data according to the 1st current state data _L0n , the 2nd current state data _L1n , the 5th current state data _L4n , the 6th current state data _L5n , the 7th current state data _L6n and the 8th current state data _L7n .

After 16 shifts, the state data of the input end of the 6th latch L5 _is : L5n _{+16 = L2n⊕L3n⊕L5n⊕L7n} , so the connection relationship between the 6th transfer module and each latch is: the 6th transfer module is _connected to the output ends of the 3rd latch L2, the 4th latch L3, the 6th latch L5 and the 8th latch L7, and the logical operation method of the 6th transfer module is: the 6th transfer module generates the 6th next state data according to the 3rd current state data _L2n , the 4th current state data _L3n , the 6th current state data _L5n and the 8th current state data _L7n .

After 16 shifts, the state data of the input end of the 7th latch L6 is: L6n ₊₁₆ = _L1n ⊕ _L4n , so the connection relationship between the 7th transfer module and each latch is: the 7th transfer module is connected to the output ends of the 2nd latch L1 and the 5th latch L4, and the logical operation method of the 7th transfer module is: the 7th transfer module generates the 7th next state data according to the 2nd current state data _L1n and the 5th current state data _L4n .

After 16 shifts, the state data of the input end of the 8th latch L7 is: L7n _{+16 = L0n⊕L2n⊕L5n} , so the connection relationship between the 8th transfer module and each latch is: the 8th transfer module is connected to the output ends of the 1st latch L0, the 3rd latch L2 and the 6th latch L5, _and the logical operation mode of the 8th transfer module is: the 8th transfer module generates the 8th next state data according to the 1st current state data _L0n , the 3rd current state data _L2n and the 6th current state data _L5n .

In the above technical solution, the state transfer circuit includes 8 transfer modules, each of which is used to perform a logic operation on the corresponding current state transfer data and output the corresponding next state data, so as to ensure that the input terminal state of the state latch circuit 100 is updated to the latest state when the state latch circuit 100 receives a clock pulse signal. In addition, the two transfer modules can share the same logic gate circuit, which can reduce the area occupied by the state transfer circuit.

The specific circuit structure can be designed in the logical operation mode of the first transfer module to the eighth transfer module, and the circuit structure shown in FIG4 is used as an example for explanation, but is not limited to the structure in FIG4. It should be noted that if the value in the XOR gate is "1", it represents the first XOR gate, and if the value in the XOR gate is "2", it represents the second XOR gate, and so on.

The first transfer module, the second transfer module and the fifth transfer module all perform logic operations on the first current state data _L0n and the second current state data _L1n , so the three transfer modules share the 20th XOR gate.

The first transfer module includes: an 18th XOR gate, a 19th XOR gate, and a 20th XOR gate. The first input end of the 18th XOR gate is connected to the output end of the 4th latch L3, the second input end of the 18th XOR gate is connected to the output end of the 7th latch L6, and the 18th XOR gate outputs _{L3n ⊕L6n} . The first input end of the 20th XOR gate is connected to the output end of the 1st latch L0, the second input end of the 20th XOR gate is connected to the output end of the 2nd latch L1, and the 20th XOR gate outputs _L0n ⊕ The output end of the 18th XOR gate is connected to the first input end of the 19th XOR gate, the output _end of the 20th XOR gate is connected to the second input _end of the 19th XOR gate, the output end of the 19th XOR gate is connected to the input _end of the first latch L0, and the 19th _XOR gate is used to output _{L0n⊕L1n⊕L3n⊕L6n , and use L0n⊕L1n⊕L3n⊕L6n} as the next state data of the input end of the first latch L0.

The second transfer module includes a 21st XOR gate, a 22nd XOR gate, and a 23rd XOR gate. The first input end of the 21st XOR gate is connected to the output end of the 3rd latch L2, the second input end of the 21st XOR gate is connected to the output end of the 5th latch L4, _and the 21st XOR gate outputs _L2n⊕L4n . The output end of the 21st XOR gate is connected to the first input end of the 22nd XOR gate, the second input end of the 22nd _XOR gate is connected to the output end of the 8th latch L7, _and the 22nd XOR gate outputs _{L2n⊕L4n⊕L7n} . The output end of the 22nd XOR gate is connected to the second input end of the 23rd XOR gate, the output end of the 20th XOR gate is connected to the first input end of the 23rd XOR gate, the first input end of the 23rd _XOR gate _{receives data L0n⊕L1n, the output end of the 23rd XOR gate is connected to the input end of the second latch L1, and L0n⊕L1n⊕L2n⊕L4n⊕L7n is used as the next state} data of the input end of the second latch L1. It should be noted here that the structure of the second transfer module can also be that the XOR gate is used to perform an XOR operation on the fifth current state data _L4n and the eighth current state data _L7n , and the first-level XOR operation result is XORed with the third current state data _L2n , and then the second-level XOR operation result is XORed with the XOR operation result output by the 20th XOR gate, and then used as the next state data of the input end of the second latch L1.

The third transfer module and the fourth transfer module both perform logic operations on the third current state data _L2n and the fourth current state data _L3n , so the third transfer module and the fourth transfer module share the 26th XOR gate. The fourth transfer module and the fifth transfer module both perform logic operations on the fifth current state data _L4n and the seventh current state data _L6n , so the fourth transfer module and the fifth transfer module share the 28th XOR gate.

The third transfer module includes a 24th XOR gate, a 25th XOR gate and a 26th XOR gate. The first input terminal of the 24th XOR gate is connected to the output terminal of the second latch L1, the second input terminal of the 24th XOR gate is connected to the output terminal of the sixth latch L5, _and the 24th XOR gate outputs _L1n⊕L5n . The first input terminal of the 26th XOR gate is connected to the output terminal of the 3rd latch L2, the second input terminal of the 26th XOR gate is connected to the output terminal of the 4th latch L3, the 26th XOR gate outputs _L2n⊕L3n , _the output terminal of the 24th XOR gate is connected to the first input terminal of the 25th XOR gate, the second input terminal of the 25th XOR gate is connected to the output terminal of the 26th XOR gate, the output terminal of the 25th XOR gate is _connected to the input terminal of the 3rd latch L2, the 25th _XOR gate outputs _{L1n⊕L2n⊕L3n⊕L5n} , _{and L1n⊕L2n⊕L3n⊕L5n is used} as the next state data _of the input terminal of the 3rd latch L2.

The 4th transfer module includes a 27th XOR gate and a 28th XOR gate, the first input end of the 28th XOR gate is connected to the output end of the 5th latch L4, the second input end of the 28th XOR gate is connected to the output end of the 7th latch L6, _and the 28th XOR gate outputs _L4n⊕L6n . The first input end of the 27th XOR gate is connected to the output end of the 26th XOR gate, the first input end of the 27th XOR gate receives _{L2n⊕L3n ,} the second input end of the 27th XOR gate is connected to the output _end of the 28th XOR gate, the output _end of the 27th XOR gate is connected to the input end of the 4th latch L3, the 27th _XOR gate outputs _{L2n⊕L3n⊕L4n⊕L6n , and uses L2n⊕L3n⊕L4n⊕L6n} as the next state data of the input end of the 4th latch L3.

The fifth transfer module includes a 29th XOR gate, a 30th XOR gate, and a 31st XOR gate. The input end is connected to the output end of the 28th XOR gate, the first input end of the 29th XOR gate receives _L4n⊕L6n , the second input end of the 29th XOR _gate is connected to the output _end of the 20th XOR gate, the second input end of the 29th XOR gate receives _{L0n⊕L1n , and} the 29th XOR gate outputs _{L0n⊕L1n⊕L4n⊕L6n .} The first input end of the 31st XOR gate is connected to the output end of the 6th latch L5, the second input end of the 31st XOR gate is connected to the output end of the 8th latch L7, _and the 31st XOR gate outputs _L5n⊕L7n . A first input terminal of the 30th XOR gate is connected to the output terminal of the 29th XOR gate, a second input terminal of the 30th XOR gate is connected to the output _{terminal of} the 31st XOR gate, the output terminal of the 30th XOR gate _is connected to the input _terminal of the 5th latch L4 _{, the} 30th _XOR gate outputs _{L0n⊕L1n⊕L4n⊕L5n⊕L6n⊕L7n , and uses L0n⊕L1n⊕L4n⊕L5n⊕L6n⊕L7n} as the next state data of the input terminal of the 5th latch L4.

The 6th transfer module and the 5th transfer module both perform logic operations on the 6th current state data _L5n and the 8th current state data _L7n , so the 6th transfer module and the 5th transfer module share the 31st XOR gate. The 6th transfer module and the 3rd transfer module both perform logic operations on the 3rd current state data _L2n and the 4th current state data _L3n , so the 6th transfer module and the 3rd transfer module share the 26th XOR gate.

The 6th transfer module includes a 32nd XOR gate, _a first input terminal of the 32nd XOR gate is connected to the output terminal of the 31st XOR gate, a first input terminal of the 32nd XOR gate receives _L5n⊕L7n , a second input terminal of the 32nd XOR gate is connected to the output terminal of the 26th XOR gate, a second input terminal of the 32nd XOR gate receives _L2n⊕L3n , _an output _terminal of the 32nd XOR gate is connected to the input terminal of the 6th latch L5, and the 32nd _XOR gate _{outputs L2n⊕L3n⊕L5n⊕L7n} , _{and L2n⊕L3n⊕L5n⊕L7n is used} as the next state data of the input terminal of the 6th latch L5.

The 7th transfer module includes a 33rd XOR gate, a first input terminal of the 33rd XOR gate is connected to the output terminal of the 2nd latch L1, a second input terminal of the 33rd XOR gate is connected to the output terminal of the 5th latch L4, an output terminal of the 33rd XOR gate is connected to the input terminal of the 7th latch L6, and the 33rd _XOR gate outputs _L1n⊕L4n , _{and L1n⊕L4n} is used as the next state data of the input terminal of the 7th latch L6.

The 8th transfer module includes a 34th XOR gate and a 35th XOR gate, the first input end of the 34th XOR gate is connected to the output _end of the 1st latch L0, the second input end of the 34th XOR gate is connected to the output end of the 3rd latch L2, the 34th XOR gate outputs _L0n⊕L2n , the output end of the 34th XOR gate is connected to the first input end of the 35th XOR gate, the second input end of the 35th XOR gate is connected to the output end of the 6th latch L5, the output end of the 35th XOR gate is connected to the input end of the 8th latch L7, the 35th _XOR gate outputs _{L0n⊕L2n⊕L5n , and uses L0n⊕L2n⊕L5n} as the next state data of the input end of the 8th latch L7. It should also be noted here that the structure of the 8th transfer module can be to first perform XOR on the 3rd current state data _L2n and the 6th current state data _L5n , and then perform XOR on the XOR result with the 1st current state data _L0n as the next state data of the input end of the 8th latch L7.

The circuit structure of the output module is designed according to the requirements. Since the first 4 bits of output data of the LFSR are the current state data of the 1st latch L0 to the 4th latch L3, there is no need to perform logic operations on the current state data of the 1st latch L0 to the 4th latch L3. The last 2 bits of output data of the LFSR are the same as the next state data of the input end of the 7th latch L6 and the next state data of the input end of the 8th latch L7, so the logic gate circuit can be shared with the 7th transfer module and the 8th transfer module. Therefore, the number of output modules is 12, and the 12 output modules output the middle 12 bits of input data. Output data.

More specifically, the 12 output modules are recorded as the 1st output module, the 2nd output module, ... the 12th output module. The output end of the 1st latch L0 outputs the 1st output data O0, the output end of the 2nd latch L1 outputs the 2nd output data O1, the output end of the 3rd latch L2 outputs the 3rd output data O2, and the output end of the 4th latch L3 outputs the 4th output data O3.

The fifth output data O4 satisfies the following formula: Out4 _n = L0 _n ⊕ L4 _n , so the connection relationship between the first output module and each latch is: the first output module is connected to the output end of the first latch L0 and the output end of the fifth latch L4. The logic operation mode of the first output module is: the first output module generates the fifth output data O4 according to the first current state data L0 _n and the fifth current state data L4 _n .

The sixth output data O5 satisfies the following formula: Out5 _n = L0 _n ⊕ L1 _n ⊕ L5 _n , so the connection relationship between the second output module and each latch is: the second output module is connected to the output ends of the first latch L0, the second latch L1 and the sixth latch L5. The logic operation mode of the second output module is: the second output module generates the sixth output data O5 according to the first current state data L0 _n , the second current state data L1 _n and the sixth current state data L5 _n .

The seventh output data O6 satisfies the following formula: Out6 _n = L0 _n ⊕ L1 _n ⊕ L2 _n ⊕ L6 _n , so the connection relationship between the third output module and each latch is: the third output module is connected to the output ends of the first latch L0, the second latch L1, the third latch _L2 and the seventh latch L6. The logic operation mode of the third output module is: the third output module generates the seventh output data O6 according to the first current state data L0 n , the second current state data L1 _n , the third current state data L2 _n and the seventh current state data L6 _n .

The 8th output data O7 satisfies the following formula: _Out7n = _{L1n ⊕L2n ⊕L3n ⊕L7n} , so the connection relationship between the 4th output module and each latch is: the 4th output module is connected to the output ends of the 2nd latch L1, the 3rd latch L2, the 4th latch L3 and the 8th latch L7, and the logical operation method of the 4th output module is: the 4th output module generates the 8th output data O7 according to the 2nd current state data _L1n , the 3rd current state data _L2n , the 4th current state data _L3n and the 8th current state data _L7n .

The ninth output data O8 satisfies the following formula: Out8 _n = L2 _n ⊕ L3 _n ⊕ L4 _n , so the connection relationship between the fifth output module and each latch is: the fifth output module is connected to the output ends of the third latch L2, the fourth latch L3 and the fifth latch L4. The logic operation mode of the fifth output module is: the fifth output module generates the ninth output data O8 according to the third current state data L2 _n , the fourth current state data L3 _n and the fifth current state data L4 _n .

The 10th output data O9 satisfies the following formula: Out9 _n = L3 _n ⊕ L4 _n ⊕ L5 _n , so the connection relationship between the 6th output module and each latch is: the 6th output module is connected to the output ends of the 4th latch L3, the 5th latch L4 and the 6th latch L5. The logical operation mode of the 6th output module is: the 6th output module generates the 10th output data O9 according to the 4th current state data L3 _n , the 5th current state data L4 _n and the 6th current state data L5 _n .

The 11th output data O10 satisfies the following formula: Out10 _n = L0 _n ⊕ L4 _n ⊕ L5 _n ⊕ L6 _n , so the connection relationship between the 7th output module and each latch is: the 7th output module is connected to the output ends of the 1st latch L0, the 5th latch L4, the 6th latch L5 and the 7th latch L6. The logical operation mode of the 7th output module is: the 7th output module is based on The eleventh output data O10 is generated based on the first current state data _L0n , the fifth current state data _L4n , the sixth current state data _L5n , and the seventh current state data _L6n .

The 12th output data O11 satisfies the following formula: Out11 _n = L1 _n ⊕ L5 _n ⊕ L6 _n ⊕ L7 _n , so the connection relationship between the 8th output module and each latch is: the 8th output module is connected to the output ends of the 2nd latch L1, the 6th latch L5, the 7th latch L6 and the 8th latch L7. The logical operation mode of the 8th output module is: the 8th output module generates the 12th output data O11 according to the 2nd current state data L1 _n , the 6th current state data L5 _n , the 7th current state data L6 _n and the 8th current state data L7 _n .

The 13th output data O12 satisfies the following formula: Out12 _n = L2 _n ⊕ L6 _n ⊕ L7 _n , so the connection relationship between the 9th output module and each latch is: the 9th output module is connected to the output ends of the 3rd latch L2, the 7th latch L6 and the 8th latch L7. The logical operation mode of the 9th output module is: the 9th output module generates the 13th output data O12 according to the 3rd current state data L2 _n , the 7th current state data L6 _n and the 8th current state data L7 _n .

The 14th output data O13 satisfies the following formula: Out13 _n = L0 _n ⊕ L3 _n ⊕ L7 _n , so the connection relationship between the 10th output module and each latch is: the 10th output module is connected to the output ends of the 1st latch L0, the 4th latch L3 and the 8th latch L7. The logical operation mode of the 10th output module is: the 10th output module generates the 14th output data O13 according to the 1st current state data L0 _n , the 4th current state data L3 _n and the 8th current state data L7 _n .

The 15th output data O14 satisfies the following formula: Out14 _n = L1 _n ⊕ L4 _n , so the connection relationship between the 11th output module and each latch is: the 11th output module is connected to the output ends of the 2nd latch L1 and the 5th latch L4, and the logical operation method of the 11th output module is: the 11th output module generates the 15th output data O14 according to the 2nd current state data L1 _n and the 5th current state data L4 _n .

The 16th output data O15 satisfies the following formula: Out15 _n = L0 _n ⊕ L2 _n ⊕ L5 _n , so the connection relationship between the 12th output module and each latch is: the 12th output module is connected to the output ends of the 1st latch L0, the 3rd latch L2 and the 6th latch L5. The logical operation mode of the 12th output module is: the 12th output module generates the 16th output data O15 according to the 1st current state data L0 _n , the 3rd current state data L2 _n and the 6th current state data L5 _n .

In the above technical solution, since a part of the output data is the same as the next state data of the input end of the state latch circuit 100, the output circuit 300 and the state transfer circuit 200 share a logic gate circuit, and a part of the output data is the same as the current state circuit of the input end of the state latch circuit 100, there is no need to design a logic gate circuit for this part of the output data, and the output data is directly output by the state latch circuit 100. Therefore, only 12 output modules need to be designed, and each output module is used to perform a logical operation on the corresponding current state transfer data and output the corresponding output data. Through such a setting, the area occupied by the output circuit can be reduced.

The circuit structures of the first output module to the twelfth output module can be designed according to requirements, and the circuit structure shown in FIG. 5 is used as an example for explanation, but is not limited to the structure in FIG. 5 .

The first output module includes a first XOR gate, a first input terminal of the first XOR gate is connected to the output terminal of the first latch L0, a second input terminal of the first XOR gate is connected to the output terminal of the fifth latch _L4 , and the first XOR gate outputs _L0n⊕L4n , _and outputs _L0n⊕L4n as the fifth output data O4.

Since the second output module, the third output module and the first transfer module all perform logic processing on the first current state data _L0n and the second current state data _L1n , the second output module, the third output module and the first transfer module share the 20th XOR gate.

The second output module includes a second XOR gate, a first input end of the second XOR gate is connected to the output end of the sixth latch L5, a second input end of the second XOR gate is connected to the output end of the 20th XOR gate, the second input end of the second XOR gate receives data _{L0n⊕L1n , the} second XOR gate outputs _{L0n⊕L1n⊕L5n , and} outputs _{L0n⊕L1n⊕L5n} as the sixth output data _O5 .

The third output module includes a third XOR gate, a first input end of the third XOR gate is connected to the output end of the third latch L2, a second input end of the third XOR gate is connected to the output end of the seventh latch _L6 , the output end of the third XOR gate outputs _L2n⊕L6n , a first input end of the fourth XOR gate is connected to the output end of the 20th XOR gate, a first input end of the fourth _XOR gate receives data _L0n⊕L1n , and the output end of the third XOR gate is connected to the _second input end of the fourth _{XOR gate} . The fourth XOR gate outputs _{L0n⊕L1n⊕L2n⊕L6n , and outputs L0n⊕L1n⊕L2n⊕L6n} as the seventh output data O6.

The fourth output module includes a fifth XOR gate and a sixth XOR gate, wherein a first input terminal of the fifth XOR gate is connected to the output terminal of the second latch L1, a second input terminal of the fifth XOR gate is connected to the output terminal of the eighth latch L7, and the fifth _XOR gate outputs _L1n⊕L7n . A first input terminal of the sixth XOR gate is connected to the output terminal of the fifth XOR gate, a second input terminal of the sixth XOR gate is connected to the output terminal of the _twenty -sixth XOR gate, a second input terminal of the sixth _XOR gate _{receives L2n⊕L3n ,} the sixth _XOR gate outputs _{L1n⊕L2n⊕L3n⊕L7n} , _{and outputs L1n⊕L2n⊕L3n⊕L7n} as the eighth output data O7.

The 5th output module includes _a 7th XOR gate, a first input terminal of the 7th XOR gate is connected to the output terminal of the 26th XOR gate, a first input terminal of the 7th XOR gate receives _L2n⊕L3n , a second input terminal of the 7th _XOR gate is connected to the output terminal of the 5th latch L4, the 7th _{XOR gate} outputs _{L2n⊕L3n⊕L4n} , _and outputs _{L2n⊕L3n⊕L4n} as the 9th output data O8.

The 6th output module includes an 8th XOR gate and a 9th XOR gate, the first input end of the 8th XOR gate is connected to the output end of the 5th latch L4, the second input end of the 8th XOR gate _is connected to the output end of the 6th latch L5, the 8th XOR gate outputs _L4n⊕L5n , the first input end of the 9th XOR gate is connected to the output end of the 4th latch L3, the second input end of the 9th XOR gate is connected to the output end of the 8th _XOR gate, the 9th XOR gate outputs _{L3n⊕L4n⊕L5n , and outputs L3n⊕L4n⊕L5n} as the 10th output data O9.

The 7th output module includes a 10th XOR gate and an 11th XOR gate, a first input end of the 10th XOR gate is connected to the output end of the 1st latch L0, a second input end of the _10th XOR _gate is connected to the output end of the 7th latch L6, the 10th XOR gate outputs _L0n⊕L6n , a first input end of the 11th XOR gate is connected to the output end of the 8th XOR gate, a first input end of the 11th XOR gate receives _L4n⊕L5n , a second input _end of the 11th XOR gate is connected to the output end of the 10th _{XOR gate ,} the 11th _XOR gate outputs _{L0n⊕L4n⊕L5n⊕L6n} , and _{outputs L0n⊕L4n⊕L5n⊕L6n} as the 11th output data O10.

The 8th output module includes a 12th XOR gate, a 13th XOR gate and a 14th XOR gate, wherein the first input end of the 12th XOR gate is connected to the output end of the 2nd latch L1, the second input end of the 12th XOR gate is connected to the output end of the 6th latch L5, _and the 12th XOR gate outputs _L1n⊕L5n . The first input end of the 14th XOR gate is connected to the output end of the 7th latch L6, the second input end of the 14th XOR gate is connected to the output end of the 8th latch L7, _and the 14th XOR gate outputs _L6n⊕L7n . A first input terminal of the 13th XOR gate is connected to the output terminal of the 12th _XOR gate. A second input terminal of the 13th _XOR gate is connected to the output terminal of the 14th XOR gate _. The 13th _XOR gate outputs _{L1n⊕L5n⊕L6n⊕L7n and outputs L1n⊕L5n⊕L6n⊕L7n} as the 12th output data O11.

The 9th output module includes a 15th XOR gate, a first input terminal _of the 15th XOR gate is connected to the output terminal of the 14th XOR gate, a first input terminal of the 15th XOR gate receives _L6n⊕L7n , a second input terminal of the 15th XOR gate is connected to the output terminal of the 3rd latch L2, the 15th _XOR gate outputs _{L2n⊕L6n⊕L7n , and} outputs _{L2n⊕L6n⊕L7n} as the 13th output data _O12 .

The 10th output module includes a 16th XOR gate and a 17th XOR gate, a first input end of the 16th XOR gate is connected to the output end of the 1st latch L0, a second input end of the 16th XOR gate is connected to the output end of the 4th latch L3, and the 16th XOR gate outputs _L0n⊕L3n . A first input end of the 17th XOR gate _is connected to the output end of the 16th XOR gate, a second input end of the 17th XOR gate is connected to the output end of the 8th latch _{L7 ,} the 17th XOR gate outputs _{L0n⊕L3n⊕L7n} , _{and outputs L0n⊕L3n⊕L7n} as the 14th output data O13.

Since the 15th output data O14 satisfies the formula _L1n⊕L4n , and the output of the 33rd XOR gate _{is L1n⊕L4n} , the 33rd _XOR gate outputs the 15th output data O14. Since the 16th output data O15 satisfies _the formula _{L0n⊕L2n⊕L5n ,} and the output of the 35th XOR gate _{is L0n⊕L2n⊕L5n ,} the 35th XOR gate outputs the 16th output data O15.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (15)

A register comprising: A state latch circuit (100), wherein a clock end receives a clock pulse signal and latches multiple bits of current state data at an input end at an output end under the triggering of a clock pulse signal; An output circuit (300) connected to the output end of the state latch circuit (100) and used for performing a logic operation on the multi-bit current state data output by the state latch circuit (100) and then outputting a multi-bit output data; A state transfer circuit (200) has an input end connected to the output end of the state latch circuit (100) and an output end connected to the input end of the state latch circuit (100), and is used to perform a logic operation on multiple bits of current state data output by the state latch circuit (100) to output as next state data. The register according to claim 1, wherein the state latch circuit (100) comprises: a plurality of latches; an input end of each latch is connected to an output end of the state transfer circuit (200), a clock end of each latch receives a clock pulse signal, an output end of each latch is connected to an input end of an output circuit (300), and an output end of each latch is connected to an input end of the state transfer circuit (200). The register according to claim 1 or 2, wherein the state transfer circuit (200) comprises: a plurality of transfer modules; each of the transfer modules receives at least two current state data, and performs a logic operation on the at least two current state data to output one of the next state data. The register according to claim 1 or 2, wherein the output circuit (300) comprises: a plurality of output modules; each of the output modules receives at least two current state data, and performs a logic operation on the at least two current state data to output one output data. The register according to claim 2, wherein the number of latches and the number of transfer modules are both 8, the current state data output by the 8 latches are recorded as the first current state data, the second current state data, ... the eighth current state data, and the 8 transfer modules are recorded as the first transfer module, the second transfer module, ... the eighth transfer module; The first transfer module performs a logic operation on the first current state data, the second current state data, the fourth current state data and the seventh current state data to generate the first next state data; The second transfer module performs a logic operation on the first current state data, the second current state data, the third current state data, the fifth current state data and the eighth current state data to generate second next state data; The third transfer module generates the third next state data according to the second current state data, the third current state data, the fourth current state data and the sixth current state data; The fourth transfer module generates fourth next state data according to the third current state data, the fourth current state data, the fifth current state data and the seventh current state data; The fifth transfer module generates fifth next state data according to the first current state data, the second current state data, the fifth current state data, the sixth current state data, the seventh current state data and the eighth current state data; The sixth transfer module transfers the data according to the third current state data, the fourth current state data, and the sixth current state data. The state data and the 8th current state data generate the 6th next state data; The seventh transfer module generates seventh next state data according to the second current state data and the fifth current state data; The eighth transfer module generates eighth next state data according to the first current state data, the third current state data and the sixth current state data. The register according to claim 5, wherein the output terminal of the first latch (L0) outputs the first output data (O0), the output terminal of the second latch (L1) outputs the second output data (O1), the output terminal of the third latch (L2) outputs the third output data (O2), and the output terminal of the fourth latch (L3) outputs the fourth output data (O3). The register according to claim 6, wherein the number of output modules is 12, and the 12 output modules are recorded as a first output module, a second output module, ... a twelfth output module; The first output module generates fifth output data (O4) according to the first current state data and the fifth current state data; The second output module generates sixth output data (O5) according to the first current state data, the second current state data and the sixth current state data; The third output module generates seventh output data (O6) according to the first current state data, the second current state data, the third current state data and the seventh current state data; The fourth output module generates eighth output data (O7) according to the second current state data, the third current state data, the fourth current state data and the eighth current state data; The fifth output module generates ninth output data (O8) according to the third current state data, the fourth current state data and the fifth current state data; The sixth output module generates a tenth output data (O9) according to the fourth current state data, the fifth current state data and the sixth current state data; The seventh output module generates an eleventh output data (O10) according to the first current state data, the fifth current state data, the sixth current state data and the seventh current state data; The eighth output module generates a twelfth output data (O11) according to the second current state data, the sixth current state data, the seventh current state data and the eighth current state data; The ninth output module generates a thirteenth output data (O12) according to the third current state data, the seventh current state data and the eighth current state data; The tenth output module generates fourteenth output data (O13) according to the first current state data, the fourth current state data and the eighth current state data; The 11th output module generates 15th output data (O14) according to the 2nd current state data and the 5th current state data; The 12th output module generates 16th output data (O15) based on the first current state data, the third current state data and the sixth current state data. The register according to claim 5, wherein: The first transfer module comprises: An 18th XOR gate, having a first input terminal connected to the output terminal of the 4th latch (L3), a second input terminal connected to the output terminal of the 7th latch (L6), and an output terminal connected to the first input terminal of the 19th XOR gate; A 19th XOR gate, a second input terminal of which is connected to the output terminal of the 20th XOR gate, and an output terminal of which is connected to the input terminal of the first latch (L0); A 20th XOR gate, a first input terminal connected to the output terminal of the first latch (L0), and a second input terminal connected to the output terminal of the second latch (L1); The second transfer module includes: A 21st XOR gate, wherein the first input terminal is connected to the output terminal of the 3rd latch (L2), the second input terminal is connected to the output terminal of the 5th latch (L4), and the output terminal is connected to the first input terminal of the 22nd XOR gate; A 22nd XOR gate, a second input terminal of which is connected to the output terminal of the 8th latch (L7), and an output terminal of which is connected to the second input terminal of the 23rd XOR gate; a 23rd XOR gate, a first input terminal connected to the output terminal of the 20th XOR gate, and an output terminal connected to the input terminal of the second latch (L1); The third transfer module includes: A 24th XOR gate, having a first input terminal connected to the output terminal of the second latch (L1), a second input terminal connected to the output terminal of the sixth latch (L5), and an output terminal connected to the first input terminal of the 25th XOR gate; a 25th XOR gate, a second input terminal connected to the output terminal of the 26th XOR gate, and an output terminal connected to the input terminal of the third latch (L2); a 26th XOR gate, a first input terminal connected to the output terminal of the third latch (L2), and a second input terminal connected to the output terminal of the fourth latch (L3); The fourth transfer module comprises: a 27th XOR gate, having a first input terminal connected to the output terminal of the 26th XOR gate, a second input terminal connected to the output terminal of the 28th XOR gate, and an output terminal connected to the input terminal of the fourth latch (L3); A 28th XOR gate, a first input terminal connected to the output terminal of the 5th latch (L4), and a second input terminal connected to the output terminal of the 7th latch (L6); The fifth transfer module comprises: A 29th XOR gate, having a first input terminal connected to the output terminal of the 28th XOR gate, a second input terminal connected to the output terminal of the 20th XOR gate, and an output terminal connected to the first input terminal of the 30th XOR gate; a 30th XOR gate, wherein the second input terminal is connected to the output terminal of the 31st XOR gate, and the output terminal is connected to the input terminal of the 5th latch (L4); A 31st XOR gate, a first input terminal connected to the output terminal of the 6th latch (L5), and a second input terminal connected to the output terminal of the 8th latch (L7); The sixth transfer module comprises: The 32nd XOR gate has a first input terminal connected to the output terminal of the 31st XOR gate, a second input terminal connected to the output terminal of the 26th XOR gate, and an output terminal connected to the input terminal of the 6th latch (L5). The register according to claim 5, wherein: Transfer Module 7 includes: A 33rd XOR gate, wherein the first input terminal is connected to the output terminal of the second latch (L1), the second input terminal is connected to the output terminal of the fifth latch (L4), and the output terminal is connected to the input terminal of the seventh latch (L6); Transfer Module 8 includes: A 34th XOR gate, having a first input terminal connected to the output terminal of the first latch (L0), a second input terminal connected to the output terminal of the third latch (L2), and an output terminal connected to the first input terminal of a 35th XOR gate; The 35th XOR gate has a second input terminal connected to the output terminal of the 6th latch (L5), and an output terminal connected to the input terminal of the 8th latch (L7). The register according to claim 5, wherein: The first output module comprises: a first XOR gate, a first input end of which is connected to the output end of the first latch (L0), a second input end of which is connected to the output end of the fifth latch (L4), and outputs fifth output data (O4); The second output module comprises: a second XOR gate, a first input end of which is connected to the output end of the sixth latch (L5), a second input end of which is connected to the output end of the 20th XOR gate, and outputs the sixth output data (O5); The third output module includes: A third XOR gate, wherein the first input terminal is connected to the output terminal of the third latch (L2), the second input terminal is connected to the output terminal of the seventh latch (L6), and the output terminal is connected to the second input terminal of the fourth XOR gate; The 4th XOR gate has a first input terminal connected to the output terminal of the 20th XOR gate, and an output terminal outputs the 7th output data (O6). The register according to claim 5, wherein: The 4th output module includes: A fifth XOR gate, wherein the first input terminal is connected to the output terminal of the second latch (L1), the second input terminal is connected to the output terminal of the eighth latch (L7), and the output terminal is connected to the first input terminal of the sixth XOR gate; The 6th XOR gate has a second input terminal connected to the output terminal of the 26th XOR gate, and an output terminal outputs the 8th output data (O7); The 5th output module includes: The 7th XOR gate has a first input terminal connected to the output terminal of the 26th XOR gate, a second input terminal connected to the output terminal of the 5th latch (L4), and an output terminal outputting the 9th output data (O8). The register according to claim 5, wherein: The 6th output module includes: an eighth XOR gate, a first input end connected to the output end of the fifth latch (L4), a second input end connected to the output end of the sixth latch (L5), and an output end connected to the second input end of the ninth XOR gate; A ninth XOR gate, a first input terminal connected to the output terminal of the fourth latch (L3), and an output terminal outputting a tenth output data (O9); The 7th output module includes: a tenth XOR gate, wherein a first input terminal is connected to the output terminal of the first latch (L0), a second input terminal is connected to the output terminal of the seventh latch (L6), and an output terminal is connected to the second input terminal of the eleventh XOR gate; The 11th XOR gate has a first input terminal connected to the output terminal of the 8th XOR gate, and an output terminal outputs the 11th output data (O10). The register according to claim 5, wherein: The 8th output module includes: A 12th XOR gate, wherein the first input terminal is connected to the output terminal of the second latch (L1), the second input terminal is connected to the output terminal of the sixth latch (L5), and the output terminal is connected to the first input terminal of the 13th XOR gate; The 13th XOR gate has a second input terminal connected to the output terminal of the 14th XOR gate, and outputs the 12th output data (O11); A 14th XOR gate, a first input terminal connected to the output terminal of the 7th latch (L6), and a second input terminal connected to the output terminal of the 8th latch (L7); The 9th output module includes: The 15th XOR gate has a first input terminal connected to the output terminal of the 14th XOR gate, a second input terminal connected to the output terminal of the 3rd latch (L2), and outputs the 13th output data (O12). The register according to claim 5, wherein: The 10th output module includes: a 16th XOR gate, wherein the first input terminal is connected to the output terminal of the first latch (L0), the second input terminal is connected to the output terminal of the fourth latch (L3), and the output terminal is connected to the first input terminal of the 17th XOR gate; The 17th XOR gate has a second input terminal connected to the output terminal of the 8th latch (L7) and outputs the 14th output data. The register according to claim 9, wherein the 33rd XOR gate outputs the 15th output data (O14); and the 35th XOR gate outputs the 16th output data (O15).