WO2024162976A1 - Pumping controller for a plurality of charge pump units - Google Patents
Pumping controller for a plurality of charge pump units Download PDFInfo
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- WO2024162976A1 WO2024162976A1 PCT/US2023/019748 US2023019748W WO2024162976A1 WO 2024162976 A1 WO2024162976 A1 WO 2024162976A1 US 2023019748 W US2023019748 W US 2023019748W WO 2024162976 A1 WO2024162976 A1 WO 2024162976A1
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- Prior art keywords
- output
- pump units
- voltage
- latch
- pumping
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Definitions
- a pumping controller to provide pumping signals to a plurality of charge pump units is disclosed.
- Charge pumps are commonly used in semiconductor devices to generate voltages greater than the available supply voltage, the available supply voltage commonly denoted as VDD.
- VDD available supply voltage
- charge pumps are used in flash memory systems to generate voltages greater than VDD for program, erase, or read operations.
- the prior art includes designs with multiple charge pump units operating in parallel.
- One limitation of these prior art designs is that because each charge pump unit starts its the charge and discharge operation at the same time according to a common pumping signal, resulting in a power surge at the beginning of each charging cycle, which can harm circuits that are sensitive to surges in current or voltage.
- Another drawback of prior art designs is that if the charge pump reaches a desired voltage level, the charging operation sometimes will continue for a period of time before it is stopped, which results in the output going higher than the desired level.
- a pumping controller for a plurality of charge pumps is disclosed. BRIEF DESCRIPTION OF THE DRAWINGS
- Figure 1 depicts a voltage regulator comprising a pumping controller and a plurality of charge pump units.
- Figure 2 depicts timing diagrams for the voltage regulator of Figure 1.
- Figures 3 and 4 depict a method of operation of the voltage regulator of Figure 1.
- FIG. 1 depicts a system comprising voltage regulator 100.
- Voltage regulator 100 comprises charge pump units 102-1, 102-2, 102-3, and 102-4.
- Charge pump units 102-1, 102-2, 102-3, and 102-4 are connected in parallel and each receives an input voltage, VDD, and generates an output voltage, VD25, that is larger than the input voltage.
- VDD input voltage
- VD25 output voltage
- four charge pump units are connected in parallel to provide output voltage VD25 so as to be able to power an attached load without drooping.
- Voltage regulator 100 further comprises pumping controller 101.
- Pumping controller 101 comprises a voltage divider comprising a first resistor 103 and a second resistor 104, which produces at node 113 a divided voltage, Vs, which is proportional to output voltage VD25.
- Comparator 106 receives divided voltage Vs on a first, non-inverting input and a reference voltage, VREF, on a second, inverting input and compares them. When Vs > VREF, the output, VDET, of comparator 106 is high, and when Vs ⁇ VREF, the output of comparator 106 is low.
- Capacitor 105 transfers ripples from VD25 to Vs to speed up comparator 106.
- Latch 107 is a gated D latch with a reset signal, that performs according to the following truth table:
- the signal RESET is provided on the reset port, R, of latch 107, by other logic or a controller that is not shown.
- a latch enable port, LAT, of latch 107 receives the signal VDET from comparator 106.
- a data port, D, of latch 107 receives a signal from inverter 112, described in more detail below.
- the output, Q is 0 regardless of the values received by the data port, D, and the latch enable port, LAT.
- the output, Q When the RESET signal on the reset port, R, is not asserted and signal received by the latch enable port, LAT, is asserted (which will occur when Vs > VREF, signifying that VD25 has reached, or exceeded, the desired voltage), the output, Q, will hold its level regardless of the value received subsequently by the data port, D.
- the RESET signal on the R port is not asserted and the signal received by the latch enable port, LAT, is not asserted (which will occur when Vs ⁇ VREF, signifying that VD25 is less than the desired voltage and additional pumping is desirable)
- the output, Q will be whatever is received by the data port, D, at the time.
- the output, Q is the signal PMP CLK, which is provided as a pumping signal to charge pump unit 102-1 and to an input of delay circuit 108.
- Delay circuit 108 passes through its received signal, PMP CLK, but with an added delay to generate signal PMP CLK’ at the output of delay circuit 108.
- PMP CLK’ is provided as a pumping signal to charge pump unit 102-2 and to an input of delay circuit 109.
- Delay circuit 109 passes through its received signal, PMP CLK’, but with an added delay to generate signal PMP CLK” at the output of delay circuit 109.
- PMP CLK is provided as a pumping signal to charge pump unit 102-3 and an input of delay circuit 110.
- Delay circuit 110 passes through its received signal, PMP CLK”, but with an added delay to generate signal PMP CLK’” at the output of delay circuit 110.
- PMP CLK is provided as a pumping signal to charge pump unit 102-4 and an input of delay circuit 111.
- Delay circuit 111 passes through its received signal, PMP CLK’ ’ ’, but with an added delay to generate signal PMP CLK’ ” ’ at the output of delay circuit 111.
- charge pump unit 102-4 is the last pump unit in the plurality of pump units 102.
- Inverter 112 receives signal PMP CLK”” and generates the inverse of PMP CLK””, which is then provided as the data signal at the data port, D, of latch 107.
- pumping controller generates an oscillating signal (PMP CLK) when RESET is low and VDET is low and generates sequentially delayed versions of that oscillating signal (PMP CLK’ PMP CLK”, PMP CLK’”, and PMP CLK””).
- PMP CLK oscillating signal
- PMP CLK remains steady at its existing value and the oscillation of the oscillating signal (PMP CLK)
- PMP CLK sequentially delayed versions of that oscillating signal
- voltage regulator 100 comprises a plurality of charge pump units 102 for receiving an input voltage (VDD) and generating an output voltage (VD25) greater than the input voltage, and a pumping controller 101 for providing a pumping signal (PMP CLK) to a first pump unit of the plurality of pump units (e.g., pump unit 102-1) and providing respective sequentially delayed versions of the pumping signal (PMP CLK’, PMP CLK”, and PMP CLK’”) to the other pump units in the plurality of pump units (e.g., pump units 102-2, 102-3, and 102-4).
- PMP CLK pumping signal
- voltage regulator 100 in this example contains four pump units 102, it is to be understood that voltage regulator 100 alternatively could include fewer than four pump units 102 or more than four pump units 102.
- FIG. 2 depicts timing diagram 200 for voltage regulator 100 and shows signals PMP CLK, VD25, and VDET.
- the output voltage VD25 does not experience an additional charging cycle that causes the output voltage to go higher than desired (in contrast to the dotted line shown for VD25, which indicates how VD25 might experience an additional voltage boost in certain prior art systems), which is due to VDET being used as the LAT input to latch 107. That is, when VDET goes high, the output of latch 107, PMP CLK, will remain in its present state and will stop oscillating (in contrast to the dotted line shown for PMP CLK, which indicates how PMP CLK might behave in certain prior art systems).
- Figure 3 depicts a method 300 of operation of voltage regulator 100 of Figures 1 and 2.
- Method 300 comprises receiving, by a plurality of charge pump units connected in parallel, an input voltage (301); providing a pumping signal to a first pump unit in the plurality of charge pump units (302); providing sequentially delayed versions of the pumping signal to the other charge pump units in the plurality of charge pump units (303); and (304) generating, by the plurality of charge pump units, an output voltage greater than the input voltage.
- Figure 4 depicts a method 400.
- Method 400 is an example of a method to perform providing a pumping signal to a first pump unit in the plurality of charge pump units (302) and providing sequentially delayed versions of the pumping signal to the other charge pump units in the plurality of charge pump units (303) in method 300.
- Method 400 comprises comparing a voltage proportional to the output voltage to a reference voltage to generate a comparator output (401); receiving, by a gated D latch with a reset port, the comparator output as a latch enable signal (402); receiving, by the gated D latch, a data signal on a data port and a reset signal on a reset port (403); generating, by the gated D latch, the pumping signal as an output (404); generating, by respective delay circuits, the sequentially delayed versions of the pumping signal (405); receiving, by an inverter, an input comprising the delayed version of the pumping signal provided to a last of other pump units in the plurality of pump units (406); generating, by the inverter, an output (407); and providing the output of the inverter as the data signal to the latch (408).
- forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/ elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Read Only Memory (AREA)
Abstract
In one example, a system comprises a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units.
Description
PUMPING CONTROLLER FOR A PLURALITY OF CHARGE PUMP UNITS
PRIORITY CLAIM
[0001] This application claims priority from U.S. Provisional Patent Application No.
63/442,807, filed on February 2, 2023, and titled, “Charge Pump Comprising Latch-Based Self- Oscillating Voltage Regulator,” and U.S. Patent Application No. 18/135,395, filed on April 17, 2023, and titled, “Pumping Controller For A Plurality Of Charge Pump Units.”
FIELD OF THE INVENTION
[0002] A pumping controller to provide pumping signals to a plurality of charge pump units is disclosed.
BACKGROUND OF THE INVENTION
[0003] Charge pumps are commonly used in semiconductor devices to generate voltages greater than the available supply voltage, the available supply voltage commonly denoted as VDD. For example, charge pumps are used in flash memory systems to generate voltages greater than VDD for program, erase, or read operations.
[0004] The prior art includes designs with multiple charge pump units operating in parallel. One limitation of these prior art designs is that because each charge pump unit starts its the charge and discharge operation at the same time according to a common pumping signal, resulting in a power surge at the beginning of each charging cycle, which can harm circuits that are sensitive to surges in current or voltage. Another drawback of prior art designs is that if the charge pump reaches a desired voltage level, the charging operation sometimes will continue for a period of time before it is stopped, which results in the output going higher than the desired level.
[0005] What is needed is an improved charge pump design and control system.
SUMMARY OF THE INVENTION
[0006] A pumping controller for a plurality of charge pumps is disclosed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 depicts a voltage regulator comprising a pumping controller and a plurality of charge pump units.
[0008] Figure 2 depicts timing diagrams for the voltage regulator of Figure 1.
[0009] Figures 3 and 4 depict a method of operation of the voltage regulator of Figure 1.
DETAILED DESCRIPTION OF THE INVENTION
[0010] Figure 1 depicts a system comprising voltage regulator 100. Voltage regulator 100 comprises charge pump units 102-1, 102-2, 102-3, and 102-4. Charge pump units 102-1, 102-2, 102-3, and 102-4 are connected in parallel and each receives an input voltage, VDD, and generates an output voltage, VD25, that is larger than the input voltage. In this example, four charge pump units are connected in parallel to provide output voltage VD25 so as to be able to power an attached load without drooping.
[0011] Voltage regulator 100 further comprises pumping controller 101. Pumping controller 101 comprises a voltage divider comprising a first resistor 103 and a second resistor 104, which produces at node 113 a divided voltage, Vs, which is proportional to output voltage VD25. Comparator 106 receives divided voltage Vs on a first, non-inverting input and a reference voltage, VREF, on a second, inverting input and compares them. When Vs > VREF, the output, VDET, of comparator 106 is high, and when Vs < VREF, the output of comparator 106 is low. Capacitor 105 transfers ripples from VD25 to Vs to speed up comparator 106.
[0012] Latch 107 is a gated D latch with a reset signal, that performs according to the following truth table:
[0013] The signal RESET is provided on the reset port, R, of latch 107, by other logic or a controller that is not shown. A latch enable port, LAT, of latch 107, receives the signal VDET from comparator 106. A data port, D, of latch 107, receives a signal from inverter 112, described
in more detail below. As shown in the above truth table, when the RESET signal on the reset port, R, is asserted, the output, Q, is 0 regardless of the values received by the data port, D, and the latch enable port, LAT. When the RESET signal on the reset port, R, is not asserted and signal received by the latch enable port, LAT, is asserted (which will occur when Vs > VREF, signifying that VD25 has reached, or exceeded, the desired voltage), the output, Q, will hold its level regardless of the value received subsequently by the data port, D. When the RESET signal on the R port is not asserted and the signal received by the latch enable port, LAT, is not asserted (which will occur when Vs < VREF, signifying that VD25 is less than the desired voltage and additional pumping is desirable), the output, Q, will be whatever is received by the data port, D, at the time.
[0014] The output, Q, is the signal PMP CLK, which is provided as a pumping signal to charge pump unit 102-1 and to an input of delay circuit 108. Delay circuit 108 passes through its received signal, PMP CLK, but with an added delay to generate signal PMP CLK’ at the output of delay circuit 108.
[0015] PMP CLK’ is provided as a pumping signal to charge pump unit 102-2 and to an input of delay circuit 109. Delay circuit 109 passes through its received signal, PMP CLK’, but with an added delay to generate signal PMP CLK” at the output of delay circuit 109.
[0016] PMP CLK” is provided as a pumping signal to charge pump unit 102-3 and an input of delay circuit 110. Delay circuit 110 passes through its received signal, PMP CLK”, but with an added delay to generate signal PMP CLK’” at the output of delay circuit 110.
[0017] PMP CLK”’ is provided as a pumping signal to charge pump unit 102-4 and an input of delay circuit 111. Delay circuit 111 passes through its received signal, PMP CLK’ ’ ’, but with an added delay to generate signal PMP CLK’ ” ’ at the output of delay circuit 111. In this example, charge pump unit 102-4 is the last pump unit in the plurality of pump units 102.
[0018] Inverter 112 receives signal PMP CLK”” and generates the inverse of PMP CLK””, which is then provided as the data signal at the data port, D, of latch 107.
[0019] The end result is that pumping controller generates an oscillating signal (PMP CLK) when RESET is low and VDET is low and generates sequentially delayed versions of that oscillating signal (PMP CLK’ PMP CLK”, PMP CLK’”, and PMP CLK””). When VDET goes high, PMP CLK remains steady at its existing value and the oscillation of the oscillating
signal (PMP CLK), and the sequentially delayed versions of that oscillating signal (PMP CLK’ PMP CLK”, PMP CLK’”, and PMP CLK””), stops.
[0020] Thus, it can be understood that voltage regulator 100 comprises a plurality of charge pump units 102 for receiving an input voltage (VDD) and generating an output voltage (VD25) greater than the input voltage, and a pumping controller 101 for providing a pumping signal (PMP CLK) to a first pump unit of the plurality of pump units (e.g., pump unit 102-1) and providing respective sequentially delayed versions of the pumping signal (PMP CLK’, PMP CLK”, and PMP CLK’”) to the other pump units in the plurality of pump units (e.g., pump units 102-2, 102-3, and 102-4).
[0021] Although voltage regulator 100 in this example contains four pump units 102, it is to be understood that voltage regulator 100 alternatively could include fewer than four pump units 102 or more than four pump units 102.
[0022] Figure 2 depicts timing diagram 200 for voltage regulator 100 and shows signals PMP CLK, VD25, and VDET. Unlike in certain prior art systems, the output voltage VD25 does not experience an additional charging cycle that causes the output voltage to go higher than desired (in contrast to the dotted line shown for VD25, which indicates how VD25 might experience an additional voltage boost in certain prior art systems), which is due to VDET being used as the LAT input to latch 107. That is, when VDET goes high, the output of latch 107, PMP CLK, will remain in its present state and will stop oscillating (in contrast to the dotted line shown for PMP CLK, which indicates how PMP CLK might behave in certain prior art systems).
[0023] Figure 3 depicts a method 300 of operation of voltage regulator 100 of Figures 1 and 2. Method 300 comprises receiving, by a plurality of charge pump units connected in parallel, an input voltage (301); providing a pumping signal to a first pump unit in the plurality of charge pump units (302); providing sequentially delayed versions of the pumping signal to the other charge pump units in the plurality of charge pump units (303); and (304) generating, by the plurality of charge pump units, an output voltage greater than the input voltage.
[0024] Figure 4 depicts a method 400. Method 400 is an example of a method to perform providing a pumping signal to a first pump unit in the plurality of charge pump units (302) and providing sequentially delayed versions of the pumping signal to the other charge pump units in the plurality of charge pump units (303) in method 300. Method 400 comprises comparing a
voltage proportional to the output voltage to a reference voltage to generate a comparator output (401); receiving, by a gated D latch with a reset port, the comparator output as a latch enable signal (402); receiving, by the gated D latch, a data signal on a data port and a reset signal on a reset port (403); generating, by the gated D latch, the pumping signal as an output (404); generating, by respective delay circuits, the sequentially delayed versions of the pumping signal (405); receiving, by an inverter, an input comprising the delayed version of the pumping signal provided to a last of other pump units in the plurality of pump units (406); generating, by the inverter, an output (407); and providing the output of the inverter as the data signal to the latch (408).
[0025] It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween. For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/ elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
Claims
1. A system comprising: a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage; and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units.
2. The system of claim 1, wherein the pumping controller comprises: a voltage divider to receive the output voltage and generate a lower voltage at a node, the voltage divider comprising a first resistor coupled to a second resistor at the node, wherein the first resistor receives the output voltage; and a capacitor coupled between the output voltage and the node.
3. The system of claim 2, wherein the pumping controller comprises: a comparator comprising a first input coupled to the node, a second input coupled to a reference voltage, and an output.
4. The system of claim 3, wherein the pumping controller comprises: a latch to generate a latch output in response to the output from the comparator received on a latch enable port, a data signal received on a data port, and a reset signal received on a reset port.
5. The system of claim 4, wherein the latch output is provided as the pumping signal to the first pump unit of the plurality of pump units.
6. The system of claim 5, wherein the pumping controller comprises: delay circuits to generate the sequentially delayed versions of the pumping signal.
7. The system of claim 6, wherein the pumping controller comprises: an inverter to receive as an input the delayed version of the pumping signal provided to a last pump unit of the other pump units of the plurality of pump units and to generate an output; wherein the output of the inverter is provided to the latch as the data signal.
8. A method comprising: receiving, by a plurality of charge pump units connected in parallel, an input voltage;
providing a pumping signal to a first pump unit in the plurality of charge pump units; providing sequentially delayed versions of the pumping signal to the other charge pump units in the plurality of charge pump units; and generating, by the plurality of charge pump units, an output voltage greater than the input voltage.
9. The method of claim 8, comprising: comparing a voltage proportional to the output voltage to a reference voltage to generate a comparator output.
10. The method of claim 9, comprising: receiving, by a gated D latch with a reset port, the comparator output on a latch enable Port; receiving, by the latch, a data signal on a data port and a reset signal on a reset port; and generating, by the latch, the pumping signal as an output.
11. The method of claim 10, comprising: generating, by respective delay circuits, the sequentially delayed versions of the pumping signal.
12. The method of claim 11, comprising: receiving, by an inverter, an input comprising the delayed version of the pumping signal provided to a last of other pump units in the plurality of pump units; and generating, by the inverter, an output.
13. The method of claim 12, comprising: providing the output of the inverter as the data signal to the latch.
14. A system comprising: a voltage regulator to generate a pumping signal for a first pump unit in a plurality of pump units connected in parallel, and to generate sequentially delayed versions of the pumping signal for the other pump units in the plurality of pump units.
15. The system of claim 14, comprising: a voltage divider to receive an output voltage from the plurality of pump units and generate a voltage proportional to the output voltage at a node, the voltage divider comprising a
first resistor coupled to a second resistor at the node, and wherein the first resistor receives the output voltage; and a capacitor comprising a first plate receiving the output voltage and a second plate coupled to the node.
16. The system of claim 15, comprising: a comparator comprising a first input coupled to the node, a second input coupled to a reference voltage, and an output.
17. The system of claim 16, comprising: a latch to generate a latch output in response to the output from the comparator received on a latch enable port, a data signal received on a data port, and a reset signal received on a reset port.
18. The system of claim 17, wherein the latch output is provided as the pumping signal.
19. The system of claim 18, comprising: delay circuits to generate the sequentially delayed versions of the pumping signal.
20. The system of claim 19, comprising: an inverter to receive as an input a last version of the sequentially delayed versions of the pumping signal and to generate an output provided to the latch as the data signal.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP23725031.1A EP4659344A1 (en) | 2023-02-02 | 2023-04-25 | Pumping controller for a plurality of charge pump units |
| CN202380092748.6A CN120642197A (en) | 2023-02-02 | 2023-04-25 | Pump controller for multiple charge pump units |
| KR1020257024669A KR20250129039A (en) | 2023-02-02 | 2023-04-25 | Pumping controller for multiple charge pump units |
| TW113102362A TWI892421B (en) | 2023-02-02 | 2024-01-22 | Pumping controller for a plurality of charge pump units |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202363442807P | 2023-02-02 | 2023-02-02 | |
| US63/442,807 | 2023-02-02 | ||
| US18/135,395 | 2023-04-17 | ||
| US18/135,395 US12206325B2 (en) | 2023-02-02 | 2023-04-17 | Pumping controller for a plurality of charge pump units |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2024162976A1 true WO2024162976A1 (en) | 2024-08-08 |
Family
ID=86424866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2023/019748 Ceased WO2024162976A1 (en) | 2023-02-02 | 2023-04-25 | Pumping controller for a plurality of charge pump units |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP4659344A1 (en) |
| KR (1) | KR20250129039A (en) |
| CN (1) | CN120642197A (en) |
| TW (1) | TWI892421B (en) |
| WO (1) | WO2024162976A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090285038A1 (en) * | 2007-03-14 | 2009-11-19 | Apple Inc. | Interleaving charge pumps for programmable memories |
| US8462578B2 (en) * | 2011-05-23 | 2013-06-11 | Freescale Semiconductor, Inc. | Charge pump circuit with fast start-up |
| CN114421760A (en) * | 2022-01-14 | 2022-04-29 | 中国电子科技集团公司第二十四研究所 | Power generation circuit in time-interleaved charge pump |
| US20230006549A1 (en) * | 2021-06-30 | 2023-01-05 | Skyworks Solutions, Inc. | Controller for radio-frequency switches |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100752A (en) * | 1997-09-12 | 2000-08-08 | Information Storage Devices, Inc. | Method and apparatus for reducing power supply current surges in a charge pump using a delayed clock line |
| US8493134B2 (en) * | 2010-03-23 | 2013-07-23 | Qualcomm Incorporated | Method and apparatus to provide a clock signal to a charge pump |
| JP6359479B2 (en) * | 2015-04-01 | 2018-07-18 | 東芝メモリ株式会社 | Charge pump and voltage generation circuit |
| US10796773B1 (en) * | 2019-05-14 | 2020-10-06 | Micron Technolgy, Inc. | Memory devices including voltage generation systems |
-
2023
- 2023-04-25 EP EP23725031.1A patent/EP4659344A1/en active Pending
- 2023-04-25 CN CN202380092748.6A patent/CN120642197A/en active Pending
- 2023-04-25 WO PCT/US2023/019748 patent/WO2024162976A1/en not_active Ceased
- 2023-04-25 KR KR1020257024669A patent/KR20250129039A/en active Pending
-
2024
- 2024-01-22 TW TW113102362A patent/TWI892421B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090285038A1 (en) * | 2007-03-14 | 2009-11-19 | Apple Inc. | Interleaving charge pumps for programmable memories |
| US8462578B2 (en) * | 2011-05-23 | 2013-06-11 | Freescale Semiconductor, Inc. | Charge pump circuit with fast start-up |
| US20230006549A1 (en) * | 2021-06-30 | 2023-01-05 | Skyworks Solutions, Inc. | Controller for radio-frequency switches |
| CN114421760A (en) * | 2022-01-14 | 2022-04-29 | 中国电子科技集团公司第二十四研究所 | Power generation circuit in time-interleaved charge pump |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20250129039A (en) | 2025-08-28 |
| TW202437246A (en) | 2024-09-16 |
| TWI892421B (en) | 2025-08-01 |
| CN120642197A (en) | 2025-09-12 |
| EP4659344A1 (en) | 2025-12-10 |
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