WO2024151267A1

WO2024151267A1 - Reducing leakage power of volatile memory

Info

Publication number: WO2024151267A1
Application number: PCT/US2023/010750
Authority: WO
Inventors: Janardan Prasad
Original assignee: Google LLC
Current assignee: Google LLC
Priority date: 2023-01-13
Filing date: 2023-01-13
Publication date: 2024-07-18
Anticipated expiration: 2025-07-13
Also published as: TW202431256A; KR20250123922A

Abstract

Systems and methods for reducing the amount of power leaked by volatile memory in memory units of memory systems. In one aspect, a memory system includes volatile memory that includes multiple memory units. The memory system includes a descriptor queue configured to maintain a sequence of descriptors each corresponding to a received memory access request. The descriptor queue includes a memory access pointer to indicate a current descriptor to be processed and a power management pointer to indicate one or more subsequent descriptors for active state transition. The memory system includes a memory controller configured to process the descriptors based on the memory access pointer and to access the memory units of the descriptors to respond to received memory access requests. The memory system includes a power manager configured to selectively transition each memory unit between the active state and a low power state.

Description

REDUCING LEAKAGE POWER OF VOLATILE MEMORY

TECHNICAL FIELD

[0001] This specification relates to computer memory and reducing the amount of power leaked by volatile computer memory.

BACKGROUND

[0002] Volatile memory is a type of computer memory that retains its data when powered, but loses its data after losing power. Two example types of volatile memory are dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM requires periodic refreshes to maintain its data while SRAM requires constant power to maintain its data.

[0003] There are multiple sources of leakage power in the transistors of SRAMs. As there can be a large amount of SRAM on a system-on-chip (SoC) and on other types of integrated circuits, the constant power requirement of SRAM can result in large amounts of wasted power and associated negative thermal characteristics.

SUMMARY

[0004] This specification relates to reducing the amount of power leaked by volatile memory, and particularly by SRAM and other types of volatile memory in which the memory can be accessed in any order. Physical memory units can be placed into low power states to reduce the amount of leakage power when the memory units are not being accessed. However, it takes some time to transition the memory units from the low power states to active states in which the memory units can be accessed. If memory units are not transitioned to the active state until an access request for data stored in the memory units is received, the transition time adds latency and imposes backpressure on the memory system. The techniques described in this document reduce power leakage of volatile memory without such latency and backpressure, even in situations in which the memory accesses are random and do not follow any schedule or defined pattern.

[0005] In general, one innovative aspect of the subject matter described in this specification can be embodied in a memory system that includes volatile memory including multiple memory units; a descriptor queue configured to maintain a sequence of descriptors each corresponding to a received memory access request for performing a memory access operation on a respective memory unit of the multiple memory units, where the descriptor queue includes a memory access pointer that indicates a current descriptor to be processed and a power management pointer that indicates one or more subsequent descriptors for active state transition; a memory controller configured to process the descriptors in the descriptor queue based on the memory access pointer and to access the memory units of the descriptors to respond to received memory access requests corresponding to the descriptors in the descriptor queue; and a power manager configured to selectively transition each memory unit between the active state and a low power state, including monitoring the power management pointer to identify the one or more subsequent descriptors and transitioning the respective memory unit for each of the one or more subsequent descriptors from the low power state to the active state prior to the one or more subsequent descriptors being processed by the memory controller. Other embodiments of this aspect include corresponding apparatus, methods, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0006] These and other implementations can each optionally include one or more of the following features. In some aspects, the descriptor queue includes a first in, first out queue and each descriptor is removed from the descriptor queue after the memory controller performs a memory access operation indicated by the descriptor. The volatile memory can include static random access memory (SRAM). The descriptor queue can include a queue manager configured to update the descriptor queue to include a descriptor of each newly received memory access request, update the memory access pointer after each descriptor is processed by the memory controller, and update the power management pointer after each descriptor is processed by the memory controller.

[0007] In some implementations, the one or more subsequent descriptors include a number of descriptors selected based on an amount of time taken for a memory unit to transition from the low power state to the active state. The number of descriptors can be based on a number of memory access operations the memory controller is capable of completing within the amount of time. The number of descriptors can be based on a number of processing unit clock cycles of a processor communicably coupled to the volatile memory that occur during the amount of time.

[0008] In some implementations, the descriptor queue includes one or more additional power management pointers that indicate an additional set of subsequent descriptors for active state transition. The additional set of subsequent descriptors includes an additional number of descriptors selected based on an amount of time taken for a memory unit corresponding to each additional descriptor to transition from the low power state to the active state. The additional number of descriptors can be based on a number of memory access operations the memory controller is capable of completing within the duration of time.

[0009] In some aspects, the power manager is configured to determine whether the respective memory unit of the current descriptor is a subsequent descriptor for active state transition; whenever the respective memory unit of the current descriptor is a subsequent descriptor for active state transition, leave the respective memory unit of the current descriptor in the active state after processing the current descriptor; and whenever the respective memory unit of the current descriptor is not a subsequent descriptor for active state transition, transition the respective memory unit of the current descriptor from the active state to the low power state. [0010] In general, another innovative aspect of the subject matter described in this specification can be embodied in methods performed by a memory controller configured to manage volatile memory that includes multiple memory units. The method includes accessing a descriptor queue that includes a sequence of descriptors each corresponding to a received memory access request, where each descriptor corresponds to a memory access operation for a respective memory unit of the multiple memory units indicated by the descriptor, a memory access pointer that indicates a current descriptor for processing, and a power management pointer that indicates one or more subsequent descriptors for active state transition. The method includes identifying, based on the power management pointer, the one or more subsequent descriptors; transitioning each subsequent descriptor that is in a low power state from the low power state to the active state; and accessing the one or more memory units for each subsequent descriptor when the memory access pointer reaches the subsequent descriptor in the descriptor queue. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0011] These and other implementations can each optionally include one or more of the following features. In some aspects, accessing the one or more memory units for each subsequent descriptor includes performing the memory access operation of the subsequent descriptor.

[0012] In some implementations, the method includes updating the memory access pointer and the power management pointer to indicate different descriptors each time the memory access operation for a descriptor is performed and the descriptor is removed from the descriptor queue. [0013] In some aspects, the method includes performing the memory access operation of the current descriptor; removing the current descriptor from the descriptor queue in response to performing the memory access operation of the current descriptor; updating the memory access pointer to indicate a next descriptor in the descriptor queue following the current descriptor; and updating the one or more subsequent descriptors for active state transition by updating the power management pointed in response to performing the memory access operation of the current descriptor.

[0014] In some aspects, the method includes determining whether the respective memory unit of the current descriptor is a subsequent descriptor for active state transition; whenever the respective memory unit of the current descriptor is a subsequent descriptor for active state transition, leaving the respective memory unit of the current descriptor in the active state after processing the current descriptor; and whenever the respective memory unit of the current descriptor is not a subsequent descriptor for active state transition, transitioning the respective memory unit of the current descriptor from the active state to the low power state.

[0015] In some implementations, the method includes identifying, as the one or more subsequent descriptors, each descriptor between the memory access pointer and the power management pointer.

[0016] In some aspects, the method includes controlling the power management pointer to identify a particular number of subsequent descriptors based on a duration of time taken for a memory unit to transition from the low power state to the active state.

[0017] In some implementations, the descriptor queue includes a first in, first out queue and each descriptor is removed from the descriptor queue after the memory controller performs the memory access operation indicated by the descriptor

[0018] In some aspects, the volatile memory includes static random access memory (SRAM). The descriptor queue can include a queue manager configured to update the descriptor queue to include a descriptor of each newly received memory access request; update the memory access pointer after each descriptor is processed by the memory controller; and update the power management pointer after each descriptor is processed by the memory controller.

[0019] In some aspects, the one or more subsequent descriptors include a number of descriptors selected based on a duration of time taken for a memory unit to transition from the low power state to the active state. The number of descriptors can be based on a number of memory access operations the memory controller is capable of completing within the duration of time. The number of descriptors can be based on a number of processing unit clock cycles of a processor communicably coupled to the volatile memory that occur during the duration of time.

[0020] In some aspects, the method includes determining that a particular descriptor corresponding to a particular memory unit is not in the descriptor queue and, in response to determining that the particular descriptor corresponding to a particular memory unit is not in the descriptor queue, transitioning the particular memory unit to the low power state.

[0021] The subject matter described in this specification can be implemented in particular embodiments so as to realize one or more of the following advantages. Managing the low power state of volatile memory such that memory units are transitioned to active states prior to being accessed reduces the leakage power of the memory units, which also reduces the amount of wasted heat produced by the leakage power. A power management pointer and a descriptor queue, which can implemented as a first in, first out (FIFO) unit, can be used to identify memory units that are about to be accessed (e.g., within a specified amount of time) and to transition the memory units immediately before (e.g., within one, two, or another appropriate number of clock cycles) the memory unit is accessed. This reduces the amount of time that the memory unit is in the active state, further reducing leakage power and associated heat. This also ensures that the memory units are in the active state in time for the memory controller to access the memory units, which reduces latency and backpressure. Using the power management pointer and descriptor queue enables these just in time transitions irrespective of the order in which memory requests are received and therefore enables low power techniques to be used in all situations rather than only situations in which memory access patterns are known or conform to a predefined pattern.

[0022] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG. 1 shows an example memory system in which a memory controller controls access to volatile memory and transitions memory units of the volatile memory between active and low power states.

[0024] FIG. 2 shows example states of a descriptor queue. [0025] FIG. 3 shows a flow diagram of an example process for transitioning memory units between active and low power states.

[0026] FIG. 4 shows a flow diagram of an example process for accessing memory units and transitioning memory units between active and low power states.

[0027] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0028] FIG. 1 shows an example memory system 100 in which a memory controller 110 controls access to volatile memory 150 and transitions memory units 152 (e.g., 152-1 to 152- N) of the volatile memory 150 between active and low power states. The memory system 100 can be part of (e.g., integrated on) or coupled to a system-on-a-chip (SOC) that may be installed on or integrated into any appropriate computing device. Because the techniques described in this specification are particularly suited to reduce power leakage of volatile memory 150 with reduced latency and backpressure, the memory system 100 can be particularly beneficial when installed on a mobile host device or other device that relies on battery power or other limited power sources. For example, reducing power leakage on portable devices, e.g., a smart phone, a smart watch or another wearable computing device, a tablet computer, or a laptop computer, can improve battery performance and operability of the portable device during prolonged time periods without access to external power.

[0029] The memory system 100 includes the memory controller 110, a power manager 120 that is configured to transition the memory units 152 between active and low power states to fulfill memory access requests, and the volatile memory 150. Examples of volatile memory 150 include cache memory and random access memory, e.g., dynamic random access memory (DRAM) and static random access memory (SRAM). The power management and memory access techniques described in this document can be used with volatile memory that requires constant power to retain data, such as SRAM.

[0030] Each memory unit 152 is a physical instance of memory, e.g., a smaller partition of a larger memory system or device. The physical instance of memory for a memory unit can be transitioned to different power states, e.g., active state to low power state, low power state to active state. The power states of physical instances of memory can be transitioned independently of the power states of physical instances of other memory units. For example, a memory unit 152 can be a group of memory cells, such as one or more rows of memory cells, one or more columns of memory cells, or one or more memory banks. The memory units 152 can be grouped or clustered based on their characteristics or other factors, including power states, operating parameters, computational applications, latency in transitioning between low power and active states, and read/write speeds. In some implementations, each memory unit 152 is a group of cells that have the same power state (e.g., active state or low power state) and transition between power states together. For example, a bank or row of memory cells may receive power on a same portion of a power distribution circuit and therefore have the same power state at all times. The memory system 100 can include any number “N” of memory units 152.

[0031] Each memory unit 152 can include a group of memory circuits that are powered together and are in the same power state together. A memory device can be partitioned into any number of banks, rows, and rows of a bank in any number of ways. As an example, a memory device with 8 megabytes (MB) capacity can be partitioned into 8 individual banks of equal size, e.g., 1 MB per bank. In this example, each bank can be a memory unit 152. Each memory bank may be a vertical partition of the memory device that can include a single physical instance or multiple physical instances of memory. For example, a 1 MB memory bank may contain a physical instance of 1 MB. As another example, a 1 MB memory bank may be partitioned into 8 physical instances of memory such that each physical instance of memory includes 128 kB of memory. In this example, each 128kB instance of memory can be a memory unit 152.

[0032] An active state for a memory unit 152 is a state in which the memory cells of the memory unit 152 can be accessed by the memory controller 110. The power manager 120 can transition memory units to a low power state to reduce the power consumption and leakage power of the memory unit 152 when the memory unit 152 is not being accessed. Example low power states include light sleep, deep sleep, and power gated. The power manager 120 can transition a memory unit 152 between the active state and a low power state by sending power state instructions to the memory unit 152. As an example, the power manager 120 can provide one or more power state instructions (e.g., a series of instructions) to one or more memory units 152 to wake-up, e.g., transition from a low power state to an active state, or power down, e.g., transition from an active state to a low power state. The power state instructions can include an input signal to the memory unit that enables the transition. The particular instructions can vary based on the type of volatile memory 150 used and the memory management techniques of the memory system 100.

[0033] The power manager 120 includes and/or maintains a status table 122 to store data indicating the current power state of each memory unit 152. The status table 122 includes a cell for each memory unit 152, with a value or label stored in the cell indicating a current power state of the memory unit 152. For example, if the possible states are “active” and “low power,” the cell for a memory unit 152 can include a label that indicates “active” or “low power” or a value representative of “active” or “low power,” such as a value of “1” for active and a value of “0” for low power. Other values can also be used.

[0034] The power manager 120 can maintain the status table 122 based on power state instructions that the power manager 120 sends to the memory units 152 and/or based on feedback received from the volatile memory 150. For example, if the power manager 120 sends, to memory unit 152-3, a power state instruction to transition from the active state to a low power state, the power manager 120 can update the cell for memory unit 152-3 from active to low power or from 0 to 1 using the example labels and values described above. In another example, the power manager 120 can wait for feedback that indicates the memory unit 152-3 successfully transitioned from the active state to the low power state.

[0035] The memory controller 110 includes a memory access engine 112, a descriptor queue 114, and a queue manager 116. The memory controller 110 can be implemented in hardware and/or software and the descriptor queue 114 and the queue manager 116 may be additional memory or hardware and/or software of the memory system 100.

[0036] The memory controller 110 is configured to receive memory access requests from agents 105, e.g., agents 105-1 to 105-N. An agent 105 can be a hardware device or software component (e.g., application or module) that provides data for storage in volatile memory 150 and/or requests data that is stored in volatile memory 150. Example agents include an operating system (OS) of a computing device, an application running on a computing device, an integrated circuit (IC) communicably coupled to the memory system 100, processor cores (e.g., a central processing unit (CPU), digital signal processor, graphics processing unit (GPU), and so on), and external interfaces.

[0037] A memory access request can be to request data from volatile memory 150 or to store data in volatile memory 150. Each memory access request can include a descriptor and, if the request is to store data, the data to be stored. The descriptor of a memory access request can include data identifying a memory location, e.g., memory address, and a memory operation, e.g., read/write. The memory location identifies the location in memory at which the memory operation is to be performed. In some implementations, the memory location may not directly identify the memory unit 152. For example, each memory unit 152 is a physical instance of memory and can correspond to a logical memory address separate that is assigned to the physical instance. In such examples, the memory controller 110 can be configured to translate the memory location to the corresponding memory unit 152 and/or to a particular location (e.g., group of cells) in the memory unit 152.

[0038] In one example, an agent 105 can send, to the memory controller 110, a memory access request corresponding to a write request to store data in volatile memory 150. The memory access request includes the data to be stored and a descriptor that includes data identifying the memory location where the data is to be stored and the write operation. The queue manager 116 can store the descriptor in the descriptor queue 114.

[0039] In another example, an agent 105 can send, to the memory controller 110, a memory access request corresponding to a read request to retrieve data that is stored in volatile memory 150. In this example, the memory access request includes a descriptor that includes data identifying the memory location from which the data is to be retrieved and the read operation. Similar to the example above, the queue manager 116 can store the descriptor in the descriptor queue 114.

[0040] The descriptor queue 114 is configured to store descriptors received from the agents 105. In some implementations, a descriptor of the descriptor queue may be a number of bits, e.g., 24 bits, and all but one bit describes the memory location, e.g., 23 -bit value, of the descriptor while the remaining bit describes the operation, e.g., read or write. Other numbers of bits for each part of the descriptor can also be used. The descriptor queue 114 can be implemented as a FIFO queue in which descriptors are processed in the order in which they are received by the memory controller 110. In other words, the descriptor queue 114 can be a FIFO unit. The descriptor queue 114 includes multiple queue positions including a first position which can store a current descriptor that is being processed and a last position which stores the last descriptor currently in the descriptor queue 114 to be processed. Each newly received descriptor can be added to the end of the queue and this queue position would be the new last queue position. [0041] The queue manager 116 can be configured to manage the descriptors stored in the descriptor queue 114 and pointers that point to descriptors in the descriptor queue 114. For example, the queue manager 116 can be configured to add a descriptor to the descriptor queue 114 (e.g., to the end or last position in the descriptor queue 114) upon receipt of a memory access request that includes the descriptor. In addition, the queue manager 116 can be configured to remove, from the descriptor queue 114, descriptors as they are processed by the memory access engine 112, as described below.

[0042] The descriptor queue 114 includes one or more memory access pointers that indicate the next descriptor in the sequence of descriptors to be processed. As described below with reference to FIG. 2, the descriptor queue 114 can include a read access pointer for read operations and a write access pointer for write operations. For example, read and write operations can be processed in groups. The read access pointer can indicate the next read operation to be processed and the write access pointer can indicate the next write operation to be processed. In some implementations, the descriptor queue includes a single memory access pointer for the next descriptor independent of the type of operation.

[0043] The descriptor queue 114 also includes a power management pointer that indicates one or more subsequent descriptors for which memory units are to be transitioned to the active state if they are not already in the active state. When a descriptor is close to being processed, e.g., within a specified number of queue positions from the first position in the descriptor queue 114, the power manager 120 can transition the memory unit 152 corresponding to the descriptor (e.g., the memory unit 152 indicated by the memory location of the descriptor) to the active state if the memory unit 152 is currently in a low power state. The power manager 120 and the power management pointer are described in more detail below.

[0044] The memory access engine 112 is configured to use the memory access pointer to process descriptors and perform the memory operations of the descriptors. Each time the memory access engine 112 finishes processing a descriptor, the memory access engine 112 can notify the queue manager 116. In response, the queue manager 116 can remove the processed descriptor from the descriptor queue 114 and update the descriptor queue 114 such that the descriptor that was in the second position is now in the first position and each other descriptor moves up one position in the descriptor queue 114. By removing the processed descriptor from the descriptor queue 114 and updating with a next descriptor to be processed, the queue manager 116 maintains a FIFO scheme for processing descriptors in the descriptor queue 114.

[0045] The memory access engine 112 can process a descriptor by identifying the operation of the descriptor and the memory location of the descriptor. The memory access engine 112 can then perform the operation at the memory unit 152 corresponding to the memory location. For example, if the operation is a read operation, the memory access engine 112 can open the memory unit 152, read the appropriate data from that memory unit 152, and send the data to the agent 105 that sent the memory access request. If the operation is a write operation, the memory access engine 112 can open the memory unit 152 and write the data to that memory unit 152. In some implementations, the memory access engine 112 may be referred to as a direct memory access engine for a coupled volatile memory device.

[0046] The power manager 120 is configured to monitor the power management pointer of the descriptor queue 114 and selectively transition memory units 152 between active and low power states. The power manager 120 can use the power management pointer to identify subsequent descriptors (e.g., those after the current descriptor being processed) for which memory units 150 should be in the active state. For each of these subsequent descriptors, the power manager 120 can identify the corresponding memory units 152 and transition them to the active state if they are not already in the active state. In this way, when the descriptor reaches the first position in the descriptor queue 114, the corresponding memory unit 152 is in the active state and the memory access engine 112 can immediately access the memory unit 152. This reduces latency in performing the memory operations of the memory access requests and therefore reduces backpressure on the memory system 110.

[0047] The power manager 120 can also be configured to transition memory units 152 back to the low power state after being accessed for a processed descriptor. For example, the power manager 120 can be configured to monitor the memory access pointer to identify a descriptor being processed. When the memory access pointer transitions to a different descriptor, the power manager 120 can determine that the previous descriptor has been processed. In another example, the memory access engine 112 can be configured to notify the power manager 120 when a descriptor has been fully processed. Such a notification can include the descriptor or at least the memory location of the descriptor.

[0048] Before transitioning a memory unit 152 back to a low power state, the power manager 120 can evaluate the descriptor queue to determine whether the memory unit 152 will be accessed again soon, e.g., within the time period that it would take to transition the memory unit 152 back to the active state if the memory unit 152 is transitioned to the low power state. For example, it may take three clock cycles to transition a memory unit from the low power state to the active state and the memory access engine 112 may be capable of processing one descriptor per clock cycle. In this example, if there is a descriptor for the same memory unit 152 within the first three positions of the descriptor queue 114, the power manager 120 can maintain the memory unit 152 in the active state so that the descriptor can be processed without delay when it reaches the first position in the descriptor queue 114. In some implementations, the power manager 120 performs this evaluation by determining whether any descriptors between the memory access pointer and the power management pointer are for that memory unit 152.

[0049] A power transition of the memory unit 152 to the active state can include activating, e.g., performing a wake-up routine, the memory unit 152 to an active state that can include an increase in power consumption. A power transition to a low power state can include powering down the memory unit to a low-power state that can include a decrease in power consumption. In some implementations, the low-power state can be distinguished between a light sleep state to reduce power consumption, and a deep sleep state to further reduce power consumption compared to the light sleep state. As an example, the deep-sleep state of a memory unit 152 may provide significant savings in power consumption compared to the light sleep state, but may also have increased latency, e.g., additional processing unit clock cycles, additional processing time, additional memory access operations, required to transition to an active state.

[0050] FIG. 2 shows example states of a descriptor queue 214. The descriptor queue 214 is an example of the descriptor queue 114 described with reference to FIG. 1, with stages A - C illustrating how memory access pointers and power management pointers can be used for processing descriptors and transitioning memory units between the active state and low power states.

[0051] Referring to stage A, the descriptor queue 214 includes descriptors 1 - 13 with descriptor 1 being in the first position 221 and descriptor 13 being in the last position 222. As described above, each descriptor can include a memory location (e.g., memory address) corresponding to a memory unit in the volatile memory and an operation, e.g., read or write. A read access pointer is a memory access pointer that is configured to keep track of descriptors for memory access requests that include instructions to read data from the memory units 150. A write access pointer is a memory access pointer that is configured to keep track of descriptors for memory access requests that include instructions to write data to the memory units 150. A power management pointer is configured to indicate a number of subsequent descriptors that follow the current descriptor being processed, e.g., by the access read pointer in the illustrated example.

[0052] In this example, the descriptor queue 214 includes both a read access pointer and a write access pointer. The memory access unit 112 can be configured to process the descriptor indicated by the access pointer that is higher in the descriptor queue 214.

[0053] The number of subsequent descriptors that are read ahead of the read access pointer can be based on the amount of time that it takes to transition a memory unit 152 from a low power state to an active state. In some implementations, the amount of time used is a minimum amount of time for the transition to occur. The amount of time can be based on and/or represented as a number of clock cycles of a hardware processor that performs the memory access operations.

[0054] In some implementations, the number of subsequent descriptors to transition to the active state and therefore indicated by the power management pointer can be determined based on a duration of time for a memory unit 152 to transition from a low power state to the active state and/or a number of memory access operations the memory unit is able to perform per clock cycle. For example, the memory access engine 112 may be capable of performing one memory operation per clock cycle. In addition, it may take a memory unit 152 at least five clock cycles to transition from the low power state to the active state. In this example, the power management pointer can indicate the descriptor that is five positions lower in the descriptor queue 214 than the current descriptor being processed. For example, as shown in stage A of FIG. 2, the power management pointer points to descriptor 6 which is five positions lower than descriptor 1.

[0055] The power manager 120 can monitor the power management pointer and identify, as the subsequent descriptors, all of the descriptors between the access pointer highest in the descriptor queue (e.g., the read access pointer in stage A) and the power management pointer. The power manager 120 can transition the memory unit 152 corresponding to each subsequent descriptor to the active state if the memory unit 152 is not already in the active state. [0056] Any number of power management pointers can be used to determine corresponding groups of subsequent descriptors for transition to the active state. For example, some memory units 152 may have different amounts of time required to transition from a lower power state to an active state. In another example, there may be different amounts of transition times depending on the low power state. For example, it may take longer to transition from a deep sleep state to the active state that it takes to transition from a light sleep state to the active state. The descriptor queue 214 can include a power management pointer for different transition times, e.g., for different groups of memory units that each have a different transition time and/or for each low power state. Each power management pointer can indicate a sequence of subsequent descriptors for which the memory units 152 corresponding to the descriptors are to be transitioned to the active state.

[0057] As an example, a first power management pointer and a first group of subsequent descriptors may correspond to a first set of memory units 152 in volatile memory 150 that belong to one cluster. The first set of memory units 152 may involve a first number of clock cycles to transition from a low power state to the active state. A second power management pointer and a second group of subsequent descriptors may correspond to a second set of memory units 152 in volatile memory 150 that belong to another cluster. The second set of memory units 152 may involve a second number of clock cycles to transition from a low power state to the active state. The first and the second power management pointers can have different numbers of subsequent descriptors to read ahead of the memory access pointer due to the difference in transition times.

[0058] The queue manager 116 can manage each power management pointer based on its respective number of descriptors and the descriptors that correspond to the memory units 152 for that power management pointer. For example, if the number of descriptors for the first set of memory units and the first power management pointer is three, the queue manager 116 can operate the first power management pointer such that the first power management pointer indicates the third descriptor (not including the current descriptor being processed) in the descriptor queue 214 that corresponds to a memory unit 152 in the first set of memory units.

[0059] In some implementations, all of the pointers, e.g., read access pointer, write access pointer, and power management pointer, may be initialized to start at the beginning of the descriptor queue 214, e.g., prior to an agent 105 submitting a memory access request. Upon receipt of a memory access request, the memory access engine 112 can group the memory access requests by operation, e.g., read, write, so that a respective pointer for the operation may track the group of operations. For example, a read access pointer may begin tracking read memory accesses and the write access pointer may begin tracking write memory accesses.

[0060] Referring again to stage A, the descriptor queue 214 shows read access pointer pointing to the first descriptor, e.g., descriptor 1, while a power management pointer points to descriptor 6. A write access pointer concurrently points to descriptor 12. In this example, descriptors 1-11 correspond to read operations and descriptors 12 and 13 correspond to write operations.

[0061] The memory access engine 112 can monitor the read access pointer and the write access pointer to obtain the next descriptor for performing a memory operation. For example, the memory access engine 112 can obtain descriptor 1 from the descriptor queue 214 and perform the read operation corresponding to descriptor 1 based on the read access pointer indicating that descriptor 1 is the next read descriptor and the read access pointer being higher in the descriptor queue 214 than the write access pointer.

[0062] The power manager 120 can monitor the power management pointer to identify descriptors for which to transition corresponding memory units to the active state. The power manager 120 can identify, as subsequent descriptors, each descriptor between the highest memory access pointer and the power management pointer, inclusive. The power manager 120 can transition the memory unit 152 corresponding to each of these subsequent descriptors to the active state. In this example, the power manager 120 can transition the memory units 152 corresponding to descriptors 2-6 to the active state based on the power management pointer pointing to descriptor 6. The memory units 152 corresponding to the subsequent descriptors, e.g., descriptors 2 - 6 in stage A, remain in the active state at least until the memory access engine 112 completes the processing of descriptor, e.g., completes the memory operation corresponding to the descriptor.

[0063] As an example, the subsequent number of descriptors being scanned by the power management pointer can be particularly advantageous when the number of memory units 152 in volatile memory 150 exceeds the number of descriptors between the memory access pointer and the power management pointer. For example, a volatile memory device, e.g., SRAM, may have 32 memory units, e.g., SRAM banks, with 5 subsequent descriptors in the descriptor queue 114 between the memory access pointer and the power management pointer. From the 32 memory units in volatile memory, up to 27 memory units will be in a power saving state, e.g., assuming all 5 descriptors being scanned correspond to 5 memory units 152.

[0064] Referring to stage B, the read access pointer has been incremented, e.g., by the queue manager 116, after descriptors 1 - 3 are processed by the memory access engine 112. The queue manager 116 also increments the power management pointer for each processed descriptor. As illustrated, the power management pointer now points to descriptor 9, e.g., five descriptors after the currently accessed descriptor 4, maintaining the same number of subsequent descriptors in the descriptor queue 214. In stage B, the power manager 120 will transition descriptors 7-9 to the active state as descriptors 4-6 were transitioned to the active state in stage A.

[0065] Referring to stage C, the read access pointer has been incremented after processing descriptors 4 - 7. Similarly, the power management pointer has been incremented to point to descriptor 12. In stage C, the power manager 120 will transition descriptors 10-12 to the active state as descriptors 7-9 were transitioned to the active state in stage A.

[0066] When the power management pointer points to a descriptor, e.g., descriptor 12 of the descriptor queue 214, the power manager 120 determines the memory addresses of a physical instance in volatile memory, e.g., determining the memory unit(s) corresponding to the descriptor, that should be transitioned to the active state. As an example, if a scanned descriptor with a descriptor value being scanned points to a memory unit 152 in volatile memory 150 that is currently in an active state, the power manager 120 will ensure the memory unit 152 remains active until the scanned descriptor is processed by the memory access engine 112.

[0067] Address reads ahead of the memory access pointers are used to determine which memory units should be transitioned to active states. Other memory units with addresses not determined in the subsequent number of descriptors scanned by the power management pointer or the current location of the memory access pointer can remain in a low power state.

[0068] FIG. 3 shows a flow diagram of an example process 300 for transitioning memory units between active and low power states. The process 300 can be performed by a memory system, e.g., the memory system 100 of FIG. 1. For ease of description, the process 300 is described as being performed by component of the memory system 100

[0069] A descriptor is received based on a power management pointer (302). For example, the power manager 120 can identify one or more descriptors between a descriptor at the first position in a descriptor queue 114 and a descriptor to which the power management pointer points, inclusive. The power manager 120 can transition the memory units corresponding to these descriptors to the active state before the descriptors are processed so that the memory access engine 112 does not have to wait to perform the memory access operation when the descriptor is processed. As described above, each descriptor can include data indicating a memory location for which a memory access operation is to be performed.

[0070] The power manager 120 determines if the memory unit 152 corresponding to the memory address of the descriptor is in the active state (304). As described above, the power manager 120 can maintain a status table 122 for the memory units 152. The power manager 120 can access the status table 122 to determine whether the memory unit 152 is in the active state. For example, the power manager 120 can access the cell corresponding to the memory unit 152 to obtain the label or value for the current state of the memory unit 152. If the memory unit 152 is in the active state, the power manager 120 can keep the memory unit in the active state (306)

[0071] If the memory unit is not in the active state, the power manager 120 can transition the memory unit 152 into the active state (308). The power manager 120 can then keep the memory unit 152 in the active state at least until the memory access operation for the memory unit is performed.

[0072] A determination is made whether the memory unit 152 has been accessed by the memory access engine (310). For example, the memory access unit 112 can be configured to notify the power manager 120 of each descriptor that has been processed. In another example, the power manager 120 can be configured to monitor the memory access pointer to determine when a descriptor has been processed. If the memory unit 152 has not been accessed, the process 300 can return to operation (306) and the memory unit 152 can be kept in the active state until it has been accessed.

[0073] To determine whether to transition the memory unit 152 back to a lower power state, the power manager 120 checks if any of the subsequent descriptors, e.g., scanned descriptors, that are to be transitioned to the active state include a memory address pointing to the memory unit 152 (312). For example, a memory access pointer and a power management pointer may indicate a number of subsequent descriptors for which the corresponding memory units 152 should be in the active state. If a descriptor between the memory access pointer and a scan pointer indicates the same memory unit 152 at which a memory access operation was just performed, the power manager 120 will maintain the memory unit in the active state. This prevents backpressure that would be caused if the memory unit 152 was transitioned to a low power state when the memory unit 152 will be accessed again in an amount of time that is less than the amount of time that it takes for the memory unit 152 to transition from a low power state to the active state.

[0074] If the power manager 120 determines that none of the subsequent descriptors between the memory access pointer and the power management pointer include a memory location that corresponds to the memory unit 152, the power manager 120 can transition the memory unit 120 to a low power state (314). Otherwise, the process 300 can return to operation (306) where the power manager 120 keeps the memory unit 152 in the active state so that the descriptor that corresponds to the memory unit 152 can be processed without delay.

[0075] FIG. 4 shows a flow diagram of an example process 400 for accessing memory units and transitioning memory units between active and low power states. The process 400 can be performed by a memory system, e.g., memory system 100, to manage volatile memory 150 to fulfill received memory access requests from one or more agents 105.

[0076] The memory controller 110 accesses a descriptor queue, e.g., descriptor queue 114 (402). The descriptor queue 114 includes a sequence of descriptors, a memory access pointer, and a power management pointer. A queue manager 116 can be configured to update the descriptor queue with a descriptor when the memory controller 110 receives a new memory access request. In some implementations, a memory access engine 114 of the memory controller 110 can be configured to process new memory requests. The descriptor queue can be a FIFO queue populated with descriptors corresponding to memory access operations from agent devices of agents 105. The memory access engine 112 can be configured to read the sequence of descriptors based on the memory access pointer to access a memory address and operation included in a descriptor from the sequence of descriptors.

[0077] The memory controller 110 identifies one or more subsequent descriptors in the descriptor queue 114 to transition to the active state (404). The power manager 120 can use the power management pointer to determine subsequent descriptors for which the corresponding memory units should be transitioned to the active state in advance of the descriptors being processed by the memory access engine 114. As described above, the number of subsequent descriptors that are identified can be based on an amount of time taken, e.g., in terms of a number of clock cycles, for a memory unit to transition from a low power state to an active state.

[0078] In some implementations, the queue manager 116 maintains a distance in terms of a number of descriptors between the memory access pointer and the power management pointer. The number of descriptors of this distance can be based on an amount of time that a memory unit 152 takes to transition from a low power state to an active state and/or a number of descriptors that can be processed as the same time. The amount of time for a transition may be represented as a number of clock cycles of a processor of the memory system 100 or of a system that includes and/or is communicably coupled to the memory system 100.

[0079] For example, if the memory system 100 can process one descriptor per clock cycle and it takes three clock cycles for a memory unit 152 to transition from a low power state to the active state, the distance between the memory access pointer and the power management pointed may be three descriptors. In this way, the power management pointer moves to a new descriptor each clock cycle and stays three descriptors ahead of the memory access pointer such that each new descriptor has three clock cycles to transition to the active state before being at the top of the descriptor queue 114.

[0080] In this way, the memory unit 152 for each descriptor will have sufficient time to transition to the active state before being processed by the memory controller 110, but without transitioning memory units 152 too early such that they are in the active state for longer than warranted. This reduces the amount of leakage power by reducing the amount of time memory units 152 are in the active state, while also reducing latency and backpressure that would otherwise be caused by memory units 152 not being in the active state when reaching the top of the descriptor queue 114.

[0081] The power manager 120 transitions the identifier subsequent memory units that are currently in a low power state to the active state (406).

[0082] The memory controller 110 accesses one or more memory units for each subsequent descriptor when the memory access pointer points to the subsequent descriptor in the descriptor queue (408). The queue manager 116 is configured to update the memory access pointer and power management pointer after each descriptor of the subsequent descriptors is processed by the memory controller 110. In some implementations, accessing one or more memory units for each subsequent descriptor includes performing the memory access operation, e.g., reading data from the memory unit, writing data to the memory unit, associated with the subsequent descriptor.

[0083] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or in addition, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0084] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a GPGPU (General purpose graphics processing unit).

[0085] Computers suitable for the execution of a computer program include, by way of example, can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0086] Computer readable media suitable for storing computer program instructions and data include all forms of non volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0087] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0088] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0089] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

CLAIMS What is claimed is:

1. A memory system, comprising: volatile memory comprising a plurality of memory units; a descriptor queue configured to maintain a sequence of descriptors each corresponding to a received memory access request for performing a memory access operation on a respective memory unit of the plurality of memory units, wherein the descriptor queue comprises a memory access pointer that indicates a current descriptor to be processed and a power management pointer that indicates one or more subsequent descriptors for active state transition; a memory controller configured to process the descriptors in the descriptor queue based on the memory access pointer and to access the memory units of the descriptors to respond to received memory access requests corresponding to the descriptors in the descriptor queue; and a power manager configured to selectively transition each memory unit between the active state and a low power state, including monitoring the power management pointer to identify the one or more subsequent descriptors and transitioning the respective memory unit for each of the one or more subsequent descriptors from the low power state to the active state prior to the one or more subsequent descriptors being processed by the memory controller.

2. The memory system of claim 1, wherein the descriptor queue comprises a first in, first out queue and each descriptor is removed from the descriptor queue after the memory controller performs a memory access operation indicated by the descriptor.

3. The memory system of claim 1 or 2, wherein the volatile memory comprises static random access memory (SRAM).

4. The memory system of any preceding claim, wherein the descriptor queue comprises a queue manager configured to: update the descriptor queue to include a descriptor of each newly received memory access request; update the memory access pointer after each descriptor is processed by the memory controller; and update the power management pointer after each descriptor is processed by the memory controller.

5. The memory system of any preceding claim, wherein the one or more subsequent descriptors comprises a number of descriptors selected based on an amount of time taken for a memory unit to transition from the low power state to the active state.

6. The memory system of claim 5, wherein the number of descriptors is based on a number of memory access operations the memory controller is capable of completing within the amount of time.

7. The memory system of claim 5, wherein the number of descriptors is based on a number of processing unit clock cycles of a processor communicably coupled to the volatile memory that occur during the amount of time.

8. The memory system of any preceding claim, wherein the descriptor queue comprises one or more additional power management pointers that indicate an additional set of subsequent descriptors for active state transition.

9. The memory system of claim 8, wherein the additional set of subsequent descriptors comprises an additional number of descriptors selected based on an amount of time taken for a memory unit corresponding to each additional descriptor to transition from the low power state to the active state.

10. The memory system of claim 9, wherein the additional number of descriptors is based on a number of memory access operations the memory controller is capable of completing within the duration of time.

11. The memory system of any preceding claim, wherein the power manager is configured to: determine whether the respective memory unit of the current descriptor is a subsequent descriptor for active state transition; whenever the respective memory unit of the current descriptor is a subsequent descriptor for active state transition, leave the respective memory unit of the current descriptor in the active state after processing the current descriptor; and whenever the respective memory unit of the current descriptor is not a subsequent descriptor for active state transition, transition the respective memory unit of the current descriptor from the active state to the low power state.

12. A method performed by a memory controller configured to manage volatile memory comprising a plurality of memory units, the method comprising: accessing a descriptor queue comprising, a sequence of descriptors each corresponding to a received memory access request, wherein each descriptor corresponds to a memory access operation for a respective memory unit of the plurality of memory units indicated by the descriptor, a memory access pointer that indicates a current descriptor for processing, and a power management pointer that indicates one or more subsequent descriptors for active state transition; identifying, based on the power management pointer, the one or more subsequent descriptors; transitioning each subsequent descriptor that is in a low power state from the low power state to the active state; and accessing the one or more memory units for each subsequent descriptor when the memory access pointer reaches the subsequent descriptor in the descriptor queue.

13. The method of claim 12, wherein accessing the one or more memory units for each subsequent descriptor comprises performing the memory access operation of the subsequent descriptor.

14. The method of claim 12 or 13, further comprising updating the memory access pointer and the power management pointer to indicate different descriptors each time the memory access operation for a descriptor is performed and the descriptor is removed from the descriptor queue.

15. The method of any of claims 12 to 14, further comprising: performing the memory access operation of the current descriptor; removing the current descriptor from the descriptor queue in response to performing the memory access operation of the current descriptor; updating the memory access pointer to indicate a next descriptor in the descriptor queue following the current descriptor; and updating the one or more subsequent descriptors for active state transition by updating the power management pointed in response to performing the memory access operation of the current descriptor.

16. The method of claim 15, further comprising: determining whether the respective memory unit of the current descriptor is a subsequent descriptor for active state transition; whenever the respective memory unit of the current descriptor is a subsequent descriptor for active state transition, leaving the respective memory unit of the current descriptor in the active state after processing the current descriptor; and whenever the respective memory unit of the current descriptor is not a subsequent descriptor for active state transition, transitioning the respective memory unit of the current descriptor from the active state to the low power state.

17. The method of any of claims 12 to 16, further comprising identifying, as the one or more subsequent descriptors, each descriptor between the memory access pointer and the power management pointer.

18. The method of claim 17, further comprising controlling the power management pointer to identify a particular number of subsequent descriptors based on a duration of time taken for a memory unit to transition from the low power state to the active state.

19. The method of claim 12, wherein the descriptor queue comprises a first in, first out queue and each descriptor is removed from the descriptor queue after the memory controller performs the memory access operation indicated by the descriptor

20. The method of claim 12, wherein the volatile memory comprises static random access memory (SRAM).

21. The method of claim 12, wherein the descriptor queue comprises a queue manager configured to: update the descriptor queue to include a descriptor of each newly received memory access request; update the memory access pointer after each descriptor is processed by the memory controller; and update the power management pointer after each descriptor is processed by the memory controller.

22. The method of any of claims 12 to 21, wherein the one or more subsequent descriptors comprise a number of descriptors selected based on a duration of time taken for a memory unit to transition from the low power state to the active state.

23. The method of claim 22, wherein the number of descriptors is based on a number of memory access operations the memory controller is capable of completing within the duration of time.

24. The method of claim 22, wherein the number of descriptors is based on a number of processing unit clock cycles of a processor communicably coupled to the volatile memory that occur during the duration of time.

25. The method of any of claims 12 to 24, further comprising: determining that a particular descriptor corresponding to a particular memory unit is not in the descriptor queue; and in response to determining that the particular descriptor corresponding to a particular memory unit is not in the descriptor queue, transitioning the particular memory unit to the low power state.