WO2024148755A1 - Refresh circuit and method, and memory - Google Patents

Abstract

Provided in the embodiments of the present disclosure are a refresh circuit and method, and a memory. The circuit comprises: a refresh command counting module, which is configured to count refresh commands, so as to generate a first count value; a refresh address generator, which is configured to output row address signals, and update the row address signals on the basis of a refresh operation; a weak address generator, which is configured to receive a refresh address selection signal, and output a plurality of weak address signals on the basis of the refresh commands when the refresh address selection signal is at a second level; and a refresh module, which is configured to execute, when the refresh address selection signal is received and in response to received refresh command signals, the refresh operation on storage rows corresponding to the row address signals or the plurality of weak address signals.

Description

A refresh circuit, method and memory

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims the priority of the Chinese patent application filed with the China Patent Office on January 9, 2023, with application number 202310026121.2 and application name “A refresh circuit, method and memory”, all contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to, but is not limited to, a refresh circuit, a refresh method, and a memory.

Background technique

Dynamic Random Access Memory (DRAM) has Error Check and Correct (ECC) mode and Error Check and Scrub (ECS) mode. Among them, the ECC mode can automatically correct the single bit of failure in DRAM, and the ECS mode can periodically check and correct data. At present, due to the gradual reduction in the size of DRAM, the data failure phenomenon in DRAM has increased rapidly, affecting the stability of the memory.

Summary of the invention

The present disclosure provides a refresh circuit, method and memory.

The technical solution of the present disclosure is achieved as follows:

In a first aspect, an embodiment of the present disclosure provides a refresh circuit, including:

A refresh command counting module, configured to count refresh commands to generate a first count value; if the first count value is less than a first threshold, output a refresh address selection signal at a first level; if the first count value is greater than or equal to the first threshold, output the refresh address selection signal at a second level;

a refresh address generator configured to output a row address signal and update the row address signal based on a refresh operation;

a weak address generator connected to the refresh command counting module, configured to receive the refresh address selection signal, and output a plurality of weak address signals based on each refresh command when the refresh address selection signal is at a second level; wherein the weak address signal is row address information recorded in performing an error check and clear (ECS) operation;

A refresh module is connected to the refresh command counting module, the refresh address generator and the weak address generator, and is configured to, when the received refresh address selection signal is at a first level, sequentially perform a refresh operation on the storage rows corresponding to the row address signal in response to the received refresh command signal; or, when the received refresh address selection signal is at a second level, sequentially perform a refresh operation on the storage rows corresponding to the multiple weak address signals in response to the received refresh command signal.

In some embodiments, the refresh command counting module is specifically configured to receive the refresh command signal; each time a refresh command signal is received, the first count value is incremented by one;

When the first count value reaches a second threshold, the first count value is reset; wherein the second threshold is greater than the first threshold.

In some embodiments, the refresh module is further configured to output a refresh clock signal; wherein, during each refresh operation, the refresh clock signal generates a refresh pulse;

The refresh address generator is further configured to receive the refresh clock signal; and to update and output the row address signal in sequence according to each refresh pulse on the refresh clock signal.

In some embodiments, the refresh address generator is further configured to receive the refresh address selection signal, and when the refresh address selection signal is at a first level, to sequentially update and output the row address signal according to each refresh pulse on the refresh clock signal, and when the refresh address selection signal is at a second level, to shield the refresh clock signal.

In some embodiments, the first count value includes M-bit sub-signals, and the first threshold is 2 ^(N-1) ;

The refresh command counting module includes M triggers cascaded in sequence, the input end of each level of the trigger is connected to its own inverting output end, the positive output end of the i-th level of the trigger is used to output the i-th bit sub-signal of the first count value, and the first level of the trigger is connected to the positive output end of the trigger. The clock end of the trigger is used to receive the refresh command signal, and the clock end of the trigger of the i+1th level is connected to the inverting output end of the trigger of the ith level;

Among them, the Nth bit sub-signal output of the first count value is the refresh address selection signal, M is an integer greater than 1, i is an integer greater than or equal to 1 and less than M, and N is an integer greater than 1 and less than or equal to M.

In some embodiments, the second threshold is 2 ^(L-1) +2 ^(N-1) , where L is a positive integer less than or equal to N;

The refresh command counting module also includes a first AND gate, a first input end of the first AND gate is connected to the positive phase output end of the Nth trigger, a second input end of the first AND gate is connected to the positive phase output end of the Lth trigger, and an output end of the first AND gate is connected to the reset ends of all the triggers.

In some embodiments, the weak address generator includes a first logic unit and a first-in first-out register, and the first-in first-out register stores a plurality of the weak address signals, wherein:

The first logic unit is configured to receive the refresh command signal and the refresh address selection signal, perform logic processing on the refresh command signal and the refresh address selection signal, and output a weak address clock signal; wherein, when the refresh address selection signal is at the second level, each time a refresh command signal is received, a pulse is generated on the weak address clock signal;

The first-in first-out register is configured to receive the weak address clock signal and output a plurality of the weak address signals according to each pulse of the weak address clock signal.

In some embodiments, the weak address signal refers to a storage row having an error bit greater than a third threshold in the ECS mode;

The weak address generator is further configured to receive a current ECS operation row address signal and a corresponding storage flag signal, and when the storage flag signal is valid, store the current ECS operation row address signal as the weak address signal; wherein the storage flag signal indicates whether an error bit of the storage row corresponding to the current ECS operation row address signal is greater than a third threshold.

In some embodiments, the weak address generator further includes a latch, an address comparator, and a second logic unit, wherein:

The latch is configured to latch the weak address signal stored last time;

The address comparator is configured to receive the current ECS operation row address signal and the weak address signal stored last time; when the current ECS operation row address signal and the weak address signal stored last time are different, output a valid update flag signal;

The second logic unit is configured to receive the storage flag signal and the update flag signal; when both the storage flag signal and the update flag signal are valid, output a valid load clock signal;

The latch is further configured to receive the loading clock signal and the current ECS operation row address signal; when the loading clock signal is valid, latch the current ECS operation row address signal as the weak address signal to be stored;

The FIFO register is further configured to receive the loading clock signal delayed by a first preset time and the weak address signal to be stored, and store the weak address signal to be stored based on the loading clock signal.

In some embodiments, the second logic unit includes a second AND gate and a pulse generator, wherein:

The first input end of the second AND gate receives the storage flag signal, the second input end of the second AND gate receives the update flag signal, the output end of the second AND gate is connected to the input end of the pulse generator, and the output end of the pulse generator is used to output the loading clock signal.

In some embodiments, the pulse generator includes a first NOT gate, a delay unit and a third AND gate, wherein:

The input end of the first NOT gate is connected to the output end of the second AND gate, the output end of the first NOT gate is connected to the input end of the delay unit, the output end of the delay unit is connected to the second input end of the third AND gate, the first input end of the third AND gate is connected to the output end of the second AND gate, and the output end of the third AND gate is used to output the loading clock signal.

In some embodiments, the refresh module includes a control subunit, a selection subunit and a refresh subunit, wherein:

The control subunit is configured to receive the refresh address selection signal; when the refresh address selection signal is at a second level, based on the refresh clock signal, generate and output a selection signal group; the selection subunit is configured to receive the selection signal group, the refresh address selection signal, the row address signal and a plurality of the weak address signals; when the refresh address selection signal is at a first level, output the row address signal as the address signal to be refreshed; when the refresh address selection signal is at a second level, based on the selection signal group, output the plurality of the weak address signals in sequence as the address signal to be refreshed;

The refresh subunit is configured to receive the refresh command signal and the address signal to be refreshed, and in response to the refresh command signal, sequentially perform a refresh operation on the storage rows indicated by the address signal to be refreshed.

In some embodiments, the control subunit includes a fourth AND gate, a pulse counting unit, a third logic unit and a fourth logic unit, wherein:

The input end of the fourth AND gate receives the refresh address selection signal and the refresh clock signal; the output end of the fourth AND gate is connected to the input end of the pulse counting unit, and the output end of the pulse counting unit outputs a counting signal group;

The input end of the third logic unit performs a first decoding process on the counting signal group to output the selection signal group;

The input end of the fourth logic unit performs a second decoding process on the counting signal group to output a reset signal of the pulse counting unit.

In some embodiments, the selection signal group includes X-bit selection sub-signals, and the third logic unit includes X NAND gates, wherein:

Each of the NAND gates has m input terminals for receiving m target counting signals or inverted signals thereof, and the output terminals of the X NAND gates correspond one-to-one to the X-bit selection sub-signals; wherein the target counting signals are the m counting signals in the counting signal group, and any two of the NAND gates do not have exactly the same inputs;

Wherein, X is a positive integer, and m is an integer greater than or equal to 2.

In some embodiments, the number of the weak address signals output based on each refresh command is X;

The selection subunit includes X+1 cascaded selectors:

The first input terminal of the first-stage selector receives the X-th weak address signal, the second input terminal of the first-stage selector receives the ground signal, and the control terminal of the first-stage selector receives the X-th selection sub-signal;

The first input end of the j-th selector receives the X+1-j-th weak address signal, the second input end of the j-th selector is connected to the output end of the j-1-th selector, and the control end of the j-th selector receives the X+1-j-th selection sub-signal; wherein j is an integer greater than or equal to 2 and less than or equal to X;

The first input end of the selector of the X+1th level receives the row address signal, the second input end of the selector of the X+1th level is connected to the output end of the selector of the Xth level, the control end of the selector of the X+1th level receives the refresh address selection signal, and the output end of the selector of the X+1th level outputs the address signal to be refreshed.

In some embodiments, when X=3, the pulse counting unit includes a first-level trigger and a second-level trigger, the third logic unit includes a first NAND gate, a second NAND gate, and a third NAND gate, and the selection subunit includes a first-level selector, a second-level selector, a third-level selector, and a fourth-level selector; wherein,

The clock terminal of the trigger of the first level is connected to the output terminal of the fourth AND gate, the input terminal of the trigger of the first level is connected to its own inverting output terminal, and the positive phase output terminal of the trigger of the first level is used to output the first bit sub-signal of the counting signal group; the clock terminal of the trigger of the second level is connected to the inverting output terminal of the trigger of the first level; the input terminal of the trigger of the second level is connected to its own inverting output terminal, and the positive phase output terminal of the trigger of the second level is used to output the second bit sub-signal of the counting signal group;

The first input end of the first NAND gate is connected to the inverting output end of the first-stage trigger, the second input end of the first NAND gate is connected to the inverting output end of the second-stage trigger, and the output end of the first NAND gate outputs the first-bit selection sub-signal; the first input end of the second NAND gate is connected to the positive-phase output end of the first-stage trigger, the second input end of the second NAND gate is connected to the inverting output end of the second-stage trigger, and the output end of the second NAND gate outputs the second-bit selection sub-signal; the first input end of the third NAND gate is connected to the inverting output end of the first-stage trigger, the second input end of the third NAND gate is connected to the positive-phase output end of the second-stage trigger, and the output end of the third NAND gate outputs the third-bit selection sub-signal;

The first input end of the selector of the first level receives the third weak address signal, the second input end of the selector of the first level receives the ground signal, and the control end of the selector of the first level receives the third selection sub-signal; the first input end of the selector of the second level receives the second weak address signal, the second input end of the selector of the second level is connected to the output end of the selector of the first level, and the control end of the selector of the second level receives the second selection sub-signal; the first input end of the selector of the third level receives the first weak address signal, the second input end of the selector of the third level is connected to the output end of the selector of the second level, and the control end of the selector of the third level receives the first selection sub-signal; the first input end of the selector of the fourth level receives the row address signal, the second input end of the selector of the fourth level is connected to the output end of the selector of the third level, the control end of the selector of the fourth level receives the refresh address selection signal, and the output end of the selector of the fourth level outputs the address signal to be refreshed.

In some embodiments, the refresh circuit further includes an ECS module and a threshold module, wherein:

The ECS module is configured to output the current ECS operation row address signal and a second count value; wherein the second count value refers to the number of error bits of the storage row corresponding to the current ECS operation row address signal;

The threshold module is configured to receive the second count value, and output the valid storage flag signal when the second count value is greater than the third threshold value; and output the invalid storage flag signal when the second count value is less than or equal to the third threshold value;

The weak address generator is further configured to receive the storage flag signal and the current ECS operation row address signal, and store the current ECS operation row address signal as the weak address signal when the storage flag signal is valid.

In some embodiments, the threshold module is further configured to receive a threshold setting signal, and determine the third threshold based on the threshold setting signal.

In a second aspect, an embodiment of the present disclosure provides a refresh method, which is applied to the refresh circuit as described in the first aspect, and the method includes:

Each time the memory receives a refresh command, the first count value is incremented by one;

When the first count value is less than a first threshold, performing a refresh operation on the next storage row according to a refresh sequence in an automatic refresh mode;

When the first count value is greater than or equal to a first threshold and less than a second threshold, refresh operations are performed on weak storage rows in sequence; wherein the weak storage row refers to a storage row whose error bit is greater than a third threshold in the ECS mode, and the second threshold is greater than the first threshold.

In some embodiments, the method further includes: when the first count value is equal to the second threshold, resetting the first count value.

In a third aspect, an embodiment of the present disclosure provides a memory, which includes the refresh circuit as described in the first aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing the principle of an ECC mode provided by an embodiment of the present disclosure;

FIG2 is a structural schematic diagram 1 of a refresh circuit provided by an embodiment of the present disclosure;

FIG3 is a second structural diagram of a refresh circuit provided by an embodiment of the present disclosure;

FIG4 is a structural schematic diagram 1 of a refresh command counting module provided by an embodiment of the present disclosure;

FIG5 is a second structural diagram of a refresh command counting module provided by an embodiment of the present disclosure;

FIG6 is a first structural diagram of a weak address generator provided by an embodiment of the present disclosure;

FIG7 is a second structural diagram of a weak address generator provided by an embodiment of the present disclosure;

FIG8 is a third structural diagram of a weak address generator provided by an embodiment of the present disclosure;

FIG9 is a fourth structural diagram of a weak address generator provided by an embodiment of the present disclosure;

FIG10 is a structural schematic diagram 1 of a refresh module provided in an embodiment of the present disclosure;

FIG11 is a second structural diagram of a refresh module provided in an embodiment of the present disclosure;

FIG12 is a third structural diagram of a refresh module provided in an embodiment of the present disclosure;

FIG13 is a fourth structural diagram of a refresh module provided in an embodiment of the present disclosure;

FIG14 is a fifth structural diagram of a refresh module provided in an embodiment of the present disclosure;

FIG15 is a third structural diagram of a refresh circuit provided by an embodiment of the present disclosure;

FIG16 is a schematic flow chart of a refreshing method provided in an embodiment of the present disclosure;

FIG. 17 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure.

Detailed ways

The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

Dynamic Random Access Memory (DRAM);

Synchronous Dynamic Random Access Memory (SDRAM);

Double Data Rate (DDR);

Low Power DDR (LPDDR);

5th generation DDR (5th DDR, DDR5);

Error Check and Correct (ECC);

Error Check and Scrub (ECS);

Error per Row Counter (EpRC).

With the miniaturization of the process, the challenge of single-bit failure has become increasingly severe. Taking DDR5 DRAM as an example, in order to cope with single-bit failures, an on-chip ECC (On-Die ECC) structure is introduced, so that DRAM can automatically correct failed single bits. Based on On-Die ECC, DDR5 also introduces ECS operation. The ECS operation will perform a complete error check and clearing of DRAM at least once within 24 hours, including error checking of all DRAM storage groups (Bank Group, BG), storage blocks (Bank, BA), storage rows (Row) and storage columns (Column, Col). The ECS operation can record the address of a row with the most data failures in a complete ECS cycle, and send it to the mode register (Mode Register, MR) for the memory controller (Controller) to read.

The working process of ECS is shown in Figure 1. The ECS address generator (ECS Address Counters) gives the storage row address of the detection object. After the ECC error correction logic module (ECC Correction Logic) detects that the data in the storage row is invalid, the count value of the error counter (EC) and the error counter per row (EpRC) is increased by one. After reading all the code words (Code Word) in the storage row, the comparison module The block (Compare) compares the current row error count with the maximum row error count (Previous High Error Count). If the current row error count is greater than the maximum row error count, the current row error count and the storage row address of the detection object will replace the maximum row error count and the maximum row error address (Previous High Error Count Row/Bank Address) and be saved in MR; if the current row error count is not greater than the maximum row error count, the maximum row error count and the maximum row error address will always be saved in MR. In particular, the error counter will be reset (Reset) every time the row address changes.

After the DRAM completes a complete ECS operation, the maximum row error address will be saved in the mode register MR<16:18>, and the maximum row error count will be saved in MR19. At the same time, the row/code word error count REC[5:0] (Row/Word Code Error Count, REC) recorded by MR is displayed as a row/code word error count within the range, and the row error count threshold (Row Error Threshold Count, RETC) can mask the code word error count that is less than the set threshold. The default value of RETC in DDR5 is 4. It should be understood that Figure 1 is from the industry standard document of the Solid State Technology Association. Those skilled in the art can refer to SPEC to understand the meaning of the various terms and abbreviations involved therein, and this part of the content does not affect the understanding of the embodiments of the present disclosure, so it will not be described in detail here.

However, the limitation of the ECC verification method (Hamming code) commonly used in DRAM is that it can only correct single-bit failures. If the memory has a double-bit failure (Double-Bit Fail) or a multi-bit failure (Multi-Bit Fail), it will cause the memory to read data errors. The ECS mode has a check cycle of 24 hours and only records the row address with the most failed bits. Other storage rows with multiple errors detected in the ECS mode will not be recorded, which cannot fundamentally improve the phenomenon of single-bit failures.

Based on this, in order to improve the occurrence of data failure, an embodiment of the present disclosure provides a refresh circuit, which performs a refresh operation based on a normal row address signal or ECS operation to detect a storage row with multiple errors, and can additionally insert a refresh operation for the storage row corresponding to the weak address signal in the normal refresh operation, thereby improving storage stability and improving data failure.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to FIG. 2 , a schematic diagram of the composition structure of a refresh circuit 10 provided in an embodiment of the present disclosure is shown. The refresh circuit 10 includes:

The refresh command counting module 101 is configured to count the refresh commands to generate a first count value; if the first count value is less than a first threshold, output a refresh address selection signal at a first level; if the first count value is greater than or equal to the first threshold, output a refresh address selection signal at a second level;

A refresh address generator 102 configured to output a row address signal and update the row address signal based on a refresh operation;

A weak address generator 103 is connected to the refresh command counting module 101 and is configured to receive a refresh address selection signal and output a plurality of weak address signals based on each refresh command when the refresh address selection signal is at a second level; wherein the weak address signal is row address information recorded in performing an error check and clear (ECS) operation;

The refresh module 104 is connected to the refresh command counting module 101, the refresh address generator 102 and the weak address generator 103, and is configured to perform a refresh operation on the storage rows corresponding to the row address signal in sequence in response to the received refresh command signal when the received refresh address selection signal is at a first level; or to perform a refresh operation on the storage rows corresponding to multiple weak address signals in sequence in response to the received refresh command signal when the received refresh address selection signal is at a second level.

It should be noted that the refresh circuit 10 of the embodiment of the present disclosure can be applied to but not limited to memories, such as DRAM, SDRAM, DDR, etc. In addition, in other analog circuits/digital circuits, the refresh circuit 10 provided by the embodiment of the present disclosure can improve storage stability.

It should be noted that since the storage unit of DRAM uses the principle of capacitor storing charge to store information, and the capacitor will gradually discharge through the resistor, the refresh operation must be performed at regular intervals. The main function of the refresh module 104 is to continuously read and write the data stored in the DRAM, which is equivalent to repeatedly charging the capacitor so that the discharged charge is replenished to ensure that the data is not lost.

It should be noted that if the data retention time of some storage cells in the storage device does not meet the specified reference time, they are called "weak cells". The above-mentioned weak address signal is the address signal corresponding to the storage cell with multiple errors detected by the ECS operation. Since ultra-high integration requires at least tens of millions of storage cells to be integrated into one chip, the probability of weak cells existing will also increase. Therefore, increasing the refresh frequency of weak cells can ensure the integrity of stored data.

It should be noted that the row address signal, refresh address selection signal, weak address signal, and refresh command signal in Figure 2 are respectively represented by Normal REF Addr, Address Exchange Flag, Out Address, and REF AB CMD in the subsequent explanation.

It should also be noted that a refresh command can perform multiple refresh operations, where the number of times can be 1 or any value greater than 1. The main function of the refresh command counting module 101 is to count the number of external refresh commands and generate a first count value, and output a refresh address selection signal (Addr Exchange Flag) based on the relationship between the first count value and the first threshold. The refresh module 104 performs a refresh operation on the storage row corresponding to the row address signal (Normal REF Addr) or a refresh operation on the storage row corresponding to the weak address signal (Out Address) according to the level state of the refresh address selection signal (Addr Exchange Flag).

Exemplarily, for the refresh address selection signal (Addr Exchange Flag), the first level refers to a low level state (0), and the second level refers to a high level state (1). Specifically, when the refresh address selection signal (Addr Exchange Flag) is 0, the refresh module 104 performs a refresh on the storage row corresponding to the row address signal (Normal REF Addr); when the refresh address selection signal (Addr Exchange Flag) is 1, the refresh module 104 performs a refresh on the storage row corresponding to the weak address signal (Out Address) generated by the weak address generator 103. In other words, the refresh address selection signal (Addr Exchange Flag) is controlled by the level state to determine the row address signal (Normal REF Addr). REF Addr) or weak address signal (Out Address) for refreshing. It should be understood that the requirements for different signal level states in different circuits are not fixed. The refresh address selection signal (Addr Exchange Flag) can also be set to a high level (1) as the first level and a low level (0) as the second level. Designers can determine this based on the internal structure of the circuit and the function of the signal in the specific circuit.

In this way, the refresh module 104 will select the storage row corresponding to the row address signal (Normal REF Address) or the weak address signal (Out Address) as the next refresh object based on the level state of the refresh address selection signal (Addr Exchange Flag). Thus, the refresh operation of the weak cell/weak address is inserted into the normal refresh mechanism to avoid the failure of the storage row corresponding to the weak address signal and improve the data stability.

In some embodiments, the refresh command counting module 101 is specifically configured to receive a refresh command signal (REF AB CMD); each time a refresh command signal (REF AB CMD) is received, the first count value is incremented by one;

When the first count value reaches a second threshold, the first count value is reset; wherein the second threshold is greater than the first threshold.

It should be noted that the refresh command counting module 101 counts the refresh command signal (REF AB CMD) to generate a first count value. When the first count value is less than the first threshold, the refresh address selection signal (Addr Exchange Flag) is at a first level, and the refresh module 104 executes a refresh of the storage row corresponding to the row address signal (Normal REF Addr); when the first count value is greater than or equal to the first threshold and less than the second threshold, the refresh address selection signal (Addr Exchange Flag) is at a second level, and the refresh module 104 executes a refresh of the storage row corresponding to the weak address signal (Out Address); when the first count value is equal to the second threshold, after the refresh module 104 completes the refresh of part or all of the weak address signals (Out Address) in the memory, the refresh command counting module 101 is reset, and the refresh address selection signal (Addr Exchange Flag) at this time is restored to the first level, and the refresh command counting module 101 performs the next cycle. That is to say, during the refresh process, after each pair of storage rows corresponding to all normal row address signals (Normal REF Address) in the memory are traversed and refreshed, the refresh of the weak address signal (Out Address) is inserted; in addition, after the storage rows corresponding to some normal row address signals (Normal REF Address) are traversed and refreshed, the refresh of the weak address signal (Out Address) may be inserted; the first threshold value set in the above two cases is different.

It should be noted that the third threshold and the first threshold are pre-set fixed values, and the first threshold and the third threshold are related to the number of refresh command signals (REF AB CMD) counted by the refresh command counting module 101; while the number of weak address signals (Out Address) in the memory is uncertain and has nothing to do with the first threshold and the second threshold, and the number of weak address signals (Out Address) is related to the performance of the memory and the environmental parameters of the current ECS test.

Specifically, the difference between the second threshold and the first threshold is the number of weak address signals (Out Address) sequentially output by the weak address generator 103 to the refresh module 104 to perform the refresh operation, which may not match the number of weak address signals (Out Address) stored in the weak address generator 103. The difference between the second threshold and the first threshold may be greater than the number of weak address signals (Out Address), or may be less than the number of weak address signals (Out Address). Therefore, it is necessary for circuit designers to modify the first threshold and the second threshold according to actual conditions to improve the above mismatch, better improve the refresh frequency of the weak address signal (Out Address), and ensure the stability of the memory.

In some embodiments, referring to FIG. 3 , the refresh module 104 is further configured to output a refresh clock signal (CBR_CLK); wherein, after each refresh operation, the refresh clock signal (CBR_CLK) generates a refresh pulse;

The refresh address generator 102 is also configured to receive a refresh clock signal (CBR_CLK); and to update and output a row address signal (Normal REF Addr) in sequence according to each refresh pulse on the refresh clock signal (CBR_CLK).

It should be noted that the refresh pulse on the refresh clock signal (CBR_CLK) is used to update the row address signal (Normal REF Addr) for refresh; in some embodiments, a refresh pulse can be generated on the refresh clock signal (CBR_CLK) before each refresh operation, and the row address signal (Normal REF Addr) for refresh is updated and output according to the refresh pulse generated before the refresh operation, and the current refresh operation refreshes the updated row address signal (Normal REF Addr); in other embodiments, a refresh pulse can be generated on the refresh clock signal (CBR_CLK) at each refresh operation or after each refresh operation, and the row address signal (Normal REF Addr) for refresh is updated and output according to the generated refresh pulse, and the next refresh operation refreshes the updated row address signal (Normal REF Addr); the present disclosure takes the latter "generating a refresh pulse on the refresh clock signal (CBR_CLK) at each refresh operation or after each refresh operation" as an example for explanation.

It should be noted that, as shown in Figure 3, when the refresh address selection signal (Addr Exchange Flag) is at the first level, the refresh address selection signal (Addr Exchange Flag) is connected to the first input terminal of the AND gate through the NOT gate, the second input terminal of the AND gate receives the refresh clock signal (CBR_CLK), and the output terminal of the AND gate serves as the counting clock of the refresh address generator 102 to update the address information of the automatic refresh.

It should also be noted that the embodiment of the present disclosure utilizes the refresh address generator 102 to count the number of refresh operations inside the memory and generate a row address signal (Normal REF Addr), and the row address signal (Normal REF Addr) indicates the next address to be refreshed in the auto refresh (AR) mechanism. The refresh address generator 102 is a counter inside the SDRAM that automatically generates row addresses in sequence in the auto refresh mode. For AR, since the refresh is performed on all storage bodies in a row, there is no need for column addressing, or the column address selection (CAS) is valid before the row address selection (RAS). Therefore, AR is also called CBR (CAS Before RAS, column positioning in advance of row) refresh. It should be understood that each refresh operation has an internal refresh command, and each refresh operation not only refreshes one row, but can refresh multiple rows of the Bank at the same time. In addition, each refresh command allows the memory to perform multiple refresh operations, which is determined by the refresh circuit designed for each DRAM product.

In some embodiments, as shown in FIG. 3 , the refresh address generator 102 is further configured to receive a refresh address selection signal (Addr Exchange Flag), when the refresh address selection signal (Addr Exchange Flag) is at a first level, the row address signal (Normal REF Addr) is updated and output in sequence according to each refresh pulse on the refresh clock signal (CBR_CLK), and when the refresh address selection signal (Addr Exchange Flag) is at a second level, the refresh clock signal (CBR_CLK) is shielded.

It should be noted that when the refresh address selection signal (Addr Exchange Flag) is at the second level, the weak address generator 103 outputs a weak address signal (Out Address). At this time, the refresh clock signal (CBR_CLK) will not be input to the refresh address generator 102, and the refresh address generator 102 stops counting, that is, the automatic refresh address does not change. Until the refresh address selection signal (Addr Exchange Flag) returns to the first level, the refresh address generator 102 outputs a row address signal (Normal REF Addr) corresponding to the order of automatic refresh and the pulse of the refresh clock signal.

In some embodiments, as shown in FIG4 , the first count value includes M-bit sub-signals, and the first threshold is 2 ^(N-1) ;

The refresh command counting module 101 includes M triggers cascaded in sequence, the input end of each stage of the trigger is connected to its own inverting output end, the positive phase output end of the i-th stage trigger is used to output the i-th bit sub-signal of the first count value, the clock end of the 1st stage trigger is used to receive the refresh command signal (REF AB CMD), and the clock end of the i+1th stage trigger is connected to the inverting output end of the i-th stage trigger;

Among them, the Nth sub-signal output of the first count value is a refresh address selection signal (Addr Exchange Flag), M is an integer greater than 1, i is an integer greater than or equal to 1 and less than M, and N is an integer greater than 1 and less than or equal to M.

It should be noted that, as shown in Fig. 4, the embodiment of the present disclosure uses 12 D flip-flops to form an asynchronous binary counter 20. Here, N is 12, and when the first count value reaches the first threshold 2 ¹¹ =2048, the refresh command counting module 101 outputs the 12th bit sub-signal of the first count value as a refresh address selection signal (Addr Exchange Flag) at the second level.

Specifically, the inverting output terminal (QB) of each D flip-flop is connected to the input terminal (D) and to the clock terminal (CLK) of the next-level D flip-flop. The positive output terminal (Q) of each D flip-flop serves as the counting terminal, and the reset terminal (RST) is reset after receiving the reset signal to start the next round of counting.

Among them, the clock terminal (CLK) of the first-stage D flip-flop 201 is used to receive the refresh command signal (REF AB CMD), the first-stage D flip-flop 201 has a first counting terminal for outputting REF AB_CNT<0>; the second-stage D flip-flop 202 has a second counting terminal for outputting REF AB_CNT<1>; the third-stage D flip-flop 203 has a third counting terminal for outputting REF AB_CNT<2>... the eleventh-stage D flip-flop 211 has an eleventh counting terminal for outputting REF AB_CNT<10>; the twelfth-stage D flip-flop 212 has a twelfth counting terminal for outputting REF AB_CNT<11>.

It should be noted that, as shown in FIG4 , the refresh command counting module 101 further includes a first buffer 21 and a first AND gate 22. The input end of the first buffer 21 is connected to the positive phase output end of the 12th level flip-flop, and the output end of the first buffer 21 outputs a refresh address selection signal (Addr Exchange Flag); the output end of the first AND gate 22 is connected to the reset end of the 12 flip-flops, the first input end of the first AND gate 22 is the counting end of the 12th level D flip-flop 212, and the second input end of the first AND gate 22 is the counting end of the 7th level D flip-flop 207 (that is, the output of the asynchronous binary counter 20 is 100001000000), that is, when the second threshold is 2 ^(7-1) +2 ^(12-1) = 2112, the asynchronous binary counter 20 is reset, which is determined by the counting rule of the counter and the internal structure of the DRAM.

In this way, when the asynchronous binary counter 20 is reset, the first count value REF AB_CNT<11:0>=000000000000, and each time a refresh command signal (REF AB CMD) is received, the count value increases once, that is, the count value REF AB_CNT increases in the order of 000000000000, 000000000001, 000000000010, 000000000011…111111111111; when the asynchronous binary counter 20 is reset, the count value returns to the initial state of 000000000000.

In some embodiments, referring to FIG5 , the second threshold is 2 ^(L-1) +2 ^(N-1) , where L is a positive integer less than or equal to N;

The refresh command counting module 101 also includes a first AND gate 22, a first input terminal of the first AND gate 22 is connected to the positive phase output terminal of the Nth trigger, a second input terminal of the first AND gate 22 is connected to the positive phase output terminal of the Lth trigger, and an output terminal of the first AND gate 22 is connected to the reset terminals of all triggers.

It should be noted that, as shown in FIG5 , the refresh command counting module 101 further includes a multiplexer 23, the input end of the multiplexer 23 is connected to the positive phase output end of the Nth to Mth triggers, and the multiplexer 23 outputs a refresh address selection signal (Addr Exchange Flag) based on a selection control signal (Choose Control). The first threshold and the second threshold can be adjusted by the multiplexer 23.

Specifically, the multiplexer 23 can select the data bit of the first count value output as the refresh address selection signal (Addr Exchange Flag), that is, select the first count value (first threshold) that needs to be satisfied when outputting the refresh address selection signal (Addr Exchange Flag). The first input end of the first AND gate 22 can output the N+1th bit of the first count value as the refresh address selection signal (Addr Exchange Flag) through the selection control signal (Choose Control) of the multiplexer, or output the N+2th bit of the first count value as the refresh address selection signal (Addr Exchange Flag)... That is, the first threshold can be ^2N /2 ^(N+1) /2 ^(N+2) .../2 ^(M-1) , so that the (N+1)/(N+2).../Mth bit of the first count value can select which bit sub-signal to output as the refresh address selection signal (Addr Exchange Flag) via the multiplexer 23 through the selection control signal (Choose Control) to adjust the first threshold. Therefore, by adjusting the time interval of the refresh address selection signal (Addr Exchange Flag) switching from the first level to the second level, the refresh frequency of the weak address signal (Out Address) can be controlled. It should be understood that the select control signal (Choose Control) has a default initial value and can also be modified through the parameters of the mode register in the test mode.

Similarly, the data bit of the first count value can also be selected as the reset flag signal output through the multiplexer, that is, the reset flag signal is selected to be output The first count value (second threshold) that needs to be met when the signal is reset. The second input terminal (REFAB CNT<L-1>) of the first AND gate can also be selected and output by the selection control signal (Choose Control) of the multiplexer to control the second threshold. The multiplexer can use the L+1th bit of the first count value as an input of the reset flag signal, or use the L+2th bit of the first count value as an input of the reset flag signal... That is, the second threshold can be (2 ^(M-1) +2 ^L )/(2 ^(M-1) +2 ^(L+1) )/(2 ^(M-1) +2 ^(L+2) )... In this way, the (L+1)/(L+2)... bit of the first count value can be selected by the selection control signal (Choose Control) of the multiplexer to output which bit of the sub-signal as another input data bit of the reset flag signal to control the second threshold. In this way, the counter can meet the circuits with different counting requirements, providing more practical application possibilities.

In some embodiments, as shown in FIG6 , the weak address generator 103 includes a first logic unit 30 and a first-in first-out register (FIFO Register) 31, and the first-in first-out register 31 stores a plurality of weak address signals (Out Address), wherein:

The first logic unit 30 is configured to receive a refresh command signal (REF AB CMD) and a refresh address selection signal (Addr Exchange Flag), perform logic processing on the refresh command signal (REF AB CMD) and the refresh address selection signal (Addr Exchange Flag), and output a weak address clock signal (Out_CLK); wherein, when the refresh address selection signal (Addr Exchange Flag) is at a second level, each time a refresh command signal (REF AB CMD) is received, a pulse is generated on the weak address clock signal (Out_CLK);

The first-in first-out register 31 is configured to receive a weak address clock signal (Out_CLK) and output multiple weak address signals (Out Address) according to each pulse on the weak address clock signal (Out_CLK).

It should be noted that there may be multiple weak units in the memory, so the number of weak address signals (Out Address) can be multiple. In this way, when the weak address clock signal (Out Address) generates a pulse, the multiple weak address signals (Out Address) in the first-in first-out register 31 can be output in sequence.

It should be noted that, as shown in FIG. 6 , the embodiment of the present disclosure is described by taking the first logic unit as an AND gate as an example. The main function of the first logic unit 30 is to perform logical AND processing on the refresh command signal (REF AB CMD) and the refresh address selection signal (Addr Exchange Flag) to generate a weak address clock signal (Out_CLK). In addition, the output of the weak address clock signal (Out_CLK) can also be achieved through a NAND gate, a NOR gate or an XOR gate. Among them, the two gate circuits of the NAND gate and the NOR gate can realize the functions of all other gate circuits. Specifically, if the function of the AND gate is realized by the NAND gate, the two input ends of a NAND gate are connected together, and then a dual-input NAND gate is connected to its input end; if the function of the AND gate is realized by the NOR gate, the NOR gate with two input ends connected together is used as the two inputs of another NOR gate; the XOR gate can also be used to realize the AND gate, but it is rarely used and will not be described in detail here.

It should also be noted that the FIFO register 31 responds to each pulse of the weak address clock signal (Out_CLK) and outputs X weak address signals at the same time, where X is the number of refresh operations performed for each refresh command signal (REF AB CMD) (in some cases, for example, each refresh operation refreshes multiple rows of a Bank at the same time, and X is the number of refreshable rows corresponding to each refresh command signal). During the period when the refresh address selection signal (Addr Exchange Flag) is at the second level, it is necessary to traverse X weak address signals (Out Address) for refreshing, thereby better improving the stability of all weak storage cells. That is to say, if the refresh address selection signal (Addr Exchange Flag) is at the second level and each time a refresh command signal (REF AB CMD) is received, a pulse is generated on the weak address clock signal (Out_CLK) output by the first logic unit 30, and the first logic unit 30 outputs the weak address clock signal (Out_CLK) to the first-in first-out register 31 according to the refresh command signal (REF AB CMD) and the refresh address selection signal (Addr Exchange Flag), so that the first-in first-out register 31 outputs a plurality of weak address signals (Out Address) in sequence based on the weak address clock signal (Out_CLK), so as to perform refresh operations on the storage rows corresponding to the plurality of weak address signals (Out Address) in turn.

Specifically, when the refresh address selection signal (Addr Exchange Flag) is at the first level or the refresh command signal (REF AB CMD) is not received, no pulse is generated on the weak address clock signal (Out_CLK), and multiple weak address signals (Out Address) will be stored in the first-in first-out register 31; when the refresh address selection signal (Addr Exchange Flag) is at the second level and the refresh command signal (REF AB CMD) is received, the first-in first-out register 31 will output the stored multiple weak address signals (Out Address) in sequence according to each pulse on the weak address clock signal (Out_CLK) for subsequent refresh operations on the weak address signals (Out Address).

In some embodiments, the weak address signal (Out Address) refers to a storage row in which the error bit is greater than a third threshold in the ECS mode;

The weak address generator 103 is further configured to receive a current ECS operation row address signal (Row Address) and a corresponding storage flag signal (Bigger_Flag), and when the storage flag signal (Bigger_Flag) is valid, store the current ECS operation row address signal (Row Address) as a weak address signal (Out Address); wherein the storage flag signal (Bigger_Flag) indicates whether an error bit of a storage row corresponding to the current ECS operation row address signal (Row Address) is greater than a third threshold.

It should be noted that the third threshold may be a fixed value or a value range. When performing ECS operations in the memory, the third threshold generally has a set default value to more efficiently detect weak storage rows and improve the error detection efficiency of ECS.

It should also be noted that, for the storage flag signal (Bigger_Flag), valid refers to a low level (0), and invalid refers to a high level (1). Specifically, when the storage flag signal (Bigger_Flag) is at a low level, it means that the error bit of the storage row corresponding to the current ECS operation row address signal (Row Address) is less than or equal to the third threshold, then the current ECS operation row address signal (Row Address) is not a weak address signal (Out Address), and the weak address generator 103 will not store it; when the storage flag signal (Bigger_Flag) is at a high level, it means that the error bit of the storage row corresponding to the current ECS operation row address signal (Row Address) is greater than the third threshold, then the current The ECS operation row address signal (Row Address) is a weak address signal (Out Address), which will be stored by the weak address generator 103 .

In some embodiments, as shown in FIG. 7 , the weak address generator 103 further includes a latch 32 , an address comparator 33 , and a second logic unit 34 , wherein:

Latch 32, configured to latch the weak address signal (Weak_Addr_ECS_) stored last time;

The address comparator 33 is configured to receive the current ECS operation row address signal (Row Address) and the weak address signal (Weak_Addr_ECS_) stored last time; when the current ECS operation row address signal (Row Address) and the weak address signal (Weak_Addr_ECS_) stored last time are different, output a valid update flag signal (Diff_Flag);

The second logic unit 34 is configured to receive a storage flag signal (Bigger_Flag) and an update flag signal (Diff_Flag); when both the storage flag signal (Bigger_Flag) and the update flag signal (Diff_Flag) are valid, output a valid load clock signal (IN_CLK);

The latch 32 is further configured to receive a loading clock signal (IN_CLK) and a current ECS operation row address signal (Row Address); when the loading clock signal (IN_CLK) is valid, the current ECS operation row address signal (Row Address) is latched as a weak address signal (Out Address) to be stored;

The first-in-first-out register 31 is also configured to receive a loading clock signal (IN_CLK) delayed by a first preset time and a weak address signal to be stored (Out Address), and to store the weak address signal to be stored (Out Address) based on the loading clock signal (IN_CLK).

It should be noted that the weak address generator 103 also includes a clock delay unit 35. The clock delay unit 35 is used to delay the loading clock signal (IN_CLK) to ensure that the weak address signal (Out Address) enters the first-in first-out register 31 first. In this way, when the rising edge of the loading clock signal (IN_CLK) arrives, the weak address signal (Out Address) can be stored.

It should be noted that after the weak address generator 103 receives the current ECS operation row address signal (Row Address), it first compares it with the last stored ECS operation weak address signal (Weak_Addr_ECS_); if the two are the same, the latch (Latch) does not need to latch and store the current ECS operation row address signal (Row Address); if the two are different, the latch (Latch) will re-latch the current ECS operation row address signal (Row Address), and send the current ECS operation row address signal (Row Address) as the weak address signal (Out Address) to be stored into the first-in first-out register 31. In this way, not only can the weak address signal (Out Address) be better latched to prepare for the next comparison, but also the weak address signal (Out Address) to be stored is provided to the latch 32.

It should be noted that the work of the first-in first-out register 31 is to access the address. When the loading clock signal (IN CLK) is valid, the weak address signal to be stored (Out Address) is stored. When a pulse is generated on the weak address clock signal (Out_CLK), the weak address signal to be stored (Out Address) is output. In addition, the first-in first-out register 31 will store or output multiple weak address signals (Out Address) stored. The weak address signal (Out Address) received first will be stored or output first, realizing the data input and output at the same time, and improving the transmission efficiency of the memory.

It should also be noted that, as shown in Figure 7, the above-mentioned first logic unit 30, first-in first-out register 31, latch 32, address comparator 33, second logic unit 34 and clock delay unit 35 together constitute a weak address generator 103, which can realize the latching and output of the weak address signal (Out Address) for subsequent refreshing of the storage row corresponding to the weak address signal (Out Address).

In some embodiments, referring to FIG. 8 , the second logic unit 34 includes a second AND gate 340 and a pulse generator 341 , wherein:

The first input end of the second AND gate 340 receives a storage flag signal (Bigger_Flag), the second input end of the second AND gate 340 receives an update flag signal (Diff_Flag), the output end of the second AND gate 340 is connected to the input end of the pulse generator 341, and the output end of the pulse generator 341 is used to output a loading clock signal (IN CLK).

It should be noted that, as shown in FIG8 , the storage flag signal (Bigger_Flag) and the update flag signal (Diff_Flag) are two input terminals of the second AND gate 340, indicating that the storage flag signal (Bigger_Flag) and the update flag signal (Diff_Flag) are both valid at a high level. It should be understood that for these two signals, it can be valid at a high level or valid at a low level. If the storage flag signal (Bigger_Flag) and the update flag signal (Diff_Flag) are valid at a low level, then to output a valid load clock signal (IN CLK), the second AND gate 340 needs to be replaced with a NOR gate to realize the relevant functions of the circuit. At the same time, if one of the two signals, the storage flag signal (Bigger_Flag) and the update flag signal (Diff_Flag), is valid at a high level and the other is valid at a low level, then a NAND gate can be used to replace the second AND gate 340 in the embodiment of the present disclosure to realize the original circuit function.

It should also be noted that the pulse generator 341 is used to generate an automatic pulse of 2 nanoseconds (ns) on the loading clock signal (IN CLK), and the latch 32 will latch the weak address signal (Out Address).

In some embodiments, as shown in FIG. 9 , the pulse generator 341 includes a first NOT gate 3410 , a delay unit 3411 and a third AND gate 3412 , wherein:

An input terminal of the first NOT gate 3410 is connected to an output terminal of the second AND gate 340, an output terminal of the first NOT gate 3410 is connected to an input terminal of a delay unit 3411, an output terminal of the delay unit 3411 is connected to a second input terminal of a third AND gate 3412, a first input terminal of the third AND gate 3412 is connected to an output terminal of the second AND gate 340, and an output terminal of the third AND gate 3412 is used to output a loading clock signal (IN CLK).

It should be noted that the function of the delay unit 3411 is to ensure that the weak address signal (Out Address) enters the latch first, so that when the rising edge of the loading clock signal (IN CLK) arrives, the weak address signal (Out Address) can be well latched.

It should also be noted that, similar to the second AND gate 340 described above, since the validity and invalidity of the signal can be defined as low level validity or high level validity, the third AND gate 3412 can also be replaced by a NOR gate to implement the relevant circuit functions. The selection is not unique and can be flexibly designed according to circuit requirements.

It should also be noted that the above-mentioned first-in first-out register 31, latch 32, address comparator 33, second AND gate 340, pulse generator 341 and clock delay unit 35 together constitute a weak address storage module 1030, and the weak address storage module 1030 and the first logic unit 30 together constitute the weak address generator 103 of the embodiment of the present disclosure.

In some embodiments, as shown in FIG. 10 , the refresh module 104 includes a control subunit 40, a selection subunit 41 and a refresh subunit 42, wherein:

The control subunit 40 is configured to receive a refresh address selection signal (Addr Exchange Flag); when the refresh address selection signal (Addr Exchange Flag) is at a second level, based on a refresh clock signal (CBR_CLK), generate and output a selection signal group (Addr_SELB<X:1>);

The selection subunit 41 is configured to receive a selection signal group (Addr_SELB<X:1>), a refresh address selection signal (Addr Exchange Flag), a row address signal (Normal REF Addr) and a plurality of weak address signals (Out Address); when the refresh address selection signal (Addr Exchange Flag) is at a first level, the row address signal (Normal REF Addr) is output as an address signal to be refreshed (Refresh Address); when the refresh address selection signal (Addr Exchange Flag) is at a second level, the plurality of weak address signals (Out Address) are sequentially output as an address signal to be refreshed (Refresh Address) based on the selection signal group (Addr_SELB<X:1>);

The refresh subunit 42 is configured to receive a refresh command signal (REF AB CMD) and an address signal to be refreshed (Refresh Address), and to perform a refresh operation on a storage row indicated by the address signal to be refreshed (Refresh Address) in response to the refresh command signal (REF AB CMD).

It should be noted that, if the refresh address selection signal (Addr Exchange Flag) output by the refresh command counting module 101 is at the first level, the selection subunit 41 outputs the row address signal (Normal REF Addr), and the refresh subunit 42 performs a normal refresh of the row address signal (Normal REF Addr); if the refresh address selection signal (Addr Exchange Flag) output by the refresh command counting module 101 is at the second level, the control subunit 40 outputs the selection signal group (Addr_SELB<X:1>) according to the refresh clock signal (CBR_CLK) generated by the refresh subunit 42, and the selection subunit 41 outputs a plurality of weak address signals (Out Address) in sequence to the refresh subunit 42 according to the selection signal group (Addr_SELB<X:1>), and performs a refresh operation on the storage row indicated by the weak address signal (Out Address). In this way, by refreshing the level state of the address selection signal (Addr Exchange Flag) and the specific value of the selection signal group (Addr_SELB<X:1>), multiple weak address signals (Out Address) can be selected and output in turn and the refresh operation can be performed on the indicated storage rows.

In some embodiments, referring to FIG. 11 , the control subunit 40 includes a fourth AND gate 400 , a pulse counting unit 401 , a third logic unit 402 , and a fourth logic unit 403 , wherein:

The input end of the fourth AND gate 400 receives the refresh address selection signal (Addr Exchange Flag) and the refresh clock signal (CBR_CLK); the output end of the fourth AND gate 400 is connected to the input end of the pulse counting unit 401, and the output end of the pulse counting unit 401 outputs the counting signal group (Addr_MUX_CNT<Y:0>);

The input end of the third logic unit 402 performs a first decoding process on the count signal group (Addr_MUX_CNTB<Y:0>) to output a selection signal group (Addr_SELB<X:1>);

The input terminal of the fourth logic unit 403 performs a second decoding process on the counting signal group (Addr_MUX_CNTB<Y:0>) to output a reset signal (RST) of the pulse counting unit 401 .

It should be noted that the number of signals Y+1 in the counting signal group (Addr_MUX_CNTB<Y:0>) output by the pulse counting unit 401 should satisfy 2 ^Y+1 >X. The embodiment of the present disclosure takes X=3 and Y=1 as an example for explanation. As shown in FIG12 , the pulse counting unit 401 is a counter composed of two D flip-flops (that is, the number of signals in the output counting signal group (Addr_MUX_CNTB<Y:0>) is 2). The pulse counting unit 401 includes a first-level trigger 4010 and a second-level trigger 4011. The clock terminal of the first-level trigger 4010 is connected to the fourth AND gate 400, the input terminal of the first-level trigger 4010 is connected to its own inverting output terminal, and the positive-phase output terminal of the first-level trigger 4010 is used to output the first-bit sub-signal Addr_MUX_CNT<0> of the counting signal group (Addr_MUX_CNTB<Y:0>); the clock terminal of the second-level trigger 4011 is connected to the inverting output terminal of the first-level trigger 4010; the input terminal of the second-level trigger 4011 is connected to its own inverting output terminal, and the positive-phase output terminal of the second-level trigger 4011 is used to output the second-bit sub-signal Addr_MUX_CNT<1> of the counting signal group (Addr_MUX_CNTB<Y:0>). It should be understood that when the refresh address selection signal (Addr Exchange Flag) is at the second level, the refresh clock signal (CBR_CLK) serves as the clock signal of the pulse counting unit 401. The pulse counting unit 401 counts the refresh clock signal (CBR_CLK) and outputs a count value. According to the output count value, it is determined that one of the selection signal groups (Addr_SELB<X:1>) is in a valid state, so as to refresh multiple weak address signals (Out Address) in sequence.

It should be noted that, as shown in FIG. 12 , the embodiment of the present disclosure is still described by taking X=3 and Y=1 as an example. The third logic unit 402 includes a first NAND gate 4020, a second NAND gate 4021 and a third NAND gate 4022. The first input terminal of the first NAND gate 4020 is connected to the inverting output terminal of the first-stage flip-flop 4010, the second input terminal of the first NAND gate 4020 is connected to the inverting output terminal of the second-stage flip-flop 4011, and the output terminal of the first NAND gate 4020 outputs the first-bit selection sub-signal (Addr_SELB<1>); the second input terminal of the second NAND gate 4021 is connected to the inverting output terminal of the second-stage flip-flop 4011. The first input terminal of the third NAND gate 4022 is connected to the inverting output terminal of the first-stage flip-flop 4010, the second input terminal of the second NAND gate 4021 is connected to the inverting output terminal of the second-stage flip-flop 4011, and the output terminal of the second NAND gate 4021 outputs the second-bit selection sub-signal (Addr_SELB<2>); the first input terminal of the third NAND gate 4022 is connected to the inverting output terminal of the first-stage flip-flop 4010, the second input terminal of the third NAND gate 4022 is connected to the positive phase output terminal of the second-stage flip-flop 4011 The output ends are connected, and the output end of the third NAND gate 4022 outputs the 3rd bit selection sub-signal (Addr_SELB<3>).

It should also be noted that the third logic unit 402 is composed of three NAND gates, indicating that the valid state of the selection signal group (Addr_SELB<3:1>) is low level valid. Specifically, when the output of the pulse counting unit 401 is 00, the first NAND gate 4020 outputs the first bit selection signal (Addr_SELB<1>); when the output of the pulse counting unit 401 is 01, the second NAND gate 4021 outputs the second bit selection signal (Addr_SELB<2>); when the output of the pulse counting unit 401 is 10, the third NAND gate 4022 outputs the third bit selection signal (Addr_SELB<3>). In this way, different selection signals are used to determine which of the multiple weak address signals (Out Address) is output, so that the multiple weak address signals (Out Address) are refreshed in sequence.

Similarly, the fourth logic unit 403 uses an AND gate to achieve the reset of the pulse counting unit 401. That is, when the output of the pulse counting unit 401 is 11, the pulse counting unit 401 starts to reset and restarts the next round of counting.

In some embodiments, the selection signal group (Addr_SELB<X:1>) includes X-bit selection sub-signals, and the third logic unit 402 includes X NAND gates, where:

Each NAND gate has m input terminals for receiving m target count signals or their inverted signals, and the output terminals of the X NAND gates correspond one-to-one to the X-bit selector signals; wherein the target count signals are the m count signals in the count signal group (Addr_MUX_CNT<Y:1>), and any two NAND gates do not have exactly the same inputs; wherein X is a positive integer, and m is an integer greater than or equal to 2.

It should be noted that the number of NAND gates in the third logic unit 402 corresponds to the number of selection sub-signals. The input end of each NAND gate can be a completely different signal or a partially different signal. The output end of each NAND gate outputs a selection sub-signal to determine which weak address signal is to be refreshed. In this way, the control sub-unit 401 realizes the sequential refresh of the weak address signal (Out Address) through the counting signal group (Addr_MUX_CNT<Y:1>) and the selection signal group (Addr_SELB<X:1>).

In some embodiments, referring to FIG. 13 , the number of weak address signals (Out Address) output based on each refresh command (REF AB CMD) is X;

The selection subunit 41 includes X+1 cascaded selectors:

The first input terminal of the first stage selector 410 receives the X-th weak address signal (Out Address X), the second input terminal of the first stage selector 410 receives the ground signal (VSS), and the control terminal of the first stage selector 410 receives the X-th selection sub-signal (Addr_SELB<X>);

The first input end of the j-th level selector receives the X+1-j-th weak address signal (Out Address), the second input end of the j-th level selector is connected to the output end of the j-1-th level selector, and the control end of the j-th level selector receives the X+1-j-th selection sub-signal (Addr_SELB<X+1-j>); wherein j is an integer greater than or equal to 2 and less than or equal to X;

The first input end of the X+1th level selector receives the row address signal (Normal REF Addr), the second input end of the X+1th level selector is connected to the output end of the Xth level selector, the control end of the X+1th level selector receives the refresh address selection signal (Addr Exchange Flag), and the output end of the X+1th level selector outputs the address signal to be refreshed (Refresh Address).

It should be noted that, as shown in FIG14 , X=3 is still taken as an example. The first input terminal of the first-level selector 410 receives the third weak address signal (Out Address 3), the second input terminal of the first-level selector 410 receives the ground signal (VSS), and the control terminal of the first-level selector 410 receives the third-bit selection sub-signal (Addr_SELB<3>); the first input terminal of the second-level selector 411 receives the second weak address signal (Out Address 2), the second input terminal of the second-level selector 411 is connected to the output terminal of the first-level selector 410, and the control terminal of the second-level selector 411 receives the second-bit selection sub-signal (Addr_SELB<2>); the first input terminal of the third-level selector 412 receives the first weak address signal (Out Address 1), the second input terminal of the third-level selector 412 is connected to the output terminal of the second-level selector 411, and the control terminal of the third-level selector 412 receives the 1st-bit selection sub-signal (Addr_SELB<1>); the first input terminal of the fourth-level selector 413 receives the row address signal (Normal REF Addr), the second input terminal of the fourth-level selector 413 is connected to the output terminal of the third-level selector 412, the control terminal of the fourth-level selector 413 receives the refresh address selection signal (Addr Exchange Flag), and the output terminal of the fourth-level selector 413 outputs the address signal to be refreshed (Refresh Address).

In this way, the selection subunit 41 outputs the weak address signal (Out Address) or the row address signal (Normal REF Addr) as the address signal to be refreshed (Refresh Address) based on the refresh address selection signal (Addr Exchange Flag) and the selection signal group (Addr_SELB<3:1>). If the refresh address selection signal (Addr Exchange Flag) is at the first level (0), the 4th level selector 413 of the selection subunit 41 outputs the row address signal (Normal REF Addr) as the address signal to be refreshed (Refresh Address); if the refresh address selection signal (Addr Exchange Flag) is at the second level (1), the 4th level selector 413 of the selection subunit 41 outputs the weak address signal (Out Address) as the address signal to be refreshed (Refresh Address). When the refresh address selection signal (Addr Exchange Flag) is at the second level and the first-bit selection sub-signal (Addr_SELB<1>) is at a low level, the third-level selector 412 of the selection sub-unit 41 will output the first weak address signal (Out Address 1) as the address signal to be refreshed (Refresh Address); when the refresh address selection signal (Addr Exchange Flag) is at the second level and the second-bit selection sub-signal (Addr_SELB<2>) is at a low level, the second-level selector 411 of the selection sub-unit 41 will output the second weak address signal (Out Address 2) as the address signal to be refreshed (Refresh Address); when the refresh address selection signal (Addr Exchange Flag) is at the second level and the third-bit selection sub-signal (Addr_SELB<3>) is at a low level, the first-level selector 410 of the selection sub-unit 41 will output the third weak address signal (Out Address 3) as the address signal to be refreshed (Refresh Address). In this way, the selection subunit 41 composed of the cascaded selectors has a unique path to output an address signal as a refresh address signal (Refresh Address) each time, so as to realize the sequential refresh of the storage rows indicated by the address signal. At the same time, by changing the circuit design, the weak address The refresh frequency of the signal (Out Address) can improve the data integrity of the memory.

In some embodiments, as shown in FIG. 15 , the refresh circuit 10 further includes an ECS module 105 and a threshold module 106 , wherein:

The ECS module 105 is configured to output a current ECS operation row address signal (Row Address) and a second count value (EpRC); wherein the second count value (EpRC) refers to the number of error bits of the storage row corresponding to the current ECS operation row address signal (Row Address);

The threshold module 106 is configured to receive the second count value (EpRC), and output a valid storage flag signal (Bigger_Flag) when the second count value (EpRC) is greater than a third threshold; and output an invalid storage flag signal (Bigger_Flag) when the second count value (EpRC) is less than or equal to the third threshold;

The weak address generator 103 is also configured to receive a storage flag signal (Bigger_Flag) and a current ECS operation row address signal (Row Address), and when the storage flag signal (Bigger_Flag) is valid, store the current ECS operation row address signal (Row Address) as a weak address signal (Out Address).

It should be noted that the ECS module 105 can be applied to related circuits that perform ECS functions in DRAM DDR5 chips. Its function is to detect weak storage rows in DRAM and store the address signals of the detected weak storage rows to obtain weak address signals (Out Address).

It should be noted that, taking the third threshold value of 6 as an example, if the error bit of the current operation row address signal (Row Address) is less than or equal to 6, the second count value (EpRC) will be masked by the memory, and the threshold module 106 outputs an invalid storage flag signal (Bigger_Flag), indicating that the current operation row address signal (Row Address) is not a weak address signal (Out Address), and the weak address generator 103 will not store the current ECS operation row address signal (Row Address); if the error bit of the current ECS operation row address signal (Row Address) is greater than 6, the threshold module 106 outputs a valid storage flag signal (Bigger_Flag), indicating that the current ECS operation row address signal (Row Address) is a weak address signal (Out Address), and the weak address generator 103 will store the current ECS operation row address signal (Row Address), and so on. As long as the error bit of the current ECS operation row address signal (Row Address) is greater than 6, the ECS module 105 and the threshold module 106 will continue to output the same row address and a valid storage flag signal (Bigger_Flag) until the row is changed. Therefore, the weak address generator 103 only needs to save the same row address once.

In some embodiments, please refer to Figure 15, the threshold module 106 is also configured to receive a threshold setting signal (TM/Fuse Thresholding Setting) and determine a third threshold based on the threshold setting signal (TM/Fuse Thresholding Setting).

It should be noted that the specific specifications of the memory are different, the threshold setting signal (TM/Fuse Thresholding Setting) is different, and the corresponding third threshold is also different. In practical applications, the threshold can be set according to the specific type of memory to reduce the error rate of the memory and improve the performance of the memory.

In another embodiment of the present disclosure, referring to FIG16, a schematic flow chart of a refresh method provided by an embodiment of the present disclosure is shown. As shown in FIG16, the method includes:

S501: Every time the memory receives a refresh command, the first count value is incremented by one.

S502: When the first count value is less than the first threshold, a refresh operation is performed on the next storage row according to a refresh sequence in the automatic refresh mode.

S503: When the first count value is greater than or equal to the first threshold and less than the second threshold, refresh the weak storage rows in sequence; wherein the weak storage row refers to a storage row whose error bit is greater than the third threshold in the ECS mode, and the second threshold is greater than the first threshold.

It should be noted that the refresh method provided in the embodiment of the present disclosure is applied to the refresh circuit provided in the aforementioned embodiment. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding.

In some embodiments, the method further comprises:

When the first count value is equal to the second threshold value, the first count value is reset.

It should be noted that when the first count value is less than the first threshold value, the refresh address selection signal generated by the refresh command counting module is at the first level, and the memory performs a refresh operation on all row address signals; when the first count value is equal to the first threshold value, the refresh command counting module generates a refresh address selection signal at the second level, indicating that it is time to start refreshing multiple weak address signals in the memory; when the first count value reaches the second threshold value from the first threshold value, it means that the memory has refreshed multiple weak address signals. At this time, the first count value will be reset, indicating that the refresh command counting module will start the next round of counting. In this way, the number of refreshes for weak address signals can be increased in normal refresh operations.

In another embodiment of the present disclosure, referring to Fig. 17, it shows a schematic diagram of the composition structure of a memory 60 provided by the embodiment of the present disclosure. As shown in Fig. 17, the memory 60 may include the refresh circuit 10 described in any one of the above embodiments.

In some embodiments, the memory 60 may include DRAM.

It should be noted that the embodiment of the present disclosure improves the refresh frequency of weak cells in DDR5, counts external refresh commands through a refresh command counting module, and takes out a specific number of refresh command signals as refresh address selection signals; before the refresh command signal is less than a specific number (the refresh address selection signal is at the first level), the refresh command counting module will refresh the row address signals output sequentially by the refresh address generator; when the refresh command signal is equal to or exceeds a specific number (the refresh address selection signal is at the second level), the refresh command counting module will refresh multiple weak address signals output sequentially by the weak address generator. In this way, by controlling the level state of the refresh address selection signal, the refresh of the weak address signal can be inserted into the normal refresh operation, and the refresh frequency of the weak address signal can be increased, thereby ensuring the data integrity of the memory.

In the embodiments of the present disclosure, for DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

In the embodiment of the present disclosure, the memory 60 includes the refresh circuit 10 described in the above embodiment, so that the refresh frequency of the weak storage row can be increased, thereby improving the performance of the memory.

The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure.

It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (21)

A refresh circuit is applied to a memory, the refresh circuit (10) comprising: A refresh command counting module (101) is configured to count refresh commands to generate a first count value; if the first count value is less than a first threshold, output a refresh address selection signal at a first level; if the first count value is greater than or equal to the first threshold, output the refresh address selection signal at a second level; A refresh address generator (102) configured to output a row address signal and update the row address signal based on a refresh operation; A weak address generator (103) is connected to the refresh command counting module (101), and is configured to receive the refresh address selection signal, and when the refresh address selection signal is at a second level, output a plurality of weak address signals based on each refresh command; wherein the weak address signal is row address information recorded in performing an error check and clear (ECS) operation; A refresh module (104) is connected to the refresh command counting module (101), the refresh address generator (102) and the weak address generator (103), and is configured to, when the received refresh address selection signal is at a first level, sequentially perform a refresh operation on the storage rows corresponding to the row address signal in response to the received refresh command signal; or, when the received refresh address selection signal is at a second level, sequentially perform a refresh operation on the storage rows corresponding to the plurality of weak address signals in response to the received refresh command signal. The refresh circuit according to claim 1, wherein the refresh command counting module (101) is specifically configured to receive the refresh command signal; and to increase the first count value by one each time the refresh command signal is received; When the first count value reaches a second threshold, the first count value is reset; wherein the second threshold is greater than the first threshold. The refresh circuit according to claim 2, wherein the refresh module (104) is further configured to output a refresh clock signal; wherein the refresh clock signal generates a refresh pulse during each refresh operation; The refresh address generator (102) is further configured to receive the refresh clock signal; and to sequentially update and output the row address signal according to each refresh pulse on the refresh clock signal. The refresh circuit according to claim 3, wherein the refresh address generator (102) is further configured to receive the refresh address selection signal, and when the refresh address selection signal is at a first level, sequentially update and output the row address signal according to each refresh pulse on the refresh clock signal, and when the refresh address selection signal is at a second level, shield the refresh clock signal. The refresh circuit according to any one of claims 2 to 4, wherein the first count value includes an M-bit sub-signal, and the first threshold is 2 ^(N-1) ; The refresh command counting module (101) comprises M triggers cascaded in sequence, the input end of each stage of the trigger is connected to its own inverting output end, the positive phase output end of the i-th stage of the trigger is used to output the i-th bit sub-signal of the first count value, the clock end of the first stage of the trigger is used to receive the refresh command signal, and the clock end of the i+1-th stage of the trigger is connected to the inverting output end of the i-th stage of the trigger; Among them, the Nth bit sub-signal output of the first count value is the refresh address selection signal, M is an integer greater than 1, i is an integer greater than or equal to 1 and less than M, and N is an integer greater than 1 and less than or equal to M. The refresh circuit according to claim 5, wherein the second threshold is 2 ^(L-1) +2 ^(N-1) , and L is a positive integer less than or equal to N; The refresh command counting module (101) further comprises a first AND gate (22), wherein a first input end of the first AND gate (22) is connected to a positive phase output end of the Nth trigger, a second input end of the first AND gate (22) is connected to a positive phase output end of the Lth trigger, and an output end of the first AND gate (22) is connected to a reset end of all the triggers. The refresh circuit according to any one of claims 1 to 6, wherein the weak address generator (103) comprises a first logic unit (30) and a first-in first-out register (31), and the first-in first-out register (31) stores a plurality of the weak address signals, wherein: The first logic unit (30) is configured to receive the refresh command signal and the refresh address selection signal, perform logic processing on the refresh command signal and the refresh address selection signal, and output a weak address clock signal; wherein, when the refresh address selection signal is at the second level, each time a refresh command signal is received, a pulse is generated on the weak address clock signal; The first-in first-out register (31) is configured to receive the weak address clock signal and output a plurality of the weak address signals according to each pulse of the weak address clock signal. The refresh circuit according to claim 7, wherein the weak address signal refers to a storage row whose error bit is greater than a third threshold in the ECS mode; The weak address generator (103) is further configured to receive a current ECS operation row address signal and a corresponding storage flag signal, and when the storage flag signal is valid, store the current ECS operation row address signal as the weak address signal; wherein the storage flag signal indicates whether an error bit of a storage row corresponding to the current ECS operation row address signal is greater than a third threshold. The refresh circuit according to claim 8, wherein the weak address generator (103) further comprises a latch (32), an address comparator (33) and a second logic unit (34), wherein: The latch (32) is configured to latch the weak address signal stored last time; The address comparator (33) is configured to receive the current ECS operation row address signal and the weak address signal stored last time; when the current ECS operation row address signal and the weak address signal stored last time are different, output a valid update flag signal; The second logic unit (34) is configured to receive the storage flag signal and the update flag signal; when both the storage flag signal and the update flag signal are valid, output a valid load clock signal; The latch (32) is further configured to receive the loading clock signal and the current ECS operation row address signal; when the loading clock signal is valid, latch the current ECS operation row address signal as the weak address signal to be stored; The first-in first-out register (31) is further configured to receive the loading clock signal delayed by a first preset time and the weak address signal to be stored, and store the weak address signal to be stored based on the loading clock signal. The refresh circuit according to claim 9, wherein the second logic unit (34) comprises a second AND gate (340) and a pulse generator (341), wherein: The first input end of the second AND gate (340) receives the storage flag signal, the second input end of the second AND gate (340) receives the update flag signal, the output end of the second AND gate (340) is connected to the input end of the pulse generator (341), and the output end of the pulse generator (341) is used to output the load clock signal. The refresh circuit according to claim 10, wherein the pulse generator (341) comprises a first NOT gate (3410), a delay unit (3411) and a third AND gate (3412), wherein: The input end of the first NOT gate (3410) is connected to the output end of the second AND gate (340), the output end of the first NOT gate (3410) is connected to the input end of the delay unit (3411), the output end of the delay unit (3411) is connected to the second input end of the third AND gate (3412), the first input end of the third AND gate (3412) is connected to the output end of the second AND gate (340), and the output end of the third AND gate (3412) is used to output the loading clock signal. The refresh circuit according to claim 3 or 4, wherein the refresh module (104) comprises a control subunit (40), a selection subunit (41) and a refresh subunit (42), wherein: The control subunit (40) is configured to receive the refresh address selection signal; when the refresh address selection signal is at a second level, generate and output a selection signal group based on the refresh clock signal; The selection subunit (41) is configured to receive the selection signal group, the refresh address selection signal, the row address signal and a plurality of the weak address signals; when the refresh address selection signal is at a first level, the row address signal is output as the address signal to be refreshed; when the refresh address selection signal is at a second level, the plurality of the weak address signals are sequentially output as the address signal to be refreshed based on the selection signal group; The refresh subunit (42) is configured to receive the refresh command signal and the address signal to be refreshed, and in response to the refresh command signal, sequentially perform a refresh operation on the storage rows indicated by the address signal to be refreshed. The refresh circuit according to claim 12, wherein the control subunit (40) comprises a fourth AND gate (400), a pulse counting unit (401), a third logic unit (402) and a fourth logic unit (403), wherein: The input end of the fourth AND gate (400) receives the refresh address selection signal and the refresh clock signal; the output end of the fourth AND gate (400) is connected to the input end of the pulse counting unit (401), and the output end of the pulse counting unit (401) outputs a counting signal group; The input end of the third logic unit (402) performs a first decoding process on the counting signal group to output the selection signal group; The input end of the fourth logic unit (403) performs a second decoding process on the counting signal group to output a reset signal for the pulse counting unit (401). The refresh circuit according to claim 13, wherein the selection signal group includes X-bit selection sub-signals, and the third logic unit (402) includes X NAND gates, wherein: Each of the NAND gates has m input terminals for receiving m target counting signals or inverted signals thereof, and the output terminals of the X NAND gates correspond one-to-one to the X-bit selection sub-signals; wherein the target counting signals are the m counting signals in the counting signal group, and any two of the NAND gates do not have exactly the same inputs; Wherein, X is a positive integer, and m is an integer greater than or equal to 2. The refresh circuit according to claim 14, wherein the number of the weak address signals output based on each of the refresh commands is X; The selection subunit (41) comprises X+1 cascaded selectors: The first input terminal of the first-stage selector receives the X-th weak address signal, the second input terminal of the first-stage selector receives the ground signal, and the control terminal of the first-stage selector receives the X-th selection sub-signal; The first input end of the j-th selector receives the X+1-j-th weak address signal, the second input end of the j-th selector is connected to the output end of the j-1-th selector, and the control end of the j-th selector receives the X+1-j-th selection sub-signal; wherein j is an integer greater than or equal to 2 and less than or equal to X; The first input end of the selector of the X+1th level receives the row address signal, the second input end of the selector of the X+1th level is connected to the output end of the selector of the Xth level, the control end of the selector of the X+1th level receives the refresh address selection signal, and the output end of the selector of the X+1th level outputs the address signal to be refreshed. The refresh circuit according to claim 15, wherein, in the case of X=3, the pulse counting unit (401) includes a first-stage trigger (4010) and a second-stage trigger (4011), the third logic unit (402) includes a first NAND gate (4020), a second NAND gate (4021) and a third NAND gate (4022), the selection subunit (41) includes a first-stage selector (410), a second-stage selector (411), a third-stage selector (412) and a fourth-stage selector (413), wherein: The clock end of the first-stage trigger (4010) is connected to the output end of the fourth AND gate (400), the input end of the first-stage trigger (4010) is connected to its own inverting output end, and the positive-phase output end of the first-stage trigger (4010) is used to output the first-bit sub-signal of the counting signal group; the clock end of the second-stage trigger (4011) is connected to the inverting output end of the first-stage trigger (4010); the input end of the second-stage trigger (4011) is connected to its own inverting output end, and the positive-phase output end of the second-stage trigger (4011) is used to output the second-bit sub-signal of the counting signal group; The first input end of the first NAND gate (4020) is connected to the inverting output end of the first-stage trigger (4010), the second input end of the first NAND gate (4020) is connected to the inverting output end of the second-stage trigger (4011), and the output end of the first NAND gate (4020) outputs the first-bit selection sub-signal; the first input end of the second NAND gate (4021) is connected to the non-inverting output end of the first-stage trigger (4010), the second input end of the second NAND gate (4021) is connected to the non-inverting output end of the first-stage trigger (4010), The second input end is connected to the inverting output end of the second-stage trigger (4011), and the output end of the second NAND gate (4021) outputs the second-bit selection sub-signal; the first input end of the third NAND gate (4022) is connected to the inverting output end of the first-stage trigger (4010), the second input end of the third NAND gate (4022) is connected to the non-inverting output end of the second-stage trigger (4011), and the output end of the third NAND gate (4022) outputs the third-bit selection sub-signal; The first input end of the first-stage selector (410) receives the third weak address signal, the second input end of the first-stage selector (410) receives the ground signal, and the control end of the first-stage selector (410) receives the third selection sub-signal; the first input end of the second-stage selector (411) receives the second weak address signal, the second input end of the second-stage selector (411) is connected to the output end of the first-stage selector (410), and the control end of the second-stage selector (411) receives the second selection sub-signal; the first input end of the third-stage selector (412) receives the second weak address signal. The first weak address signal is received, the second input end of the third-level selector (412) is connected to the output end of the second-level selector (411), and the control end of the third-level selector (412) receives the first selection sub-signal; the first input end of the fourth-level selector (413) receives the row address signal, the second input end of the fourth-level selector (413) is connected to the output end of the third-level selector (412), the control end of the fourth-level selector (413) receives the refresh address selection signal, and the output end of the fourth-level selector (413) outputs the address signal to be refreshed. The refresh circuit according to any one of claims 8 to 11, the refresh circuit (10) further comprising an ECS module (105) and a threshold module (106), wherein: The ECS module (105) is configured to output the current ECS operation row address signal and a second count value; wherein the second count value refers to the number of error bits of the storage row corresponding to the current ECS operation row address signal; The threshold module (106) is configured to receive the second count value, and output a valid storage flag signal when the second count value is greater than the third threshold value; and output an invalid storage flag signal when the second count value is less than or equal to the third threshold value; The weak address generator (103) is further configured to receive the storage flag signal and the current ECS operation row address signal, and when the storage flag signal is valid, store the current ECS operation row address signal as the weak address signal. According to the refresh circuit of claim 17, the threshold module is further configured to receive a threshold setting signal, and determine the third threshold based on the threshold setting signal. A refresh method, applied to a memory, comprising: Each time the memory receives a refresh command, the first count value is incremented by one; When the first count value is less than a first threshold, performing a refresh operation on the next storage row according to a refresh sequence in an automatic refresh mode; When the first count value is greater than or equal to a first threshold and less than a second threshold, refresh operations are performed on weak storage rows in sequence; wherein the weak storage row refers to a storage row whose error bit is greater than a third threshold in the ECS mode, and the second threshold is greater than the first threshold. The method according to claim 19, wherein the method further comprises: when the first count value is equal to the second threshold value, resetting the first count value. A memory comprising the refresh circuit (10) according to any one of claims 1 to 18.