WO2024087750A1

WO2024087750A1 - Sidelink wake-up signalling transmission

Info

Publication number: WO2024087750A1
Application number: PCT/CN2023/107975
Authority: WO
Inventors: Zhennian SUN; Haipeng Lei; Xiaodong Yu; Xin Guo
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2023-07-18
Filing date: 2023-07-18
Publication date: 2024-05-02
Anticipated expiration: 2026-01-18

Abstract

Various aspects of the present disclosure relate to user equipment, methods and apparatuses for a sidelink (SL) wake-up signalling (WUS) transmission. In an aspect, a first user equipment may include a processor; and a transceiver coupled to the processor, wherein the processor is configured to receive, via the transceiver and from a second UE, a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and monitor, via the transceiver, an SL transmission from the second UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the first UE. By implementing the embodiments of the present disclosure, the power consumption of a receiver UE can be reduced.

Description

SIDELINK WAKE-UP SIGNALLING TRANSMISSION

TECHNICAL FIELD

The present disclosure relates to wireless communications, and more specifically to user equipment, methods and apparatuses for a sidelink (SL) wake-up signalling (WUS) transmission.

BACKGROUND

A wireless communications system may include one or multiple network communication devices, such as base stations, which may be otherwise known as an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. Each network communication devices, such as a base station may support wireless communications for one or multiple user communication devices, which may be otherwise known as user equipment (UE) , or other suitable terminology. The wireless communications system may support wireless communications with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) . Additionally, the wireless communications system may support wireless communications across various radio access technologies including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) radio access technology, among other suitable radio access technologies beyond 5G (e.g., sixth generation (6G) ) .

In release-17, an SL enhancement (SL discontinuous reception (DRX) ) has been introduced for power saving of an SL user equipment (UE) . During ON duration of a DRX cycle, the UE shall monitor an SL control information (SCI) including a first stage SCI and a second stage to detect whether there are SL transmissions for this UE. For further power saving, a WUS is introduced. The detection of a WUS could active the reception status of one receiver (RX) UE to monitor the ON duration of one DRX cycle. If the UE doesn’t detect the WUS, it could still sleep to save the power.

SUMMARY

The present disclosure relates to user equipment, methods and apparatuses that support an SL wake-up signalling transmission. In a first aspect of the solution, a first UE may include a processor; and a transceiver coupled to the processor, wherein the processor is configured to receive, via the transceiver and from a second UE, an SL WUS indicative of one or more resource pools; and monitor, via the transceiver, an SL transmission from the second UE on the one or more resource pools during an on duration of a DRX cycle of the first UE. By performing receiving the SL WUS indicative of the one or more resource pools, and monitoring the SL transmission from the second UE on the one or more resource pools during the on duration of the DRX cycle of the first UE, the power consumption of the first UE can be reduced.

In some implementations of the method and apparatuses described herein, the one or more resource pools may be indicated among one of the following: at least one resource pool configured for SL transmissions; at least one resource pool including at least one resource within the on duration; at least one resource pool including at least one resource within a remaining portion of the on duration, wherein the remaining portion is associated with an SL WUS occasion for receiving the SL WUS; or at least one resource pool including at least one resource within a portion of the on duration between two SL WUS occasions for receiving the SL WUS.

In some implementations of the method and apparatuses described herein, the one or more resource pools may be indicated via one of the following: a bitmap, wherein a bit of the bitmap corresponds to a resource pool among the one or more resource pools; one or more resource pool indexes of the one or more resource pools; a start and length indicator value (SLIV) corresponding to the one or more resource pools in the case that the one or more resource pools are contiguous in frequency domain; or an indication of whether SL hybrid automatic repeat request (HARQ) feedback is enabled or disabled for the SL transmission.

In some implementations of the method and apparatuses described herein, the first UE may: in the case that the indication in the SL WUS indicates that the SL HARQ feedback is enabled for the SL transmission, determine the one or more resource pools as one or more resource pools configured with at least one physical sidelink feedback channel (PSFCH) resource within the on duration.

In some implementations of the method and apparatuses described herein, the first UE may: in the case that the indication in the SL WUS indicates that the SL HARQ feedback is disabled for the SL transmission, determine the one or more resource pools as one or more resource pools including at least one resource within the on duration.

In some implementations of the method and apparatuses described herein, the SL WUS may be received via one of the following: a sequence, sidelink control information (SCI) , at least one PSFCH resource; or at least one resource in a dedicated resource pool configured for receiving SL WUS.

In some implementations of the method and apparatuses described herein, a seed of the sequence may be generated based on one of the following: one or more resource pool indexes of the one or more resource pools; or whether SL HARQ feedback is enabled or disabled for the SL transmission.

In some implementations of the method and apparatuses described herein, the SCI via which the SL WUS may be received is a first stage SCI or a second stage SCI.

In some implementations of the method and apparatuses described herein, the SL WUS may be received on at least one PSFCH resource, and a dedicated PSFCH resource may be associated with each of the one or more resource pools.

In some implementations of the method and apparatuses described herein, the SL WUS may be received on at least one PSFCH resource; and an SL HARQ acknowledgment (ACK) may indicate that the SL HARQ feedback is enabled; and an SL HARQ negative acknowledgment (NACK) may indicate that the SL HARQ feedback is disabled.

In a second aspect of the solution, a second UE described herein may include a processor; and a transceiver coupled to the processor, wherein the processor may be configured to determine one or more resource pools for a sidelink (SL) transmission to a first UE during an on duration of a discontinuous reception (DRX) cycle of the first UE; and transmit, via the transceiver and to the first UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.

In some implementations of the method and apparatuses described herein, the one or more resource pools may be indicated among one of the following: at least one resource pool configured for SL transmissions; at least one resource pool including at least one resource within the on duration; at least one resource pool including at least one resource within a remaining portion of the on duration, wherein the remaining portion is associated with an SL WUS occasion for transmitting the SL WUS; or at least one resource pool including at least one resource within a portion of the on duration between two SL WUS occasions for transmitting the SL WUS.

In some implementations of the method and apparatuses described herein, the second UE may: in the case that the indication in the SL WUS indicates the indication that the SL HARQ feedback is enabled for the SL transmission, select one or more resource pools configured with at least one physical sidelink feedback channel (PSFCH) resources within the on duration as the one or more resource pools.

In some implementations of the method and apparatuses described herein, the second UE may: in the case that the indication in the SL WUS indicates that the SL HARQ feedback is disabled for the SL transmission, select one or more resource pools including at least one resource within the on duration as the one or more resource pools.

In some implementations of the method and apparatuses described herein, the SL WUS may be transmitted via one of the following: a sequence; sidelink control information (SCI) ; at least one PSFCH resource; or at least one resource in a dedicated resource pool configured for transmitting SL WUS.

In some implementations of the method and apparatuses described herein, the SCI via which the SL WUS may be transmitted is a first stage SCI or a second stage SCI.

In some implementations of the method and apparatuses described herein, the SL WUS may be transmitted on at least one PSFCH resource, and a dedicated PSFCH resource may be associated with each of the one or more resource pools.

In some implementations of the method and apparatuses described herein, the SL WUS may be transmitted on at least one PSFCH resource, and an SL HARQ acknowledgment (ACK) may indicate that the SL HARQ feedback is enabled; and an SL HARQ negative acknowledgment (NACK) may indicate that the SL HARQ feedback is disabled.

In a third aspect of the solution, a processor for wireless communication may comprise: at least one memory; and a controller coupled with the at least one memory and configured to cause the controller to: receive, from a user equipment (UE) , a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and monitor an SL transmission from the UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the UE.

In a fourth aspect of the solution, a processor for wireless communication may comprise: at least one memory; and a controller coupled with the at least one memory and configured to cause the controller to: determine one or more resource pools for a sidelink (SL) transmission to a user equipment (UE) during an on duration of a discontinuous reception (DRX) cycle of the UE; and transmit, to the UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.

In a fifth aspect of the solution, a method performed by a first UE described herein may include receiving, from a second UE, an SL WUS indicative of one or more resource pools; and monitoring an SL transmission from the second UE on the one or more resource pools during an on duration of a DRX cycle of the first UE.

In a sixth aspect of the solution, a method performed by a second UE described herein may include determining one or more resource pools for an SL transmission to a first UE during an on duration of a DRX cycle of the first UE; and transmitting, to the first UE, an SL WUS indicative of the one or more resource pools.

It is to be understood that the summary section is not intended to identify key or essential features of embodiments of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure. Other features of the present disclosure will become easily comprehensible through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a wireless communications system that supports an SL WUS transmission in accordance with aspects of the present disclosure.

FIG. 2 illustrates an example signalling procedure for an SL WUS transmission in accordance with aspects of the present disclosure.

FIG. 3 illustrates an example SL DRX configuration in accordance with aspects of the present disclosure.

FIG. 4 illustrates an example indication of one or more resource pools in accordance with aspects of the present disclosure.

FIG. 5 illustrates another an example indication of one or more resource pools in accordance with aspects of the present disclosure.

FIGS. 6 and 7 illustrate examples of devices that support an SL WUS transmission in accordance with aspects of the present disclosure.

FIGS. 8 and 9 illustrate examples of processors that support an SL WUS transmission in accordance with aspects of the present disclosure.

FIGS. 10 and 11 illustrate flowcharts of methods that support an SL WUS transmission in accordance with aspects of the present disclosure.

DETAILED DESCRIPTION

Principles of the present disclosure will now be described with reference to some embodiments. It is to be understood that these embodiments are described only for the purpose of illustration and help those skilled in the art to understand and implement the present disclosure, without suggesting any limitation as to the scope of the disclosure. The disclosure described herein may be implemented in various manners other than the ones described below.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

References in the present disclosure to “one embodiment, ” “an example embodiment, ” “an embodiment, ” “some embodiments, ” and the like indicate that the embodiment (s) described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment (s) . Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It shall be understood that although the terms “first” and “second” or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could also be termed as a second element, and similarly, a second element could also be termed as a first element, without departing from the scope of embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a” , “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” , “comprising” , “has” , “having” , “includes” and/or “including” , when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/or combinations thereof.

As used herein, the term “communication network” refers to a network following any suitable communication standards, such as, 5G NR, long term evolution (LTE) , LTE-advanced (LTE-A) , wideband code division multiple access (WCDMA) , high-speed packet access (HSPA) , narrow band internet of things (NB-IoT) , and so on. Further, the communications between a terminal device and a network device in the communication network may be performed according to any suitable generation communication protocols, including but not limited to, the first generation (1G) , the second generation (2G) , 2.5G, 2.75G, the third generation (3G) , the fourth generation (4G) , 4.5G, the fifth generation (5G) communication protocols, and/or any other protocols either currently known or to be developed in the future. Embodiments of the present disclosure may be applied in various communication systems. Given the rapid development in communications, there will also be future type communication technologies and systems in which the present disclosure may be embodied. It should not be seen as limiting the scope of the present disclosure to only the aforementioned systems.

As used herein, the term “network device” generally refers to a node in a communication network via which a terminal device can access the communication network and receive services therefrom. The network device may refer to a base station (BS) or an access point (AP) , for example, a node B (NodeB or NB) , a radio access network (RAN) node, an evolved NodeB (eNodeB or eNB) , a NR NB (also referred to as a gNB) , a remote radio unit (RRU) , a radio header (RH) , an infrastructure device for a V2X (vehicle-to-everything) communication, a transmission and reception point (TRP) , a reception point (RP) , a remote radio head (RRH) , a relay, an integrated access and backhaul (IAB) node, a low power node such as a femto BS, a pico BS, and so forth, depending on the applied terminology and technology.

As used herein, the term “terminal device” generally refers to any end device that may be capable of wireless communications. By way of example rather than a limitation, a terminal device may also be referred to as a communication device, a user equipment (UE) , an end user device, a subscriber station (SS) , an unmanned aerial vehicle (UAV) , a portable subscriber station, a mobile station (MS) , or an access terminal (AT) . The terminal device may include, but is not limited to, a mobile phone, a cellular phone, a smart phone, a voice over IP (VoIP) phone, a wireless local loop phone, a tablet, a wearable terminal device, a personal digital assistant (PDA) , a portable computer, a desktop computer, an image capture terminal device such as a digital camera, a gaming terminal device, a music storage and playback appliance, a vehicle-mounted wireless terminal device, a wireless endpoint, a mobile station, laptop-embedded equipment (LEE) , laptop-mounted equipment (LME) , a USB dongle, a smart device, wireless customer-premises equipment (CPE) , an internet of things (loT) device, a watch or other wearable, a head-mounted display (HMD) , a vehicle, a drone, a medical device (for example, a remote surgery device) , an industrial device (for example, a robot and/or other wireless devices operating in an industrial and/or an automated processing chain contexts) , a consumer electronics device, a device operating on commercial and/or industrial wireless networks, and the like. In the following description, the terms: “terminal device, ” “communication device, ” “terminal, ” “user equipment” and “UE, ” may be used interchangeably.

As discussed above, considering the use cases of SL further power saving has been proposed by some entities, the main object of further power saving for SL is to introduce the WUS which could further reduce the power consumption. The detection of WUS could active the reception status of one RX UE to monitor the ON duration of one DRX cycle. If the UE doesn’t detect the WUS it could still sleep to save the power.

In SL transmission, multiple resource pools could be configured. The DRX cycle and ON duration are configured in millimeters which could contain multiple TDMed resource pools. If the RX UE could identify which resource pool (s) the transmitter (TX) UE would perform SL transmissions, the power consumption could be further reduced. Thus, it needs a solution to provide some alternatives on resource pools indication based SL WUS to further reduce the power consumption.

Therefore, the present disclosure proposed a solution to support resource pool (s) activation/deactivation via an SL WUS. In this solution, an SL WUS indicates the resource pool (s) to RX UE to active the reception on this (these) resource pool (s) within the DRX ON duration of this DRX cycle. By implementing the example embodiments of the present disclosure, the power consumption can be reduced.

Aspects of the present disclosure are described in the context of a wireless communications system.

FIG. 1 illustrates an example of a wireless communications system 100 that supports an SL WUS transmission in accordance with aspects of the present disclosure. The wireless communications system 100 may include one or more network entities 102 (also referred to as network equipment (NE) ) , one or more UEs 104, a core network 106, and a packet data network 108. The wireless communications system 100 may support various radio access technologies. In some implementations, the wireless communications system 100 may be a 4G network, such as an LTE network or an LTE-advanced (LTE-A) network. In some other implementations, the wireless communications system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communications system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology including institute of electrical and electronics engineers (IEEE) 802.11 (Wi-Fi) , IEEE 802.16 (WiMAX) , IEEE 802.20. The wireless communications system 100 may support radio access technologies beyond 5G. Additionally, the wireless communications system 100 may support technologies, such as time division multiple access (TDMA) , frequency division multiple access (FDMA) , or code division multiple access (CDMA) , etc.

The one or more network entities 102 may be dispersed throughout a geographic region to form the wireless communications system 100. One or more of the network entities 102 described herein may be or include or may be referred to as a network node, a base station, a network element, a radio access network (RAN) , a base transceiver station, an access point, a NodeB, an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. A network entity 102 and a UE 104 may communicate via a communication link 110, which may be a wireless or wired connection. For example, a network entity 102 and a UE 104 may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

A network entity 102 may provide a geographic coverage area 112 for which the network entity 102 may support services (e.g., voice, video, packet data, messaging, broadcast, etc. ) for one or more UEs 104 within the geographic coverage area 112. For example, a network entity 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc. ) according to one or multiple radio access technologies. In some implementations, a network entity 102 may be moveable, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies may overlap, but the different geographic coverage areas 112 may be associated with different network entities 102. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The one or more UEs 104 (such as UE 104-1 or UE 104-2) may be dispersed throughout a geographic region of the wireless communications system 100. A UE 104 may include or may be referred to as a mobile device, a wireless device, a remote device, a remote unit, a handheld device, or a subscriber device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an internet-of-things (IoT) device, an internet-of-everything (IoE) device, or machine-type communication (MTC) device, among other examples. In some implementations, a UE 104 may be stationary in the wireless communications system 100. In some other implementations, a UE 104 may be mobile in the wireless communications system 100.

The one or more UEs 104 may be devices in different forms or having different capabilities. Some examples of UEs 104 are illustrated in FIG. 1. A UE 104 may be capable of communicating with various types of devices, such as the network entities 102, other UEs 104, or network equipment (e.g., the core network 106, the packet data network 108, a relay device, an integrated access and backhaul (IAB) node, or another network equipment) , as shown in FIG. 1. Additionally, or alternatively, a UE 104 may support communication with other network entities 102 or UEs 104, which may act as relays in the wireless communications system 100.

A UE 104 may also be able to support wireless communication directly with other UEs 104 over a communication link 114. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link 114 may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

A network entity 102 may support communications with the core network 106, or with another network entity 102, or both. For example, a network entity 102 may interface with the core network 106 through one or more backhaul links 116 (e.g., via an S1, N2, N2, or another network interface) . The network entities 102 may communicate with each other over the backhaul links 116 (e.g., via an X2, Xn, or another network interface) . In some implementations, the network entities 102 may communicate with each other directly (e.g., between the network entities 102) . In some other implementations, the network entities 102 may communicate with each other or indirectly (e.g., via the core network 106) . In some implementations, one or more network entities 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC) . An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as a radio heads, smart radio heads, or transmission-reception points (TRPs) .

In some implementations, a network entity 102 may be configured in a disaggregated architecture, which may be configured to utilize a protocol stack physically or logically distributed among two or more network entities 102, such as an integrated access backhaul (IAB) network, an open radio access network (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance) , or a virtualized RAN (vRAN) (e.g., a cloud RAN (C-RAN) ) . For example, a network entity 102 may include one or more of a CU, a DU, a radio unit (RU) , a RAN intelligent controller (RIC) (e.g., a near-real time RIC (Near-RT RIC) , a non-real time RIC (Non-RT RIC) ) , a service management and orchestration (SMO) system, or any combination thereof.

An RU may also be referred to as a radio head, a smart radio head, a remote radio head (RRH) , a remote radio unit (RRU) , or a transmission reception point (TRP) . One or more components of the network entities 102 in a disaggregated RAN architecture may be co-located, or one or more components of the network entities 102 may be located in distributed locations (e.g., separate physical locations) . In some implementations, one or more network entities 102 of a disaggregated RAN architecture may be implemented as virtual units (e.g., a virtual CU (VCU) , a virtual DU (VDU) , a virtual RU (VRU) ) .

Split of functionality between a CU, a DU, and an RU may be flexible and may support different functionalities depending upon which functions (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combinations thereof) are performed at a CU, a DU, or an RU. For example, a functional split of a protocol stack may be employed between a CU and a DU such that the CU may support one or more layers of the protocol stack and the DU may support one or more different layers of the protocol stack. In some implementations, the CU may host upper protocol layer (e.g., a layer 3 (L3) , a layer 2 (L2) ) functionality and signaling (e.g., radio resource control (RRC) , service data adaption protocol (SDAP) , packet data convergence protocol (PDCP) ) . The CU may be connected to one or more DUs or RUs, and the one or more DUs or RUs may host lower protocol layers, such as a layer 1 (L1) (e.g., physical (PHY) layer) or an L2 (e.g., radio link control (RLC) layer, medium access control (MAC) layer) functionality and signaling, and may each be at least partially controlled by the CU 160.

Additionally, or alternatively, a functional split of the protocol stack may be employed between a DU and an RU such that the DU may support one or more layers of the protocol stack and the RU may support one or more different layers of the protocol stack. The DU may support one or multiple different cells (e.g., via one or more RUs) . In some implementations, a functional split between a CU and a DU, or between a DU and an RU may be within a protocol layer (e.g., some functions for a protocol layer may be performed by one of a CU, a DU, or an RU, while other functions of the protocol layer are performed by a different one of the CU, the DU, or the RU) .

A CU may be functionally split further into CU control plane (CU-CP) and CU user plane (CU-UP) functions. A CU may be connected to one or more DUs via a midhaul communication link (e.g., F1, F1-c, F1-u) , and a DU may be connected to one or more RUs via a fronthaul communication link (e.g., open fronthaul (FH) interface) . In some implementations, a midhaul communication link or a fronthaul communication link may be implemented in accordance with an interface (e.g., a channel) between layers of a protocol stack supported by respective network entities 102 that are in communication via such communication links.

The core network 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The core network 106 may be an evolved packet core (EPC) , or a 5G core (5GC) , which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME) , an access and mobility management functions (AMF) ) and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW) , a packet data network (PDN) gateway (P-GW) , or a user plane function (UPF) ) . In some implementations, the control plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc. ) for the one or more UEs 104 served by the one or more network entities 102 associated with the core network 106.

The core network 106 may communicate with the packet data network 108 over one or more backhaul links 116 (e.g., via an S1, N2, N2, or another network interface) . The packet data network 108 may include an application server 118. In some implementations, one or more UEs 104 may communicate with the application server 118. A UE 104 may establish a session (e.g., a protocol data unit (PDU) session, or the like) with the core network 106 via a network entity 102. The core network 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server 118 using the established session (e.g., the established PDU session) . The PDU session may be an example of a logical connection between the UE 104 and the core network 106 (e.g., one or more network functions of the core network 106) .

In the wireless communications system 100, the network entities 102 and the UEs 104 may use resources of the wireless communications system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) ) to perform various operations (e.g., wireless communications) . In some implementations, the network entities 102 and the UEs 104 may support different resource structures. For example, the network entities 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the network entities 102 and the UEs 104 may support a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the network entities 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures) . The network entities 102 and the UEs 104 may support various frame structures based on one or more numerologies.

One or more numerologies may be supported in the wireless communications system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., μ=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., μ=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., μ=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., μ=2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., μ=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., μ=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames) . Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, each frame may include multiple subframes. For example, each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

Additionally or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communications system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., μ=0, μ=1, μ=2, μ=3, μ=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot may include a number (e.g., quantity) of symbols (e.g., OFDM symbols) . In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing) , a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., μ=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz –7.125 GHz) , FR2 (24.25 GHz –52.6 GHz) , FR3 (7.125 GHz –24.25 GHz) , FR4 (52.6 GHz –114.25 GHz) , FR4a or FR4-1 (52.6 GHz –71 GHz) , and FR5 (114.25 GHz –300 GHz) . In some implementations, the network entities 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FR1 may be used by the network entities 102 and the UEs 104, among other equipment or devices for cellular communications traffic (e.g., control information, data) . In some implementations, FR2 may be used by the network entities 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies) . For example, FR1 may be associated with a first numerology (e.g., μ=0) , which includes 15 kHz subcarrier spacing; a second numerology (e.g., μ=1) , which includes 30 kHz subcarrier spacing; and a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies) . For example, FR2 may be associated with a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., μ=3) , which includes 120 kHz subcarrier spacing.

In Release-17 SL, the IE SL-DRX-ConfigGC-BC is used to configure DRX related parameters for NR sidelink groupcast and broadcast communication, unicast/broadcast based communication of direct link establishment request (TS 24.587 [57] ) , and discovery message (TS 24.554 [72] ) . The IE SL-DRX-ConfigUC is used to configure sidelink DRX related parameters for unicast communication. The IE SL-DRX-ConfigUC-SemiStatic is used to indicate the semi-static sidelink DRX related parameters for unicast communication.

FIG. 2 illustrates an example signalling procedure 200 for an SL WUS transmission in accordance with aspects of the present disclosure. At 206, the UE 104-2 (also referred to a second UE) determines one or more resource pools for an SL transmission to the UE 104-1 (also referred to a first UE) during an on duration of a DRX cycle of the UE 104-1.

The UE 104-2 transmits (210) an SL WUS 212 indicative of the one or more resource pools to the UE 104-1. The UE 104-1 receives (208) the SL WUS 212 from the UE 104-2. At 214, the UE 104-1 monitors an SL transmission from the UE 104-2 on the one or more resource pools during an on duration of a DRX cycle of UE 104-1.

The details of determining the one or more resource pools during the on duration of the DRX cycle of the UE 104-1 will be discussed with reference to FIGS. 3-5. By implementing the example embodiments of FIG. 2, the UE 104-1 (the RX UE) can save power consumption because the UE 104-1 will active the reception on the resource pools within the DRX ON duration of the DRX cycle as indicated by the SL WUS.

FIG. 3 illustrates an example SL DRX configuration 300 in accordance with aspects of the present disclosure. A configuration or pre configuration may provide an SL DRX configuration including DRX cycle, DRX ON duration and the timeline for a DRX. As shown in FIG. 3, three DRX cycles are shown in time axis. Take a DRX cycle 308 as an example, the DRX cycle 308 may include a DRX on duration 302.

An SL WUS (pre-) configuration may also configure a set of SL WUS occasions, the SL WUS occasions may be before the starting of a DRX ON duration (such as an SL WUS 310) or during DRX ON duration (such as an SL WUS 312 and SL WUS 314) . In a DRX on duration, one or more resource pools may be configured. For example, in the DRX on durations 304 or 306, there may be a resource pool #0, a resource pool #1, a resource pool #2 and a resource pool #3.

An SL WUS may be transmitted via a sequence, or sidelink control information (SCI) (any of a first stage SCI, a second stage SCI, a physical sidelink feedback channel (PSFCH) or in a dedicated resource pool) . A DRX on duration may be configured up to 1600ms. If the SL WUS actives the whole DRX on duration, the RX UE may need to perform SCI monitoring for data reception. If the TX UE only uses one or more resource pools within the DRX on duration, the RX UE may not need to perform SCI monitoring on the resource pools that the TX UE will not use. If the RX UE has knowledge on this information, it may further reduce the power consumption at the RX UE side.

FIG. 4 illustrates an example indication 400 of one or more resource pools in accordance with aspects of the present disclosure. As shown in FIG. 4, in some example embodiments, an SL WUS may carry information of resource pool (s) on which it may perform sidelink transmissions to the RX UE (such as UE 104-1) . The SL WUS may explicitly indicate one or more resource pools to the RX UE. The indicated resource pools mean that the TX UE may perform sidelink transmissions on the resources of these resource pools within the DRX on duration 410 in this DRX cycle.

In some example embodiments, the one or more resource pools may be indicated from all configured resource pools. For example, multiple resource pools may be configured with a resource pool list, and the SL WUS may indicate the one or more resources pool from the configured resource pool list. As shown in FIG. 4, eight resource pools may be configured as the SL WUS indicated the resource pools from resource pool (RP) #0 to RP#7.

In some example embodiments, the one or more resource pools may be indicated from the resource pools which have resources within the DRX on duration 410 of this DRX cycle. For some DRX on duration configurations, maybe not all the configured resources pools are located within the DRX on duration. For example, if eight resource pools are configured and the DRX on duration is 20ms, then maybe only four resource pools have resources located within the 20ms DRX ON duration. In this case the SL WUS may indicate the resource pools from the resource pools which have resources within the DRX on duration of this DRX cycle.

For example, if even eight resource pools are configured and only resource pools #0, #1, #2 and #3 have resources within the DRX on duration 410 of this DRX cycle, the SL WUS may indicate the resource pools from RP#0 to RP#3 (within the DRX on duration between the SL WUS occasions 402 and 404, or between the SL WUS occasions 404 and 406) .

FIG. 5 illustrates another an example indication 500 of one or more resource pools in accordance with aspects of the present disclosure. The one or more resource pools may be indicated from the resource pools which have resource within the remaining DRX on duration of this DRX cycle. When the SL WUS occasions are located within the DRX on duration, the indicated resource pools may consider the resource pools which have resources located within the remaining DRX on duration.

For example, as shown in FIG. 5, if an SL WUS is transmitted in an SL WUS occasion 506, only resource poll#0, #1 and #2 have resources within the remaining DRX on duration 508 of the whole DRX on duration 512 related to the SL WUS occasion 506. In this case the SL WUS transmitted in SL WUS occasion 506 may indicate the resource pools from RP#0, RP#1 and RP#2.

In some example embodiments, the one or more resource pools may be indicated from a portion of the on duration between two SL WUS occasions for receiving the SL WUS. For example, if an SL WUS is transmitted in an SL WUS occasion 502, the SL WUS transmitted in SL WUS occasion 502 may indicate the resource pools between the SL WUS occasion 502 and the SL WUS occasion 504 (aduration 510) . In this case, the SL WUS occasion 506 may indicate the resource pools from RP#0, RP#1, RP#2 and RP#3.

In some example embodiments, the one or more resource pools may be indicated via a bitmap. The size of the bitmap depending on the number of the one or more resource pools (also referred to candidate resource pools) . For example, if eight resource pools are configured, then the bitmap may be eight bits, and each bit may be associated to one resource pool within the configured resource pool list. For another example, eight resource pools are configured, however only four resource pools have resources within the DRX ON duration of this DRX cycle, then the bitmap may be four bits, and each bit may be associated to one resource pool.

In some example embodiments, eight resource pools may be configured and four resource pools may have resources within the DRX on duration of this DRX cycle. However, only four resource pools are within the remaining DRX ON duration related to the SL WUS occasions 506, then the bitmap may be three bits, and each bit may be associated to one resource pool.

In some example embodiments, the SL WUS may also indicate the resource pool index (es) from the candidate resource pools. The indexing of the subset resource pools may follow the first resource overlapping with a DRX on duration or with the remaining DRX on duration in time domain.

In some example embodiments, the SL WUS may also indicate the resource pool index (es) in a start and length indicator value (SLIV) manner. In this case, the indicated resource pools are contiguous. For example, if it is determined that the candidate resource pools are RP#0 to RP #3, the SLIV may indicate the starting resource pool RP#0 within the configured list and the number of resource pools of four.

In some example embodiments, the SL WUS may carry information of an intended SL hybrid automatic repeat request (HARQ) enable/disable of its transmission to implicitly indicate the resource pool (s) to the RX UE. One resource pool may be configured with a PSFCH and without a PSFCH. If one sidelink transmission is transmitted with an SL HARQ feedback enabled, a UE may only select the resource pools configured with PSFCH resources. If one SL transmission is transmitted with an SL HARQ feedback disabled, the UE could select the resource pools configured with or without PSFCH resources.

In some example embodiments, to further reduce the number of SCI monitoring budge, the SL WUS may indicate SL HARQ enabled or disabled to the RX UE (such as UE 104-1) . If the SL WUS indicates SL HARQ enabled, the RX UE may only need to monitor the resource pools configured with PSFCH resources within its DRX on duration of this DRX cycle and skip monitoring the SCI of resource pools without configured PSFCH resources within its DRX on duration of this DRX cycle. In some example embodiments, if the SL WUS indicates SL HARQ disabled, the RX UE may need to monitor all the resource pools within its DRX on duration of this DRX cycle. In some example embodiments, the indication of an SL HARQ feedback enabled or disabled by the SL WUS may be with one bit carried by the SL WUS.

In some example embodiments, The SL WUS may be transmitted with a sequence, such as a gold sequence. When the SL WUS is transmitted with a sequence (e.g., gold sequence) , a seed of gold sequence may be generated with the resource pool index when one resource pool is indicated, or the seed of gold sequence may be generated with a combination of resource pool indexes. For example, when two resource pools are indicated and eight resource pools are configured, the seed of gold sequence may be determined by {RP#0, RP1} , {RP#0, RP2} , {RP#0, RP#3} , …, and so on. If the SL WUS transmits the SL HARQ feedback enabled or disabled, the status of this indicator may be used to generate the seed of gold sequence.

In some example embodiments, the SL WUS may be transmitted with SCI. For example, the bitmap or resource pool indexes may be carried by a first stage SCI or a second stage SCI. In some example embodiments, an indictor related to an SL HARQ feedback enabled or disabled for resource pools monitoring may be carried in the first stage SCI or second stage SCI.

In some example embodiments, the SL WUS may be transmitted on a PSFCH. A dedicated PSFCH resource may be associated to a resource pool index. The dedicated PSFCH resource may be in physical resource block (PRB) , for example, PRB#0 for resource pool#0, PRB#0 for resource pool#1, …, and so on. The dedicated PSFCH resource may be also in a cyclic shift level or a phase domain.

In some example embodiments, an SL HARQ acknowledgment (ACK) may indicate that the SL HARQ feedback is enabled. In some example embodiments, an SL HARQ negative acknowledgment (NACK) may indicate that the SL HARQ feedback is disabled.

FIG. 6 illustrates an example of a device 600 that supports the solution of an SL WUS transmission in accordance with aspects of the present disclosure. The device 600 may be an example of a UE 104-1 as described herein. The device 600 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 600 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 602, a memory 604, a transceiver 606, and, optionally, an I/O controller 608. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 602, the memory 604, the transceiver 606, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 602, the memory 604, the transceiver 606, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 602, the memory 604, the transceiver 606, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 602 and the memory 604 coupled with the processor 602 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 602, instructions stored in the memory 604) .

For example, the processor 602 may support wireless communication at the device 600 in accordance with examples as disclosed herein. The processor 602 may be configured to operable to support a means for receiving, from a second UE, an SL WUS indicative of one or more resource pools; and means for monitoring an SL transmission from the second UE on the one or more resource pools during an on duration of a DRX cycle of the first UE.

The processor 602 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 602 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 602. The processor 602 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 604) to cause the device 600 to perform various functions of the present disclosure.

The memory 604 may include random access memory (RAM) and read-only memory (ROM) . The memory 604 may store computer-readable, computer-executable code including instructions that, when executed by the processor 602 cause the device 600 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 602 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 604 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 608 may manage input and output signals for the device 600. The I/O controller 608 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 608 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 608 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 608 may be implemented as part of a processor, such as the processor 606. In some implementations, a user may interact with the device 600 via the I/O controller 608 or via hardware components controlled by the I/O controller 608.

In some implementations, the device 600 may include a single antenna 610. However, in some other implementations, the device 600 may have more than one antenna 610 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 606 may communicate bi-directionally, via the one or more antennas 610, wired, or wireless links as described herein. For example, the transceiver 606 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 606 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 610 for transmission, and to demodulate packets received from the one or more antennas 610. The transceiver 606 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 610 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 610 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

FIG. 7 illustrates an example of a device 700 that supports the solution of an SL WUS transmission in accordance with aspects of the present disclosure. The device 700 may be an example of a UE 104-2 as described herein. The device 700 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 700 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 702, a memory 704, a transceiver 706, and, optionally, an I/O controller 708. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 702, the memory 704, the transceiver 706, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 702, the memory 704, the transceiver 706, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 702, the memory 704, the transceiver 706, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 702 and the memory 704 coupled with the processor 702 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 702, instructions stored in the memory 704) .

For example, the processor 702 may support wireless communication at the device 700 in accordance with examples as disclosed herein. The processor 702 may be configured to operable to support a means for determining one or more resource pools for an SL transmission to a first UE during an on duration of a DRX cycle of the first UE; and means for transmitting, to the first UE, an SL WUS indicative of the one or more resource pools.

The processor 702 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 702 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 702. The processor 702 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 704) to cause the device 700 to perform various functions of the present disclosure.

The memory 704 may include random access memory (RAM) and read-only memory (ROM) . The memory 704 may store computer-readable, computer-executable code including instructions that, when executed by the processor 702 cause the device 700 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 702 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 704 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 708 may manage input and output signals for the device 700. The I/O controller 708 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 708 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 708 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 708 may be implemented as part of a processor, such as the processor 706. In some implementations, a user may interact with the device 700 via the I/O controller 708 or via hardware components controlled by the I/O controller 708.

In some implementations, the device 700 may include a single antenna 710. However, in some other implementations, the device 700 may have more than one antenna 710 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 706 may communicate bi-directionally, via the one or more antennas 710, wired, or wireless links as described herein. For example, the transceiver 706 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 706 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 710 for transmission, and to demodulate packets received from the one or more antennas 710. The transceiver 706 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 710 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 710 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

FIG. 8 illustrates an example of a processor 800 that supports an SL WUS transmission in accordance with aspects of the present disclosure. The processor 800 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 800 may include a controller 802 configured to perform various operations in accordance with examples as described herein. The processor 800 may optionally include at least one memory 804, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 800 may optionally include one or more arithmetic-logic units (ALUs) 800. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 800 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 800) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 802 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 800 to cause the processor 800 to support various operations of a base station in accordance with examples as described herein. For example, the controller 802 may operate as a control unit of the processor 800, generating control signals that manage the operation of various components of the processor 800. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 802 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 804 and determine subsequent instruction (s) to be executed to cause the processor 800 to support various operations in accordance with examples as described herein. The controller 802 may be configured to track memory address of instructions associated with the memory 804. The controller 802 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 802 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 800 to cause the processor 800 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 802 may be configured to manage flow of data within the processor 800. The controller 802 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 800.

The memory 804 may include one or more caches (e.g., memory local to or included in the processor 800 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 804 may reside within or on a processor chipset (e.g., local to the processor 800) . In some other implementations, the memory 804 may reside external to the processor chipset (e.g., remote to the processor 800) .

The memory 804 may store computer-readable, computer-executable code including instructions that, when executed by the processor 800, cause the processor 800 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 802 and/or the processor 800 may be configured to execute computer-readable instructions stored in the memory 804 to cause the processor 800 to perform various functions. For example, the processor 800 and/or the controller 802 may be coupled with or to the memory 804, and the processor 800, the controller 802, and the memory 804 may be configured to perform various functions described herein. In some examples, the processor 800 may include multiple processors and the memory 804 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 800 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 800 may reside within or on a processor chipset (e.g., the processor 800) . In some other implementations, the one or more ALUs 800 may reside external to the processor chipset (e.g., the processor 800) . One or more ALUs 800 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 800 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 800 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 800 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 800 to handle conditional operations, comparisons, and bitwise operations.

The processor 800 may support wireless communication in accordance with examples as disclosed herein. The processor 800 may be configured to or operable to support a means for receiving, from a second UE, an SL WUS indicative of one or more resource pools; and means for monitoring an SL transmission from the second UE on the one or more resource pools during an on duration of a DRX cycle of the first UE.

FIG. 9 illustrates an example of a processor 900 that supports an SL WUS transmission in accordance with aspects of the present disclosure. The processor 900 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 900 may include a controller 902 configured to perform various operations in accordance with examples as described herein. The processor 900 may optionally include at least one memory 904, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 900 may optionally include one or more arithmetic-logic units (ALUs) 900. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 900 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 900) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 902 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 900 to cause the processor 900 to support various operations of a UE in accordance with examples as described herein. For example, the controller 902 may operate as a control unit of the processor 900, generating control signals that manage the operation of various components of the processor 900. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 902 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 904 and determine subsequent instruction (s) to be executed to cause the processor 900 to support various operations in accordance with examples as described herein. The controller 902 may be configured to track memory address of instructions associated with the memory 904. The controller 902 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 902 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 900 to cause the processor 900 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 902 may be configured to manage flow of data within the processor 900. The controller 902 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 900.

The memory 904 may include one or more caches (e.g., memory local to or included in the processor 900 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 904 may reside within or on a processor chipset (e.g., local to the processor 900) . In some other implementations, the memory 904 may reside external to the processor chipset (e.g., remote to the processor 900) .

The memory 904 may store computer-readable, computer-executable code including instructions that, when executed by the processor 900, cause the processor 900 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 902 and/or the processor 900 may be configured to execute computer-readable instructions stored in the memory 904 to cause the processor 900 to perform various functions. For example, the processor 900 and/or the controller 902 may be coupled with or to the memory 904, and the processor 900, the controller 902, and the memory 904 may be configured to perform various functions described herein. In some examples, the processor 900 may include multiple processors and the memory 904 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 900 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 900 may reside within or on a processor chipset (e.g., the processor 900) . In some other implementations, the one or more ALUs 900 may reside external to the processor chipset (e.g., the processor 900) . One or more ALUs 900 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 900 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 900 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 900 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 900 to handle conditional operations, comparisons, and bitwise operations.

The processor 900 may support wireless communication in accordance with examples as disclosed herein. The processor 900 may be configured to or operable to support a means for determining one or more resource pools for an SL transmission to a first UE during an on duration of a DRX cycle of the first UE; and means for transmitting, to the first UE, an SL WUS indicative of the one or more resource pools.

FIG. 10 illustrates a flowchart of a method 1000 that supports an SL WUS transmission in accordance with aspects of the present disclosure. The operations of the method 1000 may be implemented by a device or its components as described herein. For example, the operations of the method 1000 may be performed by a UE 104-1 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 1005, the method may include receiving, from a second UE, an SL WUS indicative of one or more resource pools. The operations of 1005 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1005 may be performed by a device as described with reference to FIG. 1.

At 1010, the method may include monitoring an SL transmission from the second UE on the one or more resource pools during an on duration of a DRX cycle of the first UE. The operations of 1010 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1010 may be performed by a device as described with reference to FIG. 1.

FIG. 11 illustrates a flowchart of a method 1100 that supports an SL WUS transmission in accordance with aspects of the present disclosure. The operations of the method 1100 may be implemented by a device or its components as described herein. For example, the operations of the method 1100 may be performed by a UE 104-2 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 1105, the method may include determining one or more resource pools for an SL transmission to a first UE during an on duration of a DRX cycle of the first UE. The operations of 1105 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1105 may be performed by a device as described with reference to FIG. 1.

At 1110, the method may include transmitting, to the first UE, an SL WUS indicative of the one or more resource pools. The operations of 1110 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1110 may be performed by a device as described with reference to FIG. 1.

It should be noted that the methods described herein describes possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, aspects from two or more of the methods may be combined.

The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, a CPU, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer. By way of example, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable ROM (EEPROM) , flash memory, compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

As used herein, including in the claims, an article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a, ” “at least one, ” “one or more, ” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of” ) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) . Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on. Further, as used herein, including in the claims, a “set” may include one or more elements.

The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

In summary, embodiments of the present disclosure may provide the following solutions.

Clause 1. A first user equipment (UE) comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

receive, via the transceiver and from a second UE, a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and

monitor, via the transceiver, an SL transmission from the second UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the first UE.

Clause 2. The first UE of clause 1, wherein the one or more resource pools are indicated among one of the following:

at least one resource pool configured for SL transmissions;

at least one resource pool including at least one resource within the on duration;

at least one resource pool including at least one resource within a remaining portion of the on duration, wherein the remaining portion is associated with an SL WUS occasion for receiving the SL WUS; or

at least one resource pool including at least one resource within a portion of the on duration between two SL WUS occasions for receiving the SL WUS.

Clause 3. The first UE of Clause 1, wherein the one or more resource pools are indicated via one of the following:

a bitmap, wherein a bit of the bitmap corresponds to a resource pool among the one or more resource pools;

one or more resource pool indexes of the one or more resource pools;

a start and length indicator value (SLIV) corresponding to the one or more resource pools in the case that the one or more resource pools are contiguous in frequency domain; or

an indication of whether SL hybrid automatic repeat request (HARQ) feedback is enabled or disabled for the SL transmission.

Clause 4. The first UE of Clause 3, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates that the SL HARQ feedback is enabled for the SL transmission, determine the one or more resource pools as one or more resource pools configured with at least one physical sidelink feedback channel (PSFCH) resource within the on duration.

Clause 5. The first UE of Clause 3, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates that the SL HARQ feedback is disabled for the SL transmission, determine the one or more resource pools as one or more resource pools including at least one resource within the on duration.

Clause 6. The first UE of any of Clauses 1-5, wherein the SL WUS is received via one of the following:

a sequence;

sidelink control information (SCI) ;

at least one PSFCH resource; or

at least one resource in a dedicated resource pool configured for receiving SL WUS.

Clause 7. The first UE of Clause 6, wherein a seed of the sequence is generated based on one of the following:

one or more resource pool indexes of the one or more resource pools; or

whether SL HARQ feedback is enabled or disabled for the SL transmission.

Clause 8. The first UE of Clause 6, wherein the SCI via which the SL WUS is received is a first stage SCI or a second stage SCI.

Clause 9. The first UE of Clause 6, wherein the SL WUS is received on at least one PSFCH resource, and wherein a dedicated PSFCH resource is associated with each of the one or more resource pools.

Clause 10. The first UE of Clause 6, wherein the SL WUS is received on at least one PSFCH resource, and wherein:

an SL HARQ acknowledgment (ACK) indicates that the SL HARQ feedback is enabled; and

an SL HARQ negative acknowledgment (NACK) indicates that the SL HARQ feedback is disabled.

Clause 11. A second user equipment (UE) comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

determine one or more resource pools for a sidelink (SL) transmission to a first UE during an on duration of a discontinuous reception (DRX) cycle of the first UE; and

transmit, via the transceiver and to the first UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.

Clause 12. The second UE of Clause 11, wherein the one or more resource pools are indicated among one of the following:

at least one resource pool configured for SL transmissions;

at least one resource pool including at least one resource within a remaining portion of the on duration, wherein the remaining portion is associated with an SL WUS occasion for transmitting the SL WUS; or

at least one resource pool including at least one resource within a portion of the on duration between two SL WUS occasions for transmitting the SL WUS.

Clause 13. The second UE of clause 11, wherein the one or more resource pools are indicated via one of the following:

one or more resource pool indexes of the one or more resource pools;

Clause 14. The second UE of clause 13, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates the indication that the SL HARQ feedback is enabled for the SL transmission, select one or more resource pools configured with at least one physical sidelink feedback channel (PSFCH) resources within the on duration as the one or more resource pools.

Clause 15. The second UE of clause 13, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates that the SL HARQ feedback is disabled for the SL transmission, select one or more resource pools including at least one resource within the on duration as the one or more resource pools.

Clause 16. The second UE of any of clauses 11-15, wherein the SL WUS is transmitted via one of the following:

a sequence;

sidelink control information (SCI) ;

at least one PSFCH resource; or

at least one resource in a dedicated resource pool configured for transmitting SL WUS.

Clause 17. The second UE of clause 16, wherein a seed of the sequence is generated based on one of the following:

one or more resource pool indexes of the one or more resource pools; or

whether SL HARQ feedback is enabled or disabled for the SL transmission.

Clause 18. The second UE of claim 16, wherein the SCI via which the SL WUS is transmitted is a first stage SCI or a second stage SCI.

Clause 19. The second UE of Clause 16, wherein the SL WUS is transmitted on at least one PSFCH resource, and wherein a dedicated PSFCH resource is associated with each of the one or more resource pools.

Clause 20. The second UE of Clause 16, wherein the SL WUS is transmitted on at least one PSFCH resource, and wherein:

Clause 21. A processor for wireless communication, comprising:

at least one memory; and

a controller coupled with the at least one memory and configured to cause the controller to:

receive, from a user equipment (UE) , a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and

monitor an SL transmission from the UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the UE.

Clause 22. A processor for wireless communication, comprising:

at least one memory; and

determine one or more resource pools for a sidelink (SL) transmission to a user equipment (UE) during an on duration of a discontinuous reception (DRX) cycle of the UE; and

transmit, to the UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.

Clause 23. A method performed by a first user equipment (UE) comprising:

receiving, from a second UE, a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and

monitoring an SL transmission from the second UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the first UE.

Clause 24. A method performed by a second user equipment (UE) comprising:

determining one or more resource pools for a sidelink (SL) transmission to a first UE during an on duration of a discontinuous reception (DRX) cycle of the first UE; and

transmitting, to the first UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.

Claims

A first user equipment (UE) comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

receive, via the transceiver and from a second UE, a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and

monitor, via the transceiver, an SL transmission from the second UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the first UE.
The first UE of claim 1, wherein the one or more resource pools are indicated among one of the following:

at least one resource pool configured for SL transmissions;

at least one resource pool including at least one resource within the on duration;

at least one resource pool including at least one resource within a remaining portion of the on duration, wherein the remaining portion is associated with an SL WUS occasion for receiving the SL WUS; or

at least one resource pool including at least one resource within a portion of the on duration between two SL WUS occasions for receiving the SL WUS.
The first UE of claim 1, wherein the one or more resource pools are indicated via one of the following:

a bitmap, wherein a bit of the bitmap corresponds to a resource pool among the one or more resource pools;

one or more resource pool indexes of the one or more resource pools;

a start and length indicator value (SLIV) corresponding to the one or more resource pools in the case that the one or more resource pools are contiguous in frequency domain; or

an indication of whether SL hybrid automatic repeat request (HARQ) feedback is enabled or disabled for the SL transmission.
The first UE of claim 3, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates that the SL HARQ feedback is enabled for the SL transmission, determine the one or more resource pools as one or more resource pools configured with at least one physical sidelink feedback channel (PSFCH) resource within the on duration.
The first UE of claim 3, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates that the SL HARQ feedback is disabled for the SL transmission, determine the one or more resource pools as one or more resource pools including at least one resource within the on duration.
The first UE of any of claims 1-5, wherein the SL WUS is received via one of the following:

a sequence;

sidelink control information (SCI) ;

at least one PSFCH resource; or

at least one resource in adedicated resource pool configured for receiving SL WUS.
The first UE of claim 6, wherein a seed of the sequence is generated based on one of the following:

one or more resource pool indexes of the one or more resource pools; or

whether SL HARQ feedback is enabled or disabled for the SL transmission.
The first UE of claim 6, wherein the SCI via which the SL WUS is received is a first stage SCI or a second stage SCI.
The first UE of claim 6, wherein the SL WUS is received on at least one PSFCH resource, and wherein a dedicated PSFCH resource is associated with each of the one or more resource pools.
The first UE of claim 6, wherein the SL WUS is received on at least one PSFCH resource, and wherein:

an SL HARQ acknowledgment (ACK) indicates that the SL HARQ feedback is enabled; and

an SL HARQ negative acknowledgment (NACK) indicates that the SL HARQ feedback is disabled.
A second user equipment (UE) comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

determine one or more resource pools for a sidelink (SL) transmission to a first UE during an on duration of a discontinuous reception (DRX) cycle of the first UE; and

transmit, via the transceiver and to the first UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.
The second UE of claim 11, wherein the one or more resource pools are indicated among one of the following:

at least one resource pool configured for SL transmissions;

at least one resource pool including at least one resource within the on duration;

at least one resource pool including at least one resource within a remaining portion of the on duration, wherein the remaining portion is associated with an SL WUS occasion for transmitting the SL WUS; or

at least one resource pool including at least one resource within a portion of the on duration between two SL WUS occasions for transmitting the SL WUS.
The second UE of claim 11, wherein the one or more resource pools are indicated via one of the following:

a bitmap, wherein a bit of the bitmap corresponds to a resource pool among the one or more resource pools;

one or more resource pool indexes of the one or more resource pools;

a start and length indicator value (SLIV) corresponding to the one or more resource pools in the case that the one or more resource pools are contiguous in frequency domain; or

an indication of whether SL hybrid automatic repeat request (HARQ) feedback is enabled or disabled for the SL transmission.
The second UE of claim 13, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates the indication that the SL HARQ feedback is enabled for the SL transmission, select one or more resource pools configured with at least one physical sidelink feedback channel (PSFCH) resources within the on duration as the one or more resource pools.
The second UE of claim 13, wherein the processor is further configured to:

in the case that the indication in the SL WUS indicates that the SL HARQ feedback is disabled for the SL transmission, select one or more resource pools including at least one resource within the on duration as the one or more resource pools.
The second UE of any of claims 11-15, wherein the SL WUS is transmitted via one of the following:

a sequence;

sidelink control information (SCI) ;

at least one PSFCH resource; or

at least one resource in a dedicated resource pool configured for transmitting SL WUS.
The second UE of claim 16, wherein a seed of the sequence is generated based on one of the following:

one or more resource pool indexes of the one or more resource pools; or

whether SL HARQ feedback is enabled or disabled for the SL transmission.
The second UE of claim 16, wherein the SCI via which the SL WUS is transmitted is a first stage SCI or a second stage SCI.
The second UE of claim 16, wherein the SL WUS is transmitted on at least one PSFCH resource, and wherein a dedicated PSFCH resource is associated with each of the one or more resource pools.
The second UE of claim 16, wherein the SL WUS is transmitted on at least one PSFCH resource, and wherein:

an SL HARQ acknowledgment (ACK) indicates that the SL HARQ feedback is enabled; and

an SL HARQ negative acknowledgment (NACK) indicates that the SL HARQ feedback is disabled.
A processor for wireless communication, comprising:

at least one memory; and

a controller coupled with the at least one memory and configured to cause the controller to:

receive, from a user equipment (UE) , a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and

monitor an SL transmission from the UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the UE.
A processor for wireless communication, comprising:

at least one memory; and

a controller coupled with the at least one memory and configured to cause the controller to:

determine one or more resource pools for a sidelink (SL) transmission to a user equipment (UE) during an on duration of a discontinuous reception (DRX) cycle of the UE; and

transmit, to the UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.
A method performed by a first user equipment (UE) comprising:

receiving, from a second UE, a sidelink (SL) wake-up signal (WUS) indicative of one or more resource pools; and

monitoring an SL transmission from the second UE on the one or more resource pools during an on duration of a discontinuous reception (DRX) cycle of the first UE.
A method performed by a second user equipment (UE) comprising:

determining one or more resource pools for a sidelink (SL) transmission to a first UE during an on duration of a discontinuous reception (DRX) cycle of the first UE; and

transmitting, to the first UE, an SL wake-up signal (WUS) indicative of the one or more resource pools.