WO2024084366A1 - Semiconductor device and storage device - Google Patents

Abstract

Provided is a semiconductor device that enables miniaturization or higher integration. Provided is an oxide semiconductor suitable for the semiconductor device. Formed is an oxide semiconductor that has a small difference in thickness between a section provided along a first surface and a section provided along a second surface which is inclined relative to the first surface. A precursor having an aluminum content of 0.01 ppm to 500 ppm is used to deposit a layer, by automatic layer deposition (ALD), on an oxide semiconductor having an aluminum concentration of 0.01 atom percent to 10 atom percent. Furthermore, the crystallinity of the oxide semiconductor is improved by performing impurity removal processing such as microwave processing.

Description

Semiconductor device and storage device

One embodiment of the present invention relates to a method for forming a metal oxide film. Another embodiment of the present invention relates to a transistor including the metal oxide and a method for manufacturing the transistor. Another embodiment of the present invention relates to a semiconductor device using the metal oxide and a method for manufacturing the semiconductor device. Another embodiment of the present invention relates to a memory device using the metal oxide and a method for manufacturing the memory device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.

In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and have electrodes that serve as connection terminals.

Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

In addition, technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor materials that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

In addition, it is known that transistors using oxide semiconductors have extremely low leakage current when in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors. In addition, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.

Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further increasing the density of integrated circuits. There is also a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.

Furthermore, if the transistor can be made vertical, it is possible to increase the density of the integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulator.

Furthermore, in oxide semiconductors, CAAC (c-axis aligned crystalline) structure and nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 2 and 3).

Non-Patent Documents 2 and 3 disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure.

JP 2012-257187 A JP 2011-151383 A International Publication No. 2021/053473 JP 2013-211537 A

M. Oota et. al, "3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72 nm", IEDM Tech. Dig. , 2019, pp. 50-53 S. Yamazaki et al. , "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, pp. 183-186 S. Yamazaki et al. , "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, pp. 04ED18-1-04ED18-10

An object of one embodiment of the present invention is to provide a novel metal oxide and a method for forming the same. Alternatively, an object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device. Alternatively, an object of one embodiment of the present invention is to provide a transistor with a large on-state current. Alternatively, an object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a memory device with high operation speed. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing the transistor, semiconductor device, or memory device.

Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

One aspect of the present invention is a semiconductor device that includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and a first insulator, the first conductor and the second conductor each have a portion in contact with the oxide semiconductor, the third conductor overlaps the oxide semiconductor via the first insulator, the oxide semiconductor has a first portion provided along the first surface and a second portion provided along a second surface that is inclined with respect to the first surface, the ratio of the thickness of the second portion to the thickness of the first portion is 0.8 to 1.2, the oxide semiconductor includes indium and one or more selected from gallium, tin, and zinc, and the aluminum concentration of the oxide semiconductor is 0.01 atomic% to 10 atomic%.

Another aspect of the present invention is a semiconductor device that includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator, the first insulator is in contact with the top surface of the first conductor, the second conductor is located on the first insulator, the oxide semiconductor has a first portion in contact with the top surface of the first conductor, a second portion in contact with a side surface of the first insulator, and a third portion in contact with the second conductor, the second insulator is located on the oxide semiconductor, the third conductor is located on the second insulator, and overlaps with the oxide semiconductor via the second insulator, the ratio of the thickness of the second portion to the thickness of the first portion is 0.8 to 1.2, the oxide semiconductor includes indium and one or more selected from gallium, tin, and zinc, and the aluminum concentration of the oxide semiconductor is 0.01 atomic% to 10 atomic%.

Furthermore, one aspect of the present invention includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator, the first insulator being in contact with an upper surface of the first conductor, the second conductor being located on the first insulator, the first insulator and the second conductor having a first opening that reaches the first conductor, and the oxide semiconductor having, inside the first opening, a first portion that is in contact with an upper surface of the first conductor and a second portion that is in contact with a side surface of the first insulator, and a third portion that is in contact with the second conductor. The second insulator is located on the oxide semiconductor, the third conductor is located on the second insulator and overlaps with the oxide semiconductor via the second insulator at a position overlapping with the first opening, the ratio of the thickness of the second portion to the thickness of the first portion is 0.8 or more and 1.2 or less, the oxide semiconductor contains indium and one or more selected from gallium, tin, and zinc, and the aluminum concentration of the oxide semiconductor is 0.01 atomic% or more and 10 atomic% or less.

The aluminum concentration of the oxide semiconductor is preferably 0.01 atomic% or more and 5 atomic% or less.

The carbon concentration of the oxide semiconductor is preferably greater than or equal to 1×10 ¹⁷ atoms/cm ³ and less than or equal to 5×10 ¹⁹ atoms/cm ³ .

Furthermore, one aspect of the present invention is a memory device having the above-mentioned semiconductor device, a fourth conductor, a third insulator, and a capacitor, the capacitor having a fifth conductor, a fourth insulator on the fifth conductor, and a first conductor on the fourth insulator, the third insulator having a second opening reaching the fourth conductor, and at least a portion of the fifth conductor, at least a portion of the fourth insulator, and at least a portion of the first conductor are disposed in the second opening.

Another aspect of the present invention is a method for forming a metal oxide film, comprising a first step of supplying a first compound containing indium into a chamber and then supplying an oxidizing agent into the chamber, and a second step of supplying a second compound into the chamber and then supplying an oxidizing agent into the chamber, wherein the aluminum content of the first compound is 0.01 ppm or more and 500 ppm or less, the aluminum content of the second compound is less than the aluminum content of the first compound, and the second compound contains gallium, tin, or zinc.

Another aspect of the present invention is a method for forming a metal oxide film, comprising a first step of supplying a first compound containing indium into a chamber and then supplying an oxidizing agent into the chamber, and a second step of supplying a second compound into the chamber and then supplying the oxidizing agent into the chamber, wherein the aluminum content of the first compound is 0.01 ppm or more and 500 ppm or less, the aluminum content of the second compound is less than the aluminum content of the first compound, and the sum of the time for supplying the oxidizing agent in the first step and the time for supplying the oxidizing agent in the second step is 90 seconds or more.

The second compound preferably contains gallium or zinc.

It is preferable to carry out each of the first step and the second step at least once, and then to carry out microwave treatment in an oxygen-containing atmosphere.

It is preferable to perform each of the first step and the second step at least once, and then perform microwave treatment in an oxygen-containing atmosphere to form a first cycle, and to repeat the first cycle multiple times.

Another embodiment of the present invention includes a first insulator, an oxide semiconductor covering the first insulator, a first conductor and a second conductor on the oxide semiconductor, a second insulator disposed on the first conductor and the second conductor and having an opening overlapping with a region between the first conductor and the second conductor, a third insulator disposed in the opening and on the oxide semiconductor, and a third conductor disposed in the opening and on the third insulator, wherein the height of the first insulator in a cross-sectional view in a channel width direction is The semiconductor device has a first portion that is longer than the width of the edge, the oxide semiconductor has a first portion that is provided along the first surface, and a second portion that is provided along the second surface that is inclined with respect to the first surface, the ratio of the thickness of the second portion to the thickness of the first portion is 0.8 to 1.2, the oxide semiconductor has indium and one or more selected from gallium, tin, and zinc, and the aluminum concentration of the oxide semiconductor is 0.01 atomic% to 10 atomic%. The aluminum concentration of the oxide semiconductor is more preferably 0.01 atomic% to 5 atomic%. The carbon concentration of the oxide semiconductor is preferably 1×10 ¹⁷ atoms/cm ³ to 5×10 ¹⁹ atoms/cm ³ .

In a plan view, it is preferable that the side of the opening of the second insulator coincides or roughly coincides with the side of the first conductor and the side of the second conductor.

The first conductor preferably functions as one of the source electrode and drain electrode of the transistor. The second conductor preferably functions as the other of the source electrode and drain electrode of the transistor. The third conductor preferably functions as the gate electrode of the transistor.

In a cross-sectional view of the transistor in the channel width direction, it is preferable that on one side of the first insulator, the oxide semiconductor and the third conductor face each other with the third insulator in between, and on the other side of the first insulator, the oxide semiconductor and the third conductor face each other with the third insulator in between.

In a cross-sectional view of the transistor in the channel width direction, it is preferable that the first conductor contacts the oxide semiconductor on one side and the other side of the first insulator, and the second conductor contacts the oxide semiconductor on one side and the other side of the first insulator.

When viewed in a cross-sectional view of the transistor in the channel width direction, it is preferable that the height of the first insulator is greater than or equal to 2 times and less than or equal to 20 times the width of the first insulator.

Another embodiment of the present invention is a memory device including the above-described semiconductor device and a capacitor, in which one electrode of the capacitor is electrically connected to a first conductor of the semiconductor device. The capacitor is preferably disposed over a third conductor. At least a part of the capacitor is preferably overlapped with the oxide semiconductor and the third conductor.

According to one embodiment of the present invention, a novel metal oxide and a method for forming the same can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable transistor, a semiconductor device, or a memory device can be provided. According to one embodiment of the present invention, a transistor with a large on-state current can be provided. According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device or a memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

1A to 1E are cross-sectional views showing an example of a method for forming a metal oxide film.
2A to 2D are cross-sectional views showing an example of a metal oxide.
3A to 3D are cross-sectional views showing an example of a metal oxide.
4A to 4C are diagrams showing examples of ranges of atomic ratios of metal oxides.
5A to 5D are cross-sectional views showing an example of a method for forming a metal oxide film.
6A to 6C are cross-sectional views showing an example of a method for forming a metal oxide film.
FIG. 7 is a plan view and a cross-sectional view showing an example of a film forming apparatus.
8A and 8B are cross-sectional views showing an example of a film forming apparatus.
9A to 9C are cross-sectional views showing an example of a film forming apparatus.
10A and 10B are cross-sectional views showing an example of a film forming apparatus.
11A and 11B are diagrams showing an example of a method for forming a metal oxide film.
12A and 12B are diagrams showing an example of a method for forming a metal oxide film.
FIG. 13 is a diagram showing an example of a method for forming a metal oxide film.
14A to 14D are cross-sectional views showing an example of a memory device.
Fig. 15A is a plan view showing an example of a memory device, Fig. 15B and Fig. 15C are cross-sectional views showing an example of a memory device, and Fig. 15D is a circuit diagram showing an example of a memory device.
16A and 16B are cross-sectional views showing an example of a memory device.
17A to 17D are cross-sectional views showing an example of a memory device.
18A and 18B are cross-sectional views showing an example of a memory device.
19A to 19D are cross-sectional views showing an example of a memory device.
20A and 20B are cross-sectional views showing an example of a memory device.
Fig. 21A is a plan view showing an example of a semiconductor device, and Fig. 21B to Fig. 21D are cross-sectional views showing an example of the semiconductor device.
22A and 22B are cross-sectional views showing an example of a semiconductor device.
Fig. 23A is a plan view showing an example of a semiconductor device, and Fig. 23B to Fig. 23D are cross-sectional views showing an example of the semiconductor device.
24A and 24B are cross-sectional views showing an example of a semiconductor device.
25A to 25C are cross-sectional views showing an example of a semiconductor device.
26A and 26C are plan views and sectional views of an example of a storage device, respectively.
27A and 27B are plan and cross-sectional views illustrating an example of a storage device.
28A is a plan view of an example of a storage device, and FIG 28B is a cross-sectional view of the example of the storage device.
29A is a plan view of an example of a storage device, and FIG 29B is a cross-sectional view of the example of the storage device.
30A to 30C are plan layouts showing an example of a storage device.
31A to 31C are plan layouts showing an example of a storage device.
FIG. 32 is a cross-sectional view showing an example of a storage device.
FIG. 33 is a block diagram illustrating an example of a storage device.
34A and 34B are schematic diagrams showing an example of a storage device.
35A to 35D are circuit diagrams showing an example of a memory device.
FIG. 36 is a circuit diagram showing an example of a memory device.
37A and 37B are diagrams illustrating an example of an electronic component.
38A and 38B are diagrams showing an example of an electronic device, and Fig. 38C to Fig. 38E are diagrams showing an example of a mainframe computer.
FIG. 39 is a diagram showing an example of space equipment.
FIG. 40 is a diagram illustrating an example of a storage system that can be applied to a data center.
FIG. 41 is a diagram showing the results of XPS analysis of Example 1.
42A and 42B are diagrams showing the results of Hall effect measurement in Example 1.
FIG. 43 is a diagram showing the results of SIMS analysis of Example 1.
FIG. 44 is a diagram showing the results of SIMS analysis of Example 1.
FIG. 45 is a diagram showing the results of SIMS analysis of Example 1.
46A and 46B are diagrams showing the results of SIMS analysis of Example 1.
FIG. 47 is a diagram showing the results of SIMS analysis of Example 1.
FIG. 48 is a diagram showing the Id-Vg characteristics of the transistor of Example 1.
49A to 49D are cross-sectional observation images of the IGZO film of Example 1.
50A to 50D are diagrams showing the results of SIMS analysis of Example 2.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Also, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

In this specification and the like, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction. In this specification, the term "transistor" includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

In addition, in this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" can be used interchangeably.

Note that the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When an impurity is contained, for example, the defect level density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and a transition metal other than the main component of the oxide semiconductor. Specific examples of the impurity include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. In addition, for example, oxygen vacancies (also referred to as V _O ) may be formed in the oxide semiconductor due to the inclusion of an impurity.

In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. An oxynitride refers to a material whose composition contains more nitrogen than oxygen.

To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

Furthermore, in this specification and the like, the term "insulator" can be replaced with "insulating film" or "insulating layer." Furthermore, the term "conductor" can be replaced with "conductive film" or "conductive layer." Furthermore, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer."

In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In this specification, "electrically connected" includes a connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be sent and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage _Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage _Vth (higher than _Vth for a p-channel transistor).

In this specification, the top surface shape of a certain component refers to the contour shape of the component in a planar view. A planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.

In this specification, a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is less than 90°. The side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.

In this specification, when it is stated that A is in contact with B, at least a part of A is in contact with B. Therefore, for example, this can be rephrased as saying that A has an area in contact with B.

In this specification and the like, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as saying that A has a region that is located on B.

In this specification, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has an area that covers B.

In this specification, when it is stated that A overlaps with B, at least a portion of A overlaps with B. Therefore, for example, this can be rephrased as saying that A has an area that overlaps with B.

(Embodiment 1)
In this embodiment, a metal oxide according to one embodiment of the present invention and a method for forming the metal oxide will be described with reference to FIGS.

The metal oxide of one embodiment of the present invention can be used as a semiconductor material, an insulating material, or a conductive material, depending on the type, combination, composition, and the like of the elements constituting the metal oxide. The metal oxide of one embodiment of the present invention can be used, for example, in the semiconductor layer of a transistor. The metal oxide may also be called an oxide semiconductor or an oxide.

The metal oxide film formation method of one embodiment of the present invention uses the ALD (Atomic Layer Deposition) method, which allows extremely thin and uniform films to be formed. This makes it suitable for forming metal oxide films that form fine transistors.

In one embodiment of the metal oxide film forming method of the present invention, one or both of an inorganic precursor and an organic precursor can be used. Here, an organic precursor is a precursor that contains carbon as a constituent element, and an inorganic precursor is a precursor that does not contain carbon as a constituent element.

A metal oxide film formed using an inorganic precursor can have a lower impurity concentration (e.g., at least one of hydrogen concentration, carbon concentration, and nitrogen concentration) in the film compared to a metal oxide film formed using an organic precursor.

In addition, by using an organic precursor, the metal oxide film formation temperature can be lowered compared to when an inorganic precursor is used.

If a metal oxide film is formed using a precursor containing impurities, the impurities may get into the metal oxide, adversely affecting the physical properties of the metal oxide and even the characteristics of a semiconductor device that uses the metal oxide.

For example, if a metal oxide that does not contain aluminum as a main component contains a large amount of aluminum as an impurity, it may affect the physical properties of the metal oxide. Examples of metal oxides that do not contain aluminum as a main component include indium zinc oxide (In-Zn oxide) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

For example, when aluminum is present in an IGZO film in an oxidized state (such as Al ₂ O ₃ ), the IGZO film becomes highly resistive. If the highly resistive IGZO film is used in a semiconductor layer, the on-current of a transistor becomes low.

On the other hand, aluminum has a high bond dissociation energy with oxygen and functions as a carrier suppressing element. Specifically, the bond dissociation energy between aluminum and oxygen is higher than the bond dissociation energy between Ga and oxygen. For this reason, the presence of aluminum in the IGZO film can make it difficult for oxygen vacancies (Vo) to be generated. If an IGZO film in which Vo is difficult to generate is used as the semiconductor layer, it is possible to suppress the negative bias light deterioration of the transistor. For this reason, it is not necessary to completely remove aluminum from the metal oxide, and in some cases aluminum may be included in the metal oxide to an extent that does not have a detrimental effect.

Therefore, in one embodiment of the metal oxide film formation method of the present invention, a precursor with a low aluminum content is used to produce a metal oxide that does not contain aluminum as a main component. This makes it possible to prevent the aluminum concentration in the formed metal oxide film from becoming too high.

In addition, when metal oxide is formed using the ALD method, it may be difficult to sufficiently remove impurities in the film even if the metal oxide is subjected to a heat treatment after film formation. On the other hand, if a high-temperature process (e.g., a process exceeding 700°C) is performed to increase the maximum temperature in the manufacturing process of a transistor or semiconductor device in order to form a metal oxide film with a low impurity content, productivity decreases.

Therefore, in the method for forming a metal oxide film according to one embodiment of the present invention, the carbon concentration in the film is reduced by supplying a sufficient amount of oxidizing agent, for example, by making the total time of the step of supplying the oxidizing agent in the entire process of forming the metal oxide film sufficiently long, or by increasing the proportion of ozone (O ₃ ) contained in the oxidizing agent.

Furthermore, after the film is formed, it is preferable to perform a microwave treatment in an oxygen-containing atmosphere as an impurity removal treatment. By performing a microwave treatment in an oxygen-containing atmosphere, impurities in the film can be removed. This makes it possible to suppress impurities contained in raw materials such as precursors from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. Also, the crystallinity of the metal oxide can be increased.

In addition, it is preferable to perform an impurity removal process intermittently in an oxygen-containing atmosphere during film formation. By performing the impurity removal process during film formation, it is possible to more reliably remove impurities in the film compared to performing the process after film formation. In addition, the impurity removal process may be performed both during and after film formation.

From the above, by using the metal oxide film formation method of one embodiment of the present invention, a metal oxide with a low impurity content can be formed for use in the semiconductor layer of a fine transistor. In addition, by using the metal oxide film formation method of one embodiment of the present invention, a metal oxide with high crystallinity can be formed for use in the semiconductor layer of a fine transistor. This makes it possible to realize a transistor that is fine and has good electrical characteristics. In addition, it makes it possible to realize a transistor that is fine and has good reliability. In particular, it is preferable to form a metal oxide with a CAAC structure.

Specifically, one aspect of the present invention is a method for forming a metal oxide film, comprising a first step of supplying a first compound containing indium into a chamber, and then supplying an oxidizing agent into the chamber, and a second step of supplying a second compound into the chamber, and then supplying an oxidizing agent into the chamber. The method may further comprise a third step of supplying a third compound into the chamber, and then supplying an oxidizing agent into the chamber.

The aluminum content of the first compound is preferably 0.001 ppm or more, 0.01 ppm or more, or 0.1 ppm or more, and is preferably 1000 ppm or less, more preferably 500 ppm or less, more preferably 100 ppm or less, more preferably 50 ppm or less, more preferably 10 ppm or less, and even more preferably 1 ppm or less.

The second compound and the third compound each preferably contain at least one of gallium, tin, and zinc. The preferred range of the aluminum content of the second compound and the aluminum content of the third compound is the same as the preferred range of the aluminum content of the first compound. In particular, it is preferred that the second compound and the third compound each have a lower aluminum content than the first compound.

In the metal oxide film formation process, the total time for supplying the oxidizing agent in one cycle is preferably 10 seconds or more, more preferably 30 seconds or more, more preferably 60 seconds or more, more preferably 90 seconds or more, even more preferably 120 seconds or more, and preferably 150 seconds or less, 200 seconds or less, 250 seconds or less, or 300 seconds or less. When a metal oxide film is formed using two compounds, the first compound and the second compound, one cycle is performed by carrying out the above-mentioned first step and second step once each. The total time for supplying the oxidizing agent in one cycle corresponds to the sum of the time for supplying the oxidizing agent in the first step and the time for supplying the oxidizing agent in the second step. When a metal oxide film is formed using three compounds including the third compound, one cycle is performed by carrying out the above-mentioned first step, second step, and third step once each. The total time for supplying the oxidizing agent in one cycle corresponds to the sum of the time for supplying the oxidizing agent in the first to third steps.

The longer the time for which the oxidizing agent is supplied, the more the carbon concentration in the metal oxide can be reduced, which is preferable. On the other hand, the shorter the time for which the oxidizing agent is supplied, the shorter the time required to form a metal oxide film, which is preferable.

When supplying the oxidizing agent, the proportion of ozone in the gas is preferably 10% or more, more preferably 20% or more, more preferably 30% or more, more preferably 40% or more, more preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and particularly preferably 100%. A higher proportion of ozone is preferable because it promotes the oxidation of the metal and reduces the carbon concentration in the metal oxide.

When supplying the oxidizing agent, it is preferable to set the substrate temperature to 150°C or higher, 200°C or higher, or 250°C or higher. The upper limit of the substrate temperature can be the lower of the decomposition temperature of the precursor such as the first compound and the decomposition temperature of ozone (e.g., 300°C). Increasing the substrate temperature is preferable because it reduces the impurity concentration in the metal oxide.

In the method for forming a metal oxide film according to one embodiment of the present invention, after each of the first step and the second step is performed at least once, an impurity removal treatment is preferably performed under an atmosphere containing oxygen. The impurity removal treatment is a treatment for releasing impurities contained in the metal oxide from the film. In the impurity removal treatment, it is preferable to release hydrogen, carbon, nitrogen, and the like contained in the metal oxide from the film. In addition, in the impurity removal treatment, it is preferable to supply oxygen to the metal oxide. This can reduce oxygen vacancies (V _O ) and impurities in the metal oxide. By using a metal oxide in which oxygen vacancies (V _O ) and impurities are reduced, the electrical characteristics and reliability of a transistor can be improved.

Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

When performing plasma treatment or microwave treatment, it is preferable that the substrate temperature is at least room temperature (e.g., 25°C), at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and at most 500°C, or at most 450°C. It is also preferable that the heat treatment temperature is at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and at most 500°C, or at most 450°C.

The temperature during the impurity removal process is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or semiconductor device, in particular, so that the content of impurities in the metal oxide can be reduced without reducing productivity. For example, the productivity of a transistor or semiconductor device can be increased by setting the maximum temperature in the manufacturing process of a transistor or semiconductor device using the metal oxide of one embodiment of the present invention to 500° C. or lower, preferably 450° C. or lower.

Furthermore, the impurity removal process is preferably performed at a temperature lower than the decomposition temperature of both the first compound and the second compound. Furthermore, when a third compound is used, it is preferable to perform the process at a temperature lower than the decomposition temperature of the third compound. Furthermore, the impurity removal process may be performed at a temperature higher than 500°C (for example, higher than 500°C and equal to or lower than 700°C).

The impurity removal process may be performed while irradiating light (e.g., ultraviolet light). This can promote the desorption of impurities. Examples of light sources include lasers and mercury lamps. For example, oxygen radicals can be generated by photoexcitation and reacted with hydrogen, carbon, nitrogen, etc., to reduce impurities in the film and promote crystallization. By irradiating light, it may be easier to remove impurities even at a lower heating temperature than when light irradiation is not performed.

In addition, light may be irradiated during film formation. For example, in the first step, light may be irradiated onto the surface on which the metal oxide is to be formed while the first compound is being supplied into the chamber and/or while the oxidizing agent is being supplied into the chamber. The same applies to the second and third steps.

After performing each of the first step and the second step at least once, it is preferable to perform an impurity removal process in an oxygen-containing atmosphere as a first cycle, and to repeat the first cycle multiple times.

Alternatively, it is preferable to perform the first and second steps at least once each and then perform an impurity removal process in an oxygen-containing atmosphere as a first cycle, and to perform the first and second steps at least once each in an order different from that of the first cycle and then perform an impurity removal process in an oxygen-containing atmosphere as a second cycle, and to alternately repeat the first and second cycles multiple times.

In the first cycle and the second cycle, it is preferable to carry out the impurity removal treatment, for example, every time the first step or the second step is carried out fewer times, or every time both steps are carried out in a range of 5 to 10 times.

In some cases, impurities may not be sufficiently removed by simply performing an impurity removal process after forming a metal oxide film. By introducing an impurity removal process intermittently (at intervals) during film formation, it is possible to sufficiently remove impurities from the metal oxide.

Another aspect of the present invention is a method for forming a film of an indium compound using an ALD method, in which a precursor containing indium (e.g., triethylindium precursor) is supplied into a chamber, and then an oxidizing agent is supplied into the chamber. The aluminum content of the precursor is preferably 0.001 ppm or more, 0.01 ppm or more, or 0.1 ppm or more, and is preferably 1000 ppm or less, more preferably 500 ppm or less, more preferably 100 ppm or less, more preferably 50 ppm or less, more preferably 10 ppm or less, and even more preferably 1 ppm or less.

<Metal oxide>
Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Factors that cause the generation of lattice defects include a deviation in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.

When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.

In a transistor using a metal oxide, particularly when oxygen vacancies (V _O ) and impurities are present in the channel formation region in the metal oxide, the electrical characteristics may easily fluctuate and the reliability may be deteriorated. In addition, hydrogen near the oxygen vacancies may form defects (hereinafter, may be referred to as V _O H) in which hydrogen enters the oxygen vacancies, and may generate electrons that become carriers. For this reason, when oxygen vacancies are present in the channel formation region in the metal oxide, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

The types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.

Metal oxide structures are divided into single crystal structures and other structures (non-single crystal structures). Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures. A-like structures have a structure between the nc structure and the amorphous structure.

The crystallinity of the metal oxide of one embodiment of the present invention is not particularly important.

In addition, metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

Therefore, it is preferable to use a metal oxide having a crystal part for the semiconductor layer of the transistor, and it is more preferable to use a metal oxide having high crystallinity. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using such a metal oxide for the transistor, it is possible to realize a transistor having good electrical characteristics. In addition, it is possible to realize a highly reliable transistor.

In addition, it is preferable to use a metal oxide for the channel formation region of the transistor, which increases the on-current of the transistor. In order to increase the on-current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or reduce the scattering factor that contributes to the transmission of carriers. Note that the carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-current of the transistor can be increased.

Here, it is preferable to use a metal oxide having high crystallinity for the metal oxide including the channel formation region. Furthermore, it is preferable that the crystal has a crystal structure in which multiple layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS (c-axis aligned crystalline oxide semiconductors).

Furthermore, it is preferable to orient the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.

For example, the above three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron with the metal of the first layer at the center. The second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the second layer at the center. The third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the third layer at the center.

The crystal structure of the above crystals includes, for example, a YbFe ₂ O ₄ type structure, a Yb ₂ Fe ₃ O ₇ type structure, and modified structures thereof.

Furthermore, each of the first layer to the third layer is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen. Note that the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer. Furthermore, the first layer and the second layer may have the same metal element. Furthermore, it is preferable that the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.

The above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.

The metal oxide of one embodiment of the present invention preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that it contains at least one metal element having the same valence as that of indium or zinc. Examples of such metal elements include gallium and tin. In addition, it may contain one or more elements selected from yttrium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, cobalt, aluminum, etc.

Here, we consider the case where the metal oxide is an In-M-Zn oxide having indium (In), element M, and zinc (Zn). The element M is gallium or tin. Other elements that can be used for element M include yttrium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, cobalt, and aluminum. However, there are cases where a combination of multiple elements mentioned above can be used as element M.

Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), and indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO).

By increasing the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased.

Note that the metal oxide may have one or more metal elements with a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more metal elements with a higher period number in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a higher period number, the field effect mobility of the transistor may be increased in some cases. Examples of metal elements with a higher period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

The metal oxide may also contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field effect mobility of the transistor may be increased. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

Furthermore, by increasing the ratio of the number of In atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the transistor can obtain a large on-current and high frequency characteristics.

In this embodiment, In-Ga-Zn oxide may be used as an example of a metal oxide.

To form a metal oxide having the above-mentioned layered crystal structure, it is preferable to deposit atoms one layer at a time. In one embodiment of the metal oxide film formation method of the present invention, the ALD method is used, so that it is easy to form a metal oxide having the above-mentioned layered crystal structure.

Examples of the ALD method include the Thermal ALD method, in which the reaction between the precursor and reactant is carried out using only thermal energy, and the Plasma Enhanced ALD (PEALD) method, in which a plasma-excited reactant is used.

The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In addition, the PEALD method may be preferable because it can form films at lower temperatures by using plasma. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.

The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles released from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed. For example, a method of forming a first metal oxide film using a sputtering method and forming a second metal oxide film on the first metal oxide using an ALD method can be mentioned. For example, when the first metal oxide has a crystal part, the second metal oxide may grow as a crystal with the crystal part as a nucleus.

The ALD method can control the composition of the resulting film by the amount of raw material gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like. Also, for example, the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film. When forming a film while changing the raw material gas, the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

<Transistors with Metal Oxides>
Next, a case where a metal oxide (oxide semiconductor) is used for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer will be referred to as an OS transistor, and a transistor using silicon for a semiconductor layer will be referred to as a Si transistor.

By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.

An oxide semiconductor with a low carrier concentration is preferably used for the channel formation region of the transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is preferably 1×10 ¹⁸ cm ⁻³ or less, 1×10 ¹⁷ cm ⁻³ or less, 1×10 ¹⁶ cm ⁻³ or less, 1×10 ¹⁵ cm ⁻³ or less, 1×10 ¹⁴ cm ⁻³ or less, 1×10 ¹³ cm ⁻³ or less, 1×10 ¹² cm ⁻³ or less, 1×10 ¹¹ cm ⁻³ or less, or 1×10 ¹⁰ cm ⁻³ or less. The lower limit of the carrier concentration of the channel formation region is not particularly limited, but can be, for example, 1×10 ⁻⁹ cm ⁻³ .

Note that when the carrier concentration of the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

In addition, a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film may have a low density of trap states because of its low density of defect states.

In addition, the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a larger band gap than silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

In addition, in Si transistors, as transistors are miniaturized, a short channel effect (also referred to as Short Channel Effect: SCE) occurs. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.

The short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced). Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

In addition, the characteristic length is widely used as an index of resistance to short channel effects. Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.

OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.

Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, so that the energy difference between the conduction band bottom between the source region or drain region and the channel formation region can be reduced to 0.1 eV to 0.2 eV. Thus, the OS transistor can also be regarded as having an n ^{+ /} n ⁻ /n + accumulation-type junction-less transistor structure or an n ⁺ /n ⁻ /n ⁺ accumulation-type non-junction transistor structure in which the channel formation region is an n − type region and the source and drain regions are ^{n + type} regions.

By using the above-described structure, the OS transistor can have good electrical characteristics even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to achieve a gate length of 20 nm or less or 15 nm or less. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.

Furthermore, miniaturization of the OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is in any of the above ranges, the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.

<Impurities in metal oxides>
Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

As described above, if an oxide semiconductor contains a large amount of aluminum unintentionally, the physical properties of the oxide semiconductor may be affected. For example, if aluminum is present in an oxidized state (such as Al ₂ O ₃ ), the resistance of the oxide semiconductor increases. If an oxide semiconductor with a high resistance is used in a channel formation region of a transistor, the on-state current of the transistor decreases.

On the other hand, aluminum has a high bond dissociation energy with oxygen and functions as a carrier suppressing element. The presence of aluminum in an oxide semiconductor can make it difficult for oxygen vacancies (Vo) to be generated. If an oxide semiconductor in which Vo is unlikely to be generated is used in the channel formation region of a transistor, negative bias light photodegradation of the transistor can be suppressed.

Therefore, it is preferable to reduce the aluminum concentration in the oxide semiconductor so that the reliability and electrical characteristics of the transistor are both good. Alternatively, it is preferable to reduce the aluminum concentration extremely so that the on-state current of the transistor is sufficiently high.

For example, the aluminum concentration in the channel formation region of the oxide semiconductor obtained by STEM-EDX is preferably 0.01 atomic% or more, and preferably 10 atomic% or less, more preferably 5 atomic% or less, more preferably 3 atomic% or less, more preferably 1 atomic% or less, and even more preferably 0.1 atomic% or less. Or it may be 0.01 atomic% or less.

The aluminum concentration in the channel formation region of the oxide semiconductor measured by SIMS is preferably 1×10 ²² atoms/cm ³ or less, more preferably 1×10 ²¹ atoms/cm ³ or less, still more preferably 1×10 ²⁰ atoms/cm ³ or less, still more preferably 5×10 ¹⁹ atoms/cm ³ or less, still more preferably 1×10 ¹⁹ atoms/cm ³ or less, still more preferably 5×10 ¹⁸ atoms/cm ³ or less, and still more preferably 1×10 ¹⁸ atoms/cm ³ or less.

In principle, it is known that SIMS analysis is difficult to obtain accurate data near the sample surface and near the interface with a film of a different material. Therefore, when analyzing the concentration of a certain element in a film with SIMS, the average value in the region where there is no extreme fluctuation and an almost constant value is obtained is adopted as the concentration of the element. Furthermore, when the thickness of the film to be measured is small, it may not be possible to find a region where an almost constant value is obtained due to the influence of elements in adjacent films. In this case, the maximum or minimum value of the concentration of the element can be adopted as the concentration of the element in the film. Furthermore, if there is no peak indicating a maximum value or a valley indicating a minimum value, the value of the inflection point can be adopted as the concentration of the element.

The presence of aluminum and the state of the aluminum present can be confirmed by the Al2p spectrum obtained by XPS analysis of an oxide semiconductor. For example, if the peak position is in the range of 74.2 eV to 74.8 eV, it can be said that aluminum is present in an oxidized state.

When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁸ atoms/cm ³ or less, and further preferably 1×10 ¹⁸ atoms/cm ³ or less. The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁸ atoms/cm ³ or less, and still more preferably 1×10 ¹⁸ atoms/cm ³ or less.

Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, a trap state may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ^{3 or} less, and further preferably 5×10 ¹⁷ atoms/cm ³ or less.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, an electron serving as a carrier may be generated. In addition, some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 5×10 ¹⁸ atoms/cm ³ or less, and further preferably 1×10 ¹⁸ atoms/cm ³ or less.

In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be achieved.

<Film formation method 1>
Next, a method for forming a metal oxide film according to one embodiment of the present invention will be described below. In the following, a method for forming a metal oxide film using an ALD film formation apparatus (hereinafter also referred to as an ALD apparatus) will be described.

In the film forming apparatus using the ALD method, a first source gas (sometimes called a precursor, precursor, or metal precursor) for the reaction and a second source gas (sometimes called a reactant, reactant, oxidizer, or nonmetal precursor) are alternately introduced into the chamber, and the introduction of these source gases is repeated to form a film. The introduction of the source gas can be switched, for example, by switching the respective switching valves (sometimes called high-speed valves). In addition, when the source gas is introduced, an inert gas such as nitrogen (N ₂ ), argon (Ar), or helium (He) may be introduced into the chamber together with the source gas as a carrier gas. By using a carrier gas, even if the source gas has low volatility or low vapor pressure, it is possible to suppress the source gas from being adsorbed inside the piping and inside the valve, and to introduce the source gas into the chamber. In addition, the uniformity of the film formed is also improved, which is preferable.

An example of a method for forming a metal oxide film having a three-layered crystal structure, which is one aspect of the present invention, using the ALD method is described with reference to Figures 1A to 1E.

First, in the first step, as shown in FIG. 1A, precursor 11a is introduced into a chamber and the precursor 11a is adsorbed onto the surface of substrate 10.

As shown in FIG. 1A, when precursor 11a is adsorbed onto the surface of substrate 10, a self-terminating mechanism for the surface chemical reaction is activated, and precursor 11a is not further adsorbed onto the layer of precursor 11a on substrate 10. The appropriate range of substrate temperature within which the self-terminating mechanism for the surface chemical reaction operates is also called the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor.

Next, in the second step, an inert gas (e.g., argon, helium, or nitrogen) is introduced into the chamber to expel excess precursor 11a and reaction products from the chamber. The second step is also called purging.

In the second step, instead of introducing an inert gas into the chamber, a vacuum exhaust may be performed to remove excess precursors and reaction products from the chamber. In this specification, vacuum exhaust refers to exhausting at a pressure at least lower than atmospheric pressure (reduced pressure state).

Next, as a third step, as shown in FIG. 1B, a reactant 12a (e.g., an oxidizing agent) is introduced into the chamber and reacted with the precursor 11a adsorbed on the surface of the substrate 10, so that some of the components contained in the precursor 11a are desorbed while the metal elements constituting the precursor 11a are still adsorbed on the substrate 10. As a result, a layer of oxide 13a formed by oxidizing part of the precursor 11a is formed on the surface of the substrate 10.

The oxidizing agent may be ozone (O ₃ ), oxygen (O ₂ ), water (H ₂ O), nitrogen dioxide (N ₂ O), hydrogen peroxide (H ₂ O ₂ ), and plasma, radicals, ions, and the like of these.

When performing plasma ALD, oxygen may be constantly supplied as an oxidizing agent and plasma may be generated in the third step. As a result, oxygen plasma is formed in the third step and functions as reactant 12a. In this case, a precursor 11a that does not react with oxygen heated to the above temperature may be used in any step other than the third step.

Next, in the fourth step, excess reactant 12a and reaction products are discharged from the chamber by introducing an inert gas or evacuating the chamber.

Next, as shown in FIG. 1C, precursor 11b having a metal element different from precursor 11a is introduced, and a process similar to the first step is carried out to adsorb precursor 11b onto the surface of the oxide layer 13a.

Here, as shown in FIG. 1C, the precursor 11b is adsorbed to the layer of oxide 13a, and a self-terminating mechanism of the surface chemical reaction is activated, so that the precursor 11b is not further adsorbed onto the layer of precursor 11b on the substrate 10.

Next, as in the second step, excess precursor 11b and reaction products are removed from the chamber by introducing an inert gas or evacuating the chamber.

Next, as shown in FIG. 1D, reactant 12b is introduced into the chamber, and a process similar to the third step is carried out. As a result, a layer of oxide 13b, which is formed by oxidizing a portion of precursor 11b, is formed on the layer of oxide 13a.

Reactant 12b may be made of the same material as reactant 12a, or it may be made of a different material.

Next, as in the fourth step, excess reactant 12b and reaction products are discharged from the chamber by introducing an inert gas or evacuating the chamber.

Further, similarly, steps 1 to 4 are performed to form a layer of oxide 13c on the layer of oxide 13b. When forming the layer of oxide 13c, a compound having a metal element different from that of precursors 11a and 11b is used as the precursor. The reactant may be the same material as one or both of reactants 12a and 12b, or may be a material different from either of them.

In this way, by repeatedly performing the process of forming oxides 13a to 13c, a metal oxide having a layered crystal structure in which stacked structure 14 of oxides 13a to 13c is repeated can be formed (FIG. 1E). In other words, an oxide layer can be formed by performing steps 1 to 4 as one set (also referred to as one cycle), and by repeating this set, a layered crystal structure in which multiple oxide layers are stacked can be formed.

The thickness of the metal oxide with a layered crystal structure is preferably 1 nm or more and less than 100 nm, and more preferably 3 nm or more and less than 20 nm.

When forming a metal oxide with a layered crystal structure, particularly a metal oxide with a CAAC structure, the process shown in FIG. 1 is preferably performed while heating the substrate. The substrate temperature is preferably set to 200° C. or higher and 600° C. or lower, and more preferably 300° C. or higher and 450° C. or lower. The substrate temperature is preferably set to a temperature lower than the decomposition temperature of any of the precursors used. This allows the multiple types of precursors used to be adsorbed onto the target (e.g., substrate) during film formation by the ALD method without being decomposed.

By performing the above film formation while heating the substrate in such a temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be removed from the metal oxide in each of the first to fourth steps. For example, carbon in the metal oxide can be released as CO ₂ or CO. Also, for example, hydrogen in the metal oxide can be released as H ₂ O. Furthermore, at the same time as the removal of the above impurities, rearrangement of metal atoms and oxygen atoms can be performed, and each oxide layer can be arranged with high order. Therefore, a metal oxide with a highly crystalline layered crystal structure, particularly a metal oxide with a CAAC structure, can be formed.

Note that FIG. 1A illustrates an example of a configuration in which precursor 11a is adsorbed onto substrate 10, but is not limited to this. For example, an insulating film (insulating film having one or more of oxygen, nitrogen, silicon, aluminum, hafnium, etc.) or a conductive film (conductive film having one or more of tungsten, tantalum, molybdenum, zirconium, aluminum, titanium, etc.) may be provided on substrate 10, and precursor 11a may be adsorbed onto the insulating film. Alternatively, precursor 11a may be adsorbed onto a structure formed of an insulating film, a conductive film, etc. on substrate 10.

In order to form a film while heating the substrate within the above temperature range, it is preferable that the decomposition temperature of the precursor used in the film formation is not too low. On the other hand, if the decomposition temperature is too high, it is difficult to handle and the substrate temperature during film formation must be extremely high, which is not preferable. For example, the decomposition temperature of the precursor is preferably 200°C or higher and 700°C or lower, more preferably 300°C or higher and 650°C or lower, and even more preferably 400°C or higher and 600°C or lower.

Inorganic precursors contain less impurities such as hydrogen and carbon, and can prevent an increase in the impurity concentration in the metal oxide film being formed. On the other hand, inorganic precursors tend to have a higher decomposition temperature than organic precursors.

Therefore, in one embodiment of the present invention, a method for forming a metal oxide film uses an organic precursor, forms the film while heating the substrate, and performs an impurity removal process, thereby suppressing an increase in the impurity concentration in the metal oxide film being formed.

The frequency of the impurity removal treatment is not particularly limited. A higher frequency is preferable because it is easier to remove impurities, but there is a risk of lower productivity. A lower frequency is preferable because it is possible to shorten the time of the metal oxide film formation process, but there is a risk of impurities not being sufficiently removed. For example, it is preferable to repeat the process of forming oxides 13a to 13c and perform the impurity removal treatment each time multiple oxide layers are formed. For example, the impurity removal treatment can be performed each time one of oxides 13a to 13c is formed, but it is preferable to perform the impurity removal treatment each time multiple oxide layers are formed or multiple stacked structures 14 are formed, because this simplifies the process. Alternatively, the impurity removal treatment may be performed once after the metal oxide film formation is completed.

For example, the impurity removal treatment may be performed every time n oxide layers (n is an integer of 1 to 100, preferably an integer of 2 to 50, more preferably an integer of 5 to 30) are formed. For example, a metal oxide can be formed by repeatedly forming oxides 13a, 13b, 13c, 13a, and 13b in this order, performing the impurity removal treatment, forming oxides 13c, 13a, 13b, 13c, and 13a in this order, performing the impurity removal treatment, forming oxides 13b, 13c, 13a, 13b, and 13c in this order, and performing the impurity removal treatment.

In addition, for example, an impurity removal process may be performed every time m layers (m is an integer between 1 and 50, preferably between 2 and 30, more preferably between 5 and 10) of the laminate structure 14 are formed.

As mentioned above, examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment. The impurity removal treatment may also be performed while irradiating light.

The chamber in which the impurity removal process is performed may be the same as the chamber in which the first to fourth steps are performed, or it may be a different chamber. In other words, the chamber for film formation and the chamber for impurity removal process may be the same or different.

When performing plasma treatment or microwave treatment, the substrate temperature is preferably set to room temperature (e.g., 25°C) or higher, 100°C or higher, 200°C or higher, 300°C or higher, or 400°C or higher, and 500°C or lower, or 450°C or lower. The temperature of the heat treatment is preferably set to 100°C or higher, 200°C or higher, 300°C or higher, or 400°C or higher, and 500°C or lower, or 450°C or lower. The temperature during the impurity removal treatment is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of the transistor or semiconductor device, in particular, so that the content of impurities in the metal oxide can be reduced without reducing productivity.

When oxygen plasma is used in the third step described above, the processing time of the third step can be extended to allow the plasma treatment to also function as an impurity removal treatment. For example, the third step can be performed once out of multiple times for a longer processing time than the other times, making it a process that also serves as an impurity removal treatment.

Here, microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves. Furthermore, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave processing can also be called microwave-excited high-density plasma processing.

In the microwave treatment, it is preferable to use a microwave treatment device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be set to, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves in the microwave treatment device is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less. In addition, the microwave treatment device may have a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the film.

The microwave treatment is preferably carried out under reduced pressure, with the pressure being preferably from 10 Pa to 1000 Pa, and more preferably from 300 Pa to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300°C to 500°C, and can be from 400°C to 450°C.

Furthermore, after the microwave treatment or plasma treatment, a heat treatment may be performed continuously without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

The microwave treatment can be performed using, for example, oxygen gas and argon gas. Here, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 10% and less than 40%. Even more preferably, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 10% and less than 30%.

The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas to about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed. The heat treatment may be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less).

It is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and other substances from being incorporated into the metal oxide as much as possible.

By performing the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as _CO2 and CO, and hydrogen in the metal oxide can be released as _H2O .

It is preferable to perform a heat treatment after the metal oxide film is formed (after forming all the stacked structure 14 with a predetermined number of layers and before forming a film of another material or another composition). In particular, it is preferable to perform a heat treatment continuously without exposing the film to the outside air after the film is formed by the ALD method. This allows the heat treatment to be performed after the metal oxide film is formed without increasing impurities such as hydrogen or carbon in the film. The heat treatment is preferably performed at 100°C or higher and 500°C or lower, more preferably 200°C or higher and 500°C or lower, even more preferably 250°C or higher and 500°C or lower, even more preferably 300°C or higher and 500°C or lower, even more preferably 350°C or higher and 450°C or lower, and even more preferably 400°C or higher and 450°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in a nitrogen gas or inert gas atmosphere, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been released.

By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as _CO2 and CO, and hydrogen in the metal oxide can be released as _H2O . Furthermore, at the same time as removing the impurities, rearrangement of metal atoms and oxygen atoms can be carried out, improving crystallinity. Therefore, a metal oxide having a highly crystalline layered crystal structure, particularly a metal oxide having the above CAAC structure, can be formed.

In addition, after forming the metal oxide film, plasma treatment or microwave treatment may be performed.

1, the stack structure 14 of oxides 13a to 13c is repeated, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more oxide layers are repeatedly formed may be used. In addition, in FIG. 1, the oxides 13a, 13b, and 13c are repeatedly stacked without changing the order, but the present invention is not limited to this. For example, the order of the oxides 13a, 13b, and 13c may be changed each time the layers are stacked. In addition, the composition of the oxides 13a, 13b, and 13c may be changed in the middle of the film. In addition, in FIG. 1, different oxide layers are provided adjacent to each other, such as oxide 13a, oxide 13b, and oxide 13c, but the present invention is not limited to this. For example, a structure in which the same oxide layers are continuously provided, such as oxide 13a, oxide 13a, oxide 13b, oxide 13b, oxide 13c, and oxide 13c, may be used.

In addition, unless otherwise specified, in the following description of this specification, when ozone, oxygen, or water is used as a reactant or oxidant, these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states. When forming a film using an oxidant in a plasma, radical, or ionic state, a radical ALD device or plasma ALD device described below may be used.

To remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to react the precursor with the oxidizing agent sufficiently. For example, the pulse time for introducing the oxidizing agent may be increased. In the metal oxide film formation process, examples of the preferred time for supplying the oxidizing agent in one cycle are as described above. Alternatively, the oxidizing agent may be introduced multiple times. When the oxidizing agent is introduced multiple times, the same type of oxidizing agent may be introduced, or different types of oxidizing agents may be introduced. For example, water may be introduced into the chamber as the first oxidizing agent, and then the chamber may be evacuated, and ozone or oxygen not containing hydrogen may be introduced into the chamber as the second oxidizing agent, and then the chamber may be evacuated.

In the above description, an example is shown in which the first source gas is introduced into the chamber and then the second source gas is introduced into the chamber, but the present invention is not limited to this. The second source gas may be introduced into the chamber and then the first source gas may be introduced into the chamber. In other words, the third step and the fourth step may be performed first, and then the first step, the second step, the third step, and the fourth step may be performed, and thereafter the first step to the fourth step may be repeated to form a film. Furthermore, the third step and the fourth step may be repeated multiple times, and then the first step to the fourth step may be repeated to form a film.

In this way, it is preferable to perform the third step and the fourth step once or multiple times before the first step, since the film formation atmosphere in the chamber can be controlled. For example, in the third step, O ₃ and O ₂ can be introduced as oxidizing agents to create an oxygen atmosphere in the chamber. By forming a film in an oxygen atmosphere in the chamber, the oxygen concentration in the film to be formed can be increased, which is preferable. Furthermore, oxygen can be supplied to the insulator and oxide that are the base of the film. A semiconductor device formed using such a method has good characteristics and can obtain high reliability. Also, for example, in the third step, water can be introduced as an oxidizing agent to form a hydrophilic group on the formation surface. This can further improve the adsorption of the precursor.

Furthermore, after the first and second steps, the introduction of the second raw material gas in the third step and the vacuum evacuation or introduction of the inert gas in the fourth step may be repeated multiple times. In other words, the first and second steps may be performed after the first, second, third, fourth, third, fourth steps, third, fourth steps, and so on.

For example, _O3 and _O2 may be introduced as oxidizing agents in the third step, and an inert gas may be introduced in the fourth step, and this process may be repeated multiple times. When the third step and the fourth step are repeated, it is not necessary to repeatedly introduce the same type of raw material gas. For example, _H2O may be used as an oxidizing agent in the first third step, and _O3 may be used as an oxidizing agent in the second or subsequent third steps.

In this way, by repeating the introduction of an oxidizing agent and the introduction of an inert gas (or evacuation) multiple times within a short period of time within the chamber, excess hydrogen atoms, carbon atoms, etc. can be more reliably removed from the precursor adsorbed to the substrate surface and expelled from the chamber. Also, by increasing the number of types of oxidizing agents to two, more excess hydrogen atoms, etc. can be removed from the precursor adsorbed to the substrate surface. In this way, by preventing hydrogen atoms from being incorporated into the film during film formation, the amount of water, hydrogen, etc. contained in the formed film can be reduced.

By using such a method, it is possible to form a film in which the amount of desorbed water molecules is 1.0×10 ¹³ molecules/cm ² to 1.0×10 ¹⁶ molecules/cm ² , preferably 1.0×10 ¹³ molecules/cm ² to 3.0×10 ¹⁵ molecules/cm ² , in the surface temperature range of 100° C. to 700° C. or 100° C. to 500° C. as determined by TDS analysis.

The ALD method is a film formation method in which precursors and reactants are reacted using thermal energy. The temperature required for the reaction of the precursors and reactants is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., but is 100°C to 600°C, preferably 200°C to 600°C, and more preferably 300°C to 600°C.

In addition to the above precursor and reactant reactions, the ALD method in which a plasma-excited reactant is introduced into the chamber as a third source gas is sometimes called the plasma ALD method. In this case, a plasma generating device is provided at the introduction point of the third source gas. Inductively Coupled Plasma (ICP) can be used to generate plasma. In contrast, the ALD method in which the precursor and reactant react using thermal energy is sometimes called the thermal ALD method.

In the plasma ALD method, a plasma-excited reactant is introduced in the third step to form a film. Alternatively, the first to fourth steps are repeated and a plasma-excited reactant (second reactant) is introduced at the same time to form a film. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the second reactant used in the third raw material gas can be made of a material similar to the oxidizing agent. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizing agent, a nitriding agent may be used as the second reactant. As the nitriding agent, nitrogen (N ₂ ) or ammonia (NH ₃ ) can be used. Also, a mixed gas of nitrogen (N ₂ ) and hydrogen (H ₂ ) can be used as the nitriding agent. For example, a mixed gas of 5% nitrogen (N ₂ ) and 95% hydrogen (H ₂ ) can be used as the nitriding agent. By carrying out film formation while introducing plasma-excited nitrogen or ammonia, a nitride film such as a metal nitride film can be formed.

In addition, argon (Ar), helium (He) or nitrogen (N ₂ ) may be used as the carrier gas of the second reactant. By using a carrier gas such as argon, helium or nitrogen, plasma discharge becomes easy, and the plasma-excited second reactant is easily generated, so it is preferable. In addition, when forming an oxide film such as a metal oxide film using the plasma ALD method, if nitrogen is used as the carrier gas, nitrogen may be mixed into the film, and the desired film quality may not be obtained. In this case, it is preferable to use argon or helium as the carrier gas.

The ALD method can deposit extremely thin films with uniform thickness. It also has a high surface coverage rate, even on uneven surfaces.

Furthermore, by forming a film using the plasma ALD method, it is possible to form a film at an even lower temperature than with the thermal ALD method. For example, with the plasma ALD method, it is sometimes possible to form a film at temperatures below 100°C without reducing the film formation rate.

In addition, when performing plasma ALD, plasma damage can be reduced by generating plasma from a plasma source such as an inductively coupled plasma (ICP) or electron cyclotron resonance plasma (ECR) away from the substrate.

<Atomic arrangement in metal oxide crystals>
Here, the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide will be described with reference to Figures 2A to 2D and Figures 3A to 3D. In Figures 2B, 2D, 3B, and 3D, atoms are represented by spheres (circles), and bonds between metal atoms and oxygen atoms are represented by lines. In Figures 2B, 2D, 3B, and 3D, the c-axis direction in the crystal structure of In-M-Zn oxide is represented by an arrow in the figure (c-axis). In addition, the a-b plane direction in the crystal structure of In-M-Zn oxide is perpendicular to the c-axis direction represented by the arrow in Figures 2B, 2D, 3B, and 3D.

Figure 2A is a diagram showing an oxide 60 having an In-M-Zn oxide formed on a structure 50. Here, the structure refers to an element that constitutes a semiconductor device such as a transistor. The structure 50 includes conductors such as a substrate, a gate electrode, a source electrode, and a drain electrode, insulators such as a gate insulating film, an interlayer insulating film, and a base insulating film, and semiconductors such as metal oxides or silicon. Figure 2A shows a case where the surface of the structure 50 to be deposited is arranged parallel to the substrate (not shown).

Fig. 2B is an enlarged view showing the atomic arrangement in a crystal in a region 53 which is a part of the oxide 60 in Fig. 2A. The composition of the oxide 60 shown in Fig. 2A and Fig. 2B is In:M:Zn = 1:1:1 [atomic ratio], and the crystal structure is a _{YbFe2O4 type} structure. The element M is a metal element with a valence of +3.

As shown in FIG. 2B, the crystals of oxide 60 are formed by repeatedly stacking a layer 21 having indium (In) and oxygen, a layer 31 having element M and oxygen, and a layer 41 having zinc (Zn) and oxygen, in that order. Layers 21, 31, and 41 are arranged parallel or approximately parallel to the deposition surface of structure 50. That is, the a-b plane of oxide 60 is parallel or approximately parallel to the deposition surface of structure 50, and the c-axis of oxide 60 is parallel or approximately parallel to the normal direction of the deposition surface of structure 50.

As shown in FIG. 2B, each of layers 21, 31, and 41 of the crystal is composed of one metal element and oxygen, and is arranged with good crystallinity, which increases the mobility of the metal oxide.

Note that the In-M-Zn oxide with an atomic ratio of In:M:Zn = 1:1:1 is not limited to the structure shown in FIG. 2B. The order of stacking layers 21, 31, and 41 may be changed. For example, layers 21, 41, and 31 may be repeatedly stacked in this order. Alternatively, layers 21, 31, 41, 21, 41, and 31 may be repeatedly stacked in this order. Furthermore, part of the element M in layer 31 may be replaced with zinc, and part of the zinc in layer 41 may be replaced with element M.

In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] has been shown, but a crystalline In-M-Zn oxide having a composition formula of In _(1+α) M _{(1-α) O3} (ZnO) _m (α is a real number greater than 0 and less than 1, and m is a positive number) can also have a layered crystal structure. As an example, an In-M-Zn oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] is shown using Figures 2C and 2D.

Figure 2C shows an oxide 62 having an In-M-Zn oxide formed on the structure 50. Figure 2D is an enlarged view showing the atomic arrangement in the crystal in region 54, which is part of the oxide 62 in Figure 2C.

2D, the crystal of oxide 62 has layer 23 having indium (In), element M, and oxygen, layer 41 having zinc (Zn) and oxygen, and layer 31 having element M and oxygen. In oxide 62, multiple layers are repeatedly stacked in the order of layer 23, layer 41, layer 31, and layer 41. Layer 23, layer 31, and layer 41 are arranged parallel or approximately parallel to the deposition surface of structure 50. In other words, the a-b plane of oxide 62 is parallel or approximately parallel to the deposition surface of structure 50, and the c-axis of oxide 62 is parallel or approximately parallel to the normal direction of the deposition surface of structure 50.

Note that the In-M-Zn oxide with an atomic ratio of In:M:Zn = 1:3:4 is not limited to the structure shown in FIG. 2D, and the structure may be changed within the range of the atomic ratio of In:M:Zn = 1:3:4. For example, the stacking order of layers 23, 31, and 41 may be changed. Also, part of the element M in layer 31 may be replaced with zinc, and part of the zinc in layer 41 may be replaced with element M. Also, layer 21 or layer 31 may be formed instead of layer 23.

Alternatively, as shown in FIG. 3A, a laminated structure may be formed in which oxide 62 is formed on structure 50, and oxide 60 is formed on top of that. Here, FIG. 3B is an enlarged view showing the atomic arrangement in the crystal in region 56, which is a part of oxide 62 and oxide 60 in FIG. 3A.

As described above, oxide 62 is an In-M-Zn oxide with an atomic ratio of In:M:Zn = 1:3:4, and oxide 60 is an In-M-Zn oxide with an atomic ratio of In:M:Zn = 1:1:1. In other words, the oxide shown in FIG. 3A is an oxide film in which the atomic ratio changes midway through the film. In addition, as shown in FIG. 3B, by forming oxide 62 into a layered crystal structure, the crystallinity of oxide 60 on oxide 62 can be improved.

Note that the oxide 62 and the oxide 60 are not limited to the structure shown in FIG. 3B, and as described above, the structures of the oxide 62 and the oxide 60 may be changed. In addition, in FIG. 3B, the layer 21 is disposed at the boundary between the oxide 62 and the oxide 60, but this is not limited thereto. For example, the layer 23 may be formed at the boundary between the oxide 62 and the oxide 60.

As described above, the ALD method allows deposition on structures with high aspect ratios, and allows deposition with excellent coverage on the side surfaces of structures. By using the ALD method, crystalline metal oxides such as CAAC structures can be easily formed regardless of the orientation of the surface to be deposited. For example, even if the structure has a convex or concave shape, metal oxides can be formed with good coverage on the top, bottom, side, and inclined surfaces of the structure. That is, metal oxides having an approximately constant film thickness in the normal direction can be formed on each surface to be deposited. In the metal oxides formed on the top, bottom, side, and inclined surfaces of the structure, the ratio of the minimum film thickness to the maximum film thickness can be 0.5 to 1, preferably 0.7 to 1, and more preferably 0.9 to 1. In this case, when the metal oxide has a crystalline structure, its c-axis is oriented in a direction approximately parallel to the normal direction of each surface to be deposited. That is, the c-axis is oriented perpendicular to each surface to be deposited.

Here, FIG. 3C shows a case where the deposition surface of the structure 50 is arranged perpendicular to the substrate (not shown), and an oxide 64 is formed on the surface of the structure 50. FIG. 3D is an enlarged view of a region 58 which is a part of the oxide 64 in FIG. 3C. FIG. 3D shows a state where a layer 21 containing indium (In), a layer 31 containing element M, and a layer 41 containing zinc (Zn) are stacked on the side surface of the structure 50. The layer 21 containing indium is arranged parallel or approximately parallel to the deposition surface of the structure 50, the layer 31 containing element M is arranged parallel or approximately parallel to the deposition surface of the structure 50 thereon, and the layer 41 containing zinc is arranged parallel or approximately parallel to the deposition surface of the structure 50 thereon. That is, the a-b plane of the oxide 60 is parallel or approximately parallel to the deposition surface of the structure 50, and the c-axis of the oxide 60 is parallel or approximately parallel to the normal direction of the deposition surface of the structure 50. Note that in Figures 3C and 3D, an example of In-M-Zn oxide with an atomic ratio of In:M:Zn = 1:1:1 is shown, but oxides with different atomic ratios can also be formed on the surface of a structure 50 whose deposition surface is arranged perpendicular to the substrate.

In addition, in the above, examples of metal oxides with an atomic ratio of In:M:Zn = 1:1:1 and an atomic ratio of In:M:Zn = 1:3:4 are shown, but the present invention is not limited to these.

Below, the preferred range of the atomic ratio of indium, element M, and zinc in a metal oxide that can be used in the oxide shown in one embodiment of the present invention will be described with reference to Figures 4A, 4B, and 4C. Note that the atomic ratio of oxygen is not shown in Figures 4A, 4B, and 4C. The terms for the atomic ratio of indium, element M, and zinc in a metal oxide are [In], [M], and [Zn], respectively.

In Figures 4A, 4B, and 4C, the dashed lines represent the line where the atomic ratio of [In]:[M]:[Zn] = (1+α):(1-α):1 (-1≦α≦1), the line where the atomic ratio of [In]:[M]:[Zn] = (1+α):(1-α):2, the line where the atomic ratio of [In]:[M]:[Zn] = (1+α):(1-α):3, the line where the atomic ratio of [In]:[M]:[Zn] = (1+α):(1-α):4, and the line where the atomic ratio of [In]:[M]:[Zn] = (1+α):(1-α):5.

The dotted and dashed lines represent the line where the atomic ratio of [In]:[M]:[Zn] = 5:1:β (β≧0), the line where the atomic ratio of [In]:[M]:[Zn] = 2:1:β, the line where the atomic ratio of [In]:[M]:[Zn] = 1:1:β, the line where the atomic ratio of [In]:[M]:[Zn] = 1:2:β, the line where the atomic ratio of [In]:[M]:[Zn] = 1:3:β, and the line where the atomic ratio of [In]:[M]:[Zn] = 1:4:β.

In addition, metal oxides with atomic ratios of [In]:[M]:[Zn]=0:2:1, and those close to this ratio, as shown in Figures 4A, 4B, and 4C, tend to have a spinel-type crystal structure.

In addition, multiple phases may coexist in a metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn] = 0:2:1, two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. In addition, when the atomic ratio is close to [In]:[M]:[Zn] = 1:0:0, two phases, a bixbyite-type crystal structure and a layered crystal structure, tend to coexist. When multiple phases coexist in a metal oxide, grain boundaries may be formed between the different crystal structures.

Area A in FIG. 4A shows an example of a preferred range of atomic ratios of indium, element M, and zinc in the metal oxide.

By increasing the indium content of a metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide with a high indium content has a higher carrier mobility than a metal oxide with a low indium content.

On the other hand, as the content of indium and zinc in the metal oxide decreases, the carrier mobility decreases. Therefore, when the atomic ratio is [In]:[M]:[Zn]=0:1:0 or a value close to that (for example, region C shown in FIG. 4C), the insulating properties are high. Note that region C includes the aforementioned region that is likely to have a spinel crystal structure, so it is preferable to have a composition that avoids the region that is likely to have a spinel crystal structure.

For example, the metal oxide used in the channel formation region and the low resistance region preferably has an atomic ratio shown in region A of FIG. 4A, which has high carrier mobility. The metal oxide used in the channel formation region and the low resistance region may have, for example, In:Ga:Zn = 4:2:3 to 4.1, or a value close thereto. Also, for example, In:Ga:Zn = 1:1:1, or a value close thereto. On the other hand, when the metal oxide is provided so as to surround the channel formation region and the low resistance region, it is preferable to have an atomic ratio shown in region C of FIG. 4C, which has relatively high insulation. The metal oxide provided so as to surround the channel formation region and the low resistance region may have, for example, In:Ga:Zn = 1:3:4, or a value close thereto, or In:Ga:Zn = 1:3:2, or a value close thereto. Alternatively, the metal oxide provided so as to surround the channel formation region and the low resistance region may be the same as the metal oxide used in the channel formation region and the low resistance region.

In particular, in region B shown in FIG. 4B, even among regions A, excellent metal oxides with high carrier mobility and high reliability can be obtained.

Region B includes [In]:[M]:[Zn] = 4:2:3 to 4.1 and adjacent values. Nearby values include, for example, [In]:[M]:[Zn] = 5:3:4. Region B also includes [In]:[M]:[Zn] = 5:1:6 and adjacent values, and [In]:[M]:[Zn] = 5:1:7 and adjacent values. Region B also includes [In]:[M]:[Zn] = 1:1:1 and adjacent values.

As described above, the electrical conductivity characteristics of the metal oxide vary greatly depending on the atomic ratio. By forming a metal oxide film using the ALD method as described above, it is possible to form a metal oxide film having a layered crystal structure according to each atomic ratio. Therefore, by using the ALD method, it is possible to form a metal oxide film according to the desired characteristics.

<Film formation method 2>
Next, a method for forming the oxide 60 having the In-M-Zn oxide shown in FIGS. 2A and 2B will be described in detail with reference to FIGS. 5A to 5D and FIGS. 6A to 6C.

First, as shown in FIG. 5A, a raw material gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the structure 50.

The aluminum content of the indium-containing precursor is preferably 0.001 ppm or more, 0.01 ppm or more, or 0.1 ppm or more, and is preferably 1000 ppm or less, more preferably 500 ppm or less, more preferably 100 ppm or less, more preferably 50 ppm or less, more preferably 10 ppm or less, and even more preferably 1 ppm or less. The aluminum content of the indium-containing precursor may be 0.001 ppm or less.

In addition, as the precursor used in this embodiment, it is preferable to use a precursor that has been purified by performing distillation (also called rectification) two or more times. By using such a precursor, it is easy to form a film of a metal oxide with few impurities, which is preferable. By performing distillation multiple times, it is possible to further suppress impurities caused by the starting materials used in the production of the precursor from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor that has been distilled once, i.e., purified by simple distillation, may be used. By using simple distillation, it is possible to reduce production costs, which is preferable.

Here, the precursor-containing raw material gas includes, in addition to the precursor, a carrier gas such as argon, helium, or nitrogen.

Examples of precursors containing indium include trimethylindium (structural formula (101) below), triethylindium (structural formula (102) below), ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, dimethyl(2-propanolato)indium, trifluoroindium (indium(III) fluoride), indium(III) chloride, indium(III) bromide, and indium(III) iodide.

Next, the introduction of the source gas is stopped, and the chamber is purged to remove excess precursors and reaction products from the chamber.

Next, as shown in FIG. 5B, an oxidizing agent containing oxygen is introduced into the chamber as a reactant and reacted with the adsorbed precursor, so that components other than indium are desorbed while leaving indium adsorbed on the substrate, thereby forming a layer 21 in which indium and oxygen are combined.

As the oxidizing agent, ozone (O ₃ ), oxygen (O ₂ ), water (H ₂ O), nitrogen dioxide (N ₂ O), hydrogen peroxide (H ₂ O ₂ ), and plasma, radicals, and ions thereof can be used.

When supplying the oxidizing agent, the proportion of ozone in the gas is preferably 10% or more, more preferably 20% or more, more preferably 30% or more, more preferably 40% or more, more preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and particularly preferably 100%. A higher proportion of ozone is preferable because it promotes the oxidation of the metal and reduces the carbon concentration in the metal oxide.

Then, the introduction of the oxidant is stopped, and the chamber is purged to remove excess reactants and reaction products from the chamber.

Next, as shown in FIG. 5C, a source gas containing a precursor having element M is introduced into the chamber, and the precursor is adsorbed onto layer 21. Here, it is preferable to use gallium or tin as element M.

The aluminum content of the precursor having element M is preferably 0.001 ppm or more, 0.01 ppm or more, or 0.1 ppm or more, and is preferably 1000 ppm or less, more preferably 500 ppm or less, more preferably 100 ppm or less, more preferably 50 ppm or less, more preferably 10 ppm or less, and even more preferably 1 ppm or less. The aluminum content of the precursor having element M may also be 0.001 ppm or less.

Examples of precursors having gallium include trimethylgallium, triethylgallium (structural formula (103) below), tris(dimethylamido)gallium (structural formula (104) below), triphenylgallium, diethyl(3-methyl-2,4-cyclopropanediene-1-yl)gallium, [4-(1,1-dimethyl)phenyl]dimethylgallium, dimethyl(4-methylphenyl)gallium, dimethylphenylgallium, methyldiphenylgallium, ethyldimethylgallium, dimethylmethylenegallium, gallium(III) acetylacetonate, tris(2,2 ,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethyl(2-methyl-2-propanolato)gallium, methoxydimethylgallium, hydroxydimethylgallium, (methanethiolato)dimethylgallium, chlorodimethylgallium, chlorodiethylgallium, chlorodipropylgallium, bromodimethylgallium, bromodiethylgallium, dimethyliodogallium, chlorobis(2,2-dimethylpropyl)gallium, gallium(III) fluoride, gallium(III) chloride, gallium(III) bromide, and gallium(III) iodide.

Examples of precursors containing tin include tetramethyltin, tetraethyltin, tetraethenyltin, tetraallyltin, tributylvinyltin, allyltributyltin, tributylstannylacetylene, tributylphenyltin, chlorotrimethyltin, chlorotriethyltin, tin(IV) fluoride, tin(IV) chloride, tin(IV) bromide, and tin(IV) iodide.

Next, the introduction of the source gas is stopped, and the chamber is purged to remove excess precursors and reaction products from the chamber.

Next, as shown in FIG. 5D, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, so that the components other than element M are desorbed while element M is still adsorbed on the substrate, thereby forming layer 31 in which element M is combined with oxygen. At this time, some of the oxygen adsorbed on layer 31 may constitute layer 41, which will be described later.

Then, the introduction of the oxidant is stopped, and the chamber is purged to remove excess reactants and reaction products from the chamber.

Next, as shown in FIG. 6A, a raw material gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto layer 31. At this time, a part of layer 41 in which zinc and oxygen are combined may be formed.

The aluminum content of the zinc-containing precursor is preferably 0.001 ppm or more, 0.01 ppm or more, or 0.1 ppm or more, and is preferably 1000 ppm or less, more preferably 500 ppm or less, more preferably 100 ppm or less, more preferably 50 ppm or less, more preferably 10 ppm or less, and even more preferably 1 ppm or less. The aluminum content of the zinc-containing precursor may also be 0.001 ppm or less.

Examples of precursors containing zinc include dimethylzinc, diethylzinc (structural formula (105) below), bis(1-methylethyl)zinc, bis(1,1-dimethylethyl)zinc, dibutylzinc, diethenylzinc, dicyclohexylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionate)zinc, zinc fluoride, zinc chloride, chloromethylzinc, zinc bromide, bromomethylzinc, and zinc iodide.

Next, the introduction of the source gas is stopped, and the chamber is purged to remove excess precursors and reaction products from the chamber.

Next, as shown in FIG. 6B, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer 41 in which zinc and oxygen are combined.

Here, the total time for supplying the oxidizing agent in the three steps shown in Figures 5B, 5D, and 6B is preferably 10 seconds or more, more preferably 30 seconds or more, more preferably 60 seconds or more, more preferably 90 seconds or more, even more preferably 120 seconds or more, and preferably 150 seconds or less, 200 seconds or less, 250 seconds or less, or 300 seconds or less.

The longer the time for which the oxidizing agent is supplied, the more the carbon concentration in the oxide 60 can be reduced, which is preferable. On the other hand, the shorter the time for which the oxidizing agent is supplied, the shorter the time required to form the oxide 60, which is preferable.

Then, the introduction of the oxidant is stopped, and the chamber is purged to remove excess reactants and reaction products from the chamber.

Next, layer 21 is formed again on layer 41 by the method described above (FIG. 6C). By repeating the above method, oxide 60 can be formed on the substrate or structure.

Here, an example of the precursors listed above is shown below.

Note that the precursors listed above include those that contain, in addition to metal elements, either or both of carbon and chlorine. Films formed using precursors that contain carbon may contain carbon. Films formed using precursors that contain halogens such as chlorine may contain halogens such as chlorine.

The steps shown in FIGS. 5A to 5D and 6A to 6C are preferably performed while heating the substrate. For example, the substrate temperature is preferably 150° C. or more, 200° C. or more, or 250° C. or more. Also, it is preferable to set the substrate temperature to 600° C. or less, 500° C. or less, 450° C. or less, 400° C. or less, or the decomposition temperature of the precursor or less. Also, when ozone is used as the oxidizing agent, it is preferable to set the temperature to the decomposition temperature of ozone or less. By performing the above film formation while heating the substrate in such a temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be removed from the metal oxide in each process of FIGS. 5A to 6C. For example, carbon in the metal oxide can be released as CO ₂ and CO, and hydrogen in the metal oxide can be released as H ₂ O. Furthermore, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms can be performed, and each oxide layer can be arranged in a highly orderly manner. Therefore, a metal oxide having a crystalline portion can be formed. Furthermore, a metal oxide having a highly crystalline layered crystal structure, for example, a metal oxide having a CAAC structure, can be formed.

It is preferable to perform the above-mentioned impurity removal process intermittently during the formation of the oxide 60. For example, it is preferable to perform the above-mentioned impurity removal process every time the three-layer structure of the layers 21, 31, and 41 is formed n times (n is an integer of 1 to 50, preferably an integer of 2 to 30, more preferably an integer of 5 to 10). It is also preferable to perform the impurity removal process after the formation of the oxide 60.

By carrying out the impurity removal treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as _CO2 and CO, and hydrogen in the metal oxide can be released as _H2O . Furthermore, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms can be performed, and crystallinity can be improved. Thus, a metal oxide having a crystalline portion can be formed. In addition, a metal oxide having a highly crystalline layered crystal structure, particularly a metal oxide having the above CAAC structure, can be formed.

As described above, by forming oxide 60 using the ALD method, it is possible to form a metal oxide having a CAAC structure in which the c-axis is oriented approximately parallel to the normal direction of the deposition surface.

5A to 5D and 6A to 6C show an example in which layer 21 is formed as a layer containing indium, layer 31 is formed thereon as a layer containing element M, and layer 41 is further formed thereon as a layer containing zinc, but this embodiment is not limited to this. One of layer 31 and layer 41 may be formed, layer 21 may be formed thereon, and the other of layer 31 and layer 41 may be formed thereon. Alternatively, one of layer 31 and layer 41 may be formed, the other of layer 31 and layer 41 may be formed thereon, and layer 21 may be formed thereon.

When forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], the above layers 21, 31, and 41 may be formed appropriately according to the atomic ratio. For example, as shown in FIG. 6A, the formation of layer 41 may be repeated multiple times before and after the formation of layer 31, thereby forming a stack of layers 31 and 41 between two layers 21 having the desired number of atoms, number of layers, and thickness.

When manufacturing various semiconductor devices, both the metal oxide of one embodiment of the present invention and another metal oxide may be used. For example, the metal oxide of one embodiment of the present invention may be used in combination with a metal oxide having at least one of indium and zinc and aluminum (which may further contain at least one of gallium and tin).

Examples of metal oxides containing at least one of indium and zinc and aluminum include indium gallium aluminum oxide (In-Ga-Al oxide), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO).

Examples of precursors containing aluminum include trimethylaluminum, triethylaluminum, chlorodimethylaluminum, dichloromethylaluminum, bromodimethylaluminum, iododimethylaluminum, aluminum acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)aluminum, dimethylchloroaluminum, diethylchloroaluminum, aluminum(III) chloride, aluminum(III) bromide, and aluminum(III) iodide.

<Film forming equipment>
As an example of an apparatus capable of forming a film by the ALD method, the configuration of a film forming apparatus 4000 will be described with reference to Fig. 7 to Fig. 10. Fig. 7 is a schematic diagram of a multi-chamber type film forming apparatus 4000, and Figs. 8 to 10 are cross-sectional views of an ALD apparatus that can be used for the film forming apparatus 4000.

The film forming apparatus 4000 shown in FIG. 7 has a loading/unloading chamber 4002, a loading/unloading chamber 4004, a transfer chamber 4006, a film forming chamber 4008, a film forming chamber 4009, a treatment chamber 4011, and a transfer arm 4014. Here, the loading/unloading chamber 4002, the loading/unloading chamber 4004, the film forming chamber 4008, the film forming chamber 4009, and the treatment chamber 4011 are independently connected to the transfer chamber 4006 via gate valves. This allows continuous processing to be performed in the film forming chamber 4008, the film forming chamber 4009, and the treatment chamber 4011 without exposure to the atmosphere, and prevents impurities from being mixed into the film. In addition, contamination of the interface between the substrate and the film and the interface between each film is reduced, and clean interfaces are obtained.

Note that the loading/unloading chamber 4002, the loading/unloading chamber 4004, the transfer chamber 4006, the film-forming chamber 4008, the film-forming chamber 4009, and the processing chamber 4011 are preferably filled with an inert gas (such as nitrogen gas) with a controlled dew point to prevent moisture from adhering thereto, and it is desirable to maintain a reduced pressure.

An ALD device can be used in the film formation chamber 4008 and the film formation chamber 4009. Also, a film formation device other than an ALD device may be used in either the film formation chamber 4008 or the film formation chamber 4009. Examples of film formation devices that can be used in the film formation chamber 4008 and the film formation chamber 4009 include a sputtering device, a plasma enhanced CVD (PECVD: Plasma CVD) device, a thermal CVD (TCVD: Thermal CVD) device, a photo CVD (Photo CVD) device, a metal CVD (MCVD: Metal CVD) device, and a metal organic CVD (MOCVD: Metal CVD) device.

In addition, it is preferable to use a device having functions other than those of a film forming device, such as a heating device (typically, a vacuum heating device) or a plasma generating device (typically, a microwave processing device) in the processing chamber 4011.

For example, when the deposition chamber 4008 is an ALD device, the deposition chamber 4009 is a sputtering device, and the treatment chamber 4011 is a heating device, a base insulating film can be formed in the deposition chamber 4009, an oxide semiconductor film that functions as an active layer can be formed in the deposition chamber 4008, and a heat treatment can be performed after the oxide semiconductor film is formed in the treatment chamber 4011. At this time, the deposition of the base insulating film, the deposition of the oxide semiconductor film, and the heat treatment can be performed consecutively without exposure to the air. Therefore, after the metal oxide film is formed, the heat treatment can be performed without increasing impurities such as hydrogen or carbon in the film.

In addition, the film formation apparatus 4000 is configured to have a loading/unloading chamber 4002, a loading/unloading chamber 4004, a film formation chamber 4008, a film formation chamber 4009, and a processing chamber 4011, but the present invention is not limited to this. The film formation apparatus 4000 may be configured to have one film formation chamber, or three or more. The film formation apparatus 4000 may be configured to have two or more processing chambers. The film formation apparatus 4000 may be of a single-wafer type, or a batch type in which films are formed on multiple substrates at once.

<ALD Equipment>
Next, the configuration of a thermal ALD apparatus that can be used in the film forming apparatus 4000 will be described with reference to FIG. 8A. The thermal ALD apparatus has a film forming chamber (chamber 4520), a raw material supply unit 4521 (raw material supply units 4521a to 4521c), a raw material supply unit 4531, high-speed valves 4522a to 4522d that are introduction amount controllers, a gas supply unit 4532, a raw material inlet 4523, a raw material outlet 4524, and an exhaust unit 4525. The raw material inlet 4523 installed in the chamber 4520 is connected to the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, the raw material supply unit 4531, and the gas supply unit 4532 via a supply pipe and a valve, respectively, and the raw material outlet 4524 is connected to the exhaust unit 4525 via, for example, an exhaust pipe, a valve, and a pressure regulator.

The chamber 4520 includes a substrate holder 4526, and the substrate 4530 is placed on the substrate holder 4526. The substrate holder 4526 may have a rotation mechanism. A heater 4527 is provided on the outer wall of the chamber 4520, and the temperature of the inside of the chamber 4520, the substrate holder 4526, and the surface of the substrate 4530 can be controlled. The heater 4527 can control the temperature of the surface of the substrate 4530 to 100°C or higher and 600°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 400°C or higher and 450°C or lower. For example, the temperature of the heater 4527 itself can be set to 100°C or higher and 600°C or lower. By forming a film while heating the substrate within such a temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be suppressed from remaining in the metal oxide. Furthermore, at the same time as removing these impurities, metal atoms and oxygen atoms are rearranged, and each oxide layer can be arranged in a highly orderly manner. Therefore, a metal oxide having a highly crystalline layered crystal structure can be formed. Heat treatment can also be performed after the metal oxide film is formed using the heater 4527.

In the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, and the raw material supply unit 4531, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer or a heating means. Alternatively, the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, and the raw material supply unit 4531 may be configured to supply a gaseous raw material gas.

In the film formation apparatus shown in FIG. 8A, a metal oxide can be formed by appropriately selecting the raw materials (such as a volatile organometallic compound) used in the raw material supply unit 4521 and the raw material supply unit 4531 and introducing them into the chamber 4520. As described above, when forming an In-Ga-Zn oxide containing indium, gallium, and zinc as a metal oxide, it is preferable to use a film formation apparatus provided with at least three raw material supply units 4521a to 4521c and at least one raw material supply unit 4531 as shown in FIG. 8A.

For example, a precursor containing indium is supplied from raw material supply unit 4521a, a precursor containing gallium is supplied from raw material supply unit 4521b, and a precursor containing zinc is supplied from raw material supply unit 4521c. The precursors described above can be used as the precursor containing indium, the precursor containing gallium, and the precursor containing zinc.

In addition, a reactant is supplied from the raw material supply unit 4531. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

A carrier gas is supplied from the gas supply unit 4532. An inert gas such as argon (Ar), helium (He), or nitrogen (N ₂ ) can be used as the carrier gas. The precursor of the raw material supply unit 4521 and the reactant of the raw material supply unit 4531 are mixed with the carrier gas and introduced into the chamber 4520.

In addition, a piping heater 4534a is provided to cover the piping or valves between the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, the raw material supply unit 4531, and the gas supply unit 4532 and the chamber 4520. In addition, a piping heater 4534b is provided to cover the piping or valves between the exhaust device 4525 and the chamber 4520. The temperatures of the piping heater 4534a and the piping heater 4534b may be appropriately set within a range of, for example, room temperature or higher and 300°C or lower. By providing such a piping heater, it is possible to prevent the precursors supplied from the raw material supply unit 4521 from solidifying on the inner walls of the piping of the gas introduction system and the gas exhaust system. In addition, it is preferable that the temperatures of the piping heater 4534a, the piping heater 4534b, and the heater 4527 can be controlled independently. Alternatively, the temperature control of the piping heater 4534a, the piping heater 4534b, and the heater 4527 may be adjusted collectively.

The high-speed valves 4522a to 4522d can be precisely controlled in time. This allows the raw material gases supplied from the raw material supply units 4521a, 4521b, 4521c, and 4531 to be controlled and introduced into the chamber 4520.

For example, when supplying precursors contained in the raw material supply units 4521a, 4521b, and 4521c, the corresponding high-speed valves among the high-speed valves 4522a to 4522c are opened. When supplying reactants contained in the raw material supply unit 4531, the high-speed valve 4522d is opened. When purging the chamber 4520, the high-speed valves 4522a to 4522d are closed, and only the carrier gas contained in the gas supply unit 4532 is introduced into the chamber 4520.

In addition, although FIG. 8A shows an example in which three raw material supply units 4521 and one raw material supply unit 4531 are provided, this embodiment is not limited to this. One, two, or four or more raw material supply units 4521 may be provided. Also, two or more raw material supply units 4531 may be provided.

In addition, in FIG. 8A, the heater 4527, the raw material inlet 4523, and the raw material outlet 4524 are arranged at the bottom of the chamber 4520, but the arrangement of these can be set appropriately without being limited to this. In addition, in FIG. 8A, the inlets of the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, the raw material supply unit 4531, and the gas supply unit 4532 are combined into the raw material inlet 4523, but the arrangement is not limited to this and each may have a different inlet.

Next, the configuration of a plasma ALD device that can be used in the film formation apparatus 4000 will be described with reference to Figure 8B. The plasma ALD device has a film formation chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a to 4021c), a raw material supply unit 4031, high-speed valves 4022a to 4022d which are introduction amount controllers, a gas supply unit 4032, a raw material inlet 4023, a raw material inlet 4033, a raw material outlet 4024, and an exhaust device 4025. The raw material inlet 4023 and raw material inlet 4033 installed in the chamber 4020 are connected to the raw material supply unit 4021a, raw material supply unit 4021b, raw material supply unit 4021c, raw material supply unit 4031, and gas supply unit 4032 via supply pipes and valves, respectively, and the raw material outlet 4024 is connected to the exhaust device 4025 via an exhaust pipe, a valve, and a pressure regulator. In addition, a substrate holder 4026 is provided inside the chamber 4020, and a substrate 4030 is placed on the substrate holder 4026. In addition, a heater 4027 is provided on the outer wall of the chamber, and pipe heaters 4034a and 4034b are provided to cover pipes connected to the chamber.

Here, the chamber 4020 corresponds to the chamber 4520, the raw material supply unit 4021 corresponds to the raw material supply unit 4521, the raw material supply unit 4031 corresponds to the raw material supply unit 4531, the high-speed valves 4022a to 4022d correspond to the high-speed valves 4522a to 4522d, the gas supply unit 4032 corresponds to the gas supply unit 4532, the raw material inlet 4023 corresponds to the raw material inlet 4523, the raw material outlet 4024 corresponds to the raw material outlet 4524, the exhaust device 4025 corresponds to the exhaust device 4525, the substrate holder 4026 corresponds to the substrate holder 4526, the substrate 4030 corresponds to the substrate 4530, the heater 4027 corresponds to the heater 4527, the pipe heater 4034a corresponds to the pipe heater 4534a, and the pipe heater 4034b corresponds to the pipe heater 4534b. For detailed configurations, refer to the above description.

As shown in FIG. 8B, the plasma ALD device can perform film formation by the plasma ALD method in addition to the thermal ALD method by connecting a plasma generator 4028 to the chamber 4020. The plasma generator 4028 is preferably an ICP type plasma generator using a coil 4029 connected to a high-frequency power source. The high-frequency power source can output power having a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 2 MHz to 60 MHz. For example, it can output power having a frequency of 13.56 MHz. The plasma ALD method can form a film without reducing the film formation rate even at low temperatures, so it is suitable for use in a single-wafer film formation device with low film formation efficiency.

The reactant discharged from the raw material supply unit 4031 passes through the plasma generator 4028 and becomes a plasma state. The reactant in a plasma state is introduced into the chamber 4020 from the raw material inlet 4033. Although not shown in FIG. 8B, the reactant discharged from the raw material supply unit 4031 may be configured to be mixed with a carrier gas.

The substrate holder 4526 may also be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4526 may be floating or grounded.

In FIG. 8B, the raw material inlet 4033 is located at the top of the chamber 4520, the heater 4027 and the raw material inlet 4023 are located on the side of the chamber 4520, and the raw material outlet 4524 is located at the bottom of the chamber 4520, but this is not limiting and these locations can be set as appropriate.

Different configurations of ALD devices that can be used in the film forming apparatus 4000 will be described using Figures 9A to 9C. Note that detailed descriptions of configurations and functions similar to those of the ALD device shown in Figure 8B may be omitted below.

Figure 9A is a schematic diagram showing one embodiment of a plasma ALD device. The plasma ALD device 4100 is provided with a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120. The reaction chamber 4120 can be called a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively called a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. In addition, a high frequency such as RF or a microwave can be applied by a plasma generation device 4128 to a gas introduced into the plasma generation chamber 4111 to generate a plasma 4131 in the plasma generation chamber 4111. When generating the plasma 4131 using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Furthermore, plasma generated by applying such microwaves and a magnetic field is sometimes called ECR (Electron Cyclotron Resonance) plasma.

The reaction chamber 4120 also has a substrate holder 4126, on which the substrate 4130 is placed. The raw material gas introduced from the raw material inlet 4123 is decomposed by heat from a heater provided in the reaction chamber 4120 and deposited on the substrate 4130. The raw material gas introduced from the raw material inlet 4133 is turned into a plasma state by the plasma generation device 4128. The raw material gas in the plasma state recombines with electrons or other molecules before reaching the surface of the substrate 4130, and reaches the substrate 4130 in a radical state. In this way, an ALD device that uses radicals to form a film is sometimes called a radical ALD (radical-enhanced ALD) device. In addition, in the plasma ALD device 4100, a configuration in which the plasma generation chamber 4111 is provided at the top of the reaction chamber 4120 is shown, but this embodiment is not limited to this. The plasma generation chamber 4111 may be provided adjacent to the side of the reaction chamber 4120.

Figure 9B is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 has a chamber 4220. The chamber 4220 has an electrode 4213, a raw material outlet 4224, and a substrate holder 4226, and a substrate 4230 is placed on the substrate holder 4226. The electrode 4213 has a raw material inlet 4223 and a shower head 4214 that supplies the introduced raw material gas into the chamber 4220. In addition, a power source 4215 that can apply high frequency through a capacitor 4217 is connected to the electrode 4213. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode for generating plasma 4231, respectively. The raw material gas introduced from the raw material inlet 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material inlet 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The raw material gas in the plasma state is incident on the substrate 4230 due to a potential difference (also called an ion sheath) generated between the plasma 4231 and the substrate 4230.

Figure 9C is a schematic diagram showing one embodiment of a plasma ALD apparatus different from that of Figure 9B. The plasma ALD apparatus 4300 has a chamber 4320. The chamber 4320 has an electrode 4313, a raw material outlet 4324, and a substrate holder 4326, and a substrate 4330 is placed on the substrate holder 4326. The electrode 4313 has a raw material inlet 4323 and a shower head 4314 that supplies the introduced raw material gas into the chamber 4320. In addition, a power source 4315 that can apply high frequency power via a capacitor 4317 is connected to the electrode 4313. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode for generating plasma 4331, respectively. The plasma ALD apparatus 4300 differs from the plasma ALD apparatus 4200 in that it has a mesh 4319 connected to a power source 4321 capable of applying high frequency through a capacitor 4322 between the electrode 4313 and the substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The source gas introduced from the source inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced from the source inlet 4323 becomes a plasma state between the electrode 4313 and the substrate holder 4326. The charge of the source gas in the plasma state is removed by the mesh 4319, and the source gas reaches the substrate 4130 in an electrically neutral state such as radicals. Therefore, film formation can be performed with suppressed ion incidence and damage caused by plasma.

For example, a plasma process or a microwave process may be performed as the impurity removal process using a plasma ALD apparatus as shown in FIG. 8B and FIG. 9A to FIG. 9C. In this case, it is preferable because there is no need to move the film from the film formation chamber to another chamber for the impurity removal process.

Also, a plasma ALD apparatus as shown in Figures 8B and 9A to 9C may be used to perform plasma processing or microwave processing after forming a metal oxide film.

Next, different configurations of ALD apparatuses that can be used for the film forming apparatus 4000 will be described using Figures 10A and 10B.

The ALD apparatus 4400 shown in FIG. 10A has a chamber 4420 and a heater 4427 inside an outer chamber 4410, and a substrate holder 4426 inside the chamber 4420. A precursor, an oxidizer, and a carrier gas are supplied to the chamber 4420 from a raw material inlet 4423 via a raw material supply port 4414. In addition, exhaust is performed from the chamber 4420 via a raw material outlet 4424.

A substrate 4430 is placed on the substrate holder 4426. As shown in FIG. 10A, the precursor and the oxidant are each supplied from the upper side of the chamber 4420, and a film is formed on the upper surface of the substrate 4430. The precursor and the oxidant are also adsorbed onto the lower surface of the substrate 4430 before being exhausted from the lower side of the chamber 4420, so that a film is also formed on the lower surface of the substrate 4430.

Therefore, when the ALD apparatus 4400 is used in the face-up method, as shown in FIG. 10B, a film 4431a is formed on the front surface 4430a of the substrate 4430, and a film 4431b is formed on the back surface 4430b. In other words, by using the ALD apparatus 4400, a film can be formed on both sides of the substrate 4430.

Note that films 4431a and 4431b have the same or approximately the same thickness. Also, depending on the types of precursor and oxidizing agent, films 4431a and 4431b may have the same or approximately the same composition, or may have different compositions.

For example, an element that is easily adsorbed may have a higher concentration in a film formed on the front surface than in a film formed on the back surface. As an example, as described later in the examples, it has been confirmed that aluminum contained as an impurity in triethylindium has a higher concentration in film 4431a formed on the front surface of the substrate than in film 4431b formed on the back surface.

When using the ALD apparatus 4400, the film may be formed with the front surface of the substrate facing upward, which is known as the face-up method, or with the front surface of the substrate facing downward (substrate inverted), which is known as the face-down method. A method that can form a film of the desired composition can be selected as appropriate.

<Film formation sequence>
Next, a metal oxide film formation sequence using the ALD apparatus shown in Fig. 8A will be described with reference to Fig. 11 to Fig. 13. In Fig. 11 to Fig. 13, the introduction of the first source gas to the fourth source gas is indicated by ON, and a period in which the source gas is not introduced is indicated by OFF.

FIG. 11A shows a film formation sequence using the ALD apparatus shown in FIG. 8A. First, the substrate 4530 is set on the substrate holder 4526 in the chamber 4520 (step S101). Next, the temperature of the heater 4527 is adjusted (step S102). At this time, the temperatures of the pipe heaters 4534a and 4534b may also be adjusted. Next, the substrate 4530 is held on the substrate holder 4526 so that the temperature of the substrate 4530 is uniform across the substrate surface (step S103). Next, a metal oxide film is formed according to the first to fourth steps described above (step S104). Note that if temperature adjustment of the heater 4527 is not required after the substrate 4530 is set (step S101), step S102 may be omitted.

In step S104, a first source gas (source gas having a precursor) and a second source gas (source gas having a reactant) are alternately introduced into the chamber 4520 to form a film on the substrate 4530. The introduction of the first source gas and the second source gas is performed in a pulsed manner. During the period when neither the first source gas nor the second source gas is introduced, the chamber 4520 is purged. In the film formation by the ALD method, the introduction of the first source gas (first step above), the purging of the first source gas (second step above), the introduction of the second source gas (third step above), and the purging of the second source gas (fourth step above) are set as one cycle, and a film having a desired film thickness is formed by repeating this cycle. Note that although no mention is made here of the intermittent impurity removal process, the impurity removal process may be performed in the chamber 4520 or another chamber every time the cycle is repeated several times.

In addition, between step S103 and step S104, a second source gas having a reactant may be introduced into the chamber 4020. As the second source gas, it is preferable to introduce one or more selected from ozone (O ₃ ), oxygen (O ₂ ), and water (H ₂ O), which function as an oxidizing agent. By introducing water as the second source gas, a hydrophilic group can be formed on the substrate 4530, so that the adsorption of the precursor can be further improved. By introducing ozone and oxygen as the second source gas, the chamber can be made into an oxygen atmosphere, and oxygen can be supplied to the base insulating film formed on the substrate 4530. As a result, oxygen can be supplied to the metal oxide film formed on the base insulating film, and the oxygen concentration in the film can be increased. At this time, the second source gas is preferably introduced in a pulsed manner similar to the method shown in step S104, but the present invention is not limited to this. The second source gas may be introduced continuously. During the period in which the second source gas is not introduced, the chamber 4520 is evacuated.

By forming the first oxide layer in one cycle using the above-mentioned first source gas, forming the second oxide layer in one cycle using a third source gas different from the first source gas, and forming the third oxide layer in one cycle using a fourth source gas different from the first source gas, a layered crystalline oxide having multiple different oxide layers can be formed. In the following, as an example, a film formation sequence corresponding to the film formation process of In-Ga-Zn oxide shown in Figures 5 and 6 will be described with reference to Figure 11B.

FIG. 11B shows an example in which a film is formed using first to third source gases each having a different precursor in step S104 of the film formation sequence. Note that steps S101 to S103 are as described above. Here, the first source gas contains a precursor containing indium, the third source gas contains a precursor containing gallium, and the fourth source gas contains a precursor containing zinc.

As shown in FIG. 11B, first, the first source gas is introduced, and a precursor having indium is adsorbed onto the substrate 4530 (corresponding to FIG. 5A). Then, the introduction of the first source gas is stopped, and the excess first source gas in the chamber is purged.

Then, the second source gas is introduced, and the precursor having adsorbed indium is reacted with the oxidizing agent to form an indium oxide layer (corresponding to FIG. 5B). Then, the introduction of the second source gas is stopped, and the excess second source gas in the chamber is purged.

Next, the third source gas is introduced, and a precursor containing gallium is adsorbed onto the indium oxide layer (corresponding to FIG. 5C). Then, the introduction of the third source gas is stopped, and the excess third source gas in the chamber is purged.

Then, the second source gas is introduced, and the precursor having adsorbed gallium is reacted with the oxidizing agent to form a layer of gallium oxide (corresponding to FIG. 5D). Then, the introduction of the second source gas is stopped, and the excess second source gas in the chamber is purged.

Next, the fourth source gas is introduced, and the zinc-containing precursor is adsorbed onto the gallium oxide layer (corresponding to FIG. 6A). Then, the introduction of the fourth source gas is stopped, and the excess fourth source gas in the chamber is purged.

Then, a second source gas is introduced, and the precursor having adsorbed zinc is reacted with an oxidizing agent to form a layer of zinc oxide (corresponding to FIG. 6B). Then, the introduction of the second source gas is stopped, and the excess second source gas in the chamber is purged. Furthermore, using the above method, a precursor having indium is adsorbed onto the zinc oxide (corresponding to FIG. 6C).

The above process of forming indium oxide, gallium oxide, and zinc oxide constitutes one cycle. By repeating the cycle, an In-Ga-Zn oxide with a desired film thickness and an In:Ga:Zn = 1:1:1 [atomic ratio] can be formed.

The first to fourth raw material gases are introduced in a pulsed manner. The pulse time for introducing the first raw material gas, the third raw material gas, and the fourth raw material gas into the chamber 4520 is preferably 0.05 to 1 second, and more preferably 0.1 to 0.5 seconds. The time for exhausting the first raw material gas, the third raw material gas, and the fourth raw material gas from the chamber 4520 is preferably 0.1 to 15 seconds, and more preferably 0.5 to 10 seconds. The pulse time for introducing the second raw material gas into the chamber 4520 is preferably 0.05 to 30 seconds, and more preferably 0.1 to 15 seconds. The time for exhausting the second raw material gas from the chamber 4520 is preferably 0.1 to 15 seconds, and more preferably 0.1 to 5 seconds.

Note that in the sequence shown in FIG. 11B, the order of introduction of the first, third, and fourth raw material gases is not limited to this. For example, the fourth gas containing a zinc-containing precursor may be introduced first. Zinc oxide forms a crystal structure more easily than indium oxide and gallium oxide, so stable zinc oxide crystals can be formed in the bottom layer. This makes it relatively easy to form a layer of indium oxide and gallium oxide on top of zinc oxide.

The above describes the formation of an In-Ga-Zn oxide film with an atomic ratio of In:Ga:Zn = 1:1:1, but the present invention is not limited to this. Using a similar method, In-Ga-Zn oxides with different atomic ratios can be formed. It is preferable to set the number of pulses or pulse time of the precursor-containing source gas in one cycle according to the desired atomic ratio of the In-Ga-Zn oxide.

For example, in the sequence shown in FIG. 11B, in order to form an In-Ga-Zn oxide film with an atomic ratio of In:Ga:Zn=1:1:1, the first source gas containing indium, the third source gas containing gallium, and the fourth source gas containing zinc are each pulsed once in one cycle. At this time, the pulse time of each precursor is the same.

Figure 12A shows an example of a film formation sequence for In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4. In Figure 12A, in one cycle, the first source gas containing indium is pulsed once, the third source gas containing gallium is pulsed three times, and the fourth source gas containing zinc is pulsed four times. In other words, the number of pulses of the source gas containing the precursor corresponds to In:Ga:Zn = 1:3:4 [atomic ratio]. By forming the film in this manner, a metal oxide with a layered crystal structure as shown in Figure 2D can be formed.

Also, as described above, by performing film formation by the ALD method while heating the substrate, it is possible to promote rearrangement of each oxide layer. As a result, even if a film is formed according to the sequence shown in FIG. 12A, it is possible to form a layer having two types of metal elements (indium and gallium) in one oxide layer, as in layer 23 shown in FIG. 2D.

In the above, different types of precursors are introduced between the introduction of raw material gas containing a reactant, but the present invention is not limited to this. For example, raw material gas having the same type of precursor may be continuously introduced between the introduction of raw material gas containing a reactant. In this case, it is preferable that the number of pulses of the raw material gas containing the precursor in one cycle is the same as the atomic ratio of the desired In-Ga-Zn oxide.

In addition, in the above, a configuration in which only one type of precursor-containing raw material gas is introduced during the interval in which oxidation is performed with the second raw material gas is shown, but the present invention is not limited to this. During the interval in which oxidation is performed with the second raw material gas, a configuration in which two or more types of precursor-containing raw material gases are introduced may also be used. In this case, a configuration in which two or more types of precursor-containing raw material gases are introduced simultaneously may also be used. Also, during the interval in which oxidation is performed with the second raw material gas, a configuration in which the same type of precursor is introduced twice in succession may also be used.

For example, when forming an In-Ga-Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:4, the film may be formed in the sequence shown in FIG. 12B. In FIG. 12B, the first raw material gas, the third raw material gas, the fourth raw material gas, the third raw material gas, and the fourth raw material gas are introduced in this order in accordance with the crystal structure shown in FIG. 2D, in which the layers 23, 41, 31, and 41 are stacked in this order. However, the first raw material gas and the third raw material gas are introduced without the introduction of the second raw material gas in between. In other words, the oxidizing agent is introduced after the precursor containing indium contained in the first raw material gas and the precursor containing gallium contained in the third raw material gas are adsorbed. This allows the formation of a layer containing two types of metal elements (indium and gallium) in one oxide layer, as in the layer 23 shown in FIG. 2D. At this time, it is preferable that the pulse time of the first raw material gas and the third raw material gas is about half the pulse time of the fourth raw material gas. As a result, as shown in FIG. 12B, the ratio of the pulse time of the first source gas containing indium, the pulse time of the third source gas containing gallium, and the pulse time of the fourth source gas containing zinc during one cycle can be made 1:3:4, the same as the atomic ratio.

The above describes the deposition of oxides with a constant atomic ratio, but the present invention is not limited to this. Using a similar method, two or more oxides with different atomic ratios can be deposited in succession. In this case, it is preferable to set the number of pulses or pulse time of the precursor-containing source gas in one cycle according to the atomic ratio of each oxide in the layered oxides with different atomic ratios. By depositing the film in this manner, layered oxides with different atomic ratios can be deposited in a single chamber. This makes it possible to prevent impurities such as hydrogen or carbon from entering during the intervals between deposition of each oxide.

13 shows an example of a film formation sequence when an oxide of In:Ga:Zn = 1:1:1 [atomic ratio] is laminated on an oxide of In:Ga:Zn = 1:3:4 [atomic ratio]. Step 104a corresponds to an oxide of In:Ga:Zn = 1:3:4 [atomic ratio], and is the same as the sequence shown in FIG. 12A. Step 104b corresponds to an oxide of In:Ga:Zn = 1:1:1 [atomic ratio], and is the same as the sequence shown in FIG. 11B. In this way, in the first half, the number of pulses in one cycle is the first raw material gas: the third raw material gas: the fourth raw material gas = 1:3:4, and in the second half, the number of pulses in one cycle is the first raw material gas: the third raw material gas: the fourth raw material gas = 1:1:1, so that a metal oxide having a laminated structure of oxide 62 and oxide 60 shown in FIG. 3B can be formed. In other words, the first half of the film is formed with a number of pulses corresponding to an atomic ratio of In:Ga:Zn = 1:3:4, and the second half of the film is formed with a number of pulses corresponding to an atomic ratio of In:Ga:Zn = 1:1:1.

Note that, in the above, the film formation method has been described using In-Ga-Zn oxide as an example, but the present invention is not limited to this. Precursors may be appropriately selected according to the metal elements contained in the desired metal oxide. Also, in the above, the number of precursors was one or three, but this is not limited to this, and two or four or more types may be used.

In addition, in the above, an example is shown in which a film is formed using a precursor having one type of metal element, but the present invention is not limited to this. A precursor having two or more types of metal elements may be used. For example, a precursor containing indium and gallium, or a precursor containing gallium and zinc may be used. In this case, the number of raw material supply units 4521 shown in FIG. 8A etc. can be reduced.

<Metal oxide having CAAC structure>
The metal oxide having a CAAC structure will be described in detail below.

The CAAC structure has multiple crystals, and the c-axes of the multiple crystals are oriented in a specific direction. The specific direction is the thickness direction of the metal oxide having the CAAC structure, the normal direction of the surface on which the metal oxide having the CAAC structure is formed, or the normal direction of the surface of the metal oxide having the CAAC structure. When a crystal region is referred to as a crystal region, the crystal region refers to the crystal itself of the CAAC structure, or the crystal of the CAAC structure and a region in the vicinity of the crystal. Therefore, the crystal of the CAAC structure may be referred to as a crystal region of the CAAC structure.

A crystalline region is a region in which the atomic arrangement has periodicity. If the atomic arrangement is considered as a lattice arrangement, then the crystalline region is also a region in which the lattice arrangement is aligned. Furthermore, the CAAC structure has a region in which multiple crystalline regions are connected in the a-b plane direction, and this region may have distortion. Note that distortion refers to a location in a region in which multiple crystalline regions are connected where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and another region in which the lattice arrangement is aligned. In other words, a metal oxide having a CAAC structure is a metal oxide that is c-axis oriented and does not have a clear orientation in the a-b plane direction.

Each of the multiple crystal regions is composed of one or more tiny crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of one tiny crystal, the maximum diameter of the crystal region is less than 10 nm. When a crystal region is composed of many tiny crystals, the size of the crystal region may be approximately several tens of nm.

In addition, in In-M-Zn oxide (wherein element M is one or more elements selected from gallium, yttrium, tin, titanium, etc.), the CAAC structure tends to have a layered crystal structure (also called a layered structure) in which a layer having indium (In) and oxygen and a layer having element M, zinc (Zn), and oxygen are stacked. Note that the layer having indium and oxygen may contain element M or zinc. Also, the layer having element M, zinc, and oxygen may contain indium. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

When a metal oxide having a CAAC structure is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using a θ/2θ scan. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements that make up the metal oxide.

For example, multiple bright spots are observed in the electron diffraction pattern of a metal oxide having a CAAC structure. Note that one spot and another spot are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

In addition, by performing FFT (Fast Fourier Transform) analysis on the TEM image, it is possible to obtain an FFT image having a pattern that reflects reciprocal lattice space information similar to an electron beam diffraction pattern. In other words, the crystal structure (e.g., CAAC structure) can also be confirmed and evaluated using FFT analysis. For example, in the case of a cross-sectional TEM image of a metal oxide having a CAAC structure taken from a direction perpendicular to the c-axis, two spots of high intensity may be seen in the FFT image. The intensity of these two spots represents the crystallinity of the metal oxide having a CAAC structure, and the angle of the line segment connecting these two spots represents the crystal orientation of the metal oxide having a CAAC structure.

When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In addition, in a metal oxide having a CAAC structure, no clear crystal grain boundaries can be confirmed even in the vicinity of the distortion. In other words, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because metal oxides having a CAAC structure can tolerate distortion because the arrangement of oxygen atoms in the a-b plane direction is not dense, or because the bond distance between atoms changes due to the substitution of metal atoms.

Metal oxides having a CAAC structure are highly crystalline and have no clearly identified crystal grain boundaries. In other words, metal oxides having a CAAC structure are less likely to experience a decrease in electron mobility due to crystal grain boundaries. Therefore, metal oxides having a CAAC structure have stable physical properties. Therefore, metal oxides having a CAAC structure are resistant to heat and highly reliable. Therefore, metal oxides having a CAAC structure are one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor.

As described above, by using a precursor with a low aluminum content to produce a metal oxide that does not contain aluminum as a main component, it is possible to prevent the aluminum concentration in the formed metal oxide from becoming high. By using such a metal oxide in the semiconductor layer of a transistor, a transistor with a high on-state current can be produced. In addition, by performing an impurity removal process such as microwave treatment, the crystallinity of the metal oxide can be increased, thereby improving the reliability of the transistor.

This embodiment can be combined with other embodiments as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Embodiment 2)
In this embodiment, a transistor, a semiconductor device, and a memory device according to one embodiment of the present invention will be described with reference to FIGS. 14 to 32. The semiconductor device according to one embodiment of the present invention includes a transistor. The memory device according to one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

<Configuration Example 1 of Semiconductor Device>
14A to 14D illustrate an example of a semiconductor device of one embodiment of the present invention.

The transistor 200A shown in FIG. 14A has a conductor 120, an oxide semiconductor 230, an insulator 250, a conductor 240, and a conductor 260. The conductor 120, the oxide semiconductor 230, the insulator 250, the conductor 240, and the conductor 260 may each have a single-layer structure or a stacked structure of two or more layers.

The conductor 120 is disposed on the insulator 130. The conductor 120 functions as either a source or a drain.

An insulator 280 is provided on the conductor 120, and a conductor 240 is provided on the insulator 280. An opening that reaches the conductor 120 is provided in the insulator 280 and the conductor 240. The conductor 240 functions as the other of the source and the drain.

The oxide semiconductor 230 is provided along an opening provided in the insulator 280 and the conductor 240, and is in contact with the top surface of the conductor 120 inside the opening. The oxide semiconductor 230 is also in contact with the side surface of the insulator 280 inside the opening. Furthermore, the oxide semiconductor 230 has a portion in contact with the conductor 240. The oxide semiconductor 230 has a region that functions as a channel formation region.

The oxide semiconductor 230 is in contact with at least one of the top surface, side surface, and bottom surface (also referred to as the bottom surface) of the conductor 240. The transistor 200A has a so-called bottom-contact structure in which the bottom surface of the oxide semiconductor 230 is in contact with the top surface of the conductor 240 on the insulator 280. Alternatively, the transistor 200A may have a so-called top-contact structure in which the conductor 240 is provided on the oxide semiconductor 230 and the top surface of the oxide semiconductor 230 is in contact with the bottom surface of the conductor 240.

The insulator 250 is provided on the oxide semiconductor 230. The conductor 260 is located on the insulator 250 and overlaps with the oxide semiconductor 230 via the insulator 250. The conductor 260 functions as a gate.

Transistor 200A has a structure in which the channel formation region surrounds the gate. Therefore, transistor 200A can be said to be a transistor with a CAA (Channel-All-Around) structure.

In the transistor 200A shown in FIG. 14A, the surfaces of the insulator 280 and the conductor 240 at the opening are inclined with respect to the top surface of the conductor 120. In other words, the sidewalls of the opening have a tapered shape.

The sidewall of the opening is preferably tapered because this improves the coverage of the oxide semiconductor 230, the insulator 250, and the like that are provided along the opening. In addition, by using the metal oxide film formation method of one embodiment of the present invention, the oxide semiconductor 230 can be formed with good coverage.

On the other hand, in the transistor 200B shown in FIG. 14B, the surfaces of the openings of the insulator 280 and the conductor 240 are perpendicular to the top surface of the conductor 120. Otherwise, the transistor 200B has the same configuration as the transistor 200A.

When the sidewall of the opening is perpendicular to the top surface of the conductor 120, the channel length of the transistor can be shorter than when the opening has a tapered shape. Furthermore, by applying the metal oxide film formation method of one embodiment of the present invention, the oxide semiconductor 230 can be formed with good coverage even when the sidewall of the opening is perpendicular to the top surface of the conductor 120.

The transistor 200C shown in FIG. 14C has a conductor 120, an oxide semiconductor 230, an insulator 250, a conductor 240, and a conductor 260.

The conductor 120 is disposed on the insulator 130. The conductor 120 functions as either a source or a drain.

An insulator 280 is provided on the conductor 120, a conductor 260 is provided on the insulator 280, and an insulator 272 is provided on the conductor 260. An opening reaching the conductor 120 is provided in the insulator 280, the conductor 260, and the insulator 272. The conductor 260 functions as a gate.

The insulator 250 is provided along the openings provided in the insulator 280, the conductor 260, and the insulator 272, and has an opening that reaches the conductor 120. Similarly, the oxide semiconductor 230 is provided along the openings provided in the insulator 280, the conductor 260, and the insulator 272. The oxide semiconductor 230 overlaps with the conductor 260 via the insulator 250. The oxide semiconductor 230 also contacts the upper surface of the conductor 120 via the opening provided in the insulator 250.

The insulator 275 is provided so as to fill the recess in the oxide semiconductor 230. Note that if the oxide semiconductor 230 does not have a recess, the insulator 275 does not need to be provided.

The conductor 240 is provided on the oxide semiconductor 230. The conductor 240 functions as the other of the source and the drain.

Transistor 200C has a structure in which the channel formation region is surrounded by the gate. Therefore, transistor 200C can be said to be a transistor with a GAA (Gate-All-Around) structure.

In the transistor 200C shown in FIG. 14C, the surfaces of the insulator 280, the conductor 260, and the insulator 272 at the opening are inclined with respect to the top surface of the conductor 120. In other words, the sidewalls of the opening have a tapered shape.

The sidewall of the opening is preferably tapered because this improves the coverage of the insulator 250, the oxide semiconductor 230, and the like that are provided along the opening. In addition, by applying the metal oxide film formation method of one embodiment of the present invention, the oxide semiconductor 230 can be formed with good coverage.

On the other hand, in transistor 200D shown in FIG. 14D, the surfaces of insulator 280, conductor 260, and insulator 272 at the openings are perpendicular to the top surface of conductor 120. Otherwise, transistor 200D has the same configuration as transistor 200C.

When the sidewall of the opening is perpendicular to the top surface of the conductor 120, the channel length of the transistor can be shorter than when the opening has a tapered shape. Furthermore, by applying the metal oxide film formation method of one embodiment of the present invention, the oxide semiconductor 230 can be formed with good coverage even when the sidewall of the opening is perpendicular to the top surface of the conductor 120.

In each of the transistors shown in Figures 14A to 14D, the oxide semiconductor 230 has a first portion in contact with the top surface of the conductor 120, a second portion in contact with the side surface of the insulator 280, and a third portion in contact with the conductor 240.

The first and second parts are located inside an opening provided in the insulator 280.

The oxide semiconductor 230 can be in contact with one or more of the top surface, side surface, and bottom surface (also referred to as the bottom surface) of the conductor 240. Figures 14A and 14B show an example in which the oxide semiconductor 230 is in contact with the top surface and side surface of the conductor 240. Figures 14C and 14D show an example in which the oxide semiconductor 230 is in contact with the bottom surface of the conductor 240.

Here, the method for forming the oxide semiconductor 230 is preferably the metal oxide film formation method of one embodiment of the present invention shown in embodiment 1.

By forming the oxide semiconductor 230 using the ALD method, a metal oxide can be formed with good coverage on the top, bottom, side, and inclined surfaces of the structure. That is, a metal oxide can be formed with a roughly constant film thickness in the normal direction on each deposition surface. In the metal oxide formed on each of the top, bottom, side, and inclined surfaces of the structure, the ratio of the minimum film thickness to the maximum film thickness can be set to 0.5 or more and 1 or less, preferably 0.7 or more and 1 or less, more preferably 0.8 or more and 1 or less, and more preferably 0.9 or more and 1 or less.

For example, the ratio of the thickness of the second portion in contact with the side of the insulator 280 to the thickness of the first portion in contact with the conductor 120 is preferably 0.7 or more and 1.3 or less, more preferably 0.8 or more and 1.2 or less, and even more preferably 0.9 or more and 1.1 or less.

The aluminum concentration in the channel formation region of the oxide semiconductor 230 is preferably 0.01 atomic% or more and 10 atomic% or less, more preferably 5 atomic% or less, more preferably 3 atomic% or less, more preferably 1 atomic% or less, and even more preferably 0.1 atomic% or less. Alternatively, it may be 0.01 atomic% or less. As described in detail in embodiment 1, by reducing the aluminum concentration in the oxide semiconductor, both the reliability and electrical characteristics of the transistor can be improved. Furthermore, by extremely reducing the aluminum concentration, the on-current of the transistor can be increased.

The carbon concentration in the channel formation region of the oxide semiconductor 230 is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁸ atoms/cm ³ or less, and still more preferably 1×10 ¹⁸ atoms/cm ³ or less. By reducing the carbon concentration in the oxide semiconductor 230, formation of defect states can be suppressed and the reliability of the transistor can be improved.

14A to 14D, the source electrode and the drain electrode are located at different heights, so that the current flowing through the oxide semiconductor 230 flows from top to bottom or bottom to top. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

In one embodiment of the present invention, the transistor can have a source electrode, a semiconductor layer, and a drain electrode that are stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.

<Configuration example 1 of storage device>
A configuration of a memory device having a transistor and a capacitor will be described with reference to FIG. 15. FIGS. 15A to 15C are plan and cross-sectional views of a memory device having a transistor 200 and a capacitor 100. FIG. 15A is a plan view of the memory device. Also, FIGS. 15B and 15C are cross-sectional views of the memory device. Here, FIG. 15B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 15A. Also, FIG. 15C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 15A. Note that some elements are omitted in the plan view of FIG. 15A for clarity.

In the drawings and the like relating to this specification, arrows indicating the X-direction, Y-direction, and Z-direction may be attached. In the present specification, the "X-direction" is the direction along the X-axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y-direction" and "Z-direction". In addition, the X-direction, Y-direction, and Z-direction are directions that intersect with each other. For example, the X-direction, Y-direction, and Z-direction are directions that are perpendicular to each other. In the present specification, one of the X-direction, Y-direction, and Z-direction may be called the "first direction" or "first direction". In addition, the other may be called the "second direction" or "second direction". In addition, the remaining one may be called the "third direction" or "third direction".

The memory device shown in Figures 15A to 15C has an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 on the conductor 110, an insulator 180 on the conductor 110, an insulator 280, and an insulator 283 on the memory cell 150. The insulators 140, 180, 280, and 283 function as interlayer films. The conductor 110 functions as wiring.

The memory cell 150 has a capacitance element 100 on a conductor 110 and a transistor 200 on the capacitance element 100.

The capacitance element 100 has a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130. The conductor 120 functions as one of a pair of electrodes (sometimes called an upper electrode), the conductor 115 functions as the other of the pair of electrodes (sometimes called a lower electrode), and the insulator 130 functions as a dielectric. In other words, the capacitance element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.

15B and 15C, the insulator 180 has an opening 190 that reaches the conductor 110. At least a portion of the conductor 115 is disposed in the opening 190. The conductor 115 has a region that contacts the upper surface of the conductor 110 in the opening 190, a region that contacts the side surface of the insulator 180 in the opening 190, and a region that contacts at least a portion of the upper surface of the insulator 180. The insulator 130 is disposed so that at least a portion of the conductor 120 is disposed so that at least a portion of the conductor 130 is disposed in the opening 190. As shown in FIG. 15B and FIG. 15C, the conductor 120 is preferably disposed so as to fill the opening 190. The films disposed inside the opening 190 are preferably formed by the ALD method. This improves the coverage of the films. For example, the conductor 115, the insulator 130, and the conductor 120 are preferably formed by the ALD method.

In the opening 190, the capacitive element 100 has an upper electrode and a lower electrode that face each other with a dielectric between them, not only on the bottom surface but also on the side surfaces, allowing the capacitance per unit area to be increased. Therefore, the deeper the opening 190, the greater the capacitance of the capacitive element 100 can be. Increasing the capacitance per unit area of the capacitive element 100 in this way can stabilize the read operation of the memory device. It can also promote miniaturization or high integration of memory devices.

15B and 15C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductor 110. In this case, the opening 190 has a cylindrical shape. By using such a configuration, it is possible to miniaturize or highly integrate the memory device.

A conductor 115 and an insulator 130 are stacked along the sidewall of the opening 190 and the top surface of the conductor 110. In addition, a conductor 120 is provided on the insulator 130 so as to fill the opening 190. A capacitance element 100 having such a configuration may be called a trench type capacitance or a trench capacitance.

The insulator 280 is disposed on the capacitance element 100. That is, the insulator 280 is disposed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is disposed below the insulator 280.

The transistor 200 has a conductor 120, a conductor 240 on the insulator 280, an oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. The oxide semiconductor 230 functions as a semiconductor layer, the conductor 260 functions as a gate electrode, the insulator 250 functions as a gate insulator, the conductor 120 functions as one of the source electrode and the drain electrode, and the conductor 240 functions as the other of the source electrode and the drain electrode. Note that instead of the transistor 200, the transistors 200A to 200D shown in FIG. 14A to FIG. 14D may be applied.

15B and 15C, the insulator 280 and the conductor 240 have an opening 290 that reaches the conductor 120. At least a part of the oxide semiconductor 230 is disposed in the opening 290. Note that the oxide semiconductor 230 has a region that contacts the upper surface of the conductor 120 in the opening 290, a region that contacts the side surface of the conductor 240 in the opening 290, and a region that contacts at least a part of the upper surface of the conductor 240. The insulator 250 is disposed so that at least a part of it is located in the opening 290. The conductor 260 is disposed so that at least a part of it is located in the opening 290. Note that the conductor 260 is preferably disposed so as to fill the opening 290, as shown in FIG. 15B and FIG. 15C. Note that the films disposed inside the opening 290 are preferably formed by using the ALD method. This improves the coverage of the film. For example, the oxide semiconductor 230, the insulator 250, and the conductor 260 are preferably formed by an ALD method. By using the metal oxide film formation method of one embodiment of the present invention, the oxide semiconductor 230 can be formed with good coverage.

The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the top surface of the conductor 240. In this way, the oxide semiconductor 230 contacts not only the side surface but also the top surface of the conductor 240, so that the area of contact between the oxide semiconductor 230 and the conductor 240 can be increased.

15A to 15C, the transistor 200 is provided so as to overlap with the capacitor 100. The opening 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductor 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100, so that the transistor 200 and the capacitor 100 share part of their structures. With this configuration, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of the memory cell 150, so that the memory cells 150 can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.

A circuit diagram of the memory device shown in this embodiment is shown in FIG. 15D. As shown in FIG. 15D, the configuration shown in FIG. 15A to FIG. 15C functions as a memory cell of the memory device. The memory cell has a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to the transistor 200, and the capacitor C corresponds to the capacitor 100.

One of the source and drain of the transistor Tr is connected to one of a pair of electrodes of the capacitance element C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitance element C is connected to the wiring PL.

Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 260, and the wiring PL corresponds to the conductor 110. As shown in Figures 15A to 15C, it is preferable that the conductor 260 is provided extending in the Y direction, and the conductor 240 is provided extending in the X direction. With this configuration, the wiring BL and the wiring WL are provided so as to intersect with each other. Also, in Figure 15A, the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited to this. For example, the wiring PL may be provided parallel to the wiring WL (conductor 260) or parallel to the wiring BL (conductor 240).

Memory cells will be explained in more detail in a later embodiment.

[Capacitive element 100]
The capacitor 100 includes a conductor 115, an insulator 130, and a conductor 120. The conductor 110 is provided below the conductor 115. The conductor 115 has a region in contact with the conductor 110.

The conductor 110 is provided on the insulator 140. The conductor 110 functions as the wiring PL and can be provided, for example, in a planar shape. The conductors described in the [Conductor] section below can be used as the conductor 110 in a single layer or a multilayer structure. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductor 110. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved and it can function sufficiently as the wiring PL.

The conductor 115 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, in a single layer or a laminated layer. For example, titanium nitride or indium tin oxide with added silicon may be used. Alternatively, for example, a structure in which titanium nitride is laminated on tungsten may be used. Alternatively, for example, a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used. By using such a structure, when an oxide insulator is used for the insulator 130, the conductor 110 can be prevented from being oxidized by the insulator 130. Also, when an oxide insulator is used for the insulator 180, the conductor 110 can be prevented from being oxidized by the insulator 180.

The insulator 130 is provided on the conductor 115. The insulator 130 is provided so as to contact the upper surface and side surfaces of the conductor 115. In other words, it is preferable that the insulator 130 is structured so as to cover the side end portion of the conductor 110. This can prevent the conductor 115 and the conductor 120 from shorting out.

Also, the side end of the insulator 130 may be aligned with the side end of the conductor 115. By using such a structure, the insulator 130 and the conductor 115 can be formed using the same mask, simplifying the manufacturing process of the memory device.

As the insulator 130, it is preferable to use a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below. By using a high-k material as the insulator 130, the insulator 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitance element 100 can be sufficiently ensured.

The insulator 130 is preferably made of a high-k material and is preferably made of a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high-k material. For example, the insulator 130 may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, the insulator may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. Alternatively, the insulator may be made of an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By using an insulator having a relatively high dielectric strength such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown of the capacitance element 100 can be suppressed.

Also, a material that can have ferroelectricity may be used as the insulator 130. Examples of materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO _x (X is a real number greater than 0). Examples of materials that can have ferroelectricity include a material in which an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of hafnium atoms to the number of atoms of the element J1 may be set to 1:1 or close to 1:1. Examples of materials that can have ferroelectricity include a material in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. In addition, the ratio between the number of zirconium atoms and the number of atoms of element J2 can be set appropriately, for example, the ratio between the number of zirconium atoms and the number of atoms of element J2 may be set to 1: 1 or close to 1. In addition, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure, such as lead titanate (PbTiO _x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.

Also, examples of materials that can have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Also, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2. Also, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitride. It should be noted that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

Furthermore, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO ₂ N and BaTaO ₂ N, and GaFeO ₃ with a κ-alumina structure.

In the above explanation, metal oxides and metal nitrides are given as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

In addition, as a material that can have ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 130 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.

Metal oxides containing one or both of hafnium and zirconium are preferable because they can have ferroelectricity even when processed into a thin film of a few nm. Here, the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). For example, the film thickness is preferably 8 nm to 12 nm. By forming a ferroelectric layer that can be thinned, the capacitive element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In this specification, etc., a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification, etc.

In addition, metal oxides containing one or both of hafnium and zirconium are preferable because they can have ferroelectricity even in a small area. For example, even if the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ² or less, 10 μm ² or less, 1 μm ² or less, or 0.1 μm ² or less, the ferroelectricity can be maintained. In addition, even if the area is 10,000 nm ² or less, or 1,000 nm ² or less, the ferroelectricity may be maintained. By making the ferroelectric layer small in area, the occupied area of the capacitance element 100 can be reduced.

A ferroelectric material is an insulator that is polarized when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the memory device shown in this embodiment functions as a ferroelectric memory.

Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer by an external electric field. It is also presumed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 130 to manifest ferroelectricity, the insulator 130 must contain crystals. In particular, it is preferable for the insulator 130 to contain crystals having an orthorhombic crystal structure, since ferroelectricity is manifested. The crystal structure of the crystals contained in the insulator 130 may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. The insulator 130 may have an amorphous structure. In this case, the insulator 130 may be a composite structure having an amorphous structure and a crystalline structure.

The conductor 120 is provided in contact with a portion of the upper surface of the insulator 130. The side end of the conductor 120 is preferably located inside the side end of the conductor 115 in both the X direction and the Y direction. In a structure in which the insulator 130 covers the side end of the conductor 115, the side end of the conductor 120 may be located outside the side end of the conductor 115.

The conductor 120 may be a single layer or a laminate of the conductors described in the section [Conductor] described later. It is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 120. For example, titanium nitride or tantalum nitride may be used. For example, a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, the titanium nitride is in contact with the insulator 130, and the tantalum nitride is in contact with the oxide semiconductor 230. With such a structure, the conductor 120 can be prevented from being excessively oxidized by the oxide semiconductor 230. In addition, when an oxide insulator is used as the insulator 130, the conductor 120 can be prevented from being excessively oxidized by the insulator 130. Alternatively, the conductor 120 may be a structure in which tungsten is laminated on titanium nitride, for example.

In addition, since the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described later. By using a conductive material containing oxygen as the conductor 120, the conductor 120 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is preferable because it can maintain its conductivity. As the conductor 120, for example, indium tin oxide (also referred to as ITO), indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), or the like can be used in a single layer or a stacked layer.

Since the insulator 180 functions as an interlayer film, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. As the insulator 180, an insulator containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used in a single layer or a multilayer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. In this case, the insulator 180b contains at least silicon and oxygen.

Note that insulator 180 is shown as a single layer in Figures 15B and 15C, but the present invention is not limited to this. Insulator 180 may have a two-layer laminated structure, or a three-layer or more laminated structure. For example, as shown in Figures 19A to 19D, 20A, and 20B, insulator 180 may have a laminated structure of insulator 180a and insulator 180b on insulator 180a.

For the insulator 180b, it is preferable to use an insulating material that can be used for the insulator 180 described above.

For the insulator 180a, it is preferable to use an insulator having barrier properties against oxygen, as described in the [Insulator] section below. The oxygen contained in the insulator 180b may oxidize the conductor 110, increasing its resistance. By providing the insulator 180a between the insulator 180b and the conductor 110, it is possible to prevent the conductor 110 from being oxidized and its resistance from increasing.

When impurities such as hydrogen are mixed into the insulator 130, the leakage current between the upper electrode and the lower electrode may increase. Furthermore, when a material that may have ferroelectricity is used as the insulator 130, the inclusion of impurities such as hydrogen in the material that may have ferroelectricity may reduce the crystallinity of the material that may have ferroelectricity. Therefore, it is preferable to prevent impurities such as hydrogen from being mixed into the insulator 130.

Therefore, it is preferable to use an insulator having barrier properties against hydrogen, as described in the [Insulator] section below, for the insulator 180a. This can suppress the diffusion of hydrogen into the insulator 130 through the insulator 180b and the conductor 115. Silicon nitride and silicon nitride oxide each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulator 180a. In this case, the insulator 180a contains at least silicon and nitrogen.

Furthermore, it is preferable to use an insulator having the function of capturing or fixing hydrogen, as the insulator 180a, as described in the [Insulator] section below. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used as the insulator 180a. For example, a laminate film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 180a.

For example, when the insulator 180 has a three-layer structure, in addition to the insulators 180a and 180b, an insulator may be provided between the conductor 115 and the insulator 130 and the insulator 180b. An insulator that can be used for the insulator 180a can be used as the insulator. This can prevent hydrogen from diffusing into the insulator 130 through the insulator 180b.

[Transistor 200]
As shown in Figures 15A to 15C, the transistor 200 can have a structure including a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230 provided in contact with the upper surface of the conductor 120 exposed in an opening 290, a side surface of the insulator 280 in the opening 290, a side surface of the conductor 240 in the opening 290, and at least a portion of the upper surface of the conductor 240, an insulator 250 provided in contact with the upper surface of the oxide semiconductor 230, and a conductor 260 provided in contact with the upper surface of the insulator 250.

At least some of the components of the transistor 200 are disposed in the opening 290. Here, the bottom of the opening 290 is the top surface of the conductor 120, and the sidewalls of the opening 290 are the side surfaces of the insulator 280 and the side surfaces of the conductor 240.

15B and 15C show an example in which the sidewall of the opening 290 is perpendicular to the top surface of the conductor 110. In this case, the opening 290 has a cylindrical shape. By using such a configuration, it is possible to miniaturize or highly integrate the memory device.

In addition, in this embodiment, an example has been shown in which the opening 290 is circular in plan view, but the present invention is not limited to this. For example, the opening 290 may be approximately circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in plan view. In this case, the maximum width of the opening 290 may be calculated appropriately according to the shape of the top of the opening 290. For example, if the opening is rectangular in plan view, the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.

The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290. Thus, the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided to cover the oxide semiconductor 230, and the conductor 260 is provided to fill the recess of the insulator 250 that reflects the shape of the opening 290.

Here, FIG. 16A shows an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 15B. FIG. 16B shows a cross-sectional view in the XY plane including the conductor 240 (which can also be said to be a cross-sectional view between the dashed dotted line B1-B2).

As shown in FIG. 16A, the oxide semiconductor 230 has a region 230i and regions 230na and 230nb that are arranged to sandwich the region 230i.

Region 230na is a region of oxide semiconductor 230 in contact with conductor 120. At least a part of region 230na functions as one of the source region and drain region of transistor 200. Region 230nb is a region of oxide semiconductor 230 in contact with conductor 240. At least a part of region 230nb functions as the other of the source region and drain region of transistor 200. As shown in FIG. 16B, conductor 240 is in contact with the entire outer periphery of oxide semiconductor 230. Thus, the other of the source region and drain region of transistor 200 can be formed on the entire outer periphery of a portion of oxide semiconductor 230 that is formed in the same layer as conductor 240.

Region 230i is a region between regions 230na and 230nb of the oxide semiconductor 230. At least a part of region 230i functions as a channel formation region of the transistor 200. In other words, the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or in the vicinity of the region.

The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120. In FIG. 16A, the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 contact each other and the end of the region where the oxide semiconductor 230 and the conductor 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.

In a planar transistor, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be made to be a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200, and improves the frequency characteristics. Therefore, the read speed and write speed of the memory cell 150 can be improved, and a memory device with high operating speed can be provided.

Furthermore, as described above, the channel formation region, source region, and drain region can be formed in the opening 290. This allows the area occupied by the transistor 200 to be reduced compared to conventional transistors in which the channel formation region, source region, and drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, thereby increasing the memory capacity per unit area.

16B, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically in the XY plane including the channel formation region of the oxide semiconductor 230. Therefore, the side of the conductor 260 arranged at the center faces the side of the oxide semiconductor 230 through the insulator 250. That is, in a plan view, the entire circumference of the oxide semiconductor 230 becomes the channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the outer periphery length of the oxide semiconductor 230. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (maximum diameter when the opening 290 is circular in a plan view). In FIGS. 16A and 16B, the maximum width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line. In FIG. 16B, the channel width W of the transistor 200 is indicated by a double-dot chain line of a one-dot chain line. By increasing the maximum width D of the opening 290, the channel width per unit area can be increased, and the on-current can be increased.

When the opening 290 is formed by photolithography, the maximum width D of the opening 290 is set by the exposure limit of photolithography. The maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

Furthermore, in the memory device of one embodiment of the present invention, the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200. The channel length L of the transistor 200 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

In addition, by forming the opening 290 so that it has a circular shape in a plan view, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. This makes the distance between the conductor 260 and the oxide semiconductor 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.

It is preferable that the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. In addition, since hydrogen near the oxygen vacancies may form defects (hereinafter sometimes referred to as _VOH ) in which hydrogen enters the oxygen vacancies and generate electrons that serve as carriers, it is preferable that _VOH is also reduced in the channel formation region. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, it can be said that the channel formation region of the transistor is i-type (intrinsic) or substantially i-type.

Furthermore, the source and drain regions of a transistor that uses an oxide semiconductor for its semiconductor layer have more oxygen vacancies, more _VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, and thus have an increased carrier concentration and low resistance. In other words, the source and drain regions of the transistor are n-type regions that have a higher carrier concentration and lower resistance than the channel formation region.

15B and 15C, the opening 290 is provided so that the sidewall of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this. For example, the sidewall of the opening 290 may have a tapered shape. Tapered sidewalls of the opening 290 are preferable because they improve the coverage of the oxide semiconductor 230, the insulator 250, and the like provided along the opening 290.

Similarly, in Figures 15B and 15C, the opening 190 is provided so that the sidewall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this. For example, the sidewall of the opening 190 may have a tapered or inverse tapered shape. A tapered sidewall of the opening 190 is preferable because it improves the coverage of the conductor 115, insulator 130, etc. that are provided along the opening 190.

The storage device shown in Figures 17A and 17B has a configuration in which the side walls of the opening 290 are tapered. Note that Figure 15A can be referred to for a plan view of the storage device shown in Figures 17A and 17B.

By tapering the sidewall of the opening 290, the coverage of the oxide semiconductor 230 or the insulator 250 can be improved, and defects such as voids can be reduced. For example, the angle (angle θ1 shown in FIG. 17A ) between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 110 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.

The shape of the opening 290 shown in Figures 17A and 17B is a truncated cone. In this case, the opening 290 is circular in plan view and trapezoidal in cross section. The area of the upper base surface of the truncated cone (e.g., the opening provided in the conductor 240) is smaller than the area of the lower base surface of the truncated cone (the upper surface of the conductor 120 exposed at the opening 290). In this case, the maximum diameter of the opening 290 may be calculated based on the upper base surface of the truncated cone.

When the sidewall of the opening 290 is tapered, the channel length can be set by the film thickness of the insulator 280 and the angle θ1 between the side surface of the insulator 280 at the opening 290 and the top surface of the conductor 110. The perimeter of the oxide semiconductor 230 may be determined, for example, in a region facing the conductor 240 or at a position half the film thickness of the insulator 280. If necessary, the perimeter at any position of the opening 290 may be the channel width of the transistor 200. For example, the perimeter at the bottom of the opening 290 may be the channel width, or the perimeter at the top of the opening 290 may be the channel width.

17A and 17B show a configuration in which the side of the conductor 240 in the opening 290 and the side of the insulator 280 in the opening 290 coincide with each other, but the present invention is not limited to this. For example, the side of the conductor 240 in the opening 290 and the side of the insulator 280 in the opening 290 may be discontinuous. The inclination of the side of the conductor 240 in the opening 290 and the inclination of the side of the insulator 280 in the opening 290 may differ from each other. For example, the angle between the side of the conductor 240 in the opening 290 and the upper surface of the conductor 110 is preferably smaller than the angle θ1. With such a configuration, the coverage of the oxide semiconductor 230 on the side of the conductor 240 in the opening 290 is improved, and defects such as voids can be reduced.

17A and 17B, the bottom of the conductor 260 located in the opening 290 has a flat region. Note that depending on the size of the maximum width of the opening 290 (maximum diameter when the opening 290 is circular in plan view), the film thickness of the insulator 280 (corresponding to the depth of the opening 290), the film thickness of the oxide semiconductor 230, and the film thickness of the insulator 250, the bottom of the conductor 260 located in the opening 290 may not have a flat region. For example, as shown in FIGS. 17C and 17D, the shape of the bottom of the conductor 260 located in the opening 290 may be needle-like. Note that FIG. 15A can be referred to for the plan views of the memory device shown in FIGS. 17C and 17D.

Here, needle-like refers to a shape that becomes thinner toward the tip (closer to the bottom of the conductor 260 located in the opening 290). The tip of the needle may be acute-angled or may have a curved shape that is convex downward. Among needle-like shapes, a shape with an acute-angled tip may be called a V-shape.

Of the conductor 260 located in the opening 290, the region facing the oxide semiconductor 230 via the insulator 250 functions as a gate electrode. Therefore, the conductor 260 that fills the opening 290 and has a needle-shaped bottom may be called a needle-shaped gate. Also, as shown in Figures 17A and 17B, even if the conductor 260 has a shape with a flat bottom, it may still be called a needle-shaped gate.

Furthermore, by tapering the sidewall of the opening 190, the coverage of the conductor 115 or the insulator 130, etc. can be improved, and defects such as voids can be reduced. For example, the angle (angle θ2 shown in FIG. 17A) between the side surface of the insulator 180 at the opening 190 and the top surface of the conductor 110 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.

As shown in Figures 17A and 17B, the bottom of the conductor 120 located at the opening 190 has a flat region. Note that depending on the size of the maximum width of the opening 190 (maximum diameter when the opening 190 is circular in plan view), the film thickness of the insulator 180 (corresponding to the depth of the opening 190), the film thickness of the conductor 115, and the film thickness of the insulator 130, the bottom of the conductor 120 located at the opening 190 may not have a flat region. For example, as shown in Figures 17C and 17D, the shape of the bottom of the conductor 120 located at the opening 190 may be needle-shaped. Note that Figure 15A can be referred to for the plan views of the storage device shown in Figures 17C and 17D.

Furthermore, when the insulators 180 and 280 are made of the same material, the angles θ1 and θ2 are the same or approximately the same. Note that the angles θ1 and θ2 may be different depending on the materials used for the insulators 180 and 280, respectively, and the methods for forming the openings 190 and 290, respectively. For example, the angle θ1 may be greater than the angle θ2, or may be smaller than the angle θ2. Furthermore, one of the angles θ1 and θ2 may be 90 degrees or a value close to it.

As shown in Figures 15B and 15C, a part of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240. Also, Figures 15B and 15C show a configuration in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240. Note that the present invention is not limited to this. For example, a structure in which the side end of the oxide semiconductor 230 and the side end of the conductor 240 coincide in the X direction or Y direction may be used. Alternatively, a structure in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240 may be used.

The band gap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current in a memory cell, stored contents can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. Note that in a typical DRAM, the frequency of the refresh operation needs to be about once per 60 msec. However, in the memory device of one embodiment of the present invention, the frequency of the refresh operation can be about once per 10 sec, which is 10 times or more or 100 times or more. Note that in the memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to once per 1 sec to 100 sec, preferably once per 5 sec to 50 sec.

Note that the metal oxide described in embodiment 1 can be used as the oxide semiconductor 230 in a single layer or a stacked layer form.

Specific examples of the oxide semiconductor 230 include metal oxides having a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:3:4 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:2 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof. Note that the composition in the vicinity includes a range of ±30% of the desired atomic ratio. It is also preferable to use gallium as the element M.

By using a material with a high indium content for the oxide semiconductor 230, the on-state current or the field effect mobility of the transistor can be increased. Furthermore, by containing the element M, the generation of oxygen vacancies (V _{2 O 3} ) can be suppressed. The content of the element M (the ratio of the number of atoms of the element M to the sum of the numbers of atoms of all the metal elements contained) is preferably 0.1% to 10%, more preferably 0.1% to 3%, and even more preferably 0.1% to 2%. This allows the transistor to have good electrical characteristics. For example, it is preferable to use a metal oxide having a composition of In:M:Zn=40:X:10 (X is 1 to 5) [atomic ratio] or a composition close thereto. The element M is preferably one or more of the above elements, and more preferably one or more selected from gallium, tin, and yttrium. Specifically, a metal oxide having a composition of In:Sn:Zn=40:1:10 or a composition close thereto can be suitably used.

When a metal oxide film is formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.

For example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used to analyze the composition of the metal oxide used in the oxide semiconductor 230. Alternatively, a combination of these techniques may be used for the analysis. In addition, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

The atomic layer deposition (ALD) method can be suitably used to form metal oxides.

Alternatively, the metal oxide may be formed by sputtering or CVD. When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

The oxide semiconductor 230 preferably has crystallinity (also referred to as having a crystalline portion). Examples of oxide semiconductors having crystallinity (also referred to as crystalline oxide semiconductors) include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, single-crystalline oxide semiconductors, and the like. As the oxide semiconductor 230, it is preferable to use CAAC-OS or nc-OS, and it is particularly preferable to use CAAC-OS.

The CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed. For example, the oxide semiconductor 230 preferably has layered crystals that are approximately parallel to the sidewall of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 230 are formed approximately parallel to the channel length direction of the transistor 200, thereby increasing the on-state current of the transistor.

CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not become polycrystallized after the formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

In addition, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

The oxide semiconductor 230 may have a laminated structure of multiple oxide layers with different chemical compositions. For example, it may have a structure in which multiple types selected from the above metal oxides are appropriately laminated.

18A and 18B, the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b on the oxide semiconductor 230a. At least one of the oxide semiconductor 230a and the oxide semiconductor 230b is preferably formed by the metal oxide film formation method of one embodiment of the present invention.

The conductivity of the material used for oxide semiconductor 230a is preferably different from the conductivity of the material used for oxide semiconductor 230b.

For example, the oxide semiconductor 230a can be made of a material having a higher conductivity than the oxide semiconductor 230b. By using a material having a high conductivity for the oxide semiconductor 230a in contact with the conductor 120 and the conductor 240 that function as a source electrode or a drain electrode, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with a large on-state current can be obtained.

When a material with high conductivity is used for the oxide semiconductor 230b provided on the side of the conductor 260 functioning as the gate electrode, the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b. As a result, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as a normally-off transistor.

As described above, by forming the oxide semiconductor 230 into a stacked structure and using a material having a higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, a memory device that achieves both low power consumption and high performance can be obtained.

Note that the carrier concentration of the oxide semiconductor 230a is preferably higher than that of the oxide semiconductor 230b. Increasing the carrier concentration of the oxide semiconductor 230a increases the conductivity, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, resulting in a transistor with a large on-state current. Reducing the carrier concentration of the oxide semiconductor 230b decreases the conductivity, resulting in a normally-off transistor.

Here, an example is shown in which the oxide semiconductor 230a is made of a material having a higher conductivity than the oxide semiconductor 230b; however, one embodiment of the present invention is not limited to this. The oxide semiconductor 230a may be made of a material having a lower conductivity than the oxide semiconductor 230b. A configuration can be adopted in which the carrier concentration of the oxide semiconductor 230a is lower than the carrier concentration of the oxide semiconductor 230b.

The band gap of the first metal oxide used in the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used in the oxide semiconductor 230b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

The band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b. This can reduce the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240, and can provide a transistor with a large on-state current. In addition, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.

Here, an example is shown in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide, but one embodiment of the present invention is not limited to this. A configuration in which the band gap of the first metal oxide is larger than the band gap of the second metal oxide can be used.

As described above, the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the compositions of the first metal oxide and the second metal oxide different, the band gap can be controlled. For example, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. Specifically, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition therearound, and the second metal oxide can have a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition therearound. It is particularly preferable to use one or both of gallium and tin as the element M.

The first metal oxide may not contain the element M. For example, the first metal oxide used in the oxide semiconductor 230a may be an In-Zn oxide, and the second metal oxide used in the oxide semiconductor 230b may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide. More specifically, the first metal oxide may have a composition of In:Zn=1:1 [atomic ratio] or a composition therearound, or a composition of In:Zn=4:1 [atomic ratio] or a composition therearound, and the second metal oxide may have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound.

Here, an example is shown in which the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this. The content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the contents of elements other than element M may be different.

The thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

The thickness of each layer (here, oxide semiconductor 230a and oxide semiconductor 230b) constituting the oxide semiconductor 230 may be determined so that the thickness of the oxide semiconductor 230 falls within the above-mentioned range. The thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 fall within the required range. The thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor falls within the required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.

18A and 18B show a configuration in which the oxide semiconductor 230 has a two-layer stacked structure of the oxide semiconductor 230a and the oxide semiconductor 230b, but the present invention is not limited to this. The oxide semiconductor 230 may have a stacked structure of three or more layers.

When the oxide semiconductor 230 has a three-layer stacked structure, for example, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition thereabout, or a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition thereabout, and a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout may be provided in this order from the conductor 120 side. With such a configuration, the on-current of the transistor 200 can be increased and a highly reliable transistor structure with little variation can be obtained.

As the insulator 250, the insulators described in the section [Insulators] below can be used in a single layer or a multilayer. For example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferred because they are stable against heat.

In addition, the insulator 250 may be a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below. For example, hafnium oxide or aluminum oxide may be used.

The thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that the insulator 250 has a region with the above-mentioned thickness in at least a portion.

It is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

As shown in Figures 15B and 15C, a portion of the insulator 250 is located outside the opening 290, i.e., above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 covers the side end of the oxide semiconductor 230. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out. It is also preferable that the insulator 250 covers the side end of the conductor 240. This can prevent the conductor 260 and the conductor 240 from shorting out.

As shown in Figures 18A and 18B, the insulator 250 may have a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

The insulator 250b is preferably made of a material with a low dielectric constant, as described in the [Insulator] section below. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 250b contains at least oxygen and silicon. This configuration can reduce the parasitic capacitance that occurs between the conductor 260 and the conductor 240. It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.

The insulator 250a is preferably an insulator having a barrier property against oxygen, as described in the [Insulator] section below. The insulator 250a has a region in contact with the oxide semiconductor 230. When the insulator 250a has a barrier property against oxygen, it is possible to suppress oxygen from being released from the oxide semiconductor 230 during heat treatment or the like. This can suppress the formation of oxygen vacancies in the oxide semiconductor 230. This can improve the electrical characteristics and reliability of the transistor 200. For example, aluminum oxide is preferably used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.

The insulator 250c is preferably an insulator having a barrier property against hydrogen as described in the [Insulator] section below. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has high hydrogen barrier properties and is therefore suitable as the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.

The insulator 250c may further have a barrier property against oxygen. The insulator 250c is provided between the insulator 250b and the conductor 260. This prevents the oxygen contained in the insulator 250b from diffusing into the conductor 260, suppressing oxidation of the conductor 260. In addition, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.

Further, an insulator may be provided between the insulator 250b and the insulator 250c. As the insulator, it is preferable to use an insulator having a function of capturing or fixing hydrogen, as described in the section [Insulator] below. By providing the insulator, hydrogen contained in the oxide semiconductor 230 can be captured or fixed more effectively. Thus, the hydrogen concentration in the oxide semiconductor 230 can be reduced. For example, hafnium oxide may be used as the insulator. In this case, the insulator contains at least oxygen and hafnium. The insulator may have an amorphous structure.

When miniaturizing the transistor 200, the thicknesses of the insulators 250a to 250c are preferably thin and within the aforementioned range. Typically, the thicknesses of the insulators 250a, 250b, the insulator having the function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a configuration, the transistor 200 can have good electrical characteristics even when miniaturized or highly integrated.

Although Figures 18A and 18B show a configuration in which the insulator 250 has a three-layer stacked structure of insulators 250a to 250c, the present invention is not limited to this. The insulator 250 may also have a two-layer or four or more layer stacked structure. In this case, each layer included in the insulator 250 may be appropriately selected from insulators 250a to 250c and insulators that have the function of capturing or fixing hydrogen.

The conductor 260 may be a single layer or a multilayer of the conductors described in the section [Conductor] below. For example, the conductor 260 may be a highly conductive material such as tungsten.

In addition, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260. Examples of such conductive materials include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This makes it possible to suppress a decrease in the conductivity of the conductor 260.

As shown in Figures 18A and 18B, the conductor 260 may have a layered structure of a conductor 260a and a conductor 260b on the conductor 260a. In this case, for example, titanium nitride may be used as the conductor 260a, and tungsten may be used as the conductor 260b. By providing tungsten in a layered structure in this manner, the conductivity of the conductor 260 can be improved, allowing it to function sufficiently as the wiring WL.

15B and 15C, the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this. For example, a recess reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a part of the recess may be located in the opening 290. In this case, the recess may be filled with an inorganic insulating material or the like.

Furthermore, as shown in FIG. 15B and FIG. 15C, a part of the conductor 260 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. In this case, as shown in FIG. 15B, it is preferable that the side end of the conductor 260 is located inside the side end of the oxide semiconductor 230. This makes it possible to prevent a short circuit between the conductor 260 and the oxide semiconductor 230. Note that the side end of the conductor 260 may coincide with the side end of the oxide semiconductor 230, or may be located outside the side end of the oxide semiconductor 230.

The conductor 120 may be provided as described in the [Capacitive element 100] section.

15B and 15C show a configuration in which the top surface of the conductor 120 is flat, but the present invention is not limited to this. For example, a configuration in which a recess that overlaps with the opening 290 is formed on the top surface of the conductor 120 may be used. By forming at least a portion of the oxide semiconductor 230, the insulator 250, and the conductor 260 so as to fill the recess, it is possible to easily apply the gate electric field of the conductor 260 up to the vicinity of the conductor 120 of the oxide semiconductor 230.

The conductor 240 may be a single layer or a multilayer of the conductors described in the section [Conductor] below. For example, the conductor 240 may be a highly conductive material such as tungsten.

As with the conductor 260, it is preferable that the conductor 240 is made of a conductive material that is not easily oxidized or that has a function of suppressing the diffusion of oxygen. For example, titanium nitride or tantalum nitride can be used. With this configuration, it is possible to suppress excessive oxidation of the conductor 240 by the oxide semiconductor 230.

Also, for example, a structure in which tungsten is laminated on titanium nitride may be used. By laminating tungsten in this manner, the conductivity of the conductor 240 can be improved, allowing it to function adequately as the wiring BL.

In addition, when the conductor 240 is configured by stacking a first conductor and a second conductor, for example, the first conductor may be formed using a conductive material with high conductivity, and the second conductor may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductor of the conductor 240 that contacts the insulator 250, it is possible to suppress the oxygen in the insulator 250 from diffusing into the first conductor of the conductor 240. For example, it is preferable to use tungsten as the first conductor of the conductor 240, and indium tin oxide with added silicon as the second conductor of the conductor 240.

When the oxide semiconductor 230 and the conductor 120 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of the region 230na of the oxide semiconductor 230 is reduced. When the oxide semiconductor 230 comes into contact with the conductor 120, the contact resistance between the oxide semiconductor 230 and the conductor 120 is reduced. Similarly, when the oxide semiconductor 230 and the conductor 240 come into contact with each other, the resistance of the region 230nb of the oxide semiconductor 230 is reduced. Therefore, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

Since the insulators 140 and 280 function as interlayer films, it is preferable that they have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. As the insulators 140 and 280, insulators containing a material with a low dielectric constant, as described in the [Insulators] section below, can be used in a single layer or a stack. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Furthermore, it is preferable that the concentrations of impurities such as water and hydrogen in the insulator 140 and the insulator 280 are reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230.

The insulator 280 disposed in the vicinity of the channel formation region is preferably an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). By performing heat treatment on the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and _VOH . As a result, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.

The insulator 280 may be an insulator having a function of capturing or fixing hydrogen, as described in the [Insulator] section below. With such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 230 can be reduced. Magnesium oxide, aluminum oxide, or the like can be used as the insulator 280.

The insulator 280 may have a single layer structure or a laminated structure of two or more layers. For example, as shown in Figures 19A and 19B, the insulator 280 may have a laminated structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b.

The insulator 280b is preferably an insulator containing oxygen. The insulator 280b preferably has a region with a higher oxygen content than at least one of the insulators 280a and 280c. In particular, the insulator 280b preferably has a region with a higher oxygen content than each of the insulators 280a and 280c. Increasing the oxygen content of the insulator 280b makes it easier to form an i-type region in the region of the oxide semiconductor 230 that is in contact with the insulator 280b and in its vicinity.

It is more preferable to use a film that releases oxygen when heated for the insulator 280b. When the insulator 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor 230. When oxygen is supplied from the insulator 280b to the oxide semiconductor 230, particularly to the channel formation region of the oxide semiconductor 230, oxygen vacancies and _VOH in the oxide semiconductor 230 can be reduced, and the transistor can have favorable electrical characteristics and high reliability.

For example, oxygen can be supplied to the insulator 280b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Oxygen may also be supplied by forming an oxide film on the upper surface of the insulator 280b in an oxygen atmosphere by a sputtering method. The oxide film may then be removed.

The insulator 280b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method. In particular, when a sputtering method is used, hydrogen gas is not required as a deposition gas, and a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the oxide semiconductor 230 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized.

When the channel length of the transistor 200 is short, the influence of oxygen vacancies and _VOH in the channel formation region on the electrical characteristics and reliability is particularly large. By supplying oxygen from the insulator 280b to the oxide semiconductor 230, an increase in oxygen vacancies and _VOH can be suppressed at least in a region of the oxide semiconductor 230 in contact with the insulator 280b. Therefore, a transistor with a short channel length having favorable electrical characteristics and high reliability can be realized.

The insulators 280a and 280c are preferably made of an insulator having a barrier property against oxygen, as described in the [Insulator] section below. This can prevent oxygen contained in the insulator 280b from diffusing to the substrate side through the insulator 280a due to heating, and from diffusing to the insulator 250 side through the insulator 280c. In other words, by sandwiching the insulator 280b from above and below with the insulators 280a and 280c, through which oxygen does not easily diffuse, the oxygen contained in the insulator 280b can be trapped. This can effectively supply oxygen to the oxide semiconductor 230.

In addition, the oxygen contained in the insulator 280b may oxidize the conductor 120 and the conductor 240, resulting in an increase in resistance. By providing the insulator 280a between the insulator 280b and the conductor 120, the conductor 120 can be prevented from being oxidized and the resistance from increasing. By providing the insulator 280c between the insulator 280b and the conductor 240, the conductor 240 can be prevented from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, thereby reducing oxygen vacancies in the oxide semiconductor 230.

In addition, the region of the oxide semiconductor 230 in contact with the insulator 280a and the region in contact with the insulator 280c receives a smaller amount of oxygen than the region in contact with the insulator 280b. Therefore, the region of the oxide semiconductor 230 in contact with the insulator 280a and the region in contact with the insulator 280c may have low resistance. In other words, by adjusting the thickness of the insulator 280a, the range of the region 230na that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb that functions as the other of the source region and the drain region can be controlled.

As described above, the source region and drain region can be controlled by the film thickness of insulator 280a and insulator 280c, so the film thickness of insulator 280a and insulator 280c can be set appropriately according to the characteristics desired for transistor 200.

For example, as shown in Figures 19A and 19B, the film thickness of insulator 280c and the film thickness of insulator 280a may be approximately the same. Or, as shown in Figures 19C and 19D, the film thickness of insulator 280c may be smaller than the film thickness of insulator 280a. By using the configuration shown in Figures 19C and 19D, region 230na can be brought closer to the bottom of conductor 260 in opening 290. In this case, it can also be said that the range of region 230i is narrowed. This can improve the on-current of transistor 200.

19C and 19D show a configuration in which the insulator 280c is provided on the planarized insulator 280b, but the present invention is not limited to this. For example, the insulator 280c may be formed without performing planarization treatment on the insulator 280b. By not performing planarization treatment, the manufacturing cost can be reduced and the production yield can be increased. In addition, the insulators 280a, 280b, and 280c can be formed successively without exposure to the atmospheric environment. By forming the insulators 280a to 280c without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to keep the vicinity of the interface between the insulators 280a and 280b and the vicinity of the interface between the insulators 280b and 280c clean.

The insulators 280a and 280c are preferably made of an insulator having a barrier property against hydrogen, as described in the [Insulator] section below. This can prevent hydrogen from diffusing from the outside of the transistor to the oxide semiconductor 230 through the insulator 280a or the insulator 280c. Silicon nitride films and silicon nitride oxide films each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulators 280a and 280c. Note that the insulators 280a and 280c may be made of the same material or different materials.

Insulator 280a is preferably an insulator having a function of capturing or fixing hydrogen, as described in the [Insulator] section below. With such a configuration, hydrogen can be prevented from diffusing from below insulator 280a to oxide semiconductor 230, and hydrogen in oxide semiconductor 230 can be captured or fixed, thereby reducing the hydrogen concentration in oxide semiconductor 230. Insulator 280a can be prevented from diffusing from above insulator 280a to insulator 130, and hydrogen in insulator 130 can be captured or fixed, thereby reducing the hydrogen concentration in insulator 130. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used as insulator 280a. For example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as insulator 280a.

The thickness of the insulator 280a is preferably smaller than that of the insulator 280b. The thickness of the insulator 280c is preferably smaller than that of the insulator 280b. The thicknesses of the insulators 280a and 280c are preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and further preferably 3 nm or more and 5 nm or less. The thickness of the insulator 280b is preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 7 nm or more and 15 nm or less. By setting the thicknesses of the insulators 280a to 280c in the above ranges, oxygen vacancies in the oxide semiconductor 230, especially in the channel formation region, can be reduced.

For example, it is preferable to use silicon nitride for the insulators 280a and 280c, and silicon oxide for the insulator 280b. In this case, each of the insulators 280a and 280c contains at least silicon and nitrogen. Also, the insulator 280b contains at least silicon and oxygen.

20A and 20B show a configuration in which the insulator 280 has a three-layer stacked structure, but this is not a limitation of one embodiment of the present invention. The insulator 280 may have a two-layer or four or more layer stacked structure.

The insulator 283 is preferably an insulator having barrier properties against hydrogen, as described in the [Insulator] section below. This can prevent hydrogen from diffusing from outside the transistor to the oxide semiconductor 230 through the insulator 250. A silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulator 283.

Furthermore, it is preferable to use, as the insulator 283, an insulator having a function of capturing hydrogen or fixing hydrogen, as described in the section [Insulator] below. With such a structure, it is possible to suppress diffusion of hydrogen from above the insulator 283 to the oxide semiconductor 230, and further to capture or fix hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration in the oxide semiconductor 230. As the insulator 283, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. For example, the insulator 283 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

15B and 15C show a configuration having a region where the upper surface of the conductor 120 and the lower surface of the oxide semiconductor 230 are in contact with each other, but the present invention is not limited to this. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230.

For example, as shown in FIG. 20A and FIG. 20B, a conductor 125 may be provided between the conductor 120 and the oxide semiconductor 230. As the conductor 125, it is preferable to use a conductive material containing oxygen described in the section [Conductor] below. By using a conductive material containing oxygen as the conductor 125, the conductivity can be maintained even if the conductor 125 absorbs oxygen. In addition, the diffusion of oxygen in the oxide semiconductor 230 to the conductor 120 can be suppressed. As the conductor 125, for example, indium tin oxide, indium tin oxide with added silicon, indium zinc oxide, or the like can be used in a single layer or a stacked layer.

In Figs. 15B and 15C, a configuration is shown in which the conductor 240 is provided on the insulator 280. Also, a configuration is shown in which the area of the insulator 250 that does not overlap with the conductor 240 has an area that is in contact with the upper surface of the insulator 280. Note that the present invention is not limited to this.

For example, the conductor 240 may be configured to be embedded in the insulator. In this case, it is preferable that the height of the upper surface of the conductor 240 matches the height of the upper surface of the insulator. By configuring in this way, the physical distance from the conductor 260 to the conductor 240 (particularly the side end of the conductor 240) can be increased, and a short circuit between the conductor 260 and the conductor 240 can be prevented.

Here, an example of a method for manufacturing the memory cell 150 shown in FIG. 15A to FIG. 15C is described. First, an insulator 180 is formed on the conductor 110, and the insulator 180 is processed to form an opening 190 that reaches the conductor 110. Next, a conductor 115 that contacts the side surface of the insulator 180 in the opening 190 is formed, an insulator 130 is formed on the conductor 115, a conductor 120 is formed on the insulator 130, an insulator 280 is formed on the conductor 120, and a conductor 240 is formed on the insulator 280. Then, the conductor 240 and the insulator 280 are processed, respectively, to form an opening 290 that reaches the conductor 120. Next, an oxide semiconductor 230 that contacts the top surface of the conductor 120, the side surface of the insulator 280, and the top surface and side surface of the conductor 240 in the opening 290 is formed, an insulator 250 is formed on the oxide semiconductor 230, and a conductor 260 is formed on the insulator 250. In this manner, the memory cell 150 can be formed. Here, the oxide semiconductor 230 is preferably formed using the metal oxide film formation method described in embodiment 1.

<Constituent materials of semiconductor device and memory device>
Materials that can be used for the semiconductor device and the memory device will be described below. Note that for a metal oxide that can be used for the oxide semiconductor 230, reference can be made to Embodiment 1.

[substrate]
As the substrate on which the transistor 200 and the capacitor element 100 are formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate can be used. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used. Furthermore, as the semiconductor substrate, for example, a semiconductor substrate having an insulating region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, can be used. As the conductive substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be used. As the substrate, for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate can be used. Alternatively, one or more elements may be provided on the substrate, for example, a capacitance element, a resistance element, a switching element, a light-emitting element, and a memory element.

[Insulator]
Examples of the insulator include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator. Note that a material with a low dielectric constant also has a high dielectric strength.

Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids. These silicon oxides may contain nitrogen.

In addition, the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

Insulators in contact with a semiconductor, such as a gate insulator, or insulators provided near a semiconductor layer are preferably insulators having a region containing excess oxygen. For example, by providing an insulator having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.

Insulators having barrier properties against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. In addition, oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

Insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to have a barrier property against either or both of oxygen and hydrogen.

Insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these metal oxides have an amorphous structure, but crystalline regions may be formed in some parts.

In this specification and the like, the barrier property refers to a property that the corresponding substance does not easily diffuse (also referred to as a property that the corresponding substance does not easily permeate, a property that the corresponding substance has low permeability, or a function that suppresses the diffusion of the corresponding substance). The function of capturing or fixing the corresponding substance (also referred to as gettering) can be rephrased as the barrier property. Note that hydrogen when described as the corresponding substance refers to at least one of, for example, hydrogen atoms, hydrogen molecules, and substances bonded to hydrogen such as water molecules and OH ⁻ . Furthermore, impurities when described as the corresponding substance refer to impurities in the channel formation region or the semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ , etc.), copper atoms, etc. Furthermore, oxygen when described as the corresponding substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc. Specifically, the barrier property against oxygen refers to a property that at least one of oxygen atoms, oxygen molecules, etc. does not easily diffuse.

[conductor]
As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

In addition, conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

In addition, multiple conductors made of the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen. In addition, a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen. In addition, a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

When a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed in from an external insulator or the like.

[Other semiconductor materials]
The oxide semiconductor 230 can be rephrased as a semiconductor layer including a channel formation region of a transistor. A semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as the semiconductor. For example, a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material.

Here, in this specification and the like, layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

Examples of semiconductor elements that can be used in the semiconductor material include silicon and germanium. Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. The boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure. The boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic structure.

Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In the layered material boron carbonitride, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

As the semiconductor layer, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS ₂ ), molybdenum selenide (representatively MoSe ₂ ), molybdenum tellurium (representatively MoTe ₂ ), tungsten sulfide (representatively WS ₂ ), tungsten selenide (representatively WSe ₂ ), tungsten tellurium (representatively WTe ₂ ), hafnium sulfide (representatively HfS ₂ ), hafnium selenide (representatively HfSe ₂ ), zirconium sulfide (representatively ZrS ₂ ), and zirconium selenide (representatively ZrSe ₂ ). By applying the above-mentioned transition metal chalcogenide to the semiconductor layer, a memory device with a large on-current can be provided.

<Configuration Example 2 of Semiconductor Device>
Next, an example of a semiconductor device of one embodiment of the present invention will be described with reference to Fig. 21 and Fig. 22. The semiconductor device illustrated in Fig. 21 and Fig. 22 includes a transistor 200E having a different structure from the above-described transistors 200 and 200A to 200D.

FIG. 21A shows a plan view of a semiconductor device according to one embodiment of the present invention. FIG. 21B shows a cross-sectional view taken along dashed lines A1-A2 in FIG. 21A. FIG. 21B is also a cross-sectional view of the transistor 200E in the channel length direction. FIG. 21C shows a cross-sectional view taken along dashed lines A3-A4 in FIG. 21A. FIG. 21C is also a cross-sectional view of the transistor 200E in the channel width direction. FIG. 21D shows a cross-sectional view taken along dashed lines A5-A6 in FIG. 21A. FIG. 21D is also a cross-sectional view of the transistor 200E in the channel width direction. Note that some elements are omitted from the plan view of FIG. 21A for clarity. In addition, FIGS. 22A and 22B show enlarged cross-sectional views of the transistor 200E in the channel length direction.

Transistor 200E has conductor 205 (conductor 205a and conductor 205b) embedded in insulator 216, insulator 221 on insulator 216 and conductor 205, insulator 222 on insulator 221, insulator 224 on insulator 222, oxide 220 (oxide 220a and oxide 220b) on insulator 224, conductor 242a (conductor 242a1 and conductor 242a2) and conductor 242b (conductor 242b1 and conductor 242b2) on oxide 220, insulator 271a on conductor 242a, insulator 271b on conductor 242b, insulator 250 on oxide 220, and conductor 260 (conductor 260a and conductor 260b) on insulator 250.

An insulator 275 is provided on the insulators 271a and 271b, and an insulator 285 is provided on the insulator 275. The insulators 255, 250, and conductor 260 are disposed inside the openings provided in the insulators 285 and 275. An insulator 282 is provided on the insulator 285 and the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 215 is provided below the insulator 216 and the conductor 205. An insulator 255 is provided between the insulator 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 285 and the insulator 250.

Note that insulator 215, insulator 216, conductor 205, insulator 221, insulator 222, insulator 224, oxide 220, conductor 242a, conductor 242b, insulator 271a, insulator 271b, insulator 275, insulator 285, insulator 255, insulator 250, conductor 260, insulator 282, and insulator 283 may each have a single layer structure or a laminated structure.

Oxide 220 has a region that functions as a channel formation region of transistor 200E. Conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of transistor 200E. Insulator 250 has a region that functions as a first gate insulator of transistor 200E. Conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of transistor 200E. Insulator 224, insulator 222, and insulator 221 each have a region that functions as a second gate insulator of transistor 200E.

The conductor 242a has a region that functions as one of the source electrode or drain electrode of the transistor 200E. The conductor 242b has a region that functions as the other of the source electrode or drain electrode of the transistor 200E.

The oxide 220 preferably has an oxide 220a on the insulator 224 and an oxide 220b on the oxide 220a. By having the oxide 220a below the oxide 220b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 220a to the oxide 220b.

Note that the oxide 220 is not limited to a two-layer structure of the oxide 220a and the oxide 220b. The oxide 220 may be, for example, a single-layer structure of the oxide 220b, or may be a laminated structure of three or more layers.

In the oxide 220b, a channel formation region and a source region and a drain region are formed on either side of the channel formation region in the transistor 200E. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

The channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with a high carrier concentration compared to the channel formation region.

Note that the channel formation region, the source region, and the drain region may each be formed with not only oxide 220b but also oxide 220a.

In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 220. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may change continuously within each region, not necessarily in a stepwise manner from region to region. In other words, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in the region closer to the channel formation region.

It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for oxide 220 (oxide 220a and oxide 220b).

It is preferable to form at least one layer of the oxide 220 using the metal oxide film formation method of one embodiment of the present invention. In particular, it is preferable to form the oxide 220b including the channel formation region using the metal oxide film formation method of one embodiment of the present invention.

For example, it is preferable to form both oxide 220a and oxide 220b by the ALD method. Alternatively, it is preferable to form oxide 220a by the sputtering method and oxide 220b by the ALD method.

Furthermore, the preferred ranges of the aluminum concentration and the carbon concentration in the channel formation region of the oxide 220 are the same as those of the oxide semiconductor 230.

The oxide 220 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 220a, the atomic ratio of element M to the main metal element is preferably greater than the atomic ratio of element M to the main metal element in the metal oxide used for the oxide 220b. In addition, in the metal oxide used for the oxide 220a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 220b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 220a to the oxide 220b.

Furthermore, in the metal oxide used for oxide 220b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 220a. With this configuration, the transistor 200E can obtain a large on-current and high frequency characteristics.

In addition, since oxide 220a and oxide 220b have a common element other than oxygen as a main component, the defect state density at the interface between oxide 220a and oxide 220b can be reduced. The defect state density at the interface between oxide 220a and oxide 220b can be reduced. As a result, the effect of interface scattering on carrier conduction is reduced, and transistor 200E can obtain a large on-current and high frequency characteristics.

Specifically, the oxide 220a may be a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition in the vicinity thereof. The oxide 220b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn=1:1:1.2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn=1:1:2 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof. The composition in the vicinity includes a range of ±30% of the desired atomic ratio. It is preferable to use gallium as the element M. Furthermore, when a single layer of oxide 220b is provided as oxide 220, the metal oxide that can be used for oxide 220a may be applied as oxide 220b. Furthermore, the composition of the metal oxide that can be used for oxide 220a and oxide 220b is not limited to the above. For example, the composition of the metal oxide that can be used for oxide 220a may be applied to oxide 220b. Similarly, the composition of the metal oxide that can be used for oxide 220b may be applied to oxide 220a.

When a metal oxide film is formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.

Oxide 220b is preferably crystalline. In particular, it is preferable to use CAAC-OS as oxide 220b.

By using a crystalline oxide such as CAAC-OS as oxide 220b, it is possible to suppress the extraction of oxygen from oxide 220b by the source or drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 220b can be reduced, so that transistor 200E is stable against high temperatures (so-called thermal budget) in the manufacturing process.

Materials that can be used for the insulators and conductors that make up the semiconductor device shown in Figures 21A to 21D include the various materials listed in the [Insulator] and [Conductor] sections above. Representative examples are described below.

The conductor 242a has a layered structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a layered structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 in contact with the oxide 220b are preferably conductors that are not easily oxidized, such as metal nitrides. This can prevent the conductors 242a and 242b from being excessively oxidized by the oxygen contained in the oxide 220b. In addition, the conductors 242a2 and 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductors 242a1 and 242b1. This allows the conductors 242a and 242b to function as wiring or electrodes with high conductivity.

For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.

As shown in FIG. 22B, in a cross-sectional view of the channel length direction of transistor 200E, distance L2 between conductor 242a1 and conductor 242b1 is smaller than distance L1 between conductor 242a2 and conductor 242b2. Specifically, the difference between L1 and L2 is equal to or approximately equal to twice the film thickness of insulator 255. Here, the film thickness of insulator 255 refers to the film thickness in the A1-A2 direction of at least a portion of insulator 255.

The distance L2 between the conductor 242a1 and the conductor 242b1 is preferably fine because it is reflected in the channel length of the transistor 200E. For example, it is preferable that the distance L2 is 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is 1 nm or more, or 5 nm or more. For example, it is more preferable that the distance L2 is about 2 nm or more and 20 nm or less. With such a configuration, it is possible to shorten the distance between the source and the drain, and accordingly shorten the channel length. Therefore, the frequency characteristics of the transistor 200E can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

The openings in the insulator 285 and the insulator 275 overlap the region between the conductor 242a2 and the conductor 242b2. In a top view, the side of the opening in the insulator 285 coincides or roughly coincides with the side of the conductor 242a2 and the side of the conductor 242b2. In addition, a portion of the conductor 242a1 and the conductor 242b1 are formed so as to protrude into the opening. Here, a portion of the upper surface of the conductor 242a1 contacts the conductor 242a2, and a portion of the upper surface of the conductor 242b1 contacts the conductor 242b2. Therefore, the insulator 255 contacts another portion of the upper surface of the conductor 242a1, another portion of the upper surface of the conductor 242b1, the side of the conductor 242a2, and the side of the conductor 242b2 within the opening. Additionally, the insulator 250 contacts the upper surface of the oxide 220, the side of the conductor 242a1, the side of the conductor 242b1, and the side of the insulator 255.

The insulator 255 is preferably an insulator that is difficult to oxidize, such as a nitride. The insulator 255 is formed in a sidewall shape by anisotropic etching in contact with the side wall of an opening provided in the insulator 285 or the like (here, the side wall of the opening corresponds to, for example, the side surface of the insulator 285, etc.). The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and has the function of protecting the conductor 242a2 and the conductor 242b2. In order to supply oxygen to the oxide 220b, it is preferable to perform heat treatment in an atmosphere containing oxygen after the conductor 242a1 and the conductor 242b1 are separated and before the insulator 250 is formed. At this time, since the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, the conductor 242a2 and the conductor 242b2 can be prevented from being excessively oxidized. For example, silicon nitride can be used as the insulator 255.

By providing an insulator containing oxygen that is desorbed by heating (hereinafter may be referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor, thereby reducing oxygen vacancies and _VOH . However, if an excessive amount of oxygen is supplied to the source region or drain region, the on-state current or the field-effect mobility of the transistor 200E may decrease. Furthermore, the amount of oxygen supplied to the source region or drain region varies within the substrate surface, which causes variations in the characteristics of a semiconductor device including a transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses to a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized and its conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. That is, it is preferable to reduce oxygen vacancies and _VOH in the channel formation region of the oxide semiconductor. It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions and to prevent the amount of _VOH in the source and drain regions from being excessively reduced. It is also preferable to have a structure in which the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like is not likely to decrease. For example, it is preferable to have a structure in which the oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like is suppressed. Note that hydrogen in the oxide semiconductor can form _VOH , and therefore the hydrogen concentration needs to be reduced in order to reduce the amount of _VOH .

Transistor 200E is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of conductor 242a, conductor 242b, and conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

The insulator 250 in contact with the channel formation region in the oxide 220b preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 220b. Thus, _VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.

Here, as shown in FIG. 22A, it is preferable that the insulator 250 has a layered structure of an insulator 250a in contact with the oxide 220, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

It is preferable that the insulator 250a has the function of capturing or fixing hydrogen. It is also preferable to use a high dielectric constant (high-k) material for the insulator 250a. For example, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250a, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. In this embodiment, an aluminum oxide film having an amorphous structure is used as the insulator 250a. Aluminum oxide can be relatively easily formed into an amorphous film using the ALD method.

It is preferable that the insulator 250b be made of a thermally stable insulator such as silicon oxide or silicon oxynitride.

In order to suppress oxidation of conductor 242a, conductor 242b, and conductor 260, it is preferable to provide an insulator having a barrier property against oxygen near each of conductor 242a, conductor 242b, and conductor 260. The insulators are, for example, insulator 250a, insulator 250c, insulator 255, and insulator 275.

The insulator 250a and the insulator 255 preferably have a barrier property against oxygen. The insulator 250a and the insulator 255 preferably have a lower oxygen permeability than at least the insulator 285. The insulator 250a has a region in contact with the side of the conductor 242a1 and the side of the conductor 242b1. The insulator 255 has a region in contact with the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, the side of the conductor 242a2, and the side of the conductor 242b2. The insulator 250a also contacts the side of the insulator 255. Since the insulator 250a and the insulator 255 have a barrier property against oxygen, it is possible to suppress the side of the conductor 242a and the conductor 242b from being oxidized and the formation of an oxide film on the side. This suppresses a decrease in the on-current or a decrease in the field effect mobility of the transistor 200E.

Furthermore, the insulator 250a is provided in contact with the top and side surfaces of the oxide 220b, the side surfaces of the oxide 220a, the side surfaces of the insulator 224, and the top surface of the insulator 222. Since the insulator 250a has a barrier property against oxygen, it is possible to suppress the desorption of oxygen from the channel formation region of the oxide 220b when a heat treatment or the like is performed. Therefore, it is possible to reduce the formation of oxygen vacancies in the oxide 220a and the oxide 220b.

Furthermore, by providing the insulator 250a and the insulator 255, even if the insulator 285 contains an excessive amount of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 220a and the oxide 220b, and an appropriate amount of oxygen can be supplied to the oxide 220a and the oxide 220b. Therefore, it is possible to prevent the source region and the drain region from being excessively oxidized, which would cause a decrease in the on-current of the transistor 200E or a decrease in the field effect mobility.

Furthermore, it is preferable that the insulator 255 has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductors 242a2 and 242b2 from diffusing into the oxide 220b.

The insulator 250c also preferably has a barrier property against oxygen. The insulator 250c is provided between the channel formation region of the oxide 220 and the conductor 260, and between the insulator 285 and the conductor 260. This configuration can prevent oxygen contained in the channel formation region of the oxide 220 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 220. In addition, the oxygen contained in the oxide 220 and the oxygen contained in the insulator 285 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250c is preferably at least less permeable to oxygen than the insulator 285. For example, it is preferable to use a silicon nitride film as the insulator 250c.

Furthermore, it is preferable that the insulator 250c has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 220b.

The insulator 275 also preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 285 and the conductor 242a, and between the insulator 285 and the conductor 242b. This configuration can suppress the oxygen contained in the insulator 285 from diffusing to the conductor 242a and the conductor 242b. Therefore, it is possible to suppress the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 285, which increases the resistivity and reduces the on-current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 285. For example, it is preferable to use silicon nitride as the insulator 275.

Furthermore, the insulator 275 preferably has a barrier property against hydrogen. By providing an insulator having a barrier property against hydrogen near each of the source and drain regions in the oxide 220, the diffusion of hydrogen in the source and drain regions to the outside can be reduced, and the reduction in the hydrogen concentration in the source and drain regions can be suppressed. Therefore, the source and drain regions can be made n-type.

By using the above configuration, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, and a semiconductor device with good electrical characteristics can be provided. Furthermore, by using the above configuration, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, by miniaturizing the transistor 200E, the high-frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.

The insulator 250 functions as a gate insulator. The insulator 250 is provided in an opening formed in the insulator 285 together with the insulator 255 and the conductor 260. In order to miniaturize the transistor 200E, it is preferable that the thickness of the insulator 250 is thin. The thicknesses of the layers constituting the insulator 250 are preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. Note that each layer constituting the insulator 250 may have a region with the above thickness in at least a portion.

In order to make the insulator 250 thin, it is preferable to form the film using the ALD method. Also, in order to provide the insulator 250 and the insulator 255 in openings such as the insulator 285, it is preferable to form the film using the ALD method. ALD methods include the thermal ALD method, in which the reaction of the precursor and the reactant is carried out using only thermal energy, and the PEALD (Plasma Enhanced ALD) method, in which a plasma-excited reactant is used. In the PEALD method, the use of plasma allows film formation at a lower temperature, which may be preferable.

The thickness of the insulator 255 is preferably 0.5 nm or more and 20 nm or less, more preferably 0.5 nm or more and 10 nm or less, and even more preferably 0.5 nm or more and 3 nm or less. By making the insulator 255 have the above-mentioned thickness, it is possible to suppress excessive oxidation of the conductor 242a2 and the conductor 242b2. Note that the insulator 255 only needs to have a region with the above-mentioned thickness in at least a portion. If the thickness of the insulator 255 is made excessively thick, the deposition time of the insulator 255 by the ALD method will be longer and productivity will decrease, so it is preferable to keep the thickness of the insulator 255 within the above range.

Furthermore, the semiconductor device shown in FIG. 21A and the like is preferably configured to suppress hydrogen from being mixed into the transistor 200E and the like. For example, it is preferable to provide an insulator having a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200E and the like. Therefore, it is preferable that the insulators 215, 221, 222, 282, and 283 each have an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium (hafnium aluminate), oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable that the insulators 283 and 221 are made of silicon nitride or the like, which has a higher hydrogen barrier property. Also, for example, it is preferable that the insulator 282 is made of aluminum oxide or the like, which has a high ability to capture or fix hydrogen. Also, for example, the insulator 222 is preferably made of hafnium oxide or the like, which is a high dielectric constant (high-k) material that has a high ability to capture or fix hydrogen. In this way, by surrounding the top and bottom of the transistor 200E with insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen into the oxide semiconductor. This can improve the electrical characteristics and reliability of the semiconductor device.

Here, it is preferable that the region of the insulator 275 that does not overlap with the oxide 220 contacts the insulator 222, the side end of the insulator 275 contacts the insulator 255, and the upper end of the insulator 255 and the upper ends of the insulators 250a to 250c contact the insulator 282. With the above configuration, in the region sandwiched between the insulator 283 and the insulator 221, the insulator 285 is separated from the oxide 220 by the insulator 275, the insulator 285 is separated from the insulator 250b by the insulator 255 and the insulator 250a, the conductor 260 is separated from the insulator 250b by the insulator 250c, and the conductors 242a2 and 242b2 are separated from the insulator 250b by the insulator 255 and the insulator 250a.

This can suppress the diffusion of impurities such as water and hydrogen contained in the insulator 285 to the oxide 220 and the insulator 250b. Also, it can suppress the diffusion of impurities such as water and hydrogen contained in the conductor 260 to the oxide 220 through the insulator 250b. Also, it can suppress the diffusion of impurities such as water and hydrogen contained in the conductor 242a2 and the conductor 242b2 to the oxide 220 through the insulator 250b. For example, even if a contact plug is formed in contact with the upper surface of the conductor 242a2 and the conductor 242b2 and impurities such as water and hydrogen diffuse to the conductor 242a2 and the conductor 242b2 through the contact plug, the diffusion of the impurities such as water and hydrogen to the oxide 220 can be reduced. Also, the hydrogen contained in the insulator 250a and the insulator 250b can be captured and fixed to the insulator 282. With this configuration, it is possible to further reduce the diffusion of hydrogen to the oxide semiconductor. This can improve the electrical characteristics and reliability of the semiconductor device.

In the transistor 200E, the conductor 205 is arranged so as to overlap the oxide 220 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Moreover, the conductor 205 is preferably provided extending in the channel width direction, as shown in Figures 21A and 21C. With this configuration, when multiple transistors are provided, the conductor 205 functions as wiring.

As shown in Figures 21B and 21C, the conductor 205 preferably has conductor 205a and conductor 205b. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to fill the recess of conductor 205a formed along the opening. Here, the height of the upper surface of conductor 205 coincides or approximately coincides with the height of the upper surface of insulator 216.

By using a conductive material having the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 220 via the insulator 216, etc. Furthermore, by using a conductive material having the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably has titanium nitride.

Furthermore, it is preferable that the conductor 205b is made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, it is preferable that the conductor 205b contains tungsten.

The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200E can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200E and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore the diffusion of the impurities into the oxide 220 can be suppressed.

The insulator 224 in contact with the oxide 220 preferably comprises, for example, silicon oxide or silicon oxynitride. This allows oxygen to be supplied from the insulator 224 to the oxide 220, reducing oxygen deficiency.

The insulator 224 is preferably processed into an island shape, similar to the oxide 220. As a result, when multiple transistors 200E are provided, the insulators 224 are provided with approximately the same size for each transistor 200E. As a result, the amount of oxygen supplied from the insulator 224 to the oxide 220 in each transistor 200E is approximately the same. This makes it possible to suppress variation in the electrical characteristics of the transistors 200E within the substrate surface. However, this is not limited to the above, and the insulator 224 may be configured not to be patterned, similar to the insulator 222.

It is preferable to use a conductive material that is not easily oxidized or that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include conductive materials that contain nitrogen and conductive materials that contain oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260.

The insulators 271a and 271b are inorganic insulators that function as etching stoppers when processing the conductors 242a2 and 242b2, and protect the conductors 242a2 and 242b2. In addition, since the insulators 271a and 271b are in contact with the conductors 242a2 and 242b2, it is preferable that they are inorganic insulators that are unlikely to oxidize the conductors 242a and 242b. Therefore, as shown in FIG. 22A, it is preferable that the insulator 271a has a layered structure of the insulator 271a1 and the insulator 271a2 on the insulator 271a1, and the insulator 271b has a layered structure of the insulator 271b1 and the insulator 271b2 on the insulator 271b1. Here, it is preferable that the insulators 271a1 and 271b1 are made of a nitride insulator that can be used for the insulator 250c so as to prevent the conductors 242a2 and 242b2 from being oxidized. It is also preferable that the insulators 271a2 and 271b2 are made of an oxide insulator that can be used for the insulator 250b so as to function as an etching stopper. For example, silicon nitride can be used for the insulators 271a1 and 271b1, and silicon oxide can be used for the insulators 271a2 and 271b2.

In this specification, the transistor structure in which the electric field of at least the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin type structure. In this specification, the Fin type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin type structure and the S-channel structure, it is possible to increase the resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is less likely to occur.

By making the transistor 200E have the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure is a structure that electrically surrounds the channel formation region, so it can be said to be a structure substantially equivalent to a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By making the transistor 200E have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 220 and the gate insulator can be the entire bulk of the oxide 220. Therefore, it is possible to improve the current density flowing through the transistor, and it is expected to improve the on-current of the transistor or the field effect mobility of the transistor.

In this embodiment, the insulator 224 is configured to be arranged in an island shape. Therefore, as shown in FIG. 21C, at least a portion of the lower surface of the conductor 260 can be arranged below the lower surface of the oxide 220b. This allows the conductor 260 to be arranged facing the upper surface and side surface of the oxide 220b, so that the electric field of the conductor 260 can be applied to the upper surface and side surface of the oxide 220b. In this way, by configuring the insulator 224 to be arranged in an island shape, the transistor 200E can have an S-channel structure.

The conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to wrap the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260a. Since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b due to the oxygen contained in the insulator 285, etc., and the decrease in conductivity. As a conductive material that has a function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

The conductor 260b is preferably a highly conductive conductor. For example, the conductor 260b may be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

It is preferable that the insulators 216 and 285 each have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

<Configuration Example 3 of Semiconductor Device>
Next, an example of a semiconductor device of one embodiment of the present invention will be described with reference to Fig. 23 to Fig. 25. The semiconductor device illustrated in Fig. 23 to Fig. 25 includes transistors 201a and 201b, which have different structures from the above-described transistors 200 and 200A to 200E.

Note that for the components of transistors 201a and 201b that are similar to those of transistor 200E, the above description can be referred to.

23A to 23D are plan views and cross-sectional views of a semiconductor device having a transistor 201a and a transistor 201b on a substrate (not shown). Note that since the transistor 201b has a structure similar to that of the transistor 201a, the components are given the same hatching pattern as the transistor 201a and are not particularly marked with reference numerals. In addition, in the following, the transistors 201a and 201b may be collectively referred to as the transistor 201. Note that the semiconductor device shown in this embodiment can function as two 1T (transistor) 1C (capacitor) type memory cells by providing a capacitor electrically connected to the transistor 201a and a capacitor electrically connected to the transistor 201b, and can also be used in a memory device.

Figure 23A is a plan view of the semiconductor device. Figures 23B to 23D are cross-sectional views of the semiconductor device. Here, Figure 23B is a cross-sectional view between dashed lines A1-A2 in Figure 23A, and is also a cross-sectional view in the channel length direction of the transistor 201a. Also, Figure 23C is a cross-sectional view between dashed lines A3-A4 in Figure 23A, and is also a cross-sectional view in the channel width direction of the transistors 201a and 201b. Also, Figure 23D is a cross-sectional view between dashed lines A5-A6 in Figure 23A, and is also a cross-sectional view in the channel width direction of the transistors 201a and 201b. Here, the dashed line A1-A2 is perpendicular to the dashed line A3-A4 and the dashed line A5-A6, and the dashed line A3-A4 and the dashed line A5-A6 are parallel to each other. Note that in the plan view of Figure 23A, some elements are omitted for clarity. FIG. 24A shows an enlarged view of the conductor 260 in FIG. 23B and its vicinity. FIG. 24B shows an enlarged view of the insulator 225 in FIG. 23C and its vicinity. FIG. 25A shows an enlarged view of the conductor 242a in FIG. 23B and its vicinity. FIG. 25B shows an enlarged view of the insulator 225 in FIG. 23D and its vicinity.

The semiconductor device shown in Figures 23A to 23D has a stack of insulators 215, 216, and 222, and further has an insulator 225 on the insulator 222, an oxide 220 (oxide 220a and oxide 220b) on the insulator 225 and the insulator 222, a conductor 242 (conductor 242a and conductor 242b) on the oxide 220, an insulator 250 on the oxide 220, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

An insulator 275 is provided on the conductor 242, and an insulator 285 is provided on the insulator 275. The insulator 250 and the conductor 260 are disposed inside openings provided in the insulator 285 and the insulator 275. An insulator 282 is provided on the insulator 285 and the conductor 260. An insulator 283 is provided on the insulator 282.

Insulator 241a is provided in contact with the inner wall of the opening of insulator 285, etc., and conductor 239a is provided in contact with insulator 241a. Conductor 239a is in contact with conductor 242a. Insulator 241b is provided in contact with the inner wall of the opening of insulator 285, etc., and conductor 239b is provided in contact with insulator 241b. Conductor 239b is in contact with conductor 242b. Note that hereinafter, conductor 239a and conductor 239b may be collectively referred to as conductor 239. Insulator 241a and insulator 241b may be collectively referred to as insulator 241.

Note that insulator 215, insulator 216, insulator 222, insulator 225, oxide 220, conductor 242a, conductor 242b, insulator 275, insulator 285, insulator 250, conductor 260, insulator 241, conductor 239, insulator 282, and insulator 283 may each have a single layer structure or a laminated structure.

The oxide 220 has a region that functions as a channel formation region of the transistor 201. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 201. The insulator 250 has a region that functions as a first gate insulator of the transistor 201.

Note that in this embodiment, the transistors 201a and 201b are each shown as an example of a single-gate transistor without a back gate, but the present invention is not limited thereto. The transistors 200a and 200b may each be a dual-gate transistor with a back gate. For example, similar to the above-described transistor 200E, the transistor 201 may have a conductor 205 (conductor 205a and conductor 205b) embedded in the insulator 216. The transistor 201 may further have an insulator 221. In this case, the conductor 205 has a region that functions as the second gate electrode (lower gate electrode) of the transistor 201. The insulator 222 and the insulator 221 each have a region that functions as the second gate insulator of the transistor 201.

Here, as shown in FIG. 24B, in the transistor 201, the oxide 220 has a folded structure with the insulator 225 interposed therebetween. Therefore, a part of the conductor 260 facing the oxide 220 across the insulator 225 may function as a second gate electrode.

Conductor 242a has a region that functions as one of the source electrode or drain electrode of transistor 201. Conductor 242b has a region that functions as the other of the source electrode or drain electrode of transistor 201. Conductor 239a functions as a plug that connects to conductor 242a. Conductor 239b functions as a plug that connects to conductor 242b.

The oxide 220 preferably has an oxide 220a covering the insulator 225 and an oxide 220b on the oxide 220a. Here, the oxide 220a contacts the upper surface and side surface of the insulator 225 and the upper surface of the insulator 222. As shown in FIG. 24B and the like, the oxide 220a and the oxide 220b are provided so as to cover the insulator 225 having a high aspect ratio. Therefore, it is preferable that the oxide 220a and the oxide 220b are formed using a film formation method with good coverage such as the ALD method. Here, as shown in FIG. 24B, in the cross section in the channel width direction, the oxide 220a and the oxide 220b are formed so as to be folded in half through the insulator 225. With this configuration, the channel formation region of the transistor 201 can be formed on the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225, so that the channel width per unit area can be increased.

By having oxide 220a below oxide 220b, it is possible to suppress the diffusion of impurities from structures formed below oxide 220a into oxide 220b.

Note that the oxide 220 is not limited to a two-layer structure of the oxide 220a and the oxide 220b. The oxide 220 may be, for example, a single-layer structure of the oxide 220b, or may be a laminated structure of three or more layers.

In the oxide 220b, a channel formation region and a source region and a drain region are formed on either side of the channel formation region in the transistor 201. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for oxide 220 (oxide 220a and oxide 220b).

It is preferable to form at least one layer of the oxide 220 using the metal oxide film formation method of one embodiment of the present invention. In particular, it is preferable to form the oxide 220b including the channel formation region using the metal oxide film formation method of one embodiment of the present invention.

By forming at least one layer of oxide 220 using the ALD method, a metal oxide can be formed with good coverage on the top, bottom, side, and inclined surfaces of the structure. In other words, a metal oxide can be formed with a roughly constant film thickness in the normal direction on each deposition surface. In the metal oxide formed on each of the top, bottom, side, and inclined surfaces of the structure, the ratio of the minimum film thickness to the maximum film thickness can be set to 0.5 or more and 1 or less, preferably 0.7 or more and 1 or less, more preferably 0.8 or more and 1 or less, and more preferably 0.9 or more and 1 or less.

For example, in the oxide 220 shown in FIG. 24B, the ratio of the thickness of the second portion provided along the side surface of the insulator 225 to the thickness of the first portion provided along the top surface of the insulator 222 is preferably 0.7 or more and 1.3 or less, more preferably 0.8 or more and 1.2 or less, and even more preferably 0.9 or more and 1.1 or less.

Furthermore, the preferred ranges of the aluminum concentration and the carbon concentration in the channel formation region of the oxide 220 are as described above.

For example, it is preferable to form both oxide 220a and oxide 220b by the ALD method. Alternatively, it is preferable to form oxide 220a by the sputtering method and oxide 220b by the ALD method.

Materials that can be used for the insulators and conductors that make up the semiconductor device shown in Figures 23A to 23D include the various materials listed in the [Insulator] and [Conductor] sections above. You can also refer to the contents explained in the above-mentioned <Configuration example 2 of semiconductor device>. Below, we will mainly explain the points that are different from the above-mentioned configuration.

As shown in FIG. 24A, the insulator 250 may have a four-layer structure. The insulator 250 shown in FIG. 24A is preferably a layered structure of an insulator 250a in contact with the oxide 220, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, it is preferable that the insulator 250a and the insulator 250c have the function of capturing hydrogen or fixing hydrogen.

For insulator 250a and insulator 250c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.

In addition, it is preferable to use a high dielectric constant (high-k) material for the insulator 250a and the insulator 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulator 250a and the insulator 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

For the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

In this embodiment, aluminum oxide is used as the insulator 250a shown in FIG. 24A. The aluminum oxide preferably has an amorphous structure. Here, by providing the insulator 250a in contact with the oxide 220b, the hydrogen contained in the oxide 220b and the like can be more effectively captured and fixed.

In this embodiment, hafnium oxide is used as the insulator 250c shown in FIG. 24A. Here, by providing the insulator 250c between the insulators 250b and 250d, the hydrogen contained in the insulators 250b and 250d can be more effectively captured and fixed.

It is preferable that the insulator 250b be made of a thermally stable insulator such as silicon oxide or silicon oxynitride.

In order to suppress oxidation of conductor 242a, conductor 242b, and conductor 260, it is preferable to provide a barrier insulator against oxygen near each of conductor 242a, conductor 242b, and conductor 260. The insulators are, for example, insulator 250a, insulator 250d, insulator 250c, and insulator 275.

The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide 220 and the conductor 260, and between the insulator 285 and the conductor 260. This configuration can suppress the oxygen contained in the channel formation region of the oxide 220 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 220. In addition, it can suppress the oxygen contained in the oxide 220 and the oxygen contained in the insulator 285 from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 285. For example, it is preferable to use a silicon nitride film as the insulator 250d. In this case, the insulator 250d is an insulator having at least nitrogen and silicon.

Furthermore, it is preferable that the insulator 250d has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 220b.

The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d are provided in an opening formed in the insulator 285 together with the conductor 260. In order to miniaturize the transistor 201, it is preferable that the thicknesses of the insulators 250a to 250d are each thin. The thicknesses of the insulators 250a to 250d are each preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that the insulators 250a to 250d each may have a region with the above thickness at least in a portion thereof.

Note that, although the above description has been given of a configuration in which the insulator 250 has a four-layer structure of insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

The insulator 225 is formed on and in contact with the insulator 222. As shown in FIG. 24B and FIG. 25B, the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. Here, the aspect ratio of the insulator 225 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the insulator 225 in the A3-A4 direction (which can also be called the width L of the insulator 225) to the length H of the insulator 225 in a direction perpendicular to the surface on which the insulator 225 is formed (for example, the insulator 222) (which can also be called the height H of the insulator 225). In the insulator 225, the height H of the insulator 225 is at least longer than the width L of the insulator 225. The height H of the insulator 225 may be greater than 1 time the width L of the insulator 225, preferably 2 times or more, more preferably 5 times or more, and even more preferably 10 times or more. In addition, the height H of the insulator 225 is preferably 20 times or less the width L of the insulator 225.

The oxide 220a, the oxide 220b, and the conductor 242 are provided to cover the insulator 225 having such a high aspect ratio. In the transistor 201, as shown in FIG. 24B, the oxide 220a and the oxide 220b are provided so as to be folded in half with the insulator 225 in between, and the insulator 250 and the conductor 260 are provided to cover the oxide 220b. As a result, in a cross-sectional view in the channel width direction, the oxide 220 and the conductor 260 are provided facing each other with the insulator 250 in between on the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225. In other words, the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225 each function as a channel formation region. Therefore, the channel width of the transistor 201 is larger by the side surface on the A3 side and the side surface on the A4 side of the insulator 225 compared to when the insulator 225 is not provided.

By increasing the channel width as described above, the on-state current, field effect mobility, frequency characteristics, and the like of the transistor 201 can be improved. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a storage device using the semiconductor device can be increased. In addition, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the area occupied by the transistor 201. This makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the storage capacity of a storage device using the semiconductor device can be increased.

The insulator 225 can be made of an insulating material that can be used for the insulators 222, 285, and 250. In addition, since the insulator 225 has a shape with a high aspect ratio, it is preferable to form the insulator 225 in a sidewall shape on the side of a sacrificial layer (a structure used during the manufacturing process). Therefore, it is preferable to form the insulator 225 using an ALD method, which has good coverage. For example, the insulator 225 can be made of hafnium oxide formed by a thermal ALD method.

In this way, by forming the insulator 225 in a sidewall shape in contact with the side surface of the sacrificial layer, as shown in FIG. 23A, the insulator 225 of the transistor 201a and the insulator 225 of the transistor 201b can be formed simultaneously. By forming two insulators 225 in this way, the distance between the two insulators 225 can be set according to the size of the sacrificial layer. Therefore, the distance between the insulators 225 can be reduced, the area occupied by the transistors 201a and 201b can be reduced, and the semiconductor device can be highly integrated.

However, the insulator 225 is not limited to insulating materials in the strict sense. For example, metal oxides with relatively high insulating properties may be used. For example, metal oxides that can be used for the oxide 220a may be used.

The upper part of the insulator 225 may have a curved shape. Such a curved shape can prevent defects such as voids from forming in the oxide 220a, the oxide 220b, and the conductor 242 near the upper part of the insulator 225. Note that in Figures 24B and 25B, a symmetrical structure is shown in which a curved shape is provided on both the A3 side (A5 side) and the A4 side (A6 side) of the upper part of the insulator 225, but the present invention is not limited to this. For example, an asymmetrical structure may be used in which a curved shape is provided only on the A3 side (A5 side) of the upper part of the insulator 225.

The conductor 242a and the conductor 242b are disposed at a distance from each other and are provided on the oxide 220b in contact with each other. As shown in Figures 25A and 25B, the conductor 242 is provided so as to cover the insulator 225, which has a high aspect ratio. Therefore, it is preferable to form the conductor 242 using a film formation method with good coverage, such as the ALD method or the CVD method.

Here, in the vicinity of the source or drain of the transistor 201a, the oxide 220a, the oxide 220b, and the conductor 242a are provided so as to be folded in half with the insulator 225 sandwiched therebetween, as shown in FIG. 25B. As a result, in a cross-sectional view in the channel width direction, the conductor 242a contacts the oxide 220b at the top of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side. Therefore, compared to the case where the insulator 225 is not provided, the contact area between the conductor 242a and the oxide 220b is larger by the side surface on the A5 side and the side surface on the A6 side of the insulator 225. Note that FIG. 25B shows the vicinity of the conductor 242a, but the same is true for the conductor 242b. In other words, the contact area between the conductor 242b and the oxide 220b is larger, similar to the above-mentioned conductor 242a and the oxide 220b.

By increasing the contact area between the conductor 242 and the oxide 220b as described above, the on-state current, frequency characteristics, and the like of the transistor 201 can be improved without increasing the area occupied by the transistor 201. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a storage device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the storage capacity of a storage device using the semiconductor device can be increased.

As shown in Figures 23B and 23C, conductor 260 is disposed in an opening formed in insulator 285, insulator 275, conductor 242a, and conductor 242b. Conductor 260 is disposed in the opening so as to cover the upper surface of insulator 222, the side of oxide 220a, the side of oxide 220b, and the upper surface of oxide 220b via insulator 250. In addition, the upper surface of conductor 260 is disposed so as to be flush or approximately flush with the top of insulator 250 and the upper surface of insulator 285.

In the above opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 285 is improved, and defects such as voids can be reduced.

The conductor 260 functions as a first gate electrode of the transistor 201. Here, the conductor 260 is preferably provided extending in the channel width direction, as shown in Figures 23A and 23C. With this configuration, when multiple transistors are provided, the conductor 260 functions as wiring.

In FIG. 23B and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to wrap around the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of suppressing the diffusion of oxygen as the conductor 260a.

In addition, in the transistor 201, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 285 or the like. Here, the side of the insulator 285 in the opening coincides or approximately coincides with the side of the conductor 242a and the side of the conductor 242b. Therefore, the conductor 260 can be arranged so as to overlap the region between the conductor 242a and the conductor 242b without alignment.

Conductor 239a and conductor 239b are formed in the openings of insulator 275, insulator 285, insulator 282, and insulator 283, respectively. The lower surface of conductor 239a contacts the upper surface of conductor 242a, and the lower surface of conductor 239b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 239 and the height of the upper surface of insulator 283 are approximately the same.

The conductor 239 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 239 may also have a layered structure in which a first conductor is provided in contact with the side of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor.

In addition, when the conductor 239 has a layered structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the insulators 283, 282, and 285, and the first conductor arranged near the insulator 275. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. With such a configuration, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 220 through the conductors 239a and 239b.

Insulator 241a and insulator 241b are formed in contact with the inner walls of the openings of insulators 275, 285, 282, and 283, respectively. The inner side of insulator 241a contacts conductor 239a, and the inner side of insulator 241b contacts conductor 239b.

The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. By providing the insulator 241, impurities such as water and hydrogen contained in the insulator 285, etc., can be prevented from mixing into the oxide 220 through the conductors 239a and 239b. Silicon nitride is particularly suitable because it has high blocking properties against hydrogen. In addition, oxygen contained in the insulator 285 can be prevented from being absorbed by the conductors 239a and 239b.

When the insulator 241 has a layered structure as shown in FIG. 23B, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 285, and the second insulator on the inside thereof are made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 239 and also reduce hydrogen contamination of the conductor 239.

Note that, although the above describes a configuration in which the insulator 241 has a two-layer laminated structure, the present invention is not limited to this. For example, the insulator 241 may be provided as a single layer or a laminated structure of three or more layers. Also, although the above describes a configuration in which the conductor 239 has a two-layer laminated structure, the present invention is not limited to this. For example, the conductor 239 may be provided as a single layer or a laminated structure of three or more layers.

In addition, in FIG. 25B and other figures, a structure in which the conductor 239a contacts the conductor 242a only above the upper end of the insulator 225 is shown, but the present invention is not limited to this. For example, as shown in FIG. 25C, a structure in which the conductor 239a covers the insulator 225 and the oxide 220a, oxide 220b, and conductor 242a that are folded in half with the insulator 225 in between may be used. As a result, in a cross-sectional view in the channel width direction, the conductor 239a contacts the conductor 242a at the top of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side. Therefore, compared to the case in which the insulator 225 is not provided, the contact area between the conductor 239a and the conductor 242a is larger by the side surface on the A5 side and the side surface on the A6 side of the insulator 225. In addition, while FIG. 25C shows the vicinity of conductor 239a and conductor 242a, the same applies to conductor 239b and conductor 242b. In other words, the contact area between conductor 239b and conductor 242b is large, similar to the contact area between conductor 239a and conductor 242a described above.

By increasing the contact area between conductor 239 and conductor 242 as described above, the on-state current, frequency characteristics, and the like of transistor 201 can be improved without significantly increasing the area occupied by transistor 201. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a storage device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the storage capacity of a storage device using the semiconductor device can be increased.

<Configuration example 2 of storage device>
Even when a planar transistor such as the transistor 200E is used in the memory device, a structure in which the transistor and the capacitor overlap each other can be applied.

Figures 26A to 26D show an example of a memory cell composed of a planar transistor and a capacitance element.

Figure 26A is a plan view showing an outline of the arrangement of a transistor 200p and a capacitance element 100 provided below the transistor 200p in a cell when a planar transistor is used. Also, Figure 26B is a cross-sectional view corresponding to the dashed line B1-B2 shown in Figure 26A.

As shown in Figures 26A and 26B, when the capacitance element 100 is provided below the transistor 200p, an element CA such as a wiring and a plug is provided to connect the source electrode or drain electrode of the transistor 200p to one electrode (upper electrode) of the capacitance element 100.

Figure 26C is a plan view showing an outline of the arrangement of transistor 200p and capacitive element 100 provided above transistor 200p in a memory cell. Figure 26C is also a cross-sectional view corresponding to dashed line B1-B2 shown in Figure 26D.

As shown in Figures 26C and 26D, when the capacitance element 100 is provided above the transistor 200p, an element CA such as a wiring and a plug that connects the source electrode or drain electrode of the transistor 200p to one electrode (lower electrode) of the capacitance element 100 is provided. In Figures 26C and 26D, the element CA can be placed in the region where the transistor 200p and the capacitance element 100 overlap. Therefore, this is more advantageous in terms of miniaturization than when the capacitance element 100 is provided below the transistor 200p.

<Configuration example 3 of storage device>
The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device. The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 has a small off-state current; therefore, by using the transistor 200 in a storage device, stored content can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 allow high-speed reading and writing of data from and to the storage device.

An example of a memory device in which two memory cells 150 (hereinafter referred to as memory cell 150a and memory cell 150b) are connected to a common wiring will be described with reference to Figures 27A and 27B. Figure 27A is a plan view of the memory device. Figure 27B is a cross-sectional view of the area indicated by the dashed dotted line A1-A2 in Figure 27A. Note that some elements have been omitted from the plan view of Figure 27A to clarify the drawing.

Here, each of the memory cells 150a and 150b shown in FIG. 27A and FIG. 27B has the same configuration as the memory cell 150. The memory cell 150a has a capacitor element 100a and a transistor 200a, and the memory cell 150b has a capacitor element 100b and a transistor 200b. Therefore, in the memory device shown in FIG. 27A and FIG. 27B, structures having the same functions as the structures constituting the memory device shown in FIG. 15 are denoted by the same reference numerals. Note that in this section as well, the materials constituting the memory device can be the materials described in detail in <Configuration example of memory device>.

As shown in Figures 27A and 27B, a conductor 260 functioning as a wiring WL is provided in each of the memory cells 150a and 150b. A conductor 240 functioning as part of the wiring BL is provided in common to the memory cells 150a and 150b. That is, the conductor 240 is in contact with the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.

Here, the memory device shown in Figures 27A and 27B has conductors 245 and 246 that are electrically connected to memory cells 150a and 150b and function as plugs (which can also be called connection electrodes). Conductor 245 is disposed in openings formed in insulators 180, 280, and 140, and contacts the bottom surface of conductor 240. Conductor 246 is disposed in openings formed in insulators 287, 283, and 250, and contacts the top surface of conductor 240. Note that conductors 245 and 246 can be made of a conductive material that can be used for conductor 240.

The insulator 287 preferably has a low dielectric constant because it functions as an interlayer film. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. As the insulator 287, an insulator containing a material with a low dielectric constant, as described above in the [Insulator] section, can be used in a single layer or a multilayer configuration.

Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 287 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

The conductors 245 and 246 function as plugs or wirings for electrically connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the memory cells 150a and 150b. For example, the conductor 245 can be electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. 27, and the conductor 246 can be electrically connected to a similar memory device (not shown) provided above the memory device shown in FIG. 27. In this case, the conductors 245 and 246 function as part of the wiring BL. In this way, by providing a memory device or the like above or below the memory device shown in FIG. 27, the memory capacity per unit area can be increased.

In addition, memory cell 150a and memory cell 150b are configured to be linearly symmetrical with respect to the perpendicular bisector of dashed line A1-A2 as the axis of symmetry. Therefore, transistor 200a and transistor 200b are also arranged symmetrically with conductor 245 and conductor 246 in between. Here, conductor 240 functions as the other of the source electrode and drain electrode of transistor 200a and as the other of the source electrode and drain electrode of transistor 200b. In addition, transistor 200a and transistor 200b share conductor 245 and conductor 246 that function as plugs. In this way, by configuring the connection between two transistors and a plug as described above, a memory device that can be miniaturized or highly integrated can be provided.

Note that the conductor 110 functioning as the wiring PL may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b. However, as shown in FIG. 27B, the conductor 110 is provided at a distance from the conductor 245 to prevent the conductor 110 and the conductor 245 from being short-circuited.

Also, a memory cell array can be constructed by arranging the memory cells 150 in a three-dimensional matrix. As an example of a memory cell array, Figs. 28A and 28B show an example of a memory device in which 4 x 2 x 4 memory cells 150 are arranged in the X, Y, and Z directions. Fig. 28A is a plan view of the memory device. Fig. 28B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 28A. Note that some elements have been omitted from the plan view of Fig. 28A to clarify the figure.

Here, each of the memory cells 150a to 150d shown in FIG. 28A and FIG. 28B has the same configuration as the memory cell 150. The memory cell 150a has a capacitor 100a and a transistor 200a, the memory cell 150b has a capacitor 100b and a transistor 200b, the memory cell 150c has a capacitor 100c and a transistor 200c, and the memory cell 150d has a capacitor 100d and a transistor 200d. Therefore, in the memory device shown in FIG. 28A and FIG. 28B, the same reference numerals are attached to structures having the same functions as the structures constituting the memory device shown in FIG. 15. Note that in this section as well, the materials described in detail in <Configuration example of memory device> can be used as the constituent materials of the memory device.

Hereinafter, a memory device consisting of memory cells 150a to 150d is referred to as a memory unit. The memory device shown in Figures 28A and 28B has memory units 160[1,1] to 160[2,4]. Note that, below, memory units 160[1,1] to 160[2,4] may be collectively referred to as memory unit 160. Memory unit 160[1,2] is provided on memory unit 160[1,1], memory unit 160[1,3] is provided on memory unit 160[1,2], and memory unit 160[1,4] is provided on memory unit 160[1,3]. Memory unit 160[2,1] is provided adjacent to memory unit 160[1,1] in the Y direction. Memory unit 160[2,2] is provided above memory unit 160[2,1], memory unit 160[2,3] is provided above memory unit 160[2,2], and memory unit 160[2,4] is provided above memory unit 160[2,3].

As shown in FIG. 28B, memory unit 160 has memory cell 150c arranged outside memory cell 150a, and memory cell 150d arranged outside memory cell 150b, with conductor 245 at the center. In other words, it can be said that this is a memory device in which memory cell 150c is provided adjacent to memory cell 150a, and memory cell 150d is provided adjacent to memory cell 150b in the memory device shown in FIG. 27.

As shown in Figures 28A and 28B, the conductor 260 functioning as the wiring WL is shared between memory cells 150 adjacent in the Y direction. The conductor 240 functioning as part of the wiring BL is shared within the same memory unit. In other words, the conductor 240 is in contact with each of the oxide semiconductors 230 of the memory cells 150a to 150d.

A conductor 245 is provided between the conductors 240 of memory units adjacent in the Z direction. For example, as shown in FIG. 28B, the conductor 245 is provided in contact with the upper surface of the conductor 240 of memory unit 160[1,1] and the lower surface of the conductor 240 of memory unit 160[1,2]. In this manner, the wiring BL is formed by the conductors 240 and 245 provided in each memory unit 160. The conductor 245 is electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. 28. In this manner, by stacking multiple memory units in the memory device shown in FIG. 28, the memory capacity per unit area can be increased.

In addition, the memory cells 150a and 150c and the memory cells 150b and 150d are configured to be linearly symmetrical with respect to the perpendicular bisector of the dashed dotted line A1-A2. Therefore, the transistors 200a and 200c and the transistors 200b and 200d are also arranged symmetrically with the conductor 245 in between. Here, the conductor 240 functions as the other of the source electrode and drain electrode of each of the transistors 200a to 200d. The transistors 200a to 200d share the conductor 245 that functions as a plug. In this way, by configuring the connections between the four transistors and the plug as described above, a memory device that can be miniaturized or highly integrated can be provided.

As shown in FIG. 28, by stacking multiple memory cells, the cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. Note that FIG. 28 illustrates an example of a configuration in which four layers, each having two memory units, are stacked, but the present invention is not limited to this. The memory device may have one layer having at least one memory cell 150, or two or more layers may be stacked.

FIG. 28 shows a configuration in which the conductor 245 functioning as a plug is arranged between the memory cells 150. In other words, the configuration shows the conductor 245 functioning as a plug being arranged inside the memory unit 160. However, the present invention is not limited to this. The conductor 245 may be arranged outside the memory unit.

As an example of a memory cell array, FIGS. 29A and 29B show an example of a memory device in which 3×3×4 memory cells 150 are arranged in the X, Y, and Z directions. FIG. 29A is a plan view of the memory device. FIG. 29B is a cross-sectional view of the area indicated by the dashed dotted line A1-A2 in FIG. 29A. Note that some elements have been omitted from the plan view of FIG. 29A to clarify the drawing.

29A and 29B have a structure in which m layers including memory cells 150 are stacked (m is an integer of 2 or more). Here, the layer provided in the first layer (bottom) is layer 170[1], the layer provided in the second layer is layer 170[2], the layer provided in the (m-1)th layer is layer 170[m-1], and the layer provided in the mth layer (top) is layer 170[m], as shown in FIG. 29B. In other words, the memory device of one embodiment of the present invention may have a structure in which multiple layers including memory cells 150 are stacked.

As shown in FIG. 29A and FIG. 29B, the conductor 245 may be provided outside the memory unit. The conductor 245 may also be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] is electrically connected to a wiring provided in the layer 170[2]. Note that the wiring provided in the layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[2]. In other words, the wiring can be formed in the same process as the conductor 110.

29 shows a configuration in which the conductor 245 is electrically connected to a wiring provided in an upper layer of the layer including the conductor 245, but the present invention is not limited to this. For example, the conductor 245 may be electrically connected to a wiring provided in the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] may be electrically connected to a wiring provided in the layer 170[1]. The wiring provided in the layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.

Here, the planar layout of the memory device shown in FIG. 29A is shown in FIG. 30A. Specifically, the planar layout in FIG. 30A shows an area including 4×4 memory cells 150. Also shown are a conductor 260 functioning as a wiring WL, a conductor 240 functioning as a wiring BL, and an opening 290. Note that the memory cell 150 is provided in an area where the conductor 260, the conductor 240, and the opening 290 overlap. In other words, the opening 290 is provided in an area of the conductor 240 where the conductor 240 and the conductor 260 intersect.

Figure 30A shows a configuration in which memory cells 150 are arranged in a matrix. Also, a configuration in which openings 290 are arranged in a matrix is shown. Also, a configuration in which conductors 260 are provided extending in the Y direction (also called the column direction), and conductors 240 are provided extending in the X direction (also called the row direction). In other words, a configuration in which conductors 260 and 240 are orthogonal to each other is shown. Also, a configuration in which conductors 260 have a uniform width in a direction perpendicular to the direction in which conductors 260 extend (X direction), and conductors 240 have a uniform width in a direction perpendicular to the direction in which conductors 240 extend (Y direction) is shown. Note that the present invention is not limited to this.

Figure 30B is another example of a planar layout of a memory device. The planar layout of Figure 30B illustrates conductors 260, conductors 240, memory cells 150, and openings 290, similar to Figure 30A. The memory device shown in Figure 30B differs from the memory device shown in Figure 30A mainly in the arrangement of memory cells 150, the arrangement of openings 290, the shape of conductors 240, and the direction in which conductors 260 extend.

As shown in FIG. 30B, the memory cells 150 are arranged in odd and even rows with a shift of half the repeating unit of the memory cells 150. The memory cells 150 are also arranged in odd and even columns with a shift of half the repeating unit. Similarly, the openings 290 shown in FIG. 30B are arranged in odd and even rows with a shift of half the repeating unit of the openings 290. The openings 290 are also arranged in odd and even columns with a shift of half the repeating unit.

In FIG. 30B, the memory cell adjacent to the first memory cell in the X direction is the second memory cell, and the memory cell adjacent to the first memory cell in the extension direction of the conductor 260 that is closer to the second memory cell is the third memory cell. In this case, the center of the third memory cell is preferably located on a straight line that passes through the middle between the first memory cell and the second memory cell and is parallel to the Y direction. In the X direction, the third memory cell can be said to be located at a position shifted by half a repeat unit in the X direction from each of the first memory cell and the second memory cell.

In FIG. 30B, the extension direction of conductor 260 is arranged at an angle to the Y direction. On the other hand, conductor 240 is arranged extending in the X direction. That is, depending on the arrangement of memory cell 150 (or opening 290), the extension direction of conductor 260 may not be perpendicular to the extension direction of conductor 240. In other words, conductor 260 does not need to be perpendicular to conductor 240, and conductor 260 and conductor 240 are arranged to intersect.

Also, as shown in FIG. 30B, the conductor 240 has a first region and a second region. The first region is the opening 290 and the region in the vicinity thereof, and the width in the Y direction of the first region is the first width. In a plan view, the first region can be said to have a shape with rounded corners of a rectangle. The second region is a region between adjacent openings 290 in one conductor 240 (also can be said to be a region between two adjacent first regions), and the width in the Y direction of the second region is the second width. In this case, it is preferable that the second width is smaller than the first width. With this configuration, when the memory cells 150 (or the openings 290) are arranged by shifting them by half the repeat unit for each row and column, the physical distance between the conductors 240 can be reduced. Therefore, it is possible to miniaturize and highly integrate the memory device.

Figure 30C is another example of a planar layout of a memory device. The planar layout of Figure 30C illustrates conductor 260, conductor 240, memory cell 150, and opening 290, similar to Figure 30B. The memory device illustrated in Figure 30C differs from the memory device illustrated in Figure 30B mainly in the shape of the first region of conductor 240.

The first region of the conductor 240 shown in FIG. 30B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X or Y direction. On the other hand, the first region of the conductor 240 shown in FIG. 30C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X or Y direction. Even with this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (or the openings 290) are arranged with a shift of half a repeating unit in rows and columns. This allows for miniaturization and high integration of the memory device.

Figures 30B and 30C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in a plan view, but the present invention is not limited to this.

FIG. 31A is another example of a planar layout of a memory device. The planar layout of FIG. 31A illustrates conductor 260, conductor 240, memory cell 150, and opening 290, similar to FIG. 30B. The memory device illustrated in FIG. 31A differs from the memory device illustrated in FIG. 30B or FIG. 30C mainly in the shape of the first region of conductor 240.

The first region of the conductor 240 shown in FIG. 31B is circular in plan view. Even with this configuration, when the memory cells 150 (or the openings 290) are arranged in rows and columns with a shift of half a repeating unit, the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device.

Note that the first region of the conductor 240 in plan view is not limited to the shape described above. For example, the first region of the conductor 240 in plan view may be an approximately circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners.

In addition, FIG. 31A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, but the present invention is not limited to this.

Figure 31B is another example of a planar layout of a memory device. The planar layout of Figure 31B illustrates conductor 260, conductor 240, memory cell 150, and opening 290, similar to Figure 31A. The memory device shown in Figure 31B differs from the memory device shown in Figure 31A mainly in the shape of conductor 260.

The conductor 260 shown in FIG. 31B has a first region and a second region, similar to the conductor 240. The first region is the opening 290 and the region in its vicinity, and is circular in plan view. The second region is the region between adjacent openings 290 in one conductor 260 (which can also be said to be the region between two adjacent first regions). The first region of the conductor 260 overlaps with the first region of the conductor 240. With this configuration, when the memory cells 150 (or the openings 290) are arranged with a shift of half a repeat unit in rows and columns, the physical distance between the conductors 260 can be reduced. This allows for miniaturization and high integration of the memory device.

Figure 31C is another example of a planar layout of a memory device. The planar layout of Figure 31C illustrates conductor 260, conductor 240, memory cell 150, and opening 290, similar to Figure 31A. The memory device shown in Figure 31C differs from the memory device shown in Figure 31A mainly in the shape and extension direction of conductor 260.

The conductor 260 shown in FIG. 31C has a meandering shape like a triangular wave in plan view, and is provided extending in the Y direction. With this configuration, when the memory cells 150 (or the openings 290) are arranged with a shift of half a repeating unit in rows and columns, the physical distance between the conductors 260 can be reduced. This allows for miniaturization and high integration of the memory device. Note that the conductor 260 in plan view is not limited to the above, and may be meandering shaped, for example.

By using the above configuration, it is possible to reduce one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240, thereby achieving miniaturization and high integration of the memory device.

Figure 32 shows an example of the cross-sectional configuration of a memory device in which a layer having memory cells is stacked on a layer in which a driver circuit including a sense amplifier is provided.

In FIG. 32, a capacitor 100 is provided above a transistor 300, and a transistor 200 is provided above the transistor 300 and the capacitor 100.

Transistor 300 is one of the transistors contained in the sense amplifier.

The configuration of the memory cell 150 (transistor 200 and capacitive element 100) shown in FIG. 32 is as described above.

As shown in FIG. 32, the bit line can be shortened by configuring the sense amplifier so that it overlaps with the memory cell 150. This reduces the bit line capacitance, enabling the memory device to operate at high speed.

In addition, by providing the transistor 200 above the capacitor 100, the transistor 200 is not subjected to the thermal history during the manufacture of the capacitor 100. Therefore, in the transistor 200, it is possible to suppress deterioration of electrical characteristics such as fluctuations in threshold voltage and increases in parasitic resistance, as well as increases in variations in electrical characteristics due to deterioration of electrical characteristics.

The memory device shown in FIG. 32 can correspond to the memory device 80 described in embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 46 in the memory device 80. The memory cell 150 corresponds to the memory cell 32, the transistor 200 corresponds to the transistor 37, and the capacitance element 100 corresponds to the capacitance element 38.

The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

Here, in the transistor 300 shown in FIG. 32, the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape. In addition, the side and top surface of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

Note that the transistor 300 shown in FIG. 32 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.

A wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design. Here, the conductor functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

For example, on the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film. A conductor 328 is embedded in the insulators 320 and 322, and a conductor 330 is embedded in the insulators 324 and 326. The conductors 328 and 330 function as plugs or wiring.

The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve flatness.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 32, the insulator 350, the insulator 352, and the insulator 354 are stacked in this order. In addition, the conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.

The insulators 352 and 354, which function as interlayer films, can be the insulators that can be used in memory devices, as described above.

Conductors that function as plugs or wiring, such as conductors 328, 330, and 356, can be the conductors described above under [Conductors]. It is preferable to use a high-melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the material from a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

The conductor 240 of the transistor 200 is electrically connected to the low-resistance region 314b, which functions as the source region or drain region of the transistor 300, via the conductor 643, the conductor 642, the conductor 644, the conductor 645, the conductor 646, the conductor 356, the conductor 330, and the conductor 328.

The conductor 643 is embedded in the insulator 280. The conductor 642 is provided on the insulator 130 and embedded in the insulator 641. The conductor 642 can be manufactured using the same material and process as the conductor 120. The conductor 644 is embedded in the insulator 180 and the insulator 130. The conductor 645 is embedded in the insulator 647. The conductor 645 can be manufactured using the same material and process as the conductor 110. The conductor 646 is embedded in the insulator 648. The insulator 648 electrically insulates the transistor 300 from the conductor 110.

According to one embodiment of the present invention, a novel transistor, semiconductor device, and memory device can be provided. Alternatively, a transistor, semiconductor device, and memory device that can be miniaturized or highly integrated can be provided. Alternatively, a highly reliable transistor, semiconductor device, and memory device can be provided. Alternatively, a transistor with a large on-state current, and a semiconductor device and memory device including the transistor can be provided. Alternatively, a semiconductor device and memory device with little variation in transistor characteristics can be provided. Alternatively, a transistor with good electrical characteristics, and a semiconductor device and memory device including the transistor can be provided. Alternatively, a semiconductor device and memory device with low power consumption can be provided. Alternatively, a memory device with good frequency characteristics can be provided. Alternatively, a memory device with high operating speed can be provided.

This embodiment can be combined with other embodiments and examples as appropriate.

(Embodiment 3)
In this embodiment, a memory device of one embodiment of the present invention will be described with reference to Fig. 33 to Fig. 36. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

<Configuration example 4 of storage device>
33 is a block diagram illustrating a configuration example of a memory device 80 according to one embodiment of the present invention. The memory device 80 illustrated in FIG. 33 includes a layer 20 and a stacked layer 70.

Layer 20 is a layer having Si transistors. In stacked layer 70, element layers 30[1] to 30[m] (m is an integer of 2 or more) are stacked. Element layers 30[1] to 30[m] are layers having OS transistors. Layer 70, in which layers having OS transistors are stacked, can be stacked on layer 20.

Elements such as OS transistors and capacitors included in the element layers 30[1] to 30[m] constitute memory cells. Figure 33 shows an example in which the element layers 30[1] to 30[m] have multiple memory cells 32 arranged in a matrix of m rows and n columns (n is an integer of 2 or more).

In FIG. 33, the memory cell 32 in the first row and first column is indicated as memory cell 32[1,1], and the memory cell 32 in the mth row and nth column is indicated as memory cell 32[m,n]. In this embodiment and the like, an arbitrary row may be indicated as row i. An arbitrary column may be indicated as column j. Thus, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment and the like, the memory cell 32 in the ith row and jth column is indicated as memory cell 32[i,j]. In this embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 and does not exceed n.

In addition, in FIG. 33, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction are illustrated. In this embodiment and the like, the first wiring WL (first row) is indicated as wiring WL[1], and the mth wiring WL (mth row) is indicated as wiring WL[m]. Similarly, the first wiring PL (first row) is indicated as wiring PL[1], and the mth wiring PL (mth row) is indicated as wiring PL[m]. Similarly, the first wiring BL (first column) is indicated as wiring BL[1], and the nth wiring BL (nth column) is indicated as wiring BL[n]. Note that the number of layers of the element layers 30[1] to 30[m] and the number of wirings WL (and wirings PL) do not have to be the same.

The multiple memory cells 32 in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row. The multiple memory cells 32 in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.

The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on/off (conductive or non-conductive) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring CL (not shown) can be provided separately as a wiring for transmitting the backgate potential.

The memory cells 32 of each of the element layers 30[1] to 30[m] are connected to the sense amplifier 46 via the wiring BL. The wiring BL can be arranged in the horizontal and vertical directions on the substrate surface on which the layer 20 is provided. By configuring the wiring BL extending from the memory cells 32 of the element layers 30[1] to 30[m] with wiring arranged in the vertical direction in addition to wiring arranged in the horizontal direction on the substrate surface, the length of the wiring between the element layer 30 and the sense amplifier 46 can be shortened. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line are significantly reduced, so that the power consumption and signal delay can be reduced. Therefore, the power consumption and signal delay of the memory device 80 can be reduced. In addition, it is possible to operate even if the capacitance of the capacitor of the memory cell 32 is reduced. Therefore, the memory device 80 can be made smaller.

Layer 20 has a power switch 71 (PSW), a power switch 72, and a peripheral circuit 22. Peripheral circuit 22 has a drive circuit 40, a control circuit 73, and a voltage generation circuit 74. Each circuit in layer 20 has a Si transistor.

In the memory device 80, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by control circuit 73.

The control circuit 73 is a logic circuit that has the function of controlling the overall operation of the memory device 80. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 80. Alternatively, the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.

The voltage generation circuit 74 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 74. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 74, and the voltage generation circuit 74 generates a negative voltage.

The drive circuit 40 is a circuit for writing and reading data to the memory cells 32. The drive circuit 40 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and the sense amplifier 46 described above.

The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 32, reading data from the memory cell 32, and retaining the read data.

The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 32. The data (Dout) read from the memory cell 32 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 80. The data output from the output circuit 48 is the signal RDA.

The power switch 71 has a function of controlling the supply of VDD to the peripheral circuit 22. The power switch 72 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 80 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on/off of the power switch 71 is controlled by the signal PON1, and the on/off of the power switch 72 is controlled by the signal PON2. In FIG. 33, the number of power domains to which VDD is supplied in the peripheral circuit 22 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.

The element layers 30[1] to 30[m] can be stacked on the layer 20. Figure 34A shows a perspective view of the memory device 80 showing five (m=5) element layers 30[1] to 30[5] stacked on the layer 20.

In FIG. 34A, the element layer 30 provided in the first layer is shown as element layer 30[1], the element layer 30 provided in the second layer is shown as element layer 30[2], and the element layer 30 provided in the fifth layer is shown as element layer 30[5]. Also shown in FIG. 34A are wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the driving circuit is provided). Wiring BLB is an inverted bit line. Note that in order to make the drawing easier to understand, some of the wiring WL and wiring PL of each element layer 30 are omitted.

Figure 34B shows a schematic diagram illustrating a configuration example of the sense amplifier 46 connected to the wiring BL and wiring BLB shown in Figure 34A, and the memory cells 32 included in the element layers 30[1] to 30[5] connected to the wiring BL and wiring BLB. Note that a configuration in which multiple memory cells (memory cells 32) are electrically connected to one wiring BL and wiring BLB is also called a "memory string."

Figure 34B shows an example of the circuit configuration of the memory cell 32 connected to the wiring BLB. The memory cell 32 has a transistor 37 and a capacitor 38. The transistor 37, the capacitor 38, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], etc. For example, the memory cell 150 exemplified in the previous embodiment can be applied to the memory cell 32. That is, the transistor 200 can be used as the transistor 37, and the capacitor 100 can be used as the capacitor 38. The transistor 300 (see Figure 32) can be used as the transistor included in the sense amplifier 46.

In the memory cell 32, one of the source and drain of the transistor 37 is connected to the wiring BL. The other of the source and drain of the transistor 37 is connected to one electrode of the capacitor 38. The other electrode of the capacitor 38 is connected to the wiring PL. The gate of the transistor 37 is connected to the wiring WL.

The wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitance element 38. The number of wirings can be reduced by connecting multiple wirings PL together as a single wiring.

In one embodiment of the present invention, the OS transistors are stacked, and the wiring that functions as the bit line is arranged in a vertical direction to the substrate surface on which the layer 20 is provided. In addition, the transistor 37 and the capacitor 38 of the memory cell 32 are arranged in a vertical direction to the substrate surface on which the layer 20 is provided. By providing each element and each wiring in a vertical direction to the substrate surface, the length of the wiring between the element layers can be shortened and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent memory capacity and reduced power consumption can be obtained.

[Example of configuration of memory cell 32 and sense amplifier 46]
35A and 35B show a circuit diagram corresponding to the above-mentioned memory cell 32 and a diagram for explaining a circuit block corresponding to the circuit diagram. As shown in Fig. 35A and 35B, the memory cell 32 may be represented as a block in the drawings. Note that the wiring BL shown in Fig. 35A and 35B can be represented in the same manner even when replaced with wiring BLB.

35C and 35D show a circuit diagram corresponding to the above-mentioned sense amplifier 46 and a diagram explaining a circuit block corresponding to the circuit diagram. The sense amplifier 46 shows a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85. In addition to the wiring BL and wiring BLB, wiring SA_OUT and wiring SA_OUTB that output the read signal are also shown.

As shown in FIG. 35C, the switch circuit 82 has, for example, n-channel transistors 82_1 and 82_2. The transistors 82_1 and 82_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

The precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3 as shown in FIG. 35C. The precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD/2 in response to a signal EQ.

The precharge circuit 84 is composed of p-channel transistors 84_1 to 84_3 as shown in FIG. 35C. The precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD/2 in response to a signal EQB.

As shown in FIG. 35C, the amplifier circuit 85 is composed of p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4 connected to the wiring SAP or wiring SAN. The wiring SAP or wiring SAN is a wiring that has a function of providing VDD or VSS. The transistors 85_1 to 85_4 are transistors that form an inverter loop.

FIG. 35D shows a diagram for explaining a circuit block corresponding to the sense amplifier 46 described in FIG. 35C etc. As shown in FIG. 35D, the sense amplifier 46 may be represented as a block in drawings etc.

Figure 36 is a circuit diagram of the memory device 80 of Figure 33. Figure 36 illustrates the circuit blocks described in Figures 35A to 35D.

As shown in FIG. 36, the layer 70 including the element layer 30[m] has a memory cell 32. As an example, the memory cell 32 shown in FIG. 36 is connected to a pair of wirings BL[1] and BLB[1], or wirings BL[2] and BLB[2]. The memory cell 32 connected to the wiring BL is a memory cell to which data is written or read.

The wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 46[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 46[2]. The sense amplifier 46[1] and the sense amplifier 46[2] can read data in response to the various signals described in FIG. 35C.

This embodiment can be combined with other embodiments and examples as appropriate.

(Embodiment 4)
In this embodiment, application examples of the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 37 to 40. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[Electronic Components]
FIG. 37A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 37A has a semiconductor device 710 in a mold 711. In FIG. 37A, some parts are omitted in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

The semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The drive circuit layer 715 and the memory layer 716 can be monolithically stacked. In the monolithically stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as a Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be formed in which the memory is formed directly on the processor. By configuring the on-chip memory, it is possible to increase the speed of the operation of the interface between the processor and the memory.

In addition, by configuring the memory as an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and it is therefore possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

Moreover, it is preferable that the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked. By monolithically stacking the multiple memory cell arrays, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is difficult to stack them monolithically compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithically stacked configuration.

The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, a perspective view of electronic component 730 is shown in FIG. 37B. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM). Semiconductor device 735 can be used in integrated circuits such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or "intermediate substrate." In some cases, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV may be used as the through electrode.

HBM requires many wiring connections to achieve a wide memory bandwidth. For this reason, the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.

On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, or the like, space is required for the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a configuration in which OS transistors are used to stack monolithically is preferable. A composite structure may be used in which a memory cell array stacked using TSVs is combined with a memory cell array stacked monolithically.

A heat sink (heat sink) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. FIG. 37B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Electronics]
Next, a perspective view of an electronic device 6500 is shown in FIG. 38A. The electronic device 6500 shown in FIG. 38A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

The electronic device 6600 shown in FIG. 38B is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the control device 6509 and the control device 6616 described above is preferable because power consumption can be reduced.

[Mainframe computers]
Next, Fig. 38C shows a perspective view of the large scale computer 5600. The large scale computer 5600 shown in Fig. 38C has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.

The computer 5620 can have the configuration shown in the perspective view of FIG. 38D, for example. In FIG. 38D, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

The PC card 5621 shown in FIG. 38E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that FIG. 38E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.

[Space equipment]
The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

The semiconductor device of one embodiment of the present invention includes an OS transistor. The OS transistor has small changes in electrical characteristics due to radiation exposure. In other words, the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used when used in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

Figure 39 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 39 also shows a planet 6804 in space.

Although not shown in FIG. 39, the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit. The use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.

In addition, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.

The artificial satellite 6800 can generate a signal. The signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.

The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring the artificial satellite 6800 to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring the artificial satellite 6800 to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.

Note that in this embodiment, an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.

As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.

[Data Center]
The semiconductor device according to one embodiment of the present invention can be suitably used in a storage system applied to a data center or the like. The data center is required to perform long-term management of data, such as ensuring the immutability of the data. In order to manage long-term data, it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, securing a stable power source for holding the data, or securing cooling equipment required for holding the data.

By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.

In addition, the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

Figure 40 shows a storage system applicable to a data center. The storage system 7000 shown in Figure 40 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. In order to solve the problem of the slow access speed of storage 7003, storage systems typically provide cache memory within the storage to reduce the time required to store and output data.

The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

By using OS transistors as transistors for storing data in the cache memory, which hold a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced. In addition, by stacking the memory cell array, miniaturization is possible.

Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO ₂ ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.

This embodiment can be combined with other embodiments as appropriate.

In this example, an oxide semiconductor film of one embodiment of the present invention and a semiconductor device of one embodiment of the present invention were fabricated and evaluated, and the results are described.

[XPS]
First, an oxide semiconductor film of one embodiment of the present invention was formed and subjected to XPS analysis.

The sample was fabricated by forming a silicon oxide (SiOx) film with a thickness of approximately 100 nm as a base film by heat-treating a silicon substrate in a hydrogen chloride (HCl) atmosphere, and then forming an IGZO film with a thickness of approximately 20 nm as an oxide semiconductor film using the ALD method.

The SiOx film and the IGZO film were formed on both sides of the substrate. In this example, a film formation device was used in which IGZO films (corresponding to films 4431a and 4431b) were formed on both sides of the substrate (corresponding to front surface 4430a and back surface 4430b of substrate 4430) as shown in Figures 10A and 10B.

The specific method for forming the IGZO film was as follows: <IGZO film formation conditions>.

<IGZO film formation conditions>
The precursors used to form the IGZO film were triethylindium (TEI), triethylgallium (TEG), and diethylzinc (DEZ). Ozone ( _O3 ) and oxygen ( _O2 ) were used as oxidizers. The combined gas flow rate of _O3 gas and _O2 gas was 1000 sccm, and the ozone concentration was 19 wt%. _N2 gas was used as the carrier gas, and the gas flow rate was 150 sccm.

The IGZO film was formed to have a composition of In:Ga:Zn=1:1:1 [atomic ratio] (hereinafter, it may be referred to as IGZO (111) film). As a specific one-cycle film formation method, a gas having TEI was introduced into the chamber for 0.1 seconds, purged for 3 seconds, and then _O3 gas and _O2 gas were introduced for 45 seconds and purged for 3 seconds. Next, a gas having TEG was introduced into the chamber for 0.1 seconds, purged for 10 seconds, then _O3 gas and _O2 gas were introduced for 45 seconds and purged for 3 seconds. Next, a gas having DEZ was introduced into the chamber for 0.1 seconds, purged for 3 seconds, then _O3 gas and _O2 gas were introduced for 9 seconds and purged for 3 seconds. The substrate temperature during film formation was 200°C.

The surface area of the IGZO film of the prepared sample was subjected to XPS analysis. The XPS analysis was performed on the IGZO film formed on the front side of the sample. The obtained spectrum of Al2p is shown in Figure 41. In Figure 41, the horizontal axis represents binding energy [eV], and the vertical axis represents photoelectron intensity (arbitrary units).

When the IGZO film was subjected to XPS analysis, a peak derived from aluminum (Al) was detected. When the peak position is in the range of 74.2 eV to 74.8 eV, it can be said that Al exists in an oxidized state. As shown in FIG. 41, since there is a peak at about 74.3 eV, it was found that Al in the IGZO film exists in a state such as Al ₂ O ₃ .

In this specification, the peak position of the bond energy of a certain element when analyzed by XPS refers to the value of the bond energy at which the intensity of the energy spectrum is maximum within the range corresponding to the bond energy of that element.

The quantitative value of Al obtained from the XPS spectrum was approximately 4.0 atomic %. The lower detection limit for Al is approximately 1.0 atomic %.

[Hall effect measurement]
Next, the carrier concentration and resistivity of the oxide semiconductor film were measured by Hall effect measurement.

The sample was prepared by forming an IGZO (111) film with a thickness of approximately 35 nm on a quartz substrate using the ALD method.

Three types of samples, A, B, and C, were prepared for the Hall effect measurements. The three samples were prepared in the same way, except for the time the oxidizer was introduced.

The above-mentioned <IGZO film formation conditions> were applied to sample C. That is, the introduction time of the oxidizer ( _O3 gas and _O2 gas) after the introduction of the gas having TEI was 45 seconds, the introduction time of the oxidizer after the introduction of the gas having TEG was 45 seconds, and the introduction time of the oxidizer after the introduction of the gas having DEZ was 9 seconds. Furthermore, after performing a heat treatment at 450°C for 1 hour in an atmosphere of ultra-dry air, a heat treatment was performed for 1 hour in a reduced pressure atmosphere. The heating temperatures in the reduced pressure atmosphere were set to six conditions of 150°C, 200°C, 250°C, 300°C, 350°C, and 400°C.

Sample B was prepared in the same manner as sample C, except that the oxidizer was introduced for 30 seconds after the introduction of the gas containing TEI, 30 seconds after the introduction of the gas containing TEG, and 6 seconds after the introduction of the gas containing DEZ.

For sample A, the oxidant introduction time after the introduction of the gas containing TEI was 15 seconds, the oxidant introduction time after the introduction of the gas containing TEG was 15 seconds, and the oxidant introduction time after the introduction of the gas containing DEZ was 3 seconds. Otherwise, it was prepared in the same way as sample C. Furthermore, the heating temperature in the reduced pressure atmosphere was also performed at 100°C in addition to the six conditions similar to those for samples B and C.

Figure 42A shows the resistivity of the IGZO film formed on the back surface of the three samples. In Figure 42A, the horizontal axis represents the heating temperature [°C] under a reduced pressure atmosphere, and the vertical axis represents the resistivity [Ω cm].

42B shows the carrier concentration of the IGZO film formed on the back surface of the three samples, where the horizontal axis represents the heating temperature [° C.] under a reduced pressure atmosphere, and the vertical axis represents the carrier concentration [/cm ³ ].

As shown in Figures 42A and 42B, a decrease in resistivity and an increase in carrier concentration were confirmed by performing heat treatment under a reduced pressure atmosphere. In particular, it was found that the higher the heating temperature, the greater the decrease in resistivity and the greater the increase in carrier concentration.

Compared to samples A and B, sample C, which had a longer oxidizing agent introduction time, tended to have higher resistivity and lower carrier concentration than samples A and B under low heating temperature conditions (e.g., 150°C). However, under high heating temperature conditions (e.g., 200°C or higher), the resistivity and carrier concentration were comparable to those of samples A and B.

On the other hand, it was confirmed that the IGZO film formed on the front surface of each sample tended to have a higher resistivity and a lower carrier concentration than the IGZO film formed on the back surface. In particular, it was confirmed that the higher the heating temperature (e.g., 200°C or higher), the higher the resistivity and the lower the carrier concentration.

[Cross-sectional STEM-EDX measurement]
Next, the amount of Al detected in the oxide film was evaluated using cross-sectional STEM-EDX measurement.

The samples were prepared by forming a SiOx film with a thickness of approximately 100 nm as a base film by heat treating a silicon substrate in an HCl atmosphere, and then forming an oxide film using the ALD method. Four types of oxide films were prepared: an InOx film, a GaOx film, a ZnOx film, and an IGZO (111) film.

The IGZO film was formed to a thickness of about 35 nm. The method of forming the IGZO film was the same as that of the above-mentioned sample A. That is, the introduction time of the oxidizer ( _O3 gas and _O2 gas) after the introduction of the gas having TEI was 15 seconds, the introduction time of the oxidizer after the introduction of the gas having TEG was 15 seconds, and the introduction time of the oxidizer after the introduction of the gas having DEZ was 3 seconds. In addition, the substrate temperature during film formation was 200°C, and after the film formation, a heat treatment was performed at 450°C for 1 hour in an atmosphere of ultra-dry air, and then a heat treatment was performed at 400°C for 1 hour in a reduced pressure atmosphere.

The InOx film, GaOx film, and ZnOx film were each formed to a thickness of approximately 10 nm using the precursor used to form the IGZO film.

As a specific example of one cycle of the InOx film formation method, a gas containing TEI was introduced into the chamber for 0.1 seconds, and then purged for 3 seconds. Then, _O3 gas and _O2 gas were introduced for 30 seconds, and purged for 3 seconds.

In one specific cycle of the GaOx film formation, a gas containing TEG was introduced into the chamber for 0.1 seconds, purged for 10 seconds, and then _O3 gas and _O2 gas were introduced for 30 seconds and purged for 3 seconds.

In one specific cycle of the deposition method for the ZnOx film, a gas containing DEZ was introduced into the chamber for 0.1 seconds, purged for 3 seconds, and then _O3 gas and _O2 gas were introduced for 6 seconds and purged for 3 seconds.

For the InOx, GaOx, and ZnOx films, the substrate temperature during film formation was 200°C, and after film formation, a heat treatment was performed at 450°C for 1 hour in an ultra-dry air atmosphere.

For cross-sectional STEM (Scanning Transmission Electron Microscopy) observation, a Hitachi High-Tech HD-2300 was used with an accelerating voltage of 200 kV, a magnification accuracy of ±10%, and a beam diameter of 0.5 nmφ.

The results of the EDX analysis are shown in Table 1.

In the InOx film, the percentage of Al detected by EDX analysis was 7.7 atomic % on the front surface of the sample and 1.2 atomic % on the back surface.

The percentage of Al detected by EDX analysis in the GaOx film was below the detection limit on both the front and back surfaces, with the percentage below 0.2 atomic % on the front surface of the sample and below 0.1 atomic % on the back surface.

The percentage of Al detected by EDX analysis in the ZnOx film was below the detection limit on both the front and back sides, with the percentage below 0.1 atomic % on the front side of the sample and below 0.3 atomic % on the back side.

As mentioned above, Al was more clearly detected in InOx than in GaOx and ZnOx. Therefore, it was found that the InOx film formation cycle is the main source of Al contamination when forming IGZO films using the ALD method. Al is used as the starting material for synthesizing the precursor (TEI) used in forming the InOx film. Therefore, it was suggested that Al remaining in the precursor may have been mixed in during film formation. It was also found that the Al content was lower on the back side of the sample compared to the front side.

The percentage of Al detected by EDX analysis in the IGZO film was 2.4 atomic % on the front surface of the sample and 0.6 atomic % on the back surface. This shows that the amount of Al detected in the IGZO film is less than that in the InOx single film. It was also found that the Al content was less on the back surface of the sample than on the front surface.

The results of Hall effect measurements and EDX analysis show that the IGZO film formed on the front surface of the substrate contains a large amount of Al, and therefore when the temperature of the heat treatment in a reduced pressure atmosphere is high, aluminum oxide, an insulator, is likely to form. This is thought to have caused the increase in resistivity and the decrease in carrier concentration. On the other hand, the IGZO film formed on the back surface of the substrate contains a smaller proportion of Al than the front surface, so even if the temperature of the heat treatment in a reduced pressure atmosphere is high, the effect of Al (formation of aluminum oxide) is small, and it is thought that the carrier concentration increases and the resistance decreases due to the increase in oxygen vacancies (Vo) in the IGZO.

[SIMS Analysis 1]
Next, the hydrogen concentration, the carbon concentration, and the nitrogen concentration in the oxide semiconductor film were measured by SIMS.

The sample was fabricated by forming a SiOx film with a thickness of approximately 100 nm as a base film by heat treating a silicon substrate in an HCl atmosphere, and then forming an IGZO film with a thickness of approximately 20 nm using the ALD method.

Six types of samples were prepared for SIMS measurement: samples D1, D2, E1, E2, F1, and F2. Samples D, E, and F were prepared in the same manner, except for the time the oxidizing agent was introduced.

The above-mentioned <IGZO film formation conditions> were applied to sample D1. That is, the introduction time of the oxidizer ( _O3 gas and _O2 gas) after the introduction of the gas having TEI was 45 seconds, the introduction time of the oxidizer after the introduction of the gas having TEG was 45 seconds, and the introduction time of the oxidizer after the introduction of the gas having DEZ was 9 seconds. Sample D2 was further subjected to a heat treatment at 450°C for 1 hour in an atmosphere of ultra-dry air. It can be said that sample D1 and sample D2 have a time of supplying the oxidizer for 99 seconds during the process of forming one layer of IGZO. This time is also referred to as the ozone supply time for one layer hereinafter.

For sample E1, the introduction time of the oxidizing agent after the introduction of the gas containing DEZ was set to 45 seconds. Otherwise, it was prepared in the same manner as sample D1. For sample E2, a heat treatment was further performed at 450°C for 1 hour in an ultra-dry air atmosphere. For samples E1 and E2, the ozone supply time for one layer was 135 seconds.

For sample F1, the introduction time of the oxidizer after the introduction of the gas containing TEI was 60 seconds, the introduction time of the oxidizer after the introduction of the gas containing TEG was 60 seconds, and the introduction time of the oxidizer after the introduction of the gas containing DEZ was 60 seconds. For sample F2, a heat treatment was further performed at 450°C for 1 hour in an ultra-dry air atmosphere. The ozone supply time for one layer for samples F1 and F2 was 180 seconds.

The results of SIMS analysis of the hydrogen concentration (H concentration), carbon concentration (C concentration), and nitrogen concentration (N concentration) of the IGZO film formed on the back surface of each sample are shown in Figures 43 to 45. The horizontal axis indicates the depth from the sample surface, and the position at a depth of 0 nm on the left edge corresponds to the sample surface (the surface of the IGZO film).

43, the H concentration was about 5× ¹⁰ atoms/ ^cm in samples D1, E1, and F1, regardless of the ozone supply time. Also, in samples D2, E2, and F2, which were subjected to a heat treatment at 450° C., the H concentration could be reduced to about 5.5× ¹⁰ atoms/ ^cm .

44, it was confirmed that the C concentration could be reduced by increasing the ozone supply time. In the samples F1 and F2 in which the ozone supply time was 180 seconds (sec), the C concentration could be reduced to about 5×10 ¹⁸ atoms/cm ^3. It is considered that the carbon derived from the ethyl group of the precursor could be removed by increasing the ozone supply time.

As shown in FIG. 45, the N concentration was low, below the lower detection limit (3.7×10 ¹⁷ atoms/cm ³ or less), regardless of the ozone supply time and whether or not heat treatment was performed.

From the above, it was found that the hydrogen concentration in the IGZO film can be reduced by heat treatment at 450°C. It was also found that the carbon concentration in the IGZO film can be reduced by extending the ozone supply time.

[SIMS analysis 2]
Next, the aluminum concentration in the oxide semiconductor film was measured by SIMS.

The samples were prepared by forming a silicon oxide (SiOx) film with a thickness of approximately 100 nm as a base film on a silicon substrate using thermal oxidation, and then forming an oxide film with a thickness of approximately 20 nm using the ALD method. Four types of oxide films were prepared: an InOx film, a GaOx film, a ZnOx film, and an IGZO (111) film.

The SiOx film and the IGZO film were formed on both sides of the substrate. In this example, an ALD apparatus was used in which oxide films were formed on both sides of the substrate (front surface 4430a and back surface 4430b) as shown in Figures 10A and 10B.

The above-mentioned <IGZO film formation conditions> were applied to the formation of the IGZO film. That is, the introduction time of the oxidizing agent ( _O3 gas and _O2 gas) after the introduction of the gas containing TEI was set to 45 seconds, the introduction time of the oxidizing agent after the introduction of the gas containing TEG was set to 45 seconds, and the introduction time of the oxidizing agent after the introduction of the gas containing DEZ was set to 9 seconds. The substrate temperature during film formation was set to 200°C.

The InOx film, GaOx film, and ZnOx film were formed using the precursor used to form the IGZO film. The oxidizing agent was introduced for 15 seconds for the InOx film and GaOx film, and for 3 seconds for the ZnOx film.

The results of SIMS analysis of the aluminum concentration (Al concentration) of the IGZO film are shown in Figures 46A and 46B. The horizontal axis indicates the depth from the sample surface, and the position at a depth of 0 nm on the left edge corresponds to the sample surface (the surface of the IGZO film).

46A and 46B are the results of measuring the same sample with different devices. From FIG. 46A and FIG. 46B, it can be said that the same amount of quantification is possible regardless of the measuring device. The Al concentration of the IGZO film formed on the front surface is about 7.7×10 ²¹ atoms/cm ³ in FIG. 46A, and about 4.1×10 ²¹ atoms/cm ³ in FIG. 46B. On the other hand, the Al concentration of the IGZO film formed on the back surface is about 4.4×10 ²⁰ atoms/cm ³ in FIG. 46A, and about 6.8×10 ²⁰ atoms/cm ³ in FIG. 46B. As described above, from the results of the SIMS analysis, it was found that the Al concentration of the IGZO film formed on the back surface is lower than that of the IGZO film formed on the front surface.

As shown in FIG. 10A, in the film forming apparatus used in this embodiment, the precursor is supplied from above the substrate and is adsorbed onto the front surface of the substrate. The precursor is also adsorbed onto the back surface. For example, it is thought that the impurity (Al) contained in the precursor is preferentially adsorbed onto the front surface. As a result, the IGZO film formed on the back surface may have a lower Al concentration than the IGZO film formed on the front surface.

Figure 47 shows the results of SIMS analysis of the aluminum concentration (Al concentration) of the InOx film, GaOx film, and ZnOx film formed on the front surface of the substrate. The horizontal axis indicates the depth from the sample surface, and the position at a depth of 0 nm on the left edge corresponds to the sample surface (the surface of the InOx film, GaOx film, or ZnOx film).

The Al concentration of the InOx film formed on the front surface was about 7×10 ²¹ atoms/cm ^3. The Al concentration of the GaOx film and the Al concentration of the ZnOx film formed on the front surface were each below the lower detection limit, being about 9×10 ¹⁵ atoms/cm ³ .

As with the EDX analysis, the SIMS analysis also showed that InOx had a higher Al concentration than GaOx and ZnOx.

Moreover, from the results of the EDX analysis and SIMS analysis, it was found that the IGZO film formed on the front surface of the substrate has a higher Al concentration than the IGZO film formed on the back surface. Furthermore, from the XPS analysis, it was found that Al exists in the IGZO film in the form of Al ₂ O ₃ or the like. From the Hall effect measurement, it was confirmed that the IGZO film formed on the front surface of the substrate tends to have a higher resistivity and a lower carrier concentration than the IGZO film formed on the back surface. It is considered that the resistance of the IGZO film formed on the front surface is higher than that of the IGZO film formed on the back surface because the IGZO film contains more Al than the IGZO film formed on the back surface, and the Al exists in an oxidized state.

[Electrical characteristics of transistor]
Next, transistors having the structures shown in FIGS. 21A to 21D were manufactured and their electrical characteristics were evaluated.

For the insulator 215, silicon nitride with a thickness of about 60 nm and aluminum oxide with a thickness of about 40 nm were formed by sputtering. For the insulator 216, silicon oxide with a thickness of about 130 nm was formed by sputtering. For the conductor 205, a three-layer stacked structure of titanium nitride, tungsten, and titanium nitride was formed by metal CVD to a total thickness of about 130 nm.

As the insulator 221, silicon nitride was formed to a thickness of about 5 nm using the PEALD method, and as the insulator 222, hafnium oxide was formed to a thickness of about 15 nm using the ALD method. As the insulator 224, silicon oxide was formed to a thickness of about 20 nm using the sputtering method.

As oxide 220a, IGZO was formed to a thickness of about 10 nm using a sputtering method. Oxide 220a was formed to have a composition of In:Ga:Zn = 1:3:2 [atomic ratio] (IGZO (132)). In addition, IGZO (111) was formed to a thickness of about 15 nm using an ALD method as oxide 220b. The above-mentioned <IGZO film formation conditions> were applied to the formation conditions of IGZO (111). In addition, IGZO (111) formed in this embodiment corresponds to the IGZO formed on the back surface of the substrate described above.

As the conductors 242a1 and 242b1, tantalum nitride was formed to a thickness of about 5 nm using a sputtering method, and as the conductors 242a2 and 242b2, tungsten was formed to a thickness of about 15 nm using a sputtering method. As the insulators 271a and 271b, silicon nitride to a thickness of about 5 nm and silicon oxide to a thickness of about 10 nm were formed by stacking using a sputtering method. As the insulator 275, silicon nitride to a thickness of about 5 nm was formed using a PEALD method.

The insulator 280 was formed by stacking silicon oxide with a thickness of approximately 125 nm and silicon nitride with a thickness of approximately 120 nm using a sputtering method, and then planarized by CMP processing.

As the insulator 255, silicon nitride was formed to a thickness of about 10 nm using the PEALD method. As the insulator 250, silicon oxide was formed to a thickness of about 1.5 nm using the PEALD method, hafnium oxide was formed to a thickness of about 1 nm using the ALD method, and silicon nitride was formed to a thickness of about 1 nm using the ALD method. As the conductor 260, titanium nitride was formed to a thickness of about 5 nm and tungsten was formed to a thickness of about 150 nm using the metal CVD method. On the conductor 260, aluminum oxide was formed to a thickness of about 10 nm, silicon nitride was formed to a thickness of about 20 nm, and silicon oxide was formed to a thickness of about 50 nm using the sputtering method (corresponding to insulators 282 and 283).

The maximum temperature to which the transistor was subjected during the manufacturing process was 450°C.

The transistor fabricated in this example is an n-channel transistor, and was fabricated so that the channel length (L) and channel width (W) were each 20 nm.

The electrical characteristics of the transistor fabricated as described above were evaluated. Here, the Id-Vg characteristics were measured as the electrical characteristics. The Id-Vg characteristics were measured by setting the drain voltage Vd to 1.2 V, the source voltage Vs to 0 V, and sweeping the gate voltage Vg from -4 V to +4 V in 0.1 V steps. The measurement was also performed at room temperature.

Figure 48 shows the Id-Vg characteristics of the transistors included in the fabricated samples. In Figure 48, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate-source voltage (Vg) [V].

As shown in FIG. 48, a transistor exhibiting good switching characteristics could be manufactured using an oxide semiconductor according to one embodiment of the present invention.

[Microwave treatment]
Next, a microwave treatment was performed on the IGZO film having a thickness of about 3 nm, which was prepared by applying the above-mentioned <IGZO film formation conditions>, and a cross-sectional STEM observation was performed. Here, a cross-sectional observation of the IGZO film formed on the front surface of the substrate was performed.

The microwave treatment was performed using 150 sccm Ar gas and 50 sccm _O2 gas as treatment gas, with a pressure of 400 Pa, a power of 4000 W, and a treatment temperature of 250° C. The treatment times were 10 minutes, 30 minutes, and 60 minutes. Samples that were not subjected to microwave treatment were also prepared.

Cross-sectional STEM images of the prepared samples were taken using a Hitachi High-Technologies Corporation HD-2700. Figures 49A to 49D show the cross-sectional TEM images taken.

Figure 49A is a cross-sectional STEM image of a sample containing an IGZO film prepared without microwave treatment.

Figures 49B to 49D are cross-sectional STEM images of samples that were subjected to microwave treatment. The treatment time was 10 minutes in Figure 49B, 30 minutes in Figure 49C, and 60 minutes in Figure 49D.

As shown in Figures 49B to 49D, in the sample that underwent microwave processing, a layered crystal structure was confirmed in the IGZO film (see the area surrounded by the two-dot chain line). In Figure 49B, a layered crystal structure was confirmed in part of the IGZO film. In addition, in Figures 49C and 49D, which are cross-sectional STEM images of a sample that was processed for a longer time than in Figure 49B, a layered crystal structure was confirmed over the entire surface of the IGZO film, from the interface with the base to the surface layer. On the other hand, in Figure 47A, no layered crystal structure was confirmed in the IGZO film.

This shows that microwave treatment can form metal oxides with high crystallinity and a layered crystal structure.

In this example, an oxide semiconductor film according to one embodiment of the present invention was fabricated and evaluated, and the results are described.

[SIMS Analysis 3]
In this example, an IGZO film was formed using an In precursor having a lower aluminum content than the In precursor used in Example 1, and SIMS measurement was performed.

The sample was fabricated by forming a silicon oxide (SiOx) film with a thickness of approximately 100 nm as a base film by heat-treating a silicon substrate in a hydrogen chloride (HCl) atmosphere, and then forming an IGZO film with a thickness of approximately 20 nm as an oxide semiconductor film using the ALD method.

The SiOx film and the IGZO film were formed on both sides of the substrate. In this example, a film formation device was used in which IGZO films (corresponding to films 4431a and 4431b) were formed on both sides of the substrate (corresponding to front surface 4430a and back surface 4430b of substrate 4430) as shown in Figures 10A and 10B.

The precursors used to form the IGZO film were triethylindium (TEI), triethylgallium (TEG), and diethylzinc (DEZ). Ozone ( _O3 ) and oxygen ( _O2 ) were used as oxidizers. The combined gas flow rate of _O3 gas and _O2 gas was 1000 sccm, and the ozone concentration was 19 wt%. _N2 gas was used as the carrier gas, and the gas flow rate was 150 sccm.

The IGZO film was formed to have a composition of In:Ga:Zn=1:1:1 [atomic ratio] (hereinafter, it may be referred to as IGZO (111) film). As a specific one-cycle film formation method, a gas having TEI was introduced into the chamber for 0.1 seconds, purged for 3 seconds, and then _O3 gas and _O2 gas were introduced for 60 seconds and purged for 3 seconds. Next, a gas having TEG was introduced into the chamber for 0.1 seconds, purged for 10 seconds, then _O3 gas and _O2 gas were introduced for 60 seconds and purged for 3 seconds. Next, a gas having DEZ was introduced into the chamber for 0.1 seconds, purged for 3 seconds, then _O3 gas and _O2 gas were introduced for 60 seconds and purged for 3 seconds. The substrate temperature during film formation was 200 ° C. The sample prepared by the above method is called sample G1. Furthermore, a sample that was further subjected to a heat treatment at 450° C. for 1 hour in an ultra-dry air atmosphere is called sample G2.

Figures 50A to 50D show the SIMS analysis results for the aluminum concentration (Al concentration) of the IGZO film formed on the front surface of sample G1, and the hydrogen concentration (H concentration), carbon concentration (C concentration), and nitrogen concentration (N concentration) of the IGZO film formed on the front surface of each sample. The horizontal axis indicates the depth from the sample surface, with the position at a depth of 0 nm on the left edge corresponding to the sample surface (surface of the IGZO film). The background (BG, lower limit of measurement) is also shown with a dashed line.

As shown in Fig. 50A, the Al concentration in the IGZO film was below the lower limit of measurement (5.1 x ¹⁰¹⁵ atoms/ ^cm3 ). In Example 1, the IGZO film formed on the front surface tended to have a higher Al concentration than the IGZO film formed on the back surface. As described above, in this example, an In precursor with a lower aluminum content was used compared to the In precursor used in Example 1. It is believed that this was the reason why the Al concentration of the IGZO film formed on the front surface was sufficiently reduced.

As shown in Figure 50B, it was confirmed that sample G2, which had been subjected to heat treatment, had a lower H concentration than sample G1, which had not been subjected to heat treatment.

As shown in Figures 50C and 50D, it was confirmed that the C and N concentrations were sufficiently low regardless of whether heat treatment was performed or not.

From the above, it was found that by using a precursor with a low aluminum content to produce a metal oxide that does not contain aluminum as a main component, it is possible to prevent the aluminum concentration in the formed metal oxide film from becoming too high.

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, 4027: heater, 4028: plasma generator, 4029: coil, 4030: substrate, 4031: raw material supply section, 4032: gas supply section, 4033: raw material inlet, 4034a: pipe heater, 4034b: pipe heater, 4111: plasma generation chamber, 4120: reaction chamber, 4123: raw material inlet, 4124: raw material outlet, 4126: substrate holder, 4128: plasma generation apparatus, 4130: substrate, 4131: plasma, 4133: raw material inlet, 4213: electrode , 4214: shower head, 4215: power source, 4217: capacitor, 4220: chamber, 4223: raw material inlet, 4224: raw material outlet, 4226: substrate holder, 4230: substrate, 4231: plasma, 4313: electrode, 4314: shower head, 4315: power source, 4317: capacitor, 4319: mesh, 4320: chamber, 4321: power source, 4322: capacitor, 4323: raw material inlet, 4324: raw material outlet, 4326: substrate Plate holder, 4330: substrate, 4331: plasma, 4400: ALD device, 4410: outer chamber, 4414: raw material supply port, 4420: chamber, 4423: raw material inlet, 4424: raw material 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Claims (19)

an oxide semiconductor, a first conductor, a second conductor, a third conductor, and a first insulator;
the first conductor and the second conductor each have a portion in contact with the oxide semiconductor;
the third conductor overlaps with the oxide semiconductor via the first insulator;
the oxide semiconductor has a first portion provided along a first surface and a second portion provided along a second surface inclined with respect to the first surface;
a ratio of a thickness of the second portion to a thickness of the first portion is equal to or greater than 0.8 and equal to or less than 1.2;
the oxide semiconductor contains indium and one or more selected from the group consisting of gallium, tin, and zinc;
The oxide semiconductor has an aluminum concentration of not less than 0.01 atomic % and not more than 10 atomic %. an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator;
the first insulator contacts an upper surface of the first conductor;
the second conductor is located on the first insulator;
the oxide semiconductor has a first portion in contact with an upper surface of the first conductor, a second portion in contact with a side surface of the first insulator, and a third portion in contact with the second conductor;
the second insulator is located on the oxide semiconductor;
the third conductor is located on the second insulator and overlaps with the oxide semiconductor via the second insulator;
a ratio of a thickness of the second portion to a thickness of the first portion is equal to or greater than 0.8 and equal to or less than 1.2;
the oxide semiconductor contains indium and one or more selected from the group consisting of gallium, tin, and zinc;
The oxide semiconductor has an aluminum concentration of not less than 0.01 atomic % and not more than 10 atomic %. an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator;
the first insulator contacts an upper surface of the first conductor;
the second conductor is located on the first insulator;
the first insulator and the second conductor have a first opening reaching the first conductor;
the oxide semiconductor has, inside the first opening, a first portion in contact with an upper surface of the first conductor, a second portion in contact with a side surface of the first insulator, and a third portion in contact with the second conductor;
the second insulator is located on the oxide semiconductor;
the third conductor is located on the second insulator and overlaps with the oxide semiconductor via the second insulator at a position overlapping with the first opening;
a ratio of a thickness of the second portion to a thickness of the first portion is equal to or greater than 0.8 and equal to or less than 1.2;
the oxide semiconductor contains indium and one or more selected from the group consisting of gallium, tin, and zinc;
The oxide semiconductor has an aluminum concentration of not less than 0.01 atomic % and not more than 10 atomic %. A first insulator;
an oxide semiconductor covering the first insulator;
a first conductor and a second conductor on the oxide semiconductor;
a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor;
a third insulator disposed in the opening and on the oxide semiconductor;
a third conductor disposed in the opening and on the third insulator;
In a cross-sectional view in a channel width direction, a height of the first insulator is longer than a width of the first insulator,
the oxide semiconductor has a first portion provided along a first surface and a second portion provided along a second surface inclined with respect to the first surface;
a ratio of a thickness of the second portion to a thickness of the first portion is equal to or greater than 0.8 and equal to or less than 1.2;
the oxide semiconductor contains indium and one or more selected from the group consisting of gallium, tin, and zinc;
The oxide semiconductor has an aluminum concentration of not less than 0.01 atomic % and not more than 10 atomic %. In claim 4,
A semiconductor device, wherein, in a plan view, a side surface of the opening of the second insulator coincides or approximately coincides with a side surface of the first conductor and a side surface of the second conductor. In claim 4,
the first conductor functions as one of a source electrode and a drain electrode of a transistor;
the second conductor functions as the other of the source electrode and the drain electrode of the transistor;
the third conductor functions as a gate electrode of the transistor. In claim 6,
In a cross-sectional view of the transistor in a channel width direction,
the oxide semiconductor and the third conductor face each other on one side surface of the first insulator with the third insulator therebetween;
the oxide semiconductor and the third conductor face each other on the other side surface of the first insulator, with the third insulator interposed therebetween;
Semiconductor device. In claim 6,
In a cross-sectional view of the transistor in a channel width direction,
the first conductor is in contact with the oxide semiconductor on one side surface and the other side surface of the first insulator;
the second conductor is in contact with the oxide semiconductor on one side surface and the other side surface of the first insulator;
Semiconductor device. In claim 6,
In a cross-sectional view of the transistor in a channel width direction,
A semiconductor device, wherein the height of the first insulator is greater than or equal to 2 times and less than or equal to 20 times the width of the first insulator. In any one of claims 1 to 9,
The oxide semiconductor has an aluminum concentration of 0.01 atomic % or more and 5 atomic % or less. In any one of claims 1 to 9,
The semiconductor device, wherein the oxide semiconductor has a carbon concentration of greater than or equal to 1×10 ¹⁷ atoms/cm ³ and less than or equal to 5×10 ¹⁹ atoms/cm ³ . A semiconductor device comprising: the semiconductor device according to claim 3; a fourth conductor; a third insulator; and a capacitance element;
the capacitive element includes a fifth conductor, a fourth insulator on the fifth conductor, and the first conductor on the fourth insulator;
the third insulator is provided with a second opening reaching the fourth conductor;
At least a portion of the fifth conductor, at least a portion of the fourth insulator, and at least a portion of the first conductor are disposed in the second opening. A semiconductor device comprising: a semiconductor device according to any one of claims 4 to 9; and a capacitive element;
a first electrode of the capacitance element electrically connected to the first conductor of the semiconductor device; In claim 13,
the capacitive element is disposed on the third conductor;
at least a part of the capacitor overlaps with the oxide semiconductor and the third conductor. A first step of supplying a first compound containing indium into a chamber and then supplying an oxidizing agent into the chamber;
a second step of providing a second compound into the chamber and then providing the oxidizing agent into the chamber;
The aluminum content of the first compound is 0.01 ppm or more and 500 ppm or less,
the aluminum content of the second compound is less than the aluminum content of the first compound;
The method for forming a metal oxide film, wherein the second compound contains gallium, tin, or zinc. A first step of supplying a first compound containing indium into a chamber and then supplying an oxidizing agent into the chamber;
a second step of providing a second compound into the chamber and then providing the oxidizing agent into the chamber;
The aluminum content of the first compound is 0.01 ppm or more and 500 ppm or less,
the aluminum content of the second compound is less than the aluminum content of the first compound;
a sum of a time for supplying the oxidant in the first step and a time for supplying the oxidant in the second step is 90 seconds or more. In claim 16,
The method for forming a metal oxide film, wherein the second compound contains gallium or zinc. In claim 15 or 16,
A method for forming a metal oxide film, comprising carrying out each of the first step and the second step at least once, and then carrying out a microwave treatment in an atmosphere containing oxygen. In claim 15 or 16,
a first cycle is a cycle in which the first step and the second step are each performed at least once, and then a microwave treatment is performed in an atmosphere containing oxygen;
The method for forming a metal oxide film comprises repeating the first cycle a number of times.

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