WO2024065341A1 - Semiconductor device and manufacturing method therefor, and electronic device - Google Patents

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device, which relate to the technical field of semiconductors. A metal connecting hole (3) used in a semiconductor device has a relatively small resistance value and relatively high reliability. The semiconductor device comprises a substrate (10), and a lower electrically-conductive pattern (1), an upper electrically-conductive pattern (2), a lower dielectric layer (11), an upper dielectric layer (12) and a metal connecting hole (3), which are arranged on the substrate (10), wherein the lower dielectric layer (11) and the upper dielectric layer (12) are located between the lower electrically-conductive pattern (1) and the upper electrically-conductive pattern (2), the metal connecting hole (3) is located in the two dielectric layers, and the lower electrically-conductive pattern (1) and the upper electrically-conductive pattern (2) are electrically connected to each other by means of the metal connecting hole (3). The metal connecting hole (3) comprises a first metal column (31), and the bottom of the first metal column (31) is in contact with the lower electrically-conductive pattern (1). A bonding layer (A1) is provided between the first metal column (31) and the upper dielectric layer (12), and the first metal column (31) is in contact with the lower dielectric layer (11).

Description

Semiconductor device and manufacturing method thereof, and electronic device Technical Field

The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device.

Background technique

In semiconductor devices, conductive patterns located in different layers need to be electrically connected through metal vias. However, with the development of semiconductor technology, the resistance of the metal vias has become increasingly critical to device performance.

As shown in Figure 1, taking the use of tungsten (W) connecting holes V to connect the lower conductive pattern a1 and the upper conductive pattern (not shown in the figure) as an example, in the traditional tungsten deposition process using metal oxide chemical vapor deposition (MOCVD), it is necessary to first make an adhesive layer b (such as a TiN layer) before depositing tungsten to improve the adhesion between tungsten and the hole wall. However, the tungsten deposition under this process will appear a gap S, and at the same time, the contact resistance between the adhesive layer b at the bottom of the connecting hole and the lower conductive pattern a1 is high, which makes it difficult to reduce the resistance of the metal connecting hole.

Summary of the invention

The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can reduce the resistance of a metal connection hole.

The present application provides a semiconductor device, which may include a substrate, and a first conductive pattern (i.e., a lower conductive pattern), a second conductive pattern (i.e., an upper conductive pattern), a first dielectric layer, a second dielectric layer, and a metal connection hole arranged on the substrate. The second conductive pattern is located above the first conductive pattern (i.e., the second conductive pattern is located on the side of the first conductive pattern away from the substrate), the first dielectric layer and the second dielectric layer are located between the first conductive pattern and the second conductive pattern, and the first dielectric layer is located below the second dielectric layer (i.e., the first dielectric layer is close to the first conductive pattern relative to the second dielectric layer). The metal connection hole is located in the first dielectric layer and the second dielectric layer, and the first conductive pattern and the second conductive pattern are electrically connected through the metal connection hole. The metal connection hole includes a first metal column, and the bottom of the first metal column contacts the first conductive pattern. A first bonding layer is arranged between the first metal column and the second dielectric layer, and the first metal column contacts the first dielectric layer.

In the semiconductor device of the present application, a first metal column is used in the metal via, and the bottom of the first metal column is set to directly contact the first conductive pattern, so that the contact resistance between the first metal column and the first conductive pattern can be reduced. At the same time, a first bonding layer is set between the side wall of the first metal column and the second dielectric layer, that is, the side wall of the first metal column and the second dielectric layer are filled with bonding material, so that the adhesion between the first metal column and the second dielectric layer located on the upper layer can be improved, so that defects caused by the gap between the side wall of the first metal column and the second dielectric layer can be avoided, thereby improving the reliability of the metal connection hole.

In some possible implementations, the top of the first metal column contacts the second conductive pattern; that is, the top of the first metal column is directly connected to the second conductive pattern, ensuring a smaller contact resistance between the top of the first metal column and the second conductive pattern.

In some possible implementations, the metal connection hole further includes a second metal column; the second metal column is located at the top of the first metal column, and a second bonding layer is provided between the second metal column and the top of the first metal column, and between the second metal column and the second dielectric layer; the top of the second metal column contacts the second conductive pattern. In this case, by forming the second bonding layer at the bottom and sidewall of the second metal column, the probability of the polishing agent contacting the first conductive pattern when the surface of the second dielectric layer is subsequently polished can be further reduced.

In some possible implementations, the surface of the first conductive pattern has a recessed portion, and the edge of the recessed portion is located outside the hole wall of the metal connection hole; the bottom of the first metal column extends and fills the recessed portion. In this case, the first metal column forms a rivet structure at the bottom, thereby generating a "rivet effect", further reducing the probability of the polishing agent contacting the first conductive pattern when the surface of the second dielectric layer is subsequently polished.

In some possible implementations, the material used for the first bonding layer includes at least one of TiN, Ti, Ta or TaN.

In some possible implementations, the material used for the second bonding layer includes at least one of TiN, Ti, Ta or TaN.

In some possible implementations, the material used for the first dielectric layer includes SiN; and the material used for the second dielectric layer includes SiO ₂ .

In some possible implementations, the first metal pillar is manufactured using a selective deposition process.

In some possible implementations, the second metal column is manufactured using a metal oxide chemical vapor deposition process.

An embodiment of the present application also provides an electronic device, which includes a printed circuit board and a semiconductor device provided in any of the possible implementation methods described above; the semiconductor device is electrically connected to the printed circuit board.

The embodiment of the present application also provides a method for manufacturing a semiconductor device, which may include: manufacturing a first conductive pattern on a substrate. Manufacturing a first dielectric layer and a second dielectric layer in sequence on the surface of the first conductive pattern. Forming a first via hole at a position of the second dielectric layer corresponding to the first conductive pattern, and forming a first bonding layer on the side wall of the first via hole. Etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole, and leaking the first conductive pattern. Using a selective deposition process, forming a first metal column on the surface of the leaked first conductive pattern, and the first metal column extends into the second dielectric layer. Forming a second conductive pattern electrically connected to the first metal column on the surface of the second dielectric layer.

In some possible implementations, the second conductive pattern electrically connected to the first metal pillar is formed on the surface of the second dielectric layer, and may include: forming the second conductive pattern connected to the surface of the first metal pillar on the surface of the second dielectric layer, that is, the top of the first metal pillar is in direct contact with the second conductive pattern, thereby ensuring a small contact resistance between the top of the first metal pillar and the second conductive pattern.

In some possible implementations, the second conductive pattern electrically connected to the first metal pillar formed on the surface of the second dielectric layer may include: forming a second bonding layer on the surface of the substrate on which the first metal pillar is formed; forming a second metal pillar on the second bonding layer and in the first via hole by metal oxide chemical vapor deposition; and forming a second conductive pattern connected to the surface of the second metal pillar on the surface of the second dielectric layer.

In some possible implementations, the above-mentioned etching of the first dielectric layer at a position corresponding to the first via hole to form a second via hole and leaking the first conductive pattern may include: etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole, and etching the surface of the first conductive pattern to form a recessed portion; wherein the edge of the recessed portion is located on the outside of the hole wall of the second via hole.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a metal connection hole in a semiconductor device provided in the prior art;

FIG2 is a schematic diagram of a metal connection hole in a semiconductor device provided in an embodiment of the present application;

FIG3 is a schematic diagram of a metal connection hole in a semiconductor device provided in an embodiment of the present application;

FIG4 is a schematic diagram of a metal connection hole in a semiconductor device provided in an embodiment of the present application;

FIG5 is a schematic diagram of a metal connection hole in a semiconductor device provided in an embodiment of the present application;

FIG6 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

FIG7 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

FIG8 is a schematic structural diagram of a semiconductor device during manufacturing provided by an embodiment of the present application;

FIG9 is a schematic structural diagram of a semiconductor device during manufacturing provided by an embodiment of the present application;

FIG10 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

FIG11 is a schematic structural diagram of a semiconductor device during manufacturing process provided by an embodiment of the present application;

FIG12 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of a semiconductor device during the manufacturing process provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple. "Connect", "connected" and similar words are used to express the intercommunication or interaction between different components, and may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", "top", "bottom", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for relative description and clarification, and may change accordingly according to the changes in the orientation of the components in the drawings.

An embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB) and a semiconductor device connected to the printed circuit board. The semiconductor device includes conductive patterns located in different layers, and the conductive patterns in different layers are electrically connected through metal connecting holes. In the embodiment of the present application, a new type of metal connecting hole with a lower resistance is used, thereby improving the performance of the semiconductor device.

The present application does not limit the configuration of the above electronic device. For example, the electronic device may be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, or other electronic products.

The present application does not limit the configuration of the semiconductor device. For example, the semiconductor device may be a memory, a processor, a sensor, or the like.

The specific structure of the semiconductor device provided in the embodiment of the present application is schematically described below.

As shown in FIG2 , an embodiment of the present application provides a semiconductor device, which includes a substrate 10 and a first conductive pattern 1 and a second conductive pattern 2 disposed on the substrate 10 and located at different layers. The second conductive pattern 2 is located above the first conductive pattern 1 (i.e., on a side away from the substrate 10). A first dielectric layer 11 (i.e., a lower dielectric layer) and a second dielectric layer 12 (i.e., an upper dielectric layer) are disposed between the first conductive pattern 1 and the second conductive pattern 2. The first dielectric layer 11 is located below the second dielectric layer 12 (i.e., the first dielectric layer 11 is closer to the substrate 10 relative to the second dielectric layer 12). The first conductive pattern 1 and the second conductive pattern 2 are electrically connected via metal connection holes 3 disposed in the first dielectric layer 11 and the second dielectric layer 12.

The present application does not limit the specific configuration of the substrate 10 , the first conductive pattern 1 , and the second conductive pattern 2 , which can be determined in practice according to the specific structure of the semiconductor device.

Schematically, the substrate 10 may include a substrate and a transistor disposed on the substrate, the first conductive pattern 1 may be a source, a drain or a gate of the transistor, or may be a conductive pattern such as a signal line, and the second conductive pattern 2 may be a conductive pattern such as a signal line or a capacitor electrode; the present application does not limit this. For example, in some possible implementations, the first conductive pattern 1 may be a source, a drain or a gate of a transistor, and the second conductive pattern 2 may be a signal line. For another example, in some possible implementations, the first conductive pattern 1 and the second conductive pattern 2 may both be signal lines.

In addition, for the above-mentioned metal connection hole 3 located in the first dielectric layer 11 and the second dielectric layer 12, a through hole may be formed in the first dielectric layer 11 and the second dielectric layer 12, and one or more metal pillars may be formed in the through hole, thereby forming the metal connection hole 3; that is, the metal connection hole 3 may include one metal pillar, or may include two or more metal pillars. Of course, according to actual needs, the metal connection hole 3 may also include other structures, and the present application does not impose any restrictions on this. For details, please refer to the description of the metal connection hole 3.

Schematically, referring to FIG. 2 , in some possible implementations, the metal connection hole 3 includes a first metal column 31, and the bottom of the first metal column 31 is in direct contact with the first conductive pattern 1, thereby reducing the contact resistance between the first metal column 31 and the first conductive pattern 1. A first bonding layer a1 is provided between a portion of the first metal column 31 located in the second dielectric layer 12 and the second dielectric layer 12, and a portion of the first metal column 31 located in the first dielectric layer 11 is in direct contact with the first dielectric layer 11.

It should be noted here that the "top" and "bottom" involved in this application are two relative positions of components, and the "top" is closer to the substrate 10 than the "bottom"; as mentioned above, the "bottom of the first metal column 31" refers to the end of the first metal column 31 close to the substrate 10, and the "top of the first metal column 31" refers to the end of the first metal column 31 away from the substrate 10. In addition, the "direct contact" involved in this application means that there is no other component between the two components, and the two components are directly connected; such as the "bottom of the first metal column 31 is in direct contact with the first conductive pattern 1" in the above text, please refer to the corresponding relevant instructions below for details. In addition, it can be understood that by setting the first bonding layer a1 between the side wall of the first metal column 31 and the second dielectric layer 12, that is, filling the side wall of the first metal column 31 and the second dielectric layer 12 with bonding material, the adhesion between the first metal column 31 and the second dielectric layer 12 located on the upper layer can be improved, thereby avoiding defects caused by the gap between the side wall of the first metal column 31 and the second dielectric layer 12 (see the description below for details), thereby improving the reliability of the metal connection hole 3.

As for the above-mentioned “defects are caused by the gap between the side wall of the first metal pillar 31 and the second dielectric layer 12”, it can be understood that the adhesion between the metal material and the dielectric layer is poor. If the first bonding layer a1 is not provided, a gap will be generated between the side wall of the first metal pillar 31 and the second dielectric layer 12 during the process of forming the first metal pillar 31 through the deposition process. Due to the existence of the gap, when the surface of the second dielectric layer 12 is ground (such as chemical mechanical grinding) in the subsequent manufacturing process, the grinding agent will move downward from the gap position, thereby causing missing (missing) on the side wall of the first metal pillar 31. At the same time, the grinding agent contacts the first conductive pattern 1, which will cause damage (damage) to the first conductive pattern 1. Therefore, in the present application, by providing the first bonding layer a1 between the first metal pillar 31 and the second dielectric layer 12 located on the upper layer, the probability of the above-mentioned defects is reduced, thereby improving the reliability of the device.

In addition, based on the setting mode that the bottom of the first metal pillar 31 is in direct contact with the first conductive pattern 1, in the actual manufacturing process, in some possible implementation modes, a selective deposition process can be used to manufacture the first metal pillar 31, that is, selectively depositing metal material on the surface of the first conductive pattern 1 to form the first metal pillar 31, so that the bottom of the first metal pillar 31 is in direct contact with the first conductive pattern 1, thereby avoiding the problem of high contact resistance between the bottom of the first metal pillar 31 and the first conductive pattern 1 due to the bonding layer in the prior art using MOCVD (refer to FIG. 1), and also avoiding the formation of a gap in the central area of the first metal pillar 31 (refer to S in FIG. 1); that is, reducing the resistance of the metal connection hole.

It is understandable that different semiconductor devices have different performances on the improvement of the resistance of the metal connection hole 3. Generally, if the resistance of the metal connection hole 3 is increased by about 50%, the performance of the device will be improved by about 5%. Especially for more advanced semiconductor devices, the resistance of the metal connection hole 3 is increasingly becoming the key to the performance of the device. By adopting the metal connection hole in the embodiment of the present application, the restriction on the device caused by the resistance of the metal connection hole can be reduced.

The present application does not limit the conductive materials used by the first conductive pattern 1 and the second conductive pattern 2. Schematically, the first conductive pattern 1 and the second conductive pattern 2 can be made of conductive materials such as Co, Cu, and W. For example, in some possible implementations, the first conductive pattern 1 and the second conductive pattern 2 can be made of Co.

The present application does not limit the metal material used for the first metal pillar 31. For example, the first metal pillar 31 may be made of metal materials such as W, Cu, and Co. For example, in some possible implementations, the first metal pillar 31 may be made of W.

The present application does not limit the material used for the first bonding layer a1. For example, the material used for the first bonding layer a1 may include at least one of TiN, Ti, Ta, and TaN. For example, in some possible implementations, the first bonding layer a1 may be made of TiN.

In addition, the present application does not limit the materials used for the first dielectric layer 11 and the second dielectric layer 12 and the number of layers. For example, in some possible implementations, the first dielectric layer 11 can be one dielectric layer; for another example, in some possible implementations, as shown in FIG3 , the first dielectric layer 11 can include two dielectric layers (A1, A2). Similarly, the second dielectric layer 12 can be one dielectric layer or multiple dielectric layers.

In addition, the present application does not limit the insulating dielectric materials used in the first dielectric layer 11 and the second dielectric layer 12. For example, the first dielectric layer 11 and the second dielectric layer 12 may be made of insulating dielectric materials such as oxides (such as SiO ₂ ), nitrides (such as SiN), and oxynitrides (SiO _y N _x ). Schematically, in some possible implementations, the first dielectric layer 11 includes two SiN layers (A1, A2), and the second dielectric layer 12 is a SiO ₂ layer. Of course, in the area outside the metal connection hole 3, other film layer patterns may be provided between the two SiN layers (A1, A2).

In addition, in some possible implementations, as shown in FIG4 , a recessed portion T may be provided on the surface of the first conductive pattern 1, and the edge of the recessed portion T is located outside the hole wall of the metal connection hole 3. The bottom of the first metal column 31 extends and fills into the groove portion T. In this case, the first metal column 31 forms a rivet structure at the bottom, thereby generating a "rivet effect", further reducing the probability of the grinding agent contacting the first conductive pattern 1 when the surface of the second dielectric layer 12 is subsequently ground (for details, refer to the following).

In addition, the present application does not limit the electrical connection method between the first metal pillar 31 and the second conductive pattern 2 . The second conductive pattern 2 and the first metal pillar 31 may be directly connected or indirectly connected.

For example, in some possible implementations, as shown in FIG. 4 , the top of the first metal pillar 31 may be in direct contact with the second conductive pattern 2 to form an electrical connection.

For another example, in some possible implementations, as shown in FIG5 , the metal connection hole 3 may further include a second metal column 32, the second metal column 32 is located at the top of the first metal column 31, and a second bonding layer a2 is provided between the bottom of the second metal column 32 and the first metal column 31, and between the side of the second metal column 32 and the second dielectric layer 12; that is, the second bonding layer a2 wraps around the side and bottom of the second metal column 32. In this case, the top of the second metal column 32 contacts the second conductive pattern 2, that is, the second conductive pattern 2 is electrically connected to the first metal column 31 through the second metal column 32. By providing the second bonding layer a2 at the bottom and side of the second metal column, the probability of the polishing agent contacting the first conductive pattern 1 when the surface of the second dielectric layer 12 is subsequently polished can be further reduced.

The material of the second bonding layer a2 may be the same as or different from that of the first bonding layer a1, and this application does not limit this. Schematically, the material of the second bonding layer a2 may be at least one of TiN, Ti, Ta, and TaN.

For the production of the second metal column 32, in some possible implementations, metal oxide chemical vapor deposition (MOCVD) can be used for production. It should be understood that since the second metal column 32 is located at the top area of the entire metal connection hole 3, the probability of the top of the via being completely blocked during the deposition process is small, that is, the probability of a gap appearing in the central area of the second metal column 32 is small.

It should be noted here that, in the case where the metal connection hole 3 includes both the first metal column 31 and the second metal column 32, in some embodiments, as shown in FIG5 , the first bonding layer a1 located on the side of the first metal column 31 extends upward to the side of the second metal column 32, that is, the first bonding layer a1 and the second bonding layer a2 are provided between the side wall of the second metal column 32 and the second dielectric layer 12. The embodiment of the present application also provides a method for manufacturing a semiconductor device, as shown in FIG6 , the manufacturing method may include:

Step 01, referring to FIG. 7 , a first conductive pattern 1 is manufactured on a substrate 10 , and a first dielectric layer 11 and a second dielectric layer 12 are sequentially manufactured on the surface of the first conductive pattern 1 .

In some possible implementations, the substrate 10 may include a substrate and other structures disposed on the substrate. A Co conductive pattern (1) is formed on the surface of the substrate 10 through step 01. The Co conductive pattern (1) may be used as a source, a drain, a gate, etc. of a transistor. Then, a first dielectric layer 11, such as two SiN layers (A1, A2), is formed on the surface of the Co conductive pattern (1); and a second dielectric layer 12, such as a _SiO2 layer, is formed on the surface of the first dielectric layer 11.

It can be understood here that the above-mentioned first conductive pattern 1, first dielectric layer 11, and second dielectric layer 12 are not necessarily manufactured in sequence and continuously, but depend on the structure of the entire device. For example, other pattern film layers (located in the area outside the first conductive pattern 1) may be manufactured between the two SiN layers (A1, A2) in the first dielectric layer 11; similarly, other film layers may be manufactured between the first dielectric layer 11 and the second dielectric layer 12 in the area outside the first conductive pattern 1.

Step 02, referring to FIG. 8 , a first via hole V1 is formed at a position of the second dielectric layer 12 corresponding to the first conductive pattern 1, and a first adhesive layer a1 is formed on a side wall of the first via hole V1.

Schematically, in some possible implementations, referring to FIG8 (a), through step 02, first, at the position corresponding to the first conductive pattern 1, the second dielectric layer 12 is etched by dry etching to form a first via V1, and the etching stops on the first dielectric layer 11, that is, the first dielectric layer 11 serves as a contact etch stop layer (CESL). Of course, after the etching of the first via V1 is completed, post-etching treatment is required, such as wet cleaning, removal of etching byproducts, etc. Then, referring to FIG8 (b) and (c), a first bonding layer a1 is deposited on the surface of the second dielectric layer 12, and the first bonding layer a1 located at the bottom of the first via V1 and the upper surface of the second dielectric layer 12 is removed, and only the first bonding layer a1 located on the side wall of the first via V1 is retained to protect the side wall of the first via V1.

Step 03, referring to FIG. 9 , the first dielectric layer 11 is etched at a position corresponding to the first via hole V1 to form a second via hole V2, and the first conductive pattern 1 is exposed.

Schematically, in some possible implementations, referring to FIG9 , through step 03, the first dielectric layer 11 is dry-etched at a position corresponding to the first via hole V1 to form a second via hole V2, that is, a via hole V' is formed that penetrates the first dielectric layer 11 and the second dielectric layer 12. Of course, after etching is completed, post-etching processing is required, such as wet cleaning, removal of etching byproducts, etc.

Of course, in other possible implementations, as shown in FIG10, when forming the second via hole V2 in step 03, the etching depth can be controlled, and the surface of the first conductive pattern 1 is etched to form a recessed portion T, and the edge of the recessed portion T is ensured to be located outside the hole wall of the second via hole V2. In this way, as shown in FIG4, the bottom of the first metal column 31 formed subsequently can be extended and filled into the recessed portion T to form a rivet structure, thereby generating a "rivet effect". For relevant instructions, please refer to the previous text and will not be repeated here.

Step 04, referring to FIG. 11 , a selective deposition process is used to form a first metal column 31 on the surface of the leaked first conductive pattern 1 , and the first metal column 31 extends into the second dielectric layer 12 .

As shown, in some possible implementations, through step 04, a selective tungsten deposition process is used to grow W on the surface of the first conductive pattern 1 (such as a Co conductive pattern) located in the via hole V', thereby forming a first tungsten metal column (31). Before the selective tungsten deposition process is performed, the surface of the first conductive pattern 1 can be pre-treated, such as removing surface dangling bonds, to increase selectivity.

It can be understood here that based on the first bonding layer a1 formed in step 02, when the first tungsten metal column (31) is formed in step 04, the first bonding layer a1 can be filled between the first tungsten metal column (31) and the second dielectric layer 12. Since the growth rate of the metal on the bonding layer (such as TiN) is greater than the growth rate directly on the dielectric layer (such as SiO ₂ ), the bonding between tungsten (W) and the side wall can be increased by setting the first bonding layer a1. In this case, on the one hand, the process window is increased and the control difficulty of the process is reduced; on the other hand, the first bonding layer a1 can reduce the probability of the first tungsten metal column (31) and the second dielectric layer 12. The loss of the first tungsten metal column (31) (i.e., tungsten loss) and the damage of the Co conductive pattern (1) (i.e., cobalt damage) are reduced, thereby improving the reliability of the device.

Step 05, referring to FIG. 3 , a second conductive pattern 2 electrically connected to the first metal pillar 31 is formed on the surface of the second dielectric layer 12 .

Schematically, in some possible implementations, as shown in FIG3 , after the first metal pillar 31 is fabricated through step 04, the surface of the second dielectric layer 12 is directly polished, such as chemical mechanical polish (CMP). Then, a second conductive pattern 2 connected to the first metal pillar 31 is formed on the surface of the second dielectric layer 12 through step 05. In this case, the fabrication of the metal connection hole 3 does not require the use of metal oxide chemical vapor deposition (MOCVD), thereby reducing the process difficulty and cost.

Of course, as another possible implementation method, as shown in FIG. 12 (a), after the first metal pillar 31 is made in step 04, a first via hole V1 with a certain depth is left unfilled above the first metal pillar 31; then, as shown in FIG. 12 (b), through step 05, a second bonding layer a2 is first deposited on the surface of the substrate on which the first metal pillar 31 is formed, so as to cover the bonding material on the upper surface of the second dielectric layer 12, the top of the first metal pillar 31, and the sidewall of the via hole. Then, as shown in FIG. 12 (c), a second metal pillar 32 is formed on the second bonding layer a2 and in the first via hole V1 by using metal oxide chemical vapor deposition (MOCVD). In this case, the first bonding layer a1 and the second bonding layer a2 are provided between the sidewall of the second metal pillar 32 and the second dielectric layer 12. After the second metal pillar 32 is fabricated, according to the actual needs of the semiconductor device, when the surface of the second dielectric layer 12 is ground, the second metal pillar 32 and the second bonding layer a2 can be completely removed as a grinding sacrificial layer to expose the top of the first metal pillar 31, and then the second conductive pattern 2 can be fabricated (refer to the structure of FIG. 3 ). Of course, as another possible implementation method, as shown in FIG. 13 , when the surface of the second dielectric layer 12 is ground, at least a portion of the second metal pillar 32 can be retained, and then the second conductive pattern 2 can be fabricated.

Regarding other related contents in the above-mentioned semiconductor device manufacturing method embodiment, the corresponding parts in the above-mentioned semiconductor device structure embodiment can be referred to, and no further details will be given here. Regarding the related structures in the above-mentioned semiconductor device structure embodiment, they can be made correspondingly with reference to the above-mentioned semiconductor device manufacturing method embodiment, or they can be made by combining relevant technologies with appropriate adjustments, and this application does not limit this.

It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (13)

A semiconductor device, comprising: A first conductive pattern disposed on the substrate; a second conductive pattern, the second conductive pattern being located on a side of the first conductive pattern away from the substrate; A first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are located between the first conductive pattern and the second conductive pattern, and the first dielectric layer is closer to the first conductive pattern than the second dielectric layer; A metal connection hole, wherein the metal connection hole is disposed in the first dielectric layer and the second dielectric layer, and the first conductive pattern and the second conductive pattern are electrically connected through the metal connection hole; The metal connection hole includes a first metal column, the bottom of which is in contact with the first conductive pattern; a first bonding layer is disposed between the first metal column and the second dielectric layer, and the first metal column is in contact with the first dielectric layer. The semiconductor device according to claim 1, wherein: A top of the first metal column contacts the second conductive pattern. The semiconductor device according to claim 1, wherein: The metal connection hole also includes a second metal column; The second metal column is located at the top of the first metal column, and a second bonding layer is provided between the second metal column and the top of the first metal column, and between the side of the second metal column and the second dielectric layer; the top of the second metal column contacts the second conductive pattern. The semiconductor device according to any one of claims 1 to 3, characterized in that The surface of the first conductive pattern has a recessed portion, and the edge of the recessed portion is located outside the hole wall of the metal connection hole; The bottom of the first metal column extends to fill the recessed portion. The semiconductor device according to any one of claims 1 to 4, characterized in that The material of the first bonding layer includes at least one of TiN, Ti, Ta or TaN. The semiconductor device according to any one of claims 1 to 5, characterized in that The material used for the first dielectric layer includes SiN; The material of the second dielectric layer includes SiO ₂ . The semiconductor device according to any one of claims 1 to 6, characterized in that The first metal column is manufactured by a selective deposition process. The semiconductor device according to any one of claims 3 to 7, characterized in that: The second metal column is manufactured by using a metal oxide chemical vapor deposition process. An electronic device, characterized in that it comprises a printed circuit board and a semiconductor device as described in any one of claims 1 to 8; the semiconductor device is electrically connected to the printed circuit board. A method for manufacturing a semiconductor device, characterized by comprising: forming a first conductive pattern on a substrate; Sequentially forming a first dielectric layer and a second dielectric layer on the surface of the first conductive pattern; forming a first via hole at a position of the second dielectric layer corresponding to the first conductive pattern, and forming a first bonding layer on a side wall of the first via hole; Etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole, and exposing the first conductive pattern; Using a selective deposition process, a first metal column is formed on the surface of the leaked first conductive pattern, and the first metal column extends into the second dielectric layer; A second conductive pattern electrically connected to the first metal column is formed on the surface of the second dielectric layer. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The forming of a second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer comprises: A second conductive pattern connected to the surface of the first metal column is formed on the surface of the second dielectric layer. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The forming of a second conductive pattern electrically connected to the first metal pillar on the surface of the second dielectric layer comprises: forming a second bonding layer on the surface of the substrate on which the first metal pillar is formed; Forming a second metal column on the second bonding layer and in the first via hole by using a metal oxide chemical vapor deposition method; A second conductive pattern connected to the surface of the second metal column is formed on the surface of the second dielectric layer. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, characterized in that: The step of etching the first dielectric layer at a position corresponding to the first via hole to form a second via hole and leaking the first conductive pattern includes: The first dielectric layer is etched at a position corresponding to the first via hole to form a second via hole, and the surface of the first conductive pattern is etched to form a recessed portion; wherein an edge of the recessed portion is located outside a hole wall of the second via hole.

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