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WO2024060370A1 - Mémoire et système de stockage - Google Patents

Mémoire et système de stockage Download PDF

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Publication number
WO2024060370A1
WO2024060370A1 PCT/CN2022/130651 CN2022130651W WO2024060370A1 WO 2024060370 A1 WO2024060370 A1 WO 2024060370A1 CN 2022130651 W CN2022130651 W CN 2022130651W WO 2024060370 A1 WO2024060370 A1 WO 2024060370A1
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WIPO (PCT)
Prior art keywords
memory
block
control circuit
storage
control
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PCT/CN2022/130651
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English (en)
Chinese (zh)
Inventor
唐衍哲
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and relate to but are not limited to a memory and storage system.
  • DRAM Dynamic Random Access Memory
  • Random access memory is composed of multiple repeated memory cells. Each memory cell is mainly composed of a selection transistor and a storage capacitor controlled by the selection transistor. Each memory cell is electrically connected to each other through word lines and bit lines.
  • this kind of random access memory has problems such as large storage area occupied by the memory unit, complex wiring, and difficult manufacturing process.
  • embodiments of the present disclosure provide a memory and a storage system.
  • an embodiment of the present disclosure provides a memory, including:
  • control circuit layer located within the substrate; the control circuit layer includes at least part of the control circuit of the memory;
  • At least two storage structure layers are stacked on the control circuit layer in sequence; the storage structure layer is electrically connected to the control circuit layer.
  • the storage structure layer includes: a plurality of storage blocks arranged in an array;
  • the control circuit layer includes: a plurality of control blocks connected correspondingly to each of the memory blocks.
  • the storage block includes:
  • each of the word lines connects a plurality of the storage units arranged at intervals along the first direction; and the first direction is parallel to the surface of the substrate.
  • the memory further includes:
  • a bit line structure layer is located between the control circuit layer and at least two of the memory structure layers; the bit line structure layer includes a plurality of bit lines extending along a second direction; the second direction and the There is an included angle between the first directions, and the second direction is parallel to the surface of the substrate;
  • Each of the bit lines is connected to a plurality of groups of memory cells spaced apart along the second direction, wherein each group of memory cells is a plurality of memory cells stacked in a direction perpendicular to the substrate surface and connected through a first branch line. unit.
  • control block includes:
  • a first control block connected to the bit line structure layer, wherein at least a portion of the first control block is located between projection areas of two adjacent storage blocks along an extension direction of the bit line;
  • a second control block is connected to the word line, and at least part of the second control block is located within the projection area of the memory block where the connected word line is located.
  • corresponding memory blocks in different memory structure layers in a direction perpendicular to the substrate surface are aligned along the second direction.
  • two adjacent storage blocks along the second direction in the same storage structure layer share one first control block.
  • the storage structure layer includes: an upper structure layer and a lower structure layer; the storage block in the upper structure layer is a first storage block; the storage block in the lower structure layer is a second storage block. ;
  • the projections of the first spacing area and the second spacing area on the control circuit layer do not overlap.
  • the first storage block is connected to a second control block corresponding to the first storage block through a connection line running through the second spacing area;
  • the second storage block is connected to the second control block corresponding to the second storage block through a connection line located below the second storage block.
  • the second control block corresponding to the first storage block and the second storage block are connected to the second control block corresponding to the second storage block.
  • the second control blocks corresponding to the second storage blocks are arranged at intervals along the first direction.
  • the length of the connection line of the first storage block is greater than the length of the connection line of the second storage block
  • the driving capability of the second control block connected to the first storage block is greater than the driving capability of the second control block connected to the second storage block.
  • the memory further includes:
  • a power module connected to a plurality of first control blocks and/or a plurality of second control blocks, and configured to provide power signals;
  • the power module is located in the substrate, and the power module and the control circuit layer are located in the same structural layer.
  • the memory further includes:
  • a data input and output module is connected to the first control block, and the data input and output module is configured to write or read data to the storage unit through the first control block and the bit line.
  • control circuit layer further includes: a global control circuit
  • the global control circuit is connected to a plurality of the control blocks
  • the global control circuit is at least used to provide control signals to a plurality of the control blocks.
  • the global control circuit includes:
  • a global word line driver module is connected to a plurality of second control blocks, and is configured to provide control signals for a plurality of word lines in the memory blocks to which the plurality of second control blocks are connected.
  • embodiments of the present disclosure also provide a storage system, including:
  • the control circuit of the memory is disposed in the control circuit layer between the stacked storage structure layer and the substrate, and the storage structure layer and the control circuit layer are connected through a direction perpendicular to the substrate. line to connect.
  • the memory provided by the embodiments of the present disclosure can have a higher integration level and a smaller area, and the vertically stacked structure is more convenient for manufacturing and circuit wiring design.
  • Figure 1 is a schematic structural diagram of a storage system according to an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a bank in the storage system according to an embodiment of the present disclosure
  • FIG3 is a second structural diagram of a memory according to an embodiment of the present disclosure.
  • Figure 4 is a top view of a single-layer storage structure layer in a memory structure according to an embodiment of the present disclosure
  • Figure 5 is a cross-sectional view of a single-layer storage structure layer in a memory structure according to an embodiment of the present disclosure
  • Figure 6 is a cross-sectional view of a double-layer storage structure layer in a memory structure according to an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of the connection relationship between storage and units and control blocks in a memory structure according to an embodiment of the present disclosure
  • Figure 8 is a schematic diagram of the connection relationship between bit lines and multiple memory blocks in a memory structure according to an embodiment of the present disclosure
  • Figure 9 is a schematic diagram of the dislocation distribution of memory blocks in different storage structure layers in a memory structure according to an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of the connection relationship between the global control circuit and each control block and storage block in a memory structure according to an embodiment of the present disclosure
  • FIG11 is a flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure.
  • Figure 12 is a structural block diagram of a storage system according to an embodiment of the present disclosure.
  • terms can be understood, at least in part, from context of use.
  • the term "one or more” as used herein may be used in the singular to describe any feature, structure or characteristic, or may be used in the plural to describe a combination of features, structures or characteristics.
  • terms such as “a” or “the” may equally be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on context.
  • a memory which may include but is not limited to DRAM, static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.
  • SRAM static random access memory
  • FRAM ferroelectric random access memory
  • MRAM magnetic random access memory
  • PCRAM phase change random access memory
  • RRAM resistive random access memory
  • NRAM nano random access memory
  • Figure 1 shows a system architecture diagram of a memory.
  • the memory system 10 includes a plurality of memory banks (banks) arranged in parallel.
  • Each bank may include a memory cell array 11 composed of memory cells arranged in an array, and these memory cells may also be divided into multiple memory blocks (as shown in FIG. 2 ).
  • each bank also includes a row decoder 12, a column decoder 13, a word line driver circuit 14, a write driver/read amplifier 15, a row fuse repair circuit 16 and a column fuse coupled to the memory cell array. Repair circuit 17 etc.
  • Each memory cell in the memory cell array may include a gate transistor T and a storage capacitor C, and each memory cell is respectively connected to the cross-arranged word line WL and bit line BL.
  • the bit line connected to each memory cell is also connected to a sense amplifier circuit (Sense Amplifier, SA, also known as a sense amplifier).
  • SA sense amplifier circuit
  • the bit lines connected to each SA include target bit lines (Target BitLine, BLT) and reference bit lines (Reference BitLine, BLB).
  • BLT target BitLine
  • BLB Reference BitLine
  • the BLB can be a dedicated reference bit line set separately, or a bit line connected to other memory cells, such as a bit line in an adjacent memory block or a bit line in an adjacent bank.
  • the storage units connected to BLT and BLB cannot perform read and write operations at the same time.
  • the above-mentioned memory system 10 also includes a peripheral circuit 20.
  • the peripheral circuit 20 may be located between two rows of parallel banks, or may be located in the peripheral area of all banks.
  • the peripheral circuit may include a signal generator 21, a command controller 22, a delay locked loop (Delay Lock Loop, DLL) 23, a clock/address/command buffer unit 24, and a serial/parallel data receiving/transmitting bus 25, etc.
  • DLL delay locked loop
  • each bank can include multiple storage blocks, and the storage blocks here can be memory array tiles (Memory Array Tile, MAT).
  • Each MAT can include multiple parallel word lines WL extending in the same direction. These word lines are local word lines (LWL, Local WordLine). The word lines corresponding to multiple MATs in the same row can also be connected to the global word line. Line (GWL, Global WordLine) connection, not shown in the figure.
  • a word line WL can connect the selection transistors of multiple memory cells in the MAT where it is located in its extension direction, thereby turning multiple selection transistors on or off through corresponding signals to complete operations such as writing and reading data. .
  • each MAT can be controlled by an independent SA and sub-word line driver circuit (Sub WordLine Driver, SWD). It can be understood that the SWD is used to drive the sub-word line, that is, the above-mentioned local word line.
  • SWD Sub WordLine Driver
  • the SA needs to be connected to the bit line and the reference bit line, in the embodiment of the present disclosure, the bit lines at corresponding positions of adjacent MATs can be connected to the same SA.
  • the memory 100 includes:
  • control circuit layer 120 located in the substrate; the control circuit layer 120 includes at least part of the control circuit of the memory 100;
  • the memory 100 involved in the embodiment of the present disclosure may be any type of memory mentioned above.
  • the embodiment of the present disclosure takes DRAM as an example for description.
  • the substrate 110 here may include elemental semiconductor materials, such as silicon (Si), germanium (Ge), etc., or compound semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP). base made of materials.
  • elemental semiconductor materials such as silicon (Si), germanium (Ge), etc.
  • compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP). base made of materials.
  • control circuit layer 120 there is a control circuit layer 120 in the substrate 110, and the control circuit layer 120 may include a circuit structure composed of various devices and wires. At least part of the control circuit of the memory 100 is located in the control circuit layer 120 .
  • the control circuit layer 120 may include SA and SWD connected to the memory cell array 131, and so on.
  • the memory cell array of the above-mentioned memory can be arranged in layers in the memory structure layer 130.
  • the memory structure layer 130 can include at least two layers, and each layer of the memory structure layer 130 is stacked on the control circuit layer 120 in turn.
  • Each memory structure layer 130 at least includes memory cells arranged in an array, and may also include various isolation layers between the memory cells and between upper and lower layers.
  • the memory cell array in the embodiment of the present disclosure may be composed of memory cells having a "1T1C" (one selection transistor T and one storage capacitor C) structure.
  • the selection transistor is used to control the on-off of the signal between the control circuit and the memory cell.
  • the selection transistor needs to be switched to the on state to realize the charge transfer between the storage capacitor and the external connection.
  • the storage capacitor is based on the storage charge to store data. Since the potentials exhibited by the electrodes of the storage capacitor are different when the charges stored are different, the reading and writing of binary data can be realized by switching the storage state of the storage capacitor.
  • the storage capacitor when the storage capacitor is in a charged state, it represents data "1", and when the storage capacitor is in a discharged state (uncharged state), it represents data "0".
  • the storage capacitor By detecting the voltage on the electrodes of the storage capacitor, it can be determined whether its state is a charged state or a discharged state (uncharged state), thereby realizing the reading of data.
  • the peripheral circuits and the memory cell array in the memory 100 are located in the same plane parallel to the substrate surface, and the peripheral circuits are located around the memory cell array in the horizontal direction, which makes the memory 100 in the horizontal direction. It occupies a larger area and has lower integration level. It is understandable that in this case, in order to obtain higher storage density, the size of the memory unit needs to be further reduced, and the manufacturing process is relatively difficult.
  • the height difference between the peripheral circuit and the memory cell array in the vertical direction is large, and the peripheral circuit and the memory cell array are formed in the same process, the height of the conductive plug (Local Interconnect Contact, Licon) in the peripheral circuit is relatively large. High, the contact resistance is large, which will affect the driving current of the transistor, making the performance of the memory 100 poor.
  • the control circuit layer 120 is located in the substrate 110 , and the control circuit layer 120 has at least part of the control circuit of the memory 100 .
  • the control circuit layer 120 includes, but is not limited to, word line driver circuits, sense amplifier circuits, row decoders, column decoders, fuse repair circuits, power supply circuits, data input and output circuits, and the like.
  • the control circuit layer 120 can be used for operations such as encoding and decoding, detecting the memory cell array, and controlling the memory cell array to write and read data.
  • At least two sequentially stacked memory structure layers 130 are located on the control circuit layer 120 , that is, at least two memory structure layers 130 are located on the surface of the control circuit layer 120 away from the substrate 110 , and are stacked along the Z direction.
  • the storage structure layer 130 is used to perform operations such as writing and reading data according to the control signal sent by the control circuit layer 120 .
  • each memory structure layer 130 is stacked on the control circuit layer 120 in a direction perpendicular to the surface of the substrate 110, thereby forming a three-dimensional memory structure, which can reduce the size of the memory unit without further reducing the size of the memory unit.
  • the area occupied by the memory 100 in the horizontal direction is conducive to improving the integration level.
  • each memory structure layer 130 can be formed on the control circuit layer 120 in sequence without being limited by process processes such as conductive plugs, shallow trench isolation (Shallow Trench Isolation, STI), metal silicide, etc., so memory can be saved. 100 manufacturing cost, and ensures that the peripheral circuits and individual transistors in the memory cell array have better performance.
  • the storage structure layer 130 and the control circuit layer 120 are located in a two-layer structure in a vertical direction relative to the substrate 110, and can be interconnected through connecting lines perpendicular to the substrate.
  • the storage cells with the "1T1C" structure are arranged in an array on the control circuit layer. In this way, compared with the method of tiling the storage cell array and setting the control circuit on the periphery of the storage cell array, the structure of the embodiment of the present disclosure can improve the integration of the product and reduce the occupied area.
  • the memory cell array provided by the embodiments of the present disclosure can also be stacked in multiple layers in a direction perpendicular to the substrate, the data storage capacity per unit area can be further increased, reducing costs while improving memory performance.
  • the memory structure layer 130 includes: a plurality of memory blocks 132 arranged in an array; the control circuit layer includes: a plurality of memory blocks 132 connected correspondingly. Control block 121.
  • the storage block 132 may be the MAT involved in the above embodiment, and the control block 121 may include a control circuit corresponding to each storage block 132, such as SA and SWD.
  • the storage block 132 includes:
  • each of the word lines WL connects a plurality of the memory cells arranged at intervals along the first direction; and the first direction is parallel to the surface of the substrate 110 .
  • the first direction here is the above-mentioned X direction
  • the second direction perpendicular to the X direction and parallel to the substrate is the Y direction
  • the Z direction is the direction perpendicular to the substrate surface.
  • FIG. 4 is a schematic diagram of the X-Y plane
  • FIG. 5 is a schematic diagram of the X-Z plane.
  • each storage block 132 can be connected to the control block 121 individually and controlled by the control block 121 individually.
  • the word line and bit line of a storage block 132 can be independent, that is, not connected to the word line and bit line of other storage blocks 132.
  • the control block 121 corresponding to each storage block 132 is connected to each word line and bit line in the storage block 132 individually.
  • FIG. 5 show the positional relationship between each storage block 132 in a storage structure layer 130 and each control block 121 located in the control circuit layer 120. These control blocks 121 control each storage block 132 individually, and the word line WL and the bit line BL in each storage block 132 can be connected by a connection line perpendicular to the substrate direction.
  • FIG. 4 only shows a schematic diagram including one storage structure layer 130 . For ease of understanding, the control block 121 located in the control circuit layer is exposed by the semi-transparent storage block 132 . The actual structure is not a see-through structure.
  • Figure 4 shows a control block 121 that is at least partially located within the projection area of the storage block 132 and corresponds one-to-one with the storage block 132. It also shows that it is located between two storage blocks 132.
  • the two storage blocks 132 can Another common control block 121.
  • various control blocks 121 can be distributed in the control circuit layer according to actual requirements.
  • FIG. 5 only shows the positional relationship between part of the control block 121 and the storage block 132 .
  • FIG. 6 shows the positional relationship of each memory block 132 in the two-layer memory structure layer 130 in the Y-Z plane and each control block 121 in the control circuit layer 120 .
  • the two storage structure layers 130 may have mutually offset and non-overlapping areas, thereby facilitating the upper storage structure layer 130 to be connected to the control circuit layer 120 through connecting lines.
  • connection line 140 for connecting the memory structure layer 130 and the control circuit layer 120 includes a first branch line 141 connected to one end of the selection transistor T.
  • one end of the selection transistor T of each memory cell is connected to the first branch line 141, and the other end is connected to an electrode of the storage capacitor C.
  • the first branch line 141 is connected to the above-mentioned control circuit layer 120, thereby realizing the electrical connection between the memory unit and the control circuit.
  • the first branch line 141 is connected to the selection transistor T of the storage unit, and can provide a data signal to the storage unit when writing data to the storage unit, and sense a voltage signal corresponding to the data stored in the storage unit when reading.
  • the selection transistor T When the selection transistor T is turned on, the voltage signal on the first branch line 141 can be transmitted to the storage capacitor C, thereby charging the storage capacitor C and further writing data.
  • the same first branch line 141 is connected to a common end of two selection transistors T located in the memory cell array 131 of the same layer.
  • the above memory cells can be distributed in pairs, and the selection transistors of each two memory cells are connected to the same first branch line 141 .
  • the first branch line 141 can synchronously provide signal connections to two memory units located on the same layer.
  • This design can further improve the integration of the memory and enable flexible charging and discharging operations.
  • two memory cells in the memory cell array on the same layer connected by the first branch line 141 are symmetrically distributed relative to the first branch line 141 .
  • the first branch line 141 can be respectively connected to one end of the two selection transistors at the same node.
  • the structure is simple and the occupied area is saved.
  • the two storage units here may be centrally symmetrically distributed with the connection point where the first branch line 141 is located as the center, or they may be axially symmetrically distributed with the branch line where the connection point is located as the axis.
  • other distribution locations can also be designed according to specific needs.
  • the memory 100 further includes:
  • the bit line structure layer 150 is located between the control circuit layer 120 and at least two of the storage structure layers 130; the bit line structure layer 150 includes a plurality of bit lines BL extending along a second direction (only one bit line can be seen in the cross section shown in FIG. 8 ); the second direction is at an angle to the first direction, and the second direction is parallel to the surface of the substrate 110;
  • Each bit line BL connects multiple groups of memory cells spaced apart along the second direction, wherein each group of memory cells is a stack of multiple memory cells connected in a direction perpendicular to the substrate surface through a first branch line 141 . storage unit.
  • Figure 8 is a schematic cross-sectional view in the Y-Z direction.
  • memory cells located in different memory structure layers 130 can be connected to the same bit line. That is to say, the same bit line can control the same straight line in the Z direction located in multiple memory structure layers 130 . storage unit.
  • the bit line BL extending along the second direction in the bit line structure layer 150 is connected to the storage structure layer 130 and the control circuit layer 120 through a branch line perpendicular to the substrate direction.
  • each bit line BL in the bit line structure layer 150 can be connected to the memory cells in the multi-layer memory structure layer 130 , that is, the multi-layer memory structure layer 130 shares the bit line BL in the same bit line structure layer 150 .
  • connection line 140 in the second direction parallel to the substrate 110 , that is, the Y direction, multiple first branch lines 141 located on the same straight line are connected to the same bit line BL; the connection line 140 also includes The second branch line 142 connects the bit line BL and the control circuit layer 120 .
  • first branch lines 141 running through the memory structure layer 130 may be connected to the same bit line BL.
  • the same bit line BL can provide electrical connection to multiple groups of memory cells arranged in a second direction parallel to the substrate.
  • each group of memory cells is a plurality of memory cells connected to the same first branch line 141 .
  • the memory cells in the embodiment of the present disclosure are arranged in a three-dimensional structural array on the substrate 110 and the control circuit layer 120 . That is, the memory cells connected to the bit line BL include a plurality of memory cells on one surface.
  • each memory cell can be individually controlled by individually selecting the selection transistor T of each memory cell.
  • the control circuit layer 120 may include circuits and devices that are connected to the bit line BL and perform read and write operations on each memory cell through the bit line BL. Since the bit line BL extends along the second direction parallel to the substrate surface, a second branch line 142 perpendicular to the substrate is also required to be connected between the bit line BL and the control circuit layer 120.
  • control block 121 includes: a first control block connected to the bit line structure layer 150, such as SA in Figure 8, at least part of the first control block is located along Between the projection areas of two adjacent memory blocks 132 in the extension direction of the bit line BL.
  • control block 121 also includes: a second control block connected to the word line, such as SWD in Figure 9, at least part of the second control block is located where the connected word line is located.
  • the second control block may be SWD.
  • SWD is a sub-word line driver circuit, which can be used to drive the local word line WL of each memory block, that is, to provide a strobe signal for each memory cell.
  • the sub-word line in SWD is a concept for the local word line of the memory block, that is, the above-mentioned word line WL.
  • one SWD can decode the address command through the decoder, connect to a corresponding word line WL, and be used to turn on the selection transistor T of each memory cell connected to the word line WL.
  • the target memory unit For the memory unit to be read and written, that is, the target memory unit, only the drive signal needs to be provided through the SWD corresponding to the target memory unit, and the multiple word lines WL connected to the target memory unit are connected through the word line WL connected thereto. storage unit. At the same time, corresponding data signals are provided to the bit lines connected to the target memory unit, thereby achieving the purpose of independent read and write operations on the target memory unit.
  • corresponding memory blocks in different memory structure layers in a direction perpendicular to the substrate surface are aligned along the second direction.
  • two adjacent storage blocks along the second direction in the same storage structure layer share one first control block.
  • the bit lines BL at adjacent positions in the two adjacent memory blocks 132 are connected to the same SA.
  • two adjacent storage blocks 132 extending along the second direction in the same storage structure layer 130 may be connected to the same SA.
  • two adjacent memory blocks in different memory structure layers 130 can also be connected to the same SA, that is, one SA can connect the memory cells in the four memory blocks 132 through bit lines.
  • the bit line BL of the other memory block 132 serves as the reference bit line
  • the bit line BL of the memory block 132 in the working state is The bit line serves as the target bit line for SA.
  • the two storage blocks can be alternately performed for reading and writing operations, improving the usage efficiency of SA and reducing the area occupied by SA.
  • two adjacent memory blocks 132 in different memory structure layers 130 can also be connected to the same SA and reference each other.
  • the bit lines of the two memory blocks 132 cannot be shared, but two Group bit lines and serve as target bit lines and reference bit lines respectively during operation.
  • the gates G of multiple selection transistors T located on the same straight line in the second direction are connected to the same word line. WL on.
  • the second direction here is a direction perpendicular to the first direction or having a certain angle, that is, the extension directions of the word line WL and the bit line BL intersect each other.
  • Multiple selection transistors T located in the second direction are controlled by the same word line WL, so that each word line WL and bit line BL can uniquely determine a selection transistor T, thereby realizing individual control of each memory cell.
  • connection line 140 may also include a third connection line 143 connected to the control circuit layer 120 ; the word line WL is connected to the third connection line 143 .
  • Each word line WL may be connected to one or more third connection lines 143 .
  • control circuit layer 120 may include a connection terminal for connecting to the third connection line 143, and may also include a control circuit or a driving circuit for providing a control signal for the word line WL.
  • word line WL is located in a plane parallel to the surface of substrate 110 in which the gate G of select transistor T is located.
  • the word line WL Since the word line WL is used to provide a control signal to the gate G of the selection transistor T, the word line needs to be connected to the gate G of the selection transistor T.
  • connected metal lines can be used directly as the gates G of multiple selection transistors T, so the position of the word line WL is located in the plane where the gates G of the selection transistors T are located. That is to say, the word line WL runs through each layer of the memory structure 130 .
  • the storage structure layer 130 includes: an upper structure layer 130a and a lower structure layer 130b;
  • the storage block in the upper structural layer 130a is the first storage block 132a; the storage block in the lower structural layer 130b is the second storage block 132b;
  • first spacing area between adjacent first memory blocks 132a extending along the first direction in the upper structural layer 130a;
  • the projections of the first spacing area and the second spacing area on the control circuit layer do not overlap.
  • first spacing area 161 between the word lines WL in adjacent first memory blocks 132a extending along the first direction in the upper structural layer 130a, and the word lines WL extending along the first direction in the lower structural layer 130a
  • second spacing area 162 between the word lines WL in adjacent second memory blocks 132b. At least part of the word line WL of each first memory block 132a in the upper structural layer 130a may be projected in the second spacing area 162 of the lower structural layer 130b. That is to say, at least part of the word line WL in the upper structural layer 130a may be projected from the second spacing area 162 of the lower structural layer 130b.
  • the two spacing areas 162 are exposed, so that they can be connected to the control circuit layer 120 through vertical connection lines.
  • the first storage block is connected to a second control block corresponding to the first storage block, such as SWD, through a connection line that runs through the second spacing area 162;
  • the second storage block is connected to the second control block corresponding to the second storage block, such as SWD, through a connection line located below the second storage block.
  • the second control blocks corresponding to the first storage block and the second control blocks corresponding to the second storage block are arranged at intervals along the first direction, as shown in FIG. 9 .
  • the length of the connection line of the first storage block is greater than the length of the connection line of the second storage block
  • the driving capability of the second control block connected to the first storage block is greater than the driving capability of the second control block connected to the second storage block.
  • the third connection line 143 connected to each word line WL of the upper structural layer 130a is connected to the control circuit layer 120 through the second spacing area 162 between each word line WL of the lower structural layer 130b.
  • each word line in each memory block 132 may be connected to at least one third connection line 143 and connected to the control circuit layer 120 through the third connection line 143 .
  • the lower structural layer since the lower structural layer is not blocked, it can be directly connected to the control circuit layer 120 through the third connection line 143 . Therefore, the driving circuit in the control circuit layer 120 can control each word line individually.
  • the openings in the word lines at the overlapping positions in the upper structure layer 130a and the lower structure layer 130b may be staggered, that is, the first spacing region 161 and the second spacing region 162 are staggered with each other, as shown in FIG9 .
  • the third connection lines 143 connected to each word line WL in the upper structure layer 130a may extend vertically downward, and extend to the control circuit layer 120 through the opening 160 in the lower structure layer 130b.
  • Each word line WL in the lower structure layer 130b may directly extend vertically downward to the control circuit layer 120.
  • the third connection lines 143 connected to each word line WL in the upper and lower storage structure layers 130 do not affect each other, and may be distributed according to a certain rule (depending on the position of the word line and the opening), thereby having a stable and uniform structure.
  • control circuit layer 120 also includes: a global control circuit 123; the global control circuit 123 is connected to a plurality of the control blocks 121; the global control circuit is at least used to Control signals are provided to a plurality of said control blocks.
  • the above-mentioned global control circuit 123 may include: a global word line, connected to multiple second control blocks, and used to provide control signals of multiple word lines in the memory blocks connected to multiple second control blocks.
  • the area where the global control circuit 123 is located is located outside the projection area of any memory block 132 on the control circuit layer 120 .
  • the global control circuit 123 may be located in a peripheral area of the control circuit layer 120 , that is, outside the projection area of the memory structure layer 130 .
  • the global control circuit 123 may connect multiple control blocks 121 to provide control signals to the multiple control blocks 121 .
  • the global control circuit 123 may also be located between some control blocks 121 , for example, in a gap between two control blocks 121 among multiple parallel control blocks 121 .
  • the multiple control blocks 121 connected to the global control circuit 123 can be controlled in time-sharing or synchronously, depending on the functions and connection relationships between the global control circuit and the corresponding control blocks 121, which are not limited here.
  • the memory further includes:
  • a power module connected to a plurality of first control blocks and/or a plurality of second control blocks, and configured to provide power signals;
  • the power module is located in the substrate, and the power module and the control circuit layer are located in the same structural layer.
  • the power module can generate different voltages to meet the needs of each device in the memory during write, read and other operations.
  • the power module and the control circuit layer are located at substantially the same depth in the substrate to optimize the device and circuit layout of the memory.
  • the memory further includes:
  • a data input/output (I/O) module is connected to the first control block, and the data input/output module is configured to write or read data to the storage unit through the first control block.
  • Data input and output modules can be configured to exchange data with components other than memory.
  • the data input and output module can be connected to SA, and perform operations such as reading and writing data on the memory cell through SA and the bit lines connected to SA.
  • the power module and data input and output module can also be disposed in the peripheral area of the substrate and connected to multiple first control blocks or second control blocks.
  • an embodiment of the present disclosure provides a method for manufacturing a memory, including:
  • Step S101 Provide a substrate
  • Step S102 Form a control circuit layer on the substrate; wherein the control circuit layer includes at least part of the control circuit of the memory;
  • Step S103 Form at least two stacked memory structure layers on the control circuit layer; the memory structure layer includes: a memory cell array, and the memory structure layer and the control circuit are connected through connection lines perpendicular to the direction of the substrate.
  • a control circuit layer is formed on the substrate.
  • the control circuit layer may be at least partially located in the substrate.
  • the control circuit layer may be formed on the substrate by Regionalized doping, etching and other processes are performed to form the semiconductor device structure.
  • the control circuit layer may also include at least partially located on the substrate, for example, metal wiring covering the surface of the substrate.
  • control circuit layer contains at least part of the memory control circuit, and therefore may contain a large number of circuit traces and devices connected thereto.
  • the control circuit layer can also be covered with an isolation layer made of dielectric material, and then a storage structure layer is formed on the isolation layer. There is an electrical connection between the storage structure layer and the control circuit layer, so the two can be connected through wires penetrating the isolation layer. That is to say, before forming the storage structure layer, through holes can also be formed on the isolation layer and filled with conductive material.
  • a memory structure layer can be stacked on it.
  • Some contact nodes in the storage structure layer can be connected to the above-mentioned through holes through conductive materials, and then connected to the control circuit layer.
  • a multi-layer storage structure layer stacked vertically and a control circuit layer located below the storage structure layer can be formed, which effectively saves space and improves the integration of the memory.
  • an embodiment of the present disclosure also provides a storage system 200, including the memory 100 involved in any of the above embodiments and a storage controller 300 connected to the memory 100.
  • the memory system 200 can be any kind of memory chip.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be electrical, mechanical, or other forms. of.
  • the units described above as separate components may or may not be physically separated; the components shown as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure can be all integrated into one processing unit, or each unit can be separately used as a unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the control circuit of the memory is disposed in the control circuit layer between the stacked storage structure layer and the substrate, and the storage structure layer and the control circuit layer are connected through a direction perpendicular to the substrate. line to connect.
  • the memory provided by the embodiments of the present disclosure can have a higher integration level and a smaller area, and the vertically stacked structure is more convenient for manufacturing and circuit wiring design.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

Les modes de réalisation de la présente invention concernent une mémoire et un système de stockage. La mémoire comprend : un substrat ; une couche de circuit de commande située dans le substrat, la couche de circuit de commande comprenant au moins une partie d'un circuit de commande de la mémoire ; et au moins deux couches de structure de stockage, les au moins deux couches de structure de stockage étant empilées successivement sur la couche de circuit de commande, et la couche de structure de stockage étant électriquement connectée à la couche de circuit de commande.
PCT/CN2022/130651 2022-09-19 2022-11-08 Mémoire et système de stockage Ceased WO2024060370A1 (fr)

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CN202211139446.3 2022-09-19
CN202211139446.3A CN117766003A (zh) 2022-09-19 2022-09-19 存储器及存储系统

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010022369A1 (en) * 1997-12-19 2001-09-20 Takuya Fukuda Semiconductor integrated circuit device
CN109755251A (zh) * 2017-11-06 2019-05-14 三星电子株式会社 含衬底控制电路的垂直存储器器件和包含其的存储器系统
CN110291641A (zh) * 2017-02-16 2019-09-27 美光科技公司 存储器裸片区域的高效利用
CN112740403A (zh) * 2020-12-24 2021-04-30 长江存储科技有限责任公司 三维存储器器件的接触焊盘及其制造方法
CN114121968A (zh) * 2020-08-25 2022-03-01 三星电子株式会社 三维半导体存储器装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010022369A1 (en) * 1997-12-19 2001-09-20 Takuya Fukuda Semiconductor integrated circuit device
CN110291641A (zh) * 2017-02-16 2019-09-27 美光科技公司 存储器裸片区域的高效利用
CN109755251A (zh) * 2017-11-06 2019-05-14 三星电子株式会社 含衬底控制电路的垂直存储器器件和包含其的存储器系统
CN114121968A (zh) * 2020-08-25 2022-03-01 三星电子株式会社 三维半导体存储器装置
CN112740403A (zh) * 2020-12-24 2021-04-30 长江存储科技有限责任公司 三维存储器器件的接触焊盘及其制造方法

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