WO2024060059A1

WO2024060059A1 - Memory device and controlling method thereof

Info

Publication number: WO2024060059A1
Application number: PCT/CN2022/120182
Authority: WO
Inventors: Li Xu; Zuqi DONG; Jianping Li
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2024-03-28
Anticipated expiration: 2025-03-21
Also published as: CN118057964A

Abstract

A memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of memory cells include a selected memory cell connected between a selected bit line and a word line, and an unselected memory cell connected between an unselected bit line and the word line. The charge control circuit is configured to provide a precharge voltage to the unselected bit line, and the precharge voltage is between -3 volts and -5 volts.

Description

MEMORY DEVICE AND CONTROLLING METHOD THEREOF

BACKGROUND

The present disclosure relates to memory device and control method of the memory device.

The read operation of a memory cell may require multiple steps or operations to precharge sharing, charge sharing, or discharge respective bit lines before applying a read voltage via a word line to read out the result. Due to the varieties of materials of the phase-change memory (PCM) , the accuracy of the read operation may become challenging.

SUMMARY

In one aspect, a memory device is disclosed. The memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of memory cells include a selected memory cell connected between a selected bit line and a word line, and an unselected memory cell connected between an unselected bit line and the word line. The charge control circuit is configured to provide a precharge voltage to the unselected bit line, and the precharge voltage is between -3 volts and -5 volts.

In some implementations, the charge control circuit is configured to provide a first voltage to the selected bit line and the unselected bit line and control precharging the unselected bit line to the precharge voltage, charge-sharing the unselected bit line with the selected bit line to reach a reference voltage, and discharging the selected bit line to a second voltage.

In some implementations, the first voltage is 0 volt. In some implementations, the reference voltage is between -1.5 volts and -2.5 volts. In some implementations, the second voltage is between -2 volts and -4 volts.

In some implementations, the charge control circuit further includes a voltage comparator coupled to the memory cell array and configured to compare the reference voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

In some implementations, the voltage comparator is configured to determine that the selected memory cell is in a set state when the selected bit line voltage of the selected bit line is higher than the reference voltage of the unselected bit line, and determine the selected memory cell is in a reset state when the selected bit line voltage of the selected bit line is lower than the reference voltage of the unselected bit line.

In some implementations, the charge control circuit further includes a first local control gate coupled to the unselected bit line and configured to control precharging the unselected bit line to the precharge voltage, a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge-sharing the unselected bit line with the selected bit line to reach the reference voltage, and a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.

In some implementations, each memory cell includes a phase-change memory (PCM) cell. In some implementations, the PCM cell includes a PCM element and a selector in series with the PCM element.

In another aspect, a system is disclosed. The system includes a memory device and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of memory cells include a selected memory cell connected between a selected bit line and a word line, and an unselected memory cell connected between an unselected bit line and the word line. The charge control circuit is configured to provide a precharge voltage to the unselected bit line, and the precharge voltage is between -3 volts and -5 volts.

In still another aspect, a method for operating a memory device is disclosed. The memory device includes a selected memory cell connected between a selected bit line and a word line and an unselected memory cell connected between an unselected bit line and the word line. The method includes setting the selected bit line and the unselected bit line to a first voltage, precharging the unselected bit line to a precharge voltage, wherein the precharge voltage is between -3 volts and -5 volts, charge-sharing the unselected bit line with the selected bit line to reach a reference voltage, discharging the selected bit line to a second voltage, and applying a read voltage via the word line to obtain a read result.

In some implementations, the unselected bit line is electrically connected with the selected bit line to reach a same voltage level.

In some implementations, the unselected bit line and the selected bit line are disconnected, and the second voltage is provided to the selected bit line. In some implementations, the unselected bit line maintained at the reference voltage.

In some implementations, a voltage on the selected bit line is pulled up above the reference voltage, or the voltage on the selected bit line maintained at the second voltage.

In some implementations, the voltage on the selected bit line is compared with the reference voltage, and a comparison result is outputted as the read result.

In some implementations, when a voltage on the selected bit line is higher than the reference voltage, the selected memory cell is determined in a set state; and when the voltage on the selected bit line is lower than the reference voltage, the selected memory cell is determined in a reset state.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a block diagram of an exemplary system having a memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuits, according to some aspects of the present disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell, according to some aspects of the present disclosure.

FIG. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.

FIG. 5 illustrates a block diagram of an exemplary memory device including a charge control circuit, according to some aspects of the present disclosure.

FIGs. 6A-6B illustrate time sequences of a read operation of an exemplary memory device, according to some aspects of the present disclosure.

FIG. 7 illustrates a flowchart of an exemplary method of operating a memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. In addition, the term “couple” , “coupled to” , or “coupled between” may be understood as not necessarily intended to be “physically joined or attached, ” i.e., direct attachment, but can also be interpreted by indirect connection through an intermediate component.

Phase-change memory (PCM) cells are non-volatile memory devices that store data using a phase-change material. PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials, e.g., chalcogenide alloys, based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. A “set” state is a low resistance state of the PCM cell that can be obtained by creating crystalline regions in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient duration. A “reset” state, on the contrary, is a high resistance state of the PCM cell that can be obtained by creating amorphous regions in the chalcogenide material. Amorphous can be created when the chalcogenide material is heated above its melting temperature and then quickly quenched to create a formation of amorphous. The “set” state can be referred to as an “on” state, while the “reset” state can be referred to as an “off” state.

The read operation of a memory cell may require multiple steps or operations to precharge sharing, charge sharing, or discharge respective bit lines before applying a read voltage via a word line to read out the result. Specifically, to obtain a result of determining whether the memory cell is in a “set” ( “1” ) state or “reset” ( “0” ) state, a charge sharing process is required to bring the selected bit line and the unselected bit line to the same voltage level as a reference voltage before a read voltage is applied to the memory cells via a word line. The charge sharing process may include several precharge sharing, charge sharing, and discharge steps, which are controlled by applying several controlling signals to turn on and off several control gates and to apply the specific charging or discharging voltage bias into the bit lines.

Then, the selected bit line is set to a floating state, and a read voltage is applied to the word line. When the selector of the PCM cell is open, the floated bit line is charged by the word line. When the voltage difference between the word line and the bit line is higher than the reference voltage, the PCM cell is read as “1” , and when the voltage difference between the word line and the bit line is lower than the reference voltage, the PCM cell is read as “0” . However, in some implementations, because of the varieties of the PCM cell, the read voltage provided by the word line may be insufficient to charge the bit line to a voltage level higher than the reference voltage, and an error read result of the PCM cell may occur.

To address one or more of the aforementioned issues, the present disclosure provides a low precharge voltage to the unselected bit line during the precharging operation, and therefore the reference voltage of the PCM cell in the read operation may be changed to improve the accuracy of the read operation.

FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in FIG. 1, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) . In some implementations, host 108 can be configured to send or receive data to or from memory devices 104. In some implementations, the host can be a user logic, or a user interface such that the user may give instructions to the host and transmit the instructions to the memory devices or the memory array.

Memory device 104 can be any memory device disclosed in the present disclosure. As disclosed below in detail, memory device 104, such as phase-change random access memory (PCRAM) , dynamic random access memory (DRAM) , or NAND Flash memory device, can include a clock input, a command bus, a data bus, a control logic, an address register, a row decoder/word line driver, a memory cell array having memory cells, a voltage generator, a page buffer/sense amplifier, a column decoder/bit line driver, a data input/output (I/O) , according to some implementations.

Memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104, according to some implementations. Memory controller 106 can manage the data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed for operating in a high duty-cycle environment solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and write operations. Memory controller 106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 104 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 104. Any other suitable functions may be performed by memory controller 106 as well, for example, formatting memory device 104. Memory controller 106 can communicate with an external device (e.g., host 108) according to a particular communication protocol. For example, memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc. Furthermore, memory controller 106 can also be configured to control operations of memory device 104 to perform methods in accordance with some implementations of the present disclosure. For instance, in some implementations, memory controller 106 can determine whether the read voltage is higher or lower than a threshold voltage of the selected memory cell. In some implementations, memory controller 106 can determine a state of the selected memory cell is a “set” state in response to the read voltage being higher than the threshold voltage of the selected memory cell, or a state of the selected memory cell is a “reset” state in response to the read voltage is lower than the threshold voltage of the selected memory cell. It is noted that one or more of these operations of memory device 104 may also be performed partially or fully by control logic in accordance with some implementations of the present disclosure.

FIG. 2 illustrates a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits, according to some aspects of the present disclosure. Memory device 200 can be an example of memory device 104 in FIG. 1. Memory device 200 can include a memory cell array 201 and peripheral circuits 202 coupled to memory cell array 201. Memory cell array 201 can include word lines (e.g., a selected word line 214) , bit lines (e.g., a selected bit line 216 and an unselected bit line 218) , and memory cells (e.g., a selected memory cell 208 and an unselected memory cell 210) formed between word lines and bit lines. In some implementations, each memory cell (e.g., selected memory cell 208 and unselected memory cell 210) can include a PCM element (not shown) in series with a selector (not shown) . In some implementations, the memory cell (e.g., 208 or 210) can also be a DRAM cell which includes a paired transistor and capacitor. To read a selected memory cell (e.g., selected memory cell 208) , a selected word line voltage (e.g., a selected word line voltage Vwl ₁) can be applied to a selected word line (e.g., selected word line 214) , and a selected bit line voltage (e.g., a selected bit line voltage Vbl1) can be applied to a selected bit line (e.g., selected bit line 216) . The other unselected word lines will stay at an unselected word line voltage (e.g., Vwl ₀) , and the other unselected bit lines will stay at an unselected bit line voltage (e.g., Vbl0) . In some implementations, the unselected bit line voltage (e.g., Vbl0) of the unselected bit line (e.g., unselected bit line 218) is configured to be set to a reference voltage by a series of voltages during precharge sharing, charge sharing, and discharge processes before the selected word line voltage (e.g., selected word line voltage Vwl ₁) being applied to the selected word line (e.g., selected word line 214) . In some implementations, the selected bit line voltage (e.g., Vbl1) of the selected bit line (e.g., selected bit line 216) is configured to be set to a series of voltages during precharge sharing, charge sharing, and discharge processes before the selected word line voltage (e.g., selected word line voltage Vwl ₁) being applied to the selected word line (e.g., selected word line 214) . These precharge sharing, charge sharing, and discharge processes will be discussed later.

FIG. 3 illustrates a side view of a cross-section of a memory device 300 having a PCM element in series with a selector. Memory device 300 includes one or more parallel bit lines 304 (i.e., corresponding to bit line 216 in FIG. 2) above a substrate 302 and one or more parallel word lines 316 (i.e., corresponding to word line 214 in FIG. 2) above bit lines 304. Memory device 300 also includes one or more PCM cells 301 (i.e., corresponding to memory cell 208 in FIG. 2) each disposed at an intersection of a respective pair of bit line 304 and word line 316. Adjacent PCM cells 301 are separated by an insulating structure 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above selector 308. Each PCM cell 301 further includes three

electrodes

306, 310, and 314 vertically between a respective bit line 304, selector 308, PCM element 312, and a respective word line 316, respectively.

It is noted that PCM element 312 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change element can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.

Selector 308 may include an ovonic threshold switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (Va) is higher than the threshold voltage is applied (Vth) . At lower voltage (|Va| < Vth) , the high resistance of the OTS selector in its off-state keeps the off-state current (Ioff) low. At higher voltage (|Va| > Vth) , the OTS selector undergoes the OTS phenomenon and switches to the on-state with low resistance; thus, the current through the OTS selector in the on-state (Ion) increases. The volatile on-state is maintained as long as high voltage is supplied.

FIG. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in FIG. 1) including a memory cell array 401 (e.g., corresponding to 201 in FIG. 2) , and peripheral circuits, according to some aspects of the present disclosure. In some implementations, a memory cell of memory cell array 401 includes PCM cell 301.

As shown in FIG. 4, page buffer/sense amplifier 404 can be coupled to memory cell array 401 and configured to read and program (write) data from and to memory cell array 401 according to the control signals from control logic 412. In one example, page buffer/sense amplifier 404 may store one page of program data (write data) to be programmed into one page of memory cell array 201 (e.g., in FIG. 2) . In another example, page buffer/sense amplifier 404 may perform program verify operations to ensure that the data has been properly programmed into memory cells 208 coupled to selected word line 214. In still another example, page buffer/sense amplifier 404 may also sense the low power signals from selected bit line 216 that represents a data bit stored in memory cells 208 and amplify the small voltage swing to recognizable logic levels in a read operation.

Column decoder/bit line driver can be coupled to memory cell array 401 and control logic 412 and configured to be controlled by control logic 412 and select one or more memory cells (e.g., selected memory cell 208) and bit lines (e.g., selected bit line 216) . Column decoder/bit line driver 406 can be further configured to drive selected bit line 216. Column decoder/bit line driver 406 can be further configured to drive selected bit lines 216 using bit line voltages generated from voltage generator 410.

Data I/O 416 can be coupled to page buffer/sense amplifier 404 and/or column decoder/bit line driver 406 and configured to direct (route) the data input from data bus 423 to the selected memory cells 208 of memory cell array 201, as well as the data output from the selected memory cells to data bus 423.

Row decoder/word line driver 408 can be coupled to control logic 412 and memory cell array 401 and configured to be controlled by control logic 412 and select one or more memory cells (e.g., selected memory cell 208) of memory cell array 201 and a selected word line (e.g., selected word line 214) . Row decoder/word line driver 408 can be further configured to drive selected word line 214. Row decoder/word line driver 408 can be further configured to drive selected word line 214 using word line voltages generated from voltage generator 410.

Voltage generator 410 can be coupled to control logic 412 and configured to be controlled by control logic 412 according to the control signals from control logic 412 and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc. ) , bit line voltages, and source line voltages to be supplied to memory cell array 401.

Control logic 412 can be coupled to each peripheral circuit described above and configured to control the operations of each peripheral circuit. Control logic 412 is configured to receive a clock signal, a command signal, an address signal, and a data signal from a host (e.g., 108 in FIG, 1) . The command signal is received via a command bus 421. The data signal is received via a data bus 423. In some implementations, control logic 412 can be implemented by microprocessors, microcontrollers (a. k. a. microcontroller units (MCUs) ) , digital signal processors (DSPs) , application-specific integrated circuits (ASICs) , field-programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described. In some implementations, control logic 412 is coupled to word line driver 408 and configured to direct the read voltage into the selected memory cell via word line driver 408.

Address registers 414 can be coupled to control logic 412 or included in control logic 412. Address registers 414 can include state registers, command registers, and address registers for storing state information, command operation codes (OP codes) , and command addresses for controlling the operations of each peripheral circuit.

FIG. 5 illustrates a block diagram of a memory device (e.g., corresponding to 400 in FIG. 4) including a charge control circuit 500, according to some aspects of the present disclosure. As shown in FIG. 4, once control logic 412 determines that a command signal is a read command, it triggers a read operation. The read operation includes a series of precharge sharing, charge sharing, and discharge processes before the read voltage is applied to the selected word line. These precharge sharing, charge sharing, and discharge processes are performed by charge control circuit 500 in accordance with some implementations of the present disclosure. Charge control circuit 500 may include a voltage comparator 501 (e.g., corresponding to or included in page buffer/sense amplifier 404) coupled to the memory cell array (e.g., corresponding memory cell array 201 or 401) , an unselected bit line 511 (e.g., corresponding to unselected bit line 218) connected to a first input terminal 503 of voltage comparator 501, and a selected bit line 513 (e.g., corresponding to selected bit line 216) connected to s second input terminal 505 of voltage comparator 501. In some implementations, voltage comparator 501 is configured to determine if the selected bit line voltage Vbl1 of selected bit line 513 (e.g., selected bit line 216) is higher than the reference voltage held by unselected bit line 511 (e.g., corresponding to unselected bit line 218) , the selected memory cell (e.g., selected memory cell 208) is in a “set” state, and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a “reset” state.

In some implementations, at the beginning of the read operation, selected bit line 513 and unselected bit line may be initially set to a first voltage. In some implementations, the first voltage may be a ground voltage. In some implementations, the first voltage may be 0 volt.

A first local control gate 521 is coupled to unselected bit line 511 (e.g., corresponding to unselected bit line 218) and configured to control whether unselected bit line 511 is precharged to a precharge voltage (e.g., a negative voltage Vn1) during the precharge sharing process. In some implementations, the negative voltage Vn1 may be between -3 volts and -5 volts. In some implementations, the negative voltage Vn1 may be -3.6 volts. In some implementations, the negative voltage Vn1 may be -4 volts. In some implementations, the negative voltage Vn1 may be -4.5 volts. In some implementations, the negative voltage Vn1 may be -5 volts.

A second local control gate 523 is coupled between selected bit line 513 and unselected bit line 511 and configured to control whether selected bit line 513 and unselected bit line 511 are brought to the same voltage level (e.g., 1/2 of the negative voltage Vn1) during the charge sharing process. The voltage level (e.g., 1/2 of the negative voltage Vn1) after the charge sharing process can be a reference voltage, which can be used to determine whether the selected memory cell is in a “set” state or a “reset” state by comparing the selected bit line voltage Vbl1 with the reference voltage held by unselected bit line 511. For example, if the selected memory cell is in a “set” state, after applying a read voltage across the selected word line, the selected bit line voltage will be pulled up over the reference voltage. On the contrary, if the selected memory cell is in a “reset” state, after applying a read voltage across the selected word line, the selected bit line voltage will remain below the reference voltage. In some implementations, the reference voltage can be between -1.5 V and -2.5 volts. In some implementations, the reference voltage may be -1.8 volts. In some implementations, the reference voltage may be -2 volts. In some implementations, the reference voltage may be -2.25 volts. In some implementations, the reference voltage may be -2.5 volts.

A third local control gate 525 is coupled to selected bit line 513 and configured to control whether selected bit line 513 is discharged to a second voltage (e.g., a negative voltage Vn2) during the discharge process. In some implementations, the negative voltage Vn2 can be -2 volts to -4 volts, e.g., -2.5 volts. It is noted that the charge control circuit 500 in accordance with some implementations of the present disclosure is only an example of achieving the desired function or mechanism; any other control logic gate combinations to achieve the same or similar function are possible in light of the above teaching.

FIGs. 6A-6B illustrate time sequences of a read operation of an exemplary memory device, according to some aspects of the present disclosure. Specifically, FIG. 6A illustrates a “set” state read out sequence, and FIG. 6B illustrates a “reset” state read out sequence. FIG. 7 illustrates a flowchart of an exemplary method 700 of operating a memory device, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the time sequences in FIGs. 6A-6B and method 700 in FIG. 7 will be discussed together. It is understood that the operations shown in method 700 are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIGs. 6A-6B and FIG. 7.

As shown in FIG. 6A and operation 702 in FIG. 7, step 1 is an initial state in which the current (Icell) over the memory cell (e.g., selected memory cell 208) is 0 mA when the word line voltage (Vwl) has not been provided to the memory cell, and selected bit line voltage (Vbl0) and unselected bit line voltage (Vbl0) are both set at the first voltage, e.g., ground voltage or 0 volt. A selected bit line (e.g., 216 in FIG. 2) and an unselected bit line (e.g., 218 in FIG. 2) are chosen and set to the initial state. In some implementations, the first voltage of the initial state may be a ground voltage or at 0 volt.

As shown in FIG. 6A and operation 704 in FIG. 7, step 2 is a precharge sharing process in which the unselected bit line (e.g., unselected bit line 218) is precharged to the precharge voltage Vn1. During the precharge sharing process, a first local control gate (e.g., 521 in FIG. 5) is set to “on” state to precharge the unselected bit line to a precharge voltage (e.g., the negative voltage Vn1) . The precharge sharing process is used to pull one of the bit lines to a voltage (e.g., a negative voltage) such that after the following charge sharing process, two bit lines will be brought to the same voltage level (e.g., half of the previous negative voltage) . In some implementations, the precharge voltage, e.g., Vn1, may be between -3 volts and -5 volts. In some implementations, the precharge voltage may be -3.6 volts. In some implementations, the precharge voltage may be -4 volts. In some implementations, the precharge voltage may be -4.5 volts. In some implementations, the precharge voltage may be -5 volts.

As shown in FIG. 6A and operation 706 in FIG. 7, step 3 is a charge sharing process in which the selected bit line and the unselected bit line are electrically connected such that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage. During the charge sharing process, the first local control gate is set to “off” state to discontinue precharging the unselected bit line, and a second local control gate (e.g., 523 in FIG. 5) is set to “on” state at the same time such that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage. In some implementations, the reference voltage can be between -1.5 V and -2.5 volts. In some implementations, the reference voltage may be -1.8 volts. In some implementations, the reference voltage may be -2 volts. In some implementations, the reference voltage may be -2.25 volts. In some implementations, the reference voltage may be -2.5 volts.

As shown in FIG. 6A and operation 708 in FIG. 7, step 4 is a discharge process in which the selected bit line is discharged to the second voltage Vn2. The second local control gate is set to “off” state to discontinue charge sharing of the selected bit line and the unselected bit line, and a third local control gate (e.g., 525 in FIG. 5) is set to “on” state at the same time to discharge the selected bit line to a second voltage (e.g., a negative voltage Vn2) , and then the third local control gate is set to “off” state to discontinue discharging the selected bit line. In some implementations, the negative voltage Vn2 can be -2 volts to -4 volts, e.g., -2.5 volts. After the third local control gate is set to “off” state, the selected bit line is in a floating state.

As shown in FIG. 6A and operation 710 in FIG. 7, step 5 is a reading process in which a read voltage, e.g., the word line voltage (Vwl) , is provided to the memory cell. Since the memory cell is in the “set” state, the current across the memory cell increases, and the selected bit line voltage is pulled up over the reference voltage held by the unselected bit line. Voltage comparator 501 (corresponding to or included in sense amplifier 404) can thus determine the memory cell is in the “set” state by sensing the flag is changed from 0 (Vbl0 > Vbl1) to 1 (Vbl0 <Vbl1) . After the selected bit line is discharged to the negative voltage and the unselected bit line remains at the reference voltage, the read voltage is applied via a respective word line and gets the read result. If a selected memory cell (e.g., selected memory cell 208 in FIG. 2) on the selected bit line (e.g., selected bit line 216 in FIG. 2) is in “set” state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is higher than the set threshold voltage of the selected memory cell, while the unselected bit line will remain at the reference voltage. A readout data (e.g., a readout voltage or a readout current) of the memory cell in the “set” state can be obtained.

On the contrary, as shown in FIG. 6B, if the memory cell is in the “reset” state, the current across the memory cell remains the same, and the selected bit line voltage is not pulled up over the reference voltage. Voltage comparator 501 (corresponding to or included in sense amplifier 404) can thus determine that the memory cell is in the “reset” state by sensing the flag is not changed from 0 to 1. If the selected memory cell on the selected bit line is in a “reset” state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is lower than the reset threshold voltage of the selected memory cell. A readout data (e.g., a readout voltage or a readout current) of the memory cell in the “reset” state can be obtained.

Step 6 is a recovery process in which both the selected bit line and the unselected bit line are reset to the initial state, which is the ground voltage or 0 volt. After the read result is read out, the selected bit line and the unselected bit line are reset to the initial state during a recovery process, and the read operation is completed.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, wherein the plurality of memory cells comprise:

a selected memory cell connected between a selected bit line and a word line; and

an unselected memory cell connected between an unselected bit line and the word line; and

a charge control circuit coupled to the memory cell array and configured to provide a precharge voltage to the unselected bit line, wherein the precharge voltage is between -3 volts and -5 volts.
The memory device of claim 1, wherein the charge control circuit is configured to provide a first voltage to the selected bit line and the unselected bit line and control precharging the unselected bit line to the precharge voltage, charge-sharing the unselected bit line with the selected bit line to reach a reference voltage, and discharging the selected bit line to a second voltage.
The memory device of claim 2, wherein the first voltage is 0 volt.
The memory device of claim 2, wherein the reference voltage is between -1.5 volts and -2.5 volts.
The memory device of claim 2, wherein the second voltage is between -2 volts and -4 volts.
The memory device of any one of claims 2-5, wherein the charge control circuit further comprises:

a voltage comparator coupled to the memory cell array and configured to compare the reference voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.
The memory device of claim 6, wherein the voltage comparator is configured to determine the selected memory cell is in a set state when the selected bit line voltage of the selected bit line is higher than the reference voltage of the unselected bit line, and determine the selected memory cell is in a reset state when the selected bit line voltage of the selected bit line is lower than the reference voltage of the unselected bit line.
The memory device of any one of claims 2-7, wherein the charge control circuit further comprises:

a first local control gate coupled to the unselected bit line and configured to control precharging the unselected bit line to the precharge voltage;

a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge-sharing the unselected bit line with the selected bit line to reach the reference voltage; and

a third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage.
The memory device of any one of claims 1-8, wherein each memory cell comprises a phase-change memory (PCM) cell.
The memory device of claim 9, wherein the PCM cell comprises a PCM element and a selector in series with the PCM element.
A system, comprising:

a memory device, comprising:

a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, wherein the plurality of memory cells comprise:

a selected memory cell connected between a selected bit line and a word line; and

an unselected memory cell connected between an unselected bit line and the word line; and

a charge control circuit coupled to the memory cell array and configured to provide a precharge voltage to the unselected bit line, wherein the precharge voltage is between -3 volts and -5 volts; and

a memory controller coupled to the memory device and configured to control the memory device.
A method for operating a memory device, the memory device comprising a selected memory cell connected between a selected bit line and a word line and an unselected memory cell connected between an unselected bit line and the word line, the method comprising:

setting the selected bit line and the unselected bit line to a first voltage;

precharging the unselected bit line to a precharge voltage, wherein the precharge voltage is between -3 volts and -5 volts;

charge-sharing the unselected bit line with the selected bit line to reach a reference voltage;

discharging the selected bit line to a second voltage; and

applying a read voltage via the word line to obtain a read result.
The method of claim 12, wherein the first voltage is 0 volt.
The method of any one of claims 12-13, wherein the reference voltage is between -1.5 volts and -2.5 volts.
The method of any one of claims 12-14, wherein the second voltage is between -2 volts and -4 volts.
The method of claim 12, wherein charge-sharing the unselected bit line with the selected bit line to reach the reference voltage, comprises:

electrically connecting the unselected bit line with the selected bit line to reach a same voltage level.
The method of claim 16, wherein discharging the selected bit line to the second voltage, comprising:

disconnecting the unselected bit line and the selected bit line; and

providing the second voltage to the selected bit line.
The method of claim 17, further comprising:

maintaining the unselected bit line at the reference voltage.
The method of claim 12, wherein applying the read voltage via the word line to obtain the read result, comprises:

pulling up a voltage on the selected bit line above the reference voltage; or

maintaining the voltage on the selected bit line at the second voltage.
The method of claim 19, further comprising:

comparing the voltage on the selected bit line with the reference voltage; and

outputting a comparison result as the read result.
The method of claim 12, wherein applying the read voltage via the word line to obtain the read result, comprises:

when a voltage on the selected bit line is higher than the reference voltage, determining the selected memory cell is in a set state; and

when the voltage on the selected bit line is lower than the reference voltage, determining the selected memory cell is in a reset state.