WO2024040514A1

WO2024040514A1 - Nitride-based electronic device

Info

Publication number: WO2024040514A1
Application number: PCT/CN2022/114807
Authority: WO
Inventors: Weipeng Li
Original assignee: Innoscience Shenzhen Semiconductor Co Ltd
Current assignee: Innoscience Shenzhen Semiconductor Co Ltd
Priority date: 2022-08-25
Filing date: 2022-08-25
Publication date: 2024-02-29
Anticipated expiration: 2025-02-25
Also published as: CN116134689A; WO2024040514A9

Abstract

A nitride-based electronic device having a control terminal, a first conduction terminal and a second conduction terminal is disclosed. The nitride-based electronic device comprises: a main switching element which may be a transistor, an auxiliary switching circuit and a clamping circuit. By implementing the clamping circuit provided by the present invention, it is no need to connect a large value resistor in series with a gate of the transistor directly, the impact on driving speed of the transistor can be minimized. Moreover, the gate-source voltage of the transistor can be clamped to a fixed value over a wide range of driving voltages, allowing the electronic device to have high compatibility and low conduction loss.

Description

NITRIDE-BASED ELECTRONIC DEVICE

Field of the Invention:

The present invention generally relates to an electronic device with clamping circuit. More specifically, the present invention relates to a nitride-based compound electronic device with clamping circuit.

Background of the Invention:

Direct bandgap materials, such as III-V compound materials have been widely used for high-power and high-frequency devices because of their low power losses and fast switching transition in comparison with silicon (Si) metal oxide semiconductor (MOS) materials. For example, gallium nitride (GaN) field effect transistor (FET) has been widely used in making power devices in fast chargers for mobile devices. However, due to different operation voltages, it is different for III-V compound-based devices to cooperate with Si-MOS based devices. Conventionally, a clamping circuit as shown in FIG. 1 can be used to address such issue. As shown, the clamping circuit may include a Si Zener diode D1 and resistor Rg connected in series with a gate of a GaN transistor Q1. However, the clamping circuit of FIG. 1 may induce a significant gate leakage current. Moreover, the gate-source voltage of the transistor can only be clamped to a fixed value when a driving voltage is higher than the breakdown voltage of the Zener diode. When the driving voltage is lower than the breakdown voltage of the Zener diode, a portion of the gate-source voltage will be lost, causing increase of conduction loss. Therefore, the conventional clamping circuit cannot be compatible with a wide range of driving voltages such as from 5V to 10V or above.

Summary of the Invention:

One objective of the present invention is to address above shortcomings of conventional clamping circuits and provide a clamping circuit design tailor-made for nitride-based transistor.

In according with one aspect of the present disclosure, a nitride-based electronic device having a control terminal, a first conduction terminal and a second conduction terminal is provided. The nitride-based electronic device comprises: a main switching element having a first conduction node connected to the first conduction terminal and a second conduction node connected to the second conduction terminal; an auxiliary switching circuit having a first conduction node connected to the control terminal and a second conduction node connected to a control node of the main switching element; a clamping circuit having a first node connected to a control node of the auxiliary switching circuit and a second node connected to the second conduction node of the main switching element; a capacitor having a first electrode connected to the first node of the clamping circuit and a second electrode connected to the second node of the clamping circuit; a first resistor having a first electrode connected to the first conduction node of the auxiliary switching circuit and a second electrode connected to the first node of the clamping circuit; and a second resistor having a first electrode connected to the control node of the main switching element and a second electrode connected to the second conduction node of the main switching element.

By implementing the clamping circuit provided by the present invention, it is no need to connect a large value resistor in series with the transistor gate directly, the impact on driving speed of the transistor can be minimized. Moreover, the gate-source voltage of transistor can be clamped to a fixed value over a wide range of driving voltages, allowing the electronic device to have high compatibility and low conduction loss.

Brief Description of the Drawings:

Aspects of the present disclosure may be readily understood from the following detailed description with reference to the accompanying figures. The illustrations may not necessarily be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. For simplicity, common reference numerals may be used throughout the drawings and detailed description to indicate the same or similar components.

FIG. 1 shows a circuit diagram for a conventional clamping circuit;

FIG. 2 shows a circuit block diagram for a nitride-based electronic device according to some embodiments of the present invention;

FIG. 3 shows an exemplary main switching element in the nitride-based electronic device of FIG. 2;

FIG. 4 shows an exemplary auxiliary switching element in the nitride-based electronic device of FIG. 2;

FIG. 5 shows another exemplary auxiliary switching element in the nitride-based electronic device of FIG. 2;

FIG. 6 shows an exemplary clamping circuit in the nitride-based electronic device of FIG. 2;

FIG. 7 shows another exemplary auxiliary switching element in the nitride-based electronic device of FIG. 2;

FIG. 8 shows a cross sectional view of various functional components in an IC chip 50 for forming the electronic device according to the present invention; and

FIG. 9 shows a flowchart of a method for manufacturing a nitride-based electronic device according to one embodiment of the present invention.

Detailed Description:

In the following description, preferred examples of the present disclosure will be set forth as embodiments which are to be regarded as illustrative rather than restrictive. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 2 is a circuit block diagram for an electronic device 100 according to some embodiments of the present invention. As shown in FIG. 2, the electronic device 100 may have a control terminal Ctrl, a conduction terminal Cdct1 and a conduction terminal Cdct2.

The electronic device 100 may comprise a main switching element 120. The main switching element 120 may have a control node 121. The main switching element 120 may have a first conduction node 122 connected to the first conduction terminal Cdct1. The main switching element 120 may have a second conduction node 123 connected to the second conduction terminal Cdct2.

The electronic device 100 may further comprise an auxiliary switching circuit 140. The auxiliary switching circuit 140 may have a control node 141. The auxiliary switching circuit 140 may have a first conduction node 142 connected to the control terminal Ctrl. The auxiliary switching circuit 140 may have a second conduction node 143 connected to the control node 121 of the main switching element 120.

The electronic device 100 may further comprise a clamping circuit 160 having a first node 161 and a second node 162. The clamping circuit 160 may have a first node 161 connected to the control node 141 of the auxiliary switching circuit 140. The clamping circuit 160 may have a second node 162 connected to the second conduction node 123 of main switching element 120 and the second conduction terminal Cdct2.

The electronic device 100 may further comprise a capacitor C1. The capacitor C1 may have a first electrode connected to the first node 161 of the clamping circuit 160 and the control node 141 of the auxiliary switching circuit 140. The capacitor C1 may have a second electrode connected to the second node 162 of the clamping circuit 160, the second conduction node 123 of the main switching element 120 and the second conduction terminal Cdct2.

The electronic device 100 may further comprise a first resistor R1. The first resistor R1 may have a first electrode connected to the first conduction node 142 of the auxiliary switching circuit 140 and the control terminal Ctrl. The first resistor R1 may have a second electrode connected to the control node 141 of the auxiliary switching circuit 140 and the first node 161 of the clamping circuit 160.

The electronic device 100 may further comprise a second resistor R2. The second resistor R2 may have a first electrode connected to the control node 121 of the main switching element 120 and the second conduction node 143 of the auxiliary switching circuit. The second resistor R2 may have a second electrode connected to the second node 162 of the clamping circuit 160, the second conduction node 123 of the main switching element 120, the second electrode of the capacitor C1 and the second conduction terminal Cdct2.

Referring to FIG. 3, in some embodiments, the main switching element 120 may be a main nitride-based transistor Qm having a gate G acting as the control node 121 of the main switching element, a drain D acting as the first conduction node 122 of the main switching element and a source S acting as the second conduction node 123 of the main switching element. In some embodiments, the main nitride-based transistor Qm is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .

Referring to FIG. 4, in some embodiments, the auxiliary switching circuit 140 may comprise an auxiliary nitride-based depletion-mode (D-mode) transistor Qa having a gate G connected to the control node 141 of the auxiliary switching circuit, a drain D connected to the first conduction node 142 of the auxiliary switching circuit and a source S connected to the second conduction node 143 of the auxiliary switching circuit. In some embodiments, the auxiliary nitride-based D-mode transistor Qa may be a AlGaN/GaN D-mode HEMT.

Referring to FIG. 5, in some other embodiments, the auxiliary switching circuit 140 may comprise an auxiliary nitride-based enhance-mode E-mode transistor Qa having a gate G connected to the control node 141 of the auxiliary switching circuit, a drain D connected to the first conduction node 142 of the auxiliary switching circuit and a source S connected to the second conduction node 143 of the auxiliary switching circuit. The auxiliary switching circuit may further comprise a diode D1 having an anode connected to the source of the auxiliary nitride-based E-mode transistor Qa and a cathode connected to the drain of the auxiliary nitride-based E-mode transistor Qa. In some embodiments, the auxiliary nitride-based E-mode transistor Qa may be a AlGaN/GaN E-mode HEMT

Referring to FIG. 6, in some embodiments, the clamping circuit 160 may comprise a clamping rectifier Dc having an anode connected to the first node 161 of the clamping circuit 160 and a cathode connected to the second node 162 of the clamping circuit 160. In some embodiments, the clamping rectifier Dc may be a clamping diode or a clamping nitride-based transistor having a source and a gate electrically shorted together to act as the anode of the clamping rectifier and a drain to act as the cathode of the clamping rectifier. In some embodiments, the clamping nitride-based transistor may be a AlGaN/GaN enhancement-mode (E-mode) HEMT.

Referring to FIG. 7, in some embodiments, the clamping circuit 160 may comprise a plurality of clamping rectifiers Dc1, Dc2, …, DcN connected in series, where N is the number of clamping rectifiers. The clamping circuit 160 may include a first clamping rectifier Dc1 having an anode connected to the first node 161 of the clamping circuit 160. The clamping circuit 160 may include a last clamping rectifier DcN having a cathode connected to the second node 162 of the clamping circuit 160. In some embodiments, each of the plurality of clamping rectifiers Dc1, Dc2, …, DcN may be a clamping diode or a clamping nitride-based transistor having a source and a gate electrically shorted together to act as an anode of the clamping rectifier and a drain to act as a cathode of the clamping rectifier. In some embodiments, the clamping nitride-based transistor Qc may be a AlGaN/GaN enhancement-mode (E-mode) HEMT.

In some embodiments, the electronic device 100 according to the present invention may be integrated into a nitride-based integrated circuit (IC) chip. In some embodiments, the main switching element 120, the auxiliary switching circuit 140 and the clamping circuit 160 may be integrated into the IC chip 50. In some embodiments, the main switching element 120, the auxiliary switching circuit 140, the clamping circuit 160, the first resistor R1, the second resistor R2 and the capacitor C1 may be integrated into a nitride-based integrated circuit IC chip.

FIG. 8 shows a cross sectional view of various functional components in an IC chip 50 for forming the electronic device 100 according to the present invention. As shown, the functional components may include one or more transistor structure 50Q, one or more rectifier structure 50D, one or more resistor structure 50R and one or more capacitor structure 50C.

For forming the various functional components, the IC chip 50 may comprise a substrate 502, one or more nitride-based semiconductor layers 504, 506, gate structures 510, source/drain (S/D) electrodes 516, one or more second passivation layers 524, 526 and 528, one or more

conductive vias

532, 536, one or more

conductive layers

542, 546, a protection layer 554, conductive pads 570 and one or more isolation regions 580.

The substrate 502 may be a semiconductor substrate. The exemplary materials of the substrate 502 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable semiconductor materials. In some embodiments, the substrate 502 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 502 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The nitride-based semiconductor layer 504 is disposed over the substrate 502. The exemplary materials of the nitride-based semiconductor layer 504 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y)N where x+y ≤ 1, Al _yGa _(1–y)N where y ≤ 1. The exemplary structures of the nitride-based semiconductor layer 504 can include, for example but are not limited to, multilayered structure, superlattice structure and composition-gradient structures.

The nitride-based semiconductor layer 506 is disposed on the nitride-based semiconductor layer 504. The exemplary materials of the nitride-based semiconductor layer 506 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y)N where x+y ≤ 1, Al _yGa _(1–y)N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 504 and 506 are selected such that the nitride-based semiconductor layer 506 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 504, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 504 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 506 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 504 and 506 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based IC chip is available to include one or more GaN-based high-electron-mobility transistors (HEMT) .

In some embodiments, the nitride-based IC chip may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated) . The buffer layer can be disposed between the substrate 502 and the nitride-based semiconductor layer 504. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 502 and the nitride-based semiconductor layer 504, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

The nucleation layer may be formed between the substrate 502 and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 502 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The gate structures 510 are disposed on/over/above the second nitride-based semiconductor layer 506. Each of the gate structures 510 may include an optional gate semiconductor layer 512 and a gate metal layer 514. The gate semiconductor layer 512 and the gate metal layer 514 are stacked on the nitride-based semiconductor layer 506. The gate semiconductor layer 512 are between the nitride-based semiconductor layer 506 and the gate metal layer 514. The gate semiconductor layer 512 and the gate metal layer 514 may form a Schottky barrier. In some embodiments, the nitride-based IC chip may further include an optional dielectric layer (not shown) between the gate semiconductor layer 512 and the gate metal layer 514.

The exemplary materials of the gate semiconductor layer 512 can include, for example but are not limited to, group III-V nitride semiconductor materials, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a impurity, such as Be, Mg, Zn, Cd, and Mg.

In some embodiments, the nitride-based semiconductor layer 504 includes undoped GaN and the nitride-based semiconductor layer 506 includes AlGaN, and the doped III-V compound semiconductor layers 512 are GaN layers which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the bidirectional switching device 51 into an off-state condition.

In some embodiments, the gate metal layer 514 may include metals or metal compounds. The gate metal layer 514 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate metal layer 514 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

The S/D electrodes 516 are disposed on the nitride-based semiconductor layer 506. The “S/D” electrode means each of the S/D electrodes 516 can serve as a source electrode or a drain electrode, depending on the device design. The S/D electrodes 516 can be located at two opposite sides of the corresponding gate structure 510 although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device. Each of the gate structure 510 can be arranged such that each of the gate structure 510 is located between the at least two of the S/D electrodes 516. The gate structures 510 and the S/D electrodes 516 can collectively act as at least one nitride-based/GaN-based HEMT with the 2DEG region.

In the exemplary illustration, the adjacent S/D electrodes 516 are symmetrical about the gate structure 510 therebetween. In some embodiments, the adjacent S/D electrodes 516 can be optionally asymmetrical about the gate structure 510 therebetween. That is, one of the S/D electrodes 516 may be closer to the gate structure 510 than another one of the S/D electrodes 516.

In some embodiments, the S/D electrodes 516 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the S/D electrodes 516 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The S/D electrodes 516 may be a single layer, or plural layers of the same or different composition. In some embodiments, the S/D electrodes 516 may form ohmic contacts with the nitride-based semiconductor layer 506. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes 516. In some embodiments, each of the S/D electrodes 516 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The passivation layer 524 is disposed over the nitride-based semiconductor layer 506. The passivation layer 524 can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements) . The passivation layer 524 covers a top surface of the nitride-based semiconductor layer 506. The passivation layer 524 may cover the gate structures 510. The passivation layer 524 can at least cover opposite two sidewalls of the gate structures 510. The S/D electrodes 516 can penetrate/pass through the passivation layer 524 to contact the nitride-based semiconductor layer 506. The exemplary materials of the passivation layer 524 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, poly (2-ethyl-2-oxazoline) (PEOX) , or combinations thereof. In some embodiments, the passivation layer 524 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The passivation layer 526 is disposed above the passivation layer 524 and the S/D electrodes 516. The passivation layer 526 covers the passivation layer 524 and the S/D electrodes 516. The passivation layer 526 can serve as a planarization layer which has a level top surface to support other layers/elements. The exemplary materials of the passivation layer 526 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer 526 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The conductive vias 532 are disposed within the passivation layer 526 and passivation layer 524. The conductive vias 532 penetrate the passivation layer 526 and passivation layer 524. The conductive vias 532 extend longitudinally to electrically couple with the gate structure 510 and the S/D electrodes 516, respectively. The upper surfaces of the conductive vias 532 are free from coverage of the passivation layer 526. The exemplary materials of the conductive vias 532 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The conductive layer 542 are disposed on the passivation layer 526 and the conductive vias 532. The conductive layer 542 are in contact with the conductive vias 532. The exemplary materials of the conductive layer 542 can include, for example but are not limited to, conductive materials. The conductive layer 542 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The passivation layer 528 is disposed above the passivation layer 526 and the conductive layer 542. The passivation layer 528 covers the passivation layer 526 and the conductive layer 542. The passivation layer 528 can serve as a planarization layer which has a level top surface to support other layers/elements. The exemplary materials of the passivation layer 528 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer 528 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The conductive vias 536 are disposed within the passivation layer 528. The conductive vias 536 penetrate the passivation layer 528. The conductive vias 536 extend longitudinally to electrically couple with the conductive layer 542. The upper surfaces of the conductive vias 536 are free from coverage of the passivation layer 536. The exemplary materials of the conductive vias 536 can include, for example, but are not limited to, conductive materials, such as metals or alloys.

The conductive layer 546 are disposed on the passivation layer 528 and the conductive vias 536. The conductive layer 546 ss in contact with the conductive vias 536. The exemplary materials of the conductive layer 546 can include, for example but are not limited to, conductive materials. The conductive layer 546 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The protection layer 554 is disposed above the passivation layer 528 and the conductive layer 546. The protection layer 554 covers the passivation layer 528 and the conductive layer 546. The protection layer 554 can prevent the conductive layer 546 from oxidizing. Some portions of the conductive layer 546 can be exposed through openings in the protection layer 554 to form the conductive pads 570, which are configured to electrically connect to external elements (e.g., an external circuit) .

The conductive pads 570 may include one or more conductive pads to act as terminals of the IC chip.

Conductive layers

542 and 546 may also be configured to form conductor structures including, but not limited to transistor gate G, transistor source S, transistor drain D, rectifier anode A, rectifier cathode C, capacitor terminals C _bottom and C _top, resistor terminals R _p and R _N, or other conductor structures.

Although the conductor structures and various functional components are described as being arranged at specific positions in FIG. 8, selection, configuration and quantity of the conductor structures and various functional components can vary depending on design specifications.

FIG. 9 shows a flowchart of a method for manufacturing a nitride-based electronic device having a control terminal, a first conduction terminal and a second conduction terminal according to one embodiment of the present invention. The method may comprise the following steps:

S902: configuring a main switching element which has a control node, a first conduction node connected to the first conduction terminal and a second conduction node connected to the second conduction terminal;

S904: configuring an auxiliary switching circuit which has a control node, a first conduction node connected to the control terminal and a second conduction node connected to the control node of the main switching element;

S904: configuring a clamping circuit which has a first node connected to the control node of the auxiliary switching circuit and a second node connected to the second conduction terminal;

S906: forming a capacitor which has a first electrode connected to the first node of the clamping circuit and a second electrode connected to the second conduction terminal;

S908: forming a first resistor which has a first electrode connected to the control terminal and a second electrode connected to control node of the auxiliary switching circuit and the first node of the clamping circuit; and

S910: forming a second resistor which has a first electrode connected to the control node of the main switching element and a second electrode connected to the second conduction terminal.

In some embodiments, the main switching element is configured by forming a main nitride-based transistor having a gate acting as the control node of the main switching element, a drain acting as the first conduction node of the main switching element and a source acting as the second conduction node of the main switching element.

In some embodiments, the auxiliary switching circuit is configured by forming an auxiliary nitride-based depletion-mode (D-mode) transistor having a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit.

In some embodiments, the auxiliary switching circuit is configured by: forming an auxiliary nitride-based enhance-mode (E-mode) transistor which has a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit; and forming a rectifier which has an anode connected to the source of the auxiliary nitride-based E-mode transistor and a cathode connected to the drain of the auxiliary nitride-based E-mode transistor.

In some embodiments, the clamping circuit is configured by forming a clamping rectifier which has an anode connected to the first node of the clamping circuit and a cathode connected to the second node of the clamping circuit.

In some embodiments, the clamping rectifier is constituted with a clamping nitride-based transistor which has a source and a gate electrically shorted together to act as the anode of the clamping rectifier and a drain to act as the cathode of the clamping rectifier.

In some embodiments, the clamping circuit is configured by forming a plurality of clamping rectifiers connected in series, the plurality of clamping rectifiers including a first clamping rectifier having an anode connected to the first node of the clamping circuit and a last clamping rectifier having a cathode connected to the second node of the clamping circuit.

In some embodiments, each of the plurality of clamping rectifiers is constituted with a clamping nitride-based transistor having a source and a gate electrically shorted together to act as an anode of the clamping rectifier and a drain to act as a cathode of the clamping rectifier.

In some embodiments, the method for manufacturing a nitride-based electronic device further comprise integrating the main switching element, the auxiliary switching circuit and the clamping circuit into a nitride-based integrated circuit (IC) chip.

In some embodiments, the method for manufacturing a nitride-based electronic device further comprise integrating the main switching element, the auxiliary switching circuit, the clamping circuit, the first resistor, the second resistor and the capacitor into a nitride-based IC chip.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. While the apparatuses disclosed herein have been described with reference to particular structures, shapes, materials, composition of matter and relationships…etc., these descriptions and illustrations are not limiting. Modifications may be made to adapt a particular situation to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto.

Claims

A nitride-based electronic device, comprising:

a control terminal;

a first conduction terminal;

a second conduction terminal;

a main switching element having a first conduction node connected to the first conduction terminal and a second conduction node connected to the second conduction terminal;

an auxiliary switching circuit having a first conduction node connected to the control terminal and a second conduction node connected to a control node of the main switching element;

a clamping circuit having a first node connected to a control node of the auxiliary switching circuit and a second node connected to the second conduction node of the main switching element;

a capacitor having a first electrode connected to the first node of the clamping circuit and a second electrode connected to the second node of the clamping circuit;

a first resistor having a first electrode connected to the first conduction node of the auxiliary switching circuit and a second electrode connected to the first node of the clamping circuit; and

a second resistor having a first electrode connected to the control node of the main switching element and a second electrode connected to the second conduction node of the main switching element.
The nitride-based electronic device according to claim 1, wherein the main switching element is a main nitride-based transistor having a gate acting as the control node of the main switching element, a drain acting as the first conduction node of the main switching element and a source acting as the second conduction node of the main switching element.
The nitride-based electronic device according to claim 2, wherein the main nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor HEMT.
The nitride-based electronic device according to any one of claims 1 to 3, wherein the auxiliary switching circuit comprises an auxiliary nitride-based depletion-mode (D-mode) transistor having a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit.
The nitride-based electronic device according to claim 4, wherein the auxiliary nitride-based D-mode transistor is a AlGaN/GaN D-mode high-electron-mobility transistor HEMT.
The nitride-based electronic device according to any one of claims 1 to 5, wherein the auxiliary switching circuit comprises:

an auxiliary nitride-based enhance-mode (E-mode) transistor having a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit; and

a diode having an anode connected to the source of the auxiliary nitride-based E-mode transistor and a cathode connected to the drain of the auxiliary nitride-based E-mode transistor.
The nitride-based electronic device according to claim 6, wherein the auxiliary nitride-based E-mode transistor is a AlGaN/GaN E-mode high-electron-mobility transistor HEMT.
The nitride-based electronic device according to any one of claims 1 to 7, wherein the clamping circuit comprises a clamping rectifier having an anode connected to the first node of the clamping circuit and a cathode connected to the second node of the clamping circuit.
The nitride-based electronic device according to claim 8, wherein the clamping rectifier is constituted with a clamping nitride-based transistor having a source and a gate electrically shorted together to act as the anode of the clamping rectifier and a drain to act as the cathode of the clamping rectifier.
The nitride-based electronic device according to claim 9, wherein the clamping nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor HEMT.
The nitride-based electronic device according to any one of claims 1 to 7, wherein the clamping circuit comprises a plurality of clamping rectifiers connected in series and including a first clamping rectifier having an anode connected to the first node of the clamping circuit and a last clamping rectifier having a cathode connected to the second node of the clamping circuit.
The nitride-based electronic device according to claim 11, wherein each of the plurality of clamping rectifiers is constituted with a clamping nitride-based transistor having a source and a gate electrically shorted together to act as an anode of the clamping rectifier and a drain to act as a cathode of the clamping rectifier.
The nitride-based electronic device according to claim 12, wherein the clamping nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor HEMT.
The nitride-based electronic device according to any one of claims 1 to 13, wherein the main switching element, the auxiliary switching circuit and the clamping circuit are integrated into a nitride-based integrated circuit (IC) chip.
The nitride-based electronic device according to any one of claims 1 to 13, wherein the main switching element, the auxiliary switching circuit, the clamping circuit, the first resistor, the second resistor and the capacitor are integrated into a nitride-based integrated circuit (IC) chip.
A method for manufacturing a nitride-based electronic device, the nitride-based electronic device having a control terminal, a first conduction terminal and a second conduction terminal, the method comprising:

configuring a main switching element which has a control node, a first conduction node connected to the first conduction terminal and a second conduction node connected to the second conduction terminal;

configuring an auxiliary switching circuit which has a control node, a first conduction node connected to the control terminal and a second conduction node connected to the control node of the main switching element;

configuring a clamping circuit which has a first node connected to the control node of the auxiliary switching circuit and a second node connected to the second conduction terminal;

forming a capacitor which has a first electrode connected to the first node of the clamping circuit and a second electrode connected to the second conduction terminal;

forming a first resistor which has a first electrode connected to the control terminal and a second electrode connected to control node of the auxiliary switching circuit and the first node of the clamping circuit; and

forming a second resistor which has a first electrode connected to the control node of the main switching element and a second electrode connected to the second conduction terminal.
The method according to claim 16, wherein the main switching element is configured by forming a main nitride-based transistor having a gate acting as the control node of the main switching element, a drain acting as the first conduction node of the main switching element and a source acting as the second conduction node of the main switching element.
The method according to claims 16 or 17, wherein the auxiliary switching circuit is configured by forming an auxiliary nitride-based depletion-mode (D-mode) transistor having a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit.
The method according to claims 16 or 17, wherein the auxiliary switching circuit is configured by:

forming an auxiliary nitride-based enhance-mode (E-mode) transistor which has a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit; and

forming a rectifier which has an anode connected to the source of the auxiliary nitride-based E-mode transistor and a cathode connected to the drain of the auxiliary nitride-based E-mode transistor.
The method according to any one of claims 16 to 19, wherein the clamping circuit is configured by forming a clamping rectifier which has an anode connected to the first node of the clamping circuit and a cathode connected to the second node of the clamping circuit.
The method according to claim 20, wherein the clamping rectifier is constituted with a clamping nitride-based transistor which has a source and a gate electrically shorted together to act as the anode of the clamping rectifier and a drain to act as the cathode of the clamping rectifier.
The method according to any one of claims 16 to 19, wherein the clamping circuit is configured by forming a plurality of clamping rectifiers connected in series, the plurality of clamping rectifiers including a first clamping rectifier having an anode connected to the first node of the clamping circuit and a last clamping rectifier having a cathode connected to the second node of the clamping circuit.
The method according to claim 22, wherein each of the plurality of clamping rectifiers is constituted with a clamping nitride-based transistor having a source and a gate electrically shorted together to act as an anode of the clamping rectifier and a drain to act as a cathode of the clamping rectifier.
The method according to any one of claims 16 to 23, further comprising integrating the main switching element, the auxiliary switching circuit and the clamping circuit into a nitride-based integrated circuit (IC) chip.
The method according to any one of claims 16 to 23, further comprising integrating the main switching element, the auxiliary switching circuit, the clamping circuit, the first resistor, the second resistor and the capacitor into a nitride-based integrated circuit (IC) chip.