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WO2023236043A1 - 移位寄存器及其驱动方法、显示基板、显示装置 - Google Patents

移位寄存器及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2023236043A1
WO2023236043A1 PCT/CN2022/097393 CN2022097393W WO2023236043A1 WO 2023236043 A1 WO2023236043 A1 WO 2023236043A1 CN 2022097393 W CN2022097393 W CN 2022097393W WO 2023236043 A1 WO2023236043 A1 WO 2023236043A1
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WIPO (PCT)
Prior art keywords
transistor
signal
electrode
node
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
PCT/CN2022/097393
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English (en)
French (fr)
Inventor
陈腾
史大为
王文涛
蒋发明
刘帅卓
李传勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chongqing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chongqing BOE Display Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chongqing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2022/097393 priority Critical patent/WO2023236043A1/zh
Priority to CN202280001685.4A priority patent/CN117546231B/zh
Publication of WO2023236043A1 publication Critical patent/WO2023236043A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically relates to a shift register and a driving method thereof, a display substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a shift register, including: a storage subcircuit, a node control subcircuit and an output control subcircuit;
  • the storage sub-circuit is electrically connected to the first node and the first power terminal respectively, and is configured to store the voltage difference between the signal of the first node and the signal of the first power terminal;
  • the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node and the second node respectively, and is configured to control the signal input terminal under the control of the first clock signal terminal.
  • the signal is provided to the first node, and under the control of the second clock signal terminal, the signal of the first node is provided to the second node;
  • the output control subcircuit is electrically connected to the second node, the first power terminal, the second power terminal and the signal output terminal respectively, and is configured to provide the first power terminal or the third power terminal to the signal output terminal under the control of the second node.
  • the signal from the second power terminal is electrically connected to the second node, the first power terminal, the second power terminal and the signal output terminal respectively, and is configured to provide the first power terminal or the third power terminal to the signal output terminal under the control of the second node. The signal from the second power terminal.
  • the output control subcircuit includes: a first output control subcircuit and a second output control subcircuit;
  • the first output control sub-circuit is electrically connected to the second node, the third node, the first power terminal and the second power terminal respectively, and is configured to provide the first power terminal to the third node under the control of the second node. Or the signal from the second power terminal;
  • the second output control subcircuit is electrically connected to the third node, the first power terminal, the second power terminal and the signal output terminal respectively, and is configured to provide the first power terminal to the signal output terminal under the control of the third node. Or the signal at the second power supply terminal.
  • Some possible implementations also include: noise reduction subcircuit;
  • the noise reduction sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, the second node and the third node respectively, and is arranged at the first clock signal terminal, Under the control of the second clock signal terminal and the third node, a signal of the first power terminal or the second power terminal is provided to the second node.
  • the storage subcircuit includes: a capacitor, and the capacitor includes: a first plate and a second plate;
  • the first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power terminal.
  • the node control sub-circuit includes: a first transistor and a second transistor;
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node.
  • the first output control sub-circuit includes: a third transistor and a fourth transistor
  • the second output control sub-circuit includes: a fifth transistor and a sixth transistor
  • the control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the third node;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power terminal, and the second electrode of the fourth transistor is electrically connected to the third node;
  • the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;
  • the control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal;
  • the third transistor and the fourth transistor have opposite transistor types, and the fifth transistor and the sixth transistor have opposite transistor types.
  • the noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;
  • the control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;
  • the control electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second node;
  • the control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the second electrode of the tenth transistor;
  • the control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal;
  • the seventh transistor and the eighth transistor have the same transistor type, the ninth transistor and the tenth transistor have the same transistor type, and the seventh transistor and the ninth transistor have the opposite transistor type.
  • the storage sub-circuit includes: a capacitor, the capacitor includes: a first plate and a second plate; the node control sub-circuit includes: a first transistor and a second transistor; the output control Sub-circuit includes: third transistor, fourth transistor, fifth transistor and sixth transistor
  • the first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power terminal;
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;
  • the control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the third node;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power terminal, and the second electrode of the fourth transistor is electrically connected to the third node;
  • the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;
  • the control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal;
  • the first, second, third and fifth transistors are P-type transistors
  • the fourth and sixth transistors are N-type transistors and are oxide transistors.
  • a noise reduction subcircuit the storage subcircuit includes: a capacitor, the capacitor includes: a first plate and a second plate; the node control subcircuit includes: a first transistor and a second transistor; the output control sub-circuit includes: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor ;
  • the first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power terminal;
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;
  • the control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the third node;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power terminal, and the second electrode of the fourth transistor is electrically connected to the third node;
  • the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;
  • the control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal;
  • the control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;
  • the control electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second node;
  • the control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the second electrode of the tenth transistor;
  • the control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal;
  • the first, second, third, fifth, seventh and eighth transistors are P-type transistors
  • the fourth, sixth, ninth and tenth transistors are N-type transistors
  • the clock signal at the first clock signal terminal and the clock signal at the second clock signal terminal are mutually inverted signals
  • the signal at the signal input terminal is a first pulse signal, and the duration of the first pulse signal is equal to the period of the clock signal at the first clock signal terminal,
  • the signal at the signal output end is a second pulse signal
  • the duration of the second pulse signal is equal to the duration of the first pulse signal
  • the starting time of the second pulse signal is the duration of the first pulse signal. End Time.
  • the clock signal at the first clock signal terminal and the clock signal at the second clock signal terminal are mutually inverted signals
  • the signal at the signal input terminal is a third pulse signal, and the duration of the third pulse signal is equal to N times the period of the clock signal at the first clock signal terminal, where N is a positive integer greater than or equal to 2;
  • the signal at the signal output end is a fourth pulse signal
  • the duration of the fourth pulse signal is equal to the duration of the third pulse signal
  • the start time of the fourth pulse signal is the same as the start time of the third pulse signal.
  • the difference in start times is equal to the period of the clock signal at the first clock signal terminal.
  • the present disclosure also provides a display substrate, including: a display area and a non-display area; the display substrate includes: a base and a circuit structure layer disposed on the base; the circuit structure layer includes: located on A gate drive circuit in the non-display area and a pixel circuit arranged in an array in the display area.
  • the gate drive circuit includes: a plurality of cascaded above-mentioned shift registers.
  • the pixel circuit includes: a light-emitting signal line, a scanning signal line and a reset signal. Wire;
  • the signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the i+1-th stage shift register, 1 ⁇ i ⁇ M-1, M is the total number of stages of the shift register;
  • the gate driving circuit is electrically connected to at least one of a light-emitting signal line, a scanning signal line and a reset signal line.
  • the method further includes: a first clock signal line, a second clock signal line, a first power line and a second power line extending along the first direction, the first power line, the second power line, the A clock signal line and a second clock signal line are arranged along a second direction, and the first direction intersects the second direction;
  • the first power terminals of all shift registers are electrically connected to the first power line
  • the second power terminals of all shift registers are electrically connected to the second power line
  • the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock
  • the signal lines are electrically connected.
  • the second clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal line.
  • the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line.
  • the second clock signal terminal of the i+1 stage shift register is electrically connected to the first clock signal line.
  • the shift register includes: first to tenth transistors and a capacitor, the capacitor includes: a first plate and a second plate;
  • the circuit structure layer includes: stacked on a substrate in sequence The first semiconductor layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the second semiconductor layer, the fourth insulating layer, the third conductive layer and the fifth insulating layer layer and the fourth conductive layer;
  • the first semiconductor layer includes: an active layer of a first transistor, an active layer of a second transistor, an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a seventh transistor and an eighth transistor.
  • the active layer of a transistor includes: an active layer of a first transistor, an active layer of a second transistor, an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a seventh transistor and an eighth transistor.
  • the first conductive layer includes: a control electrode of the first transistor, a control electrode of the second transistor, a control electrode of the third transistor, a control electrode of the fifth transistor, a control electrode of the seventh transistor, a control electrode of the eighth transistor, The first plate of the capacitor and the signal output line;
  • the second conductive layer includes: a second plate of the capacitor
  • the second semiconductor layer includes: an active layer of a fourth transistor, an active layer of a sixth transistor, an active layer of a ninth transistor, and an active layer of a tenth transistor;
  • the third conductive layer includes: a control electrode of a fourth transistor, a control electrode of a sixth transistor, a control electrode of a ninth transistor, and a control electrode of a tenth transistor;
  • the fourth conductive layer includes: a first clock signal line, a second clock signal line, a first power line, a second power line, a first pole and a second pole of a first transistor to a first pole and a sixth transistor.
  • the signal output lines are respectively connected to the second pole of the fifth transistor and the second pole of the sixth transistor;
  • the first connection signal line is respectively connected to the active layer of the third transistor and the control electrode of the ninth transistor;
  • the second connection signal line is respectively connected to the active layer of the third transistor and the control electrode of the eighth transistor;
  • the third connection signal line is respectively connected to the control electrode of the tenth transistor and the control electrode of the second transistor.
  • the fifth transistor and the sixth transistor are located on the same side of the first power line, and the fifth transistor and the sixth transistor are arranged along the first direction;
  • the third transistor is located on a side of the fifth transistor away from the first power line, and the fourth transistor is located on a side of the sixth transistor away from the first power line.
  • the third transistor and the fourth transistor are arranged along the first direction.
  • the third transistor and the fifth transistor are arranged along the second direction, and the fourth transistor and the sixth transistor are arranged along the second direction;
  • the eighth transistor is located on a side of the third transistor away from the fifth transistor, and the ninth transistor is located on a side of the fourth transistor away from the sixth transistor.
  • the eighth transistor and the ninth transistor are arranged along the first direction, and the third transistor and the eighth transistor are arranged on the side of the fourth transistor away from the sixth transistor.
  • the transistors are arranged along the second direction, and the fourth transistor and the ninth transistor are arranged along the second direction;
  • the seventh transistor is located on the side of the eighth transistor away from the third transistor, and the tenth transistor is located on the side of the ninth transistor away from the fourth transistor.
  • the seventh transistor and the tenth transistor are arranged along the first direction, and the seventh transistor and the eighth transistor are arranged on the side of the ninth transistor away from the fourth transistor.
  • the transistors are arranged along the second direction, and the ninth transistor and the tenth transistor are arranged along the second direction;
  • the second transistor is located between the seventh transistor and the tenth transistor, the first transistor is located on a side of the seventh transistor away from the eighth transistor, and the capacitor is located on a side of the tenth transistor away from the ninth transistor;
  • the second power line is located on a side of the capacitor away from the tenth transistor
  • the first clock signal line is located on a side of the second power line away from the capacitor
  • the second clock signal line is located on a side of the first clock signal line away from the second power line.
  • the active layer of the first transistor and the active layer of the second transistor are an integrally formed structure, and the active layer of the seventh transistor and the active layer of the eighth transistor are an integrally formed structure;
  • the active layer of the third transistor includes: a first active connection part, a second active connection part and a third active connection part; the first active connection part and the third active connection part extend along the first direction, and the The two active connection parts extend along the second direction and are respectively connected to the first active connection part and the third active connection part;
  • the first active connection part is located on a side of the second active connection part close to the integrated structure of the active layer of the seventh transistor and the active layer of the eighth transistor, and the third active connection part is located on the second active connection part A side of the integrated structure away from the active layer of the seventh transistor and the active layer of the eighth transistor;
  • a straight line extending in the second direction passes through the first active connection and the active layer of the second transistor
  • a straight line extending in the second direction passes through the third active connection and the active layer of the first transistor.
  • the first plate of the capacitor includes: a first capacitor body part and a first capacitor connection part that are connected to each other;
  • the control electrode of the first transistor and the control electrode of the seventh transistor have an integrated structure and are located on the side of the first capacitor connection part away from the first capacitor main part;
  • the virtual straight line extending along the second direction passes through the control electrode of the eighth transistor and the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the virtual straight line extending along the second direction passes through the control electrode of the third transistor and the control electrode of the eighth transistor;
  • the virtual straight line extending in the second direction passes through the control electrode of the fifth transistor and the control electrode of the third transistor.
  • the virtual straight line extending in the second direction passes through the signal output line and the control electrode of the second transistor.
  • the second plate of the capacitor includes: a second capacitor body part and a second capacitor connection part that are connected to each other, and the second capacitor connection part is located on one side of the second capacitor body part;
  • the area of the first capacitor body part of the first plate of the capacitor is larger than the area of the second capacitor body part of the second plate of the capacitor;
  • the orthographic projection of the second capacitor main body part and the second capacitor connection part on the substrate at least partially overlaps with the orthographic projection of the first capacitor main body part of the first plate of the capacitor on the substrate, and overlaps with the orthographic projection of the first capacitor plate of the capacitor on the substrate. Orthographic projections of the first capacitor connecting portion on the substrate do not overlap.
  • the orthographic projection of the active layer of the sixth transistor on the substrate and the orthographic projection of the active layer of the fifth transistor on the substrate are respectively located opposite to the orthographic projection of the signal output line on the substrate.
  • a straight line extending along the first direction passes through the active layer of the fifth transistor and the active layer of the sixth transistor;
  • a straight line extending in the first direction passes through the active layer of the fourth transistor and the third active connection portion of the active layer of the third transistor;
  • the straight line extending along the first direction passes through the active layer of the ninth transistor and the active layer of the eighth transistor, and the straight line extending along the first direction passes through the active layer of the tenth transistor and the active layer of the seventh transistor.
  • the virtual straight line extending along the second direction passes through the control electrode of the fourth transistor, the control electrode of the sixth transistor, and the control electrode of the ninth transistor;
  • the control electrode of the tenth transistor includes: a first electrode connection part, a second electrode connection part and a third electrode connection part.
  • the first electrode connecting part and the third electrode connecting part extend along the second direction, and the second electrode connecting part extends along the first direction and are connected to the first electrode connecting part and the third electrode connecting part respectively;
  • the first electrode connection part is located on a side of the second electrode connection part close to the control electrode of the ninth transistor, and the third electrode connection part is located on a side of the second electrode connection part away from the control electrode of the ninth transistor;
  • the virtual straight line extending in the second direction passes through the orthographic projection of the first electrode connection portion of the control electrode of the tenth transistor on the substrate and the orthographic projection of the first capacitor main body portion of the first plate of the capacitor on the substrate;
  • the orthographic projection of the third electrode connecting portion of the control electrode of the tenth transistor on the substrate is located at the orthographic projection of the first plate of the capacitor on the substrate and is far away from the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the side of the orthographic projection on the base is located at the orthographic projection of the first plate of the capacitor on the substrate and is far away from the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the fifth insulating layer is provided with multiple via hole patterns
  • the multiple via hole patterns include: first to third via holes provided in the first insulating layer, the second insulating layer and the fifth insulating layer.
  • Six via holes the seventh to thirteenth via holes are opened in the second to fifth insulating layers, the fourteenth via holes are opened in the third to fifth insulating layers, and the fourth insulating layer is opened in The fifteenth to eighteenth via holes from the fifth insulating layer to the fifth insulating layer and the nineteenth to twenty-second via holes opened in the fifth insulating layer;
  • the third via hole exposes the active layer of the third transistor, and the twenty-second via hole exposes the control electrode of the tenth transistor;
  • the number of third via holes is four.
  • a virtual straight line extending along the first direction passes through the first third via hole and the second third via hole, and the first third via hole and the second third via hole
  • the via hole exposes the first active connection portion of the active layer of the third transistor
  • a virtual straight line extending in the first direction passes through the third third via hole and the fourth third via hole
  • the third third via hole The three via holes and the fourth third via hole expose the third active connection portion of the active layer of the third transistor
  • a virtual straight line extending in the second direction passes through the second third via hole and the third third via hole.
  • the number of the twenty-second via holes is two.
  • the first twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor.
  • the second twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor.
  • the first pole of the third transistor, the first pole of the fifth transistor, the first pole of the seventh transistor and the first power line are integrally formed structures, and the first pole of the fourth transistor, the first pole of the fourth transistor and the first power line
  • the first pole of the six transistors, the first pole of the tenth transistor and the second power line are of an integrated structure
  • the second pole of the first transistor and the first pole of the second transistor are of an integrated structure
  • the second pole of the third transistor is of an integrated structure.
  • the second pole of the fourth transistor and the second pole of the fourth transistor are integrally formed.
  • the second pole of the second transistor, the second pole of the eighth transistor and the first pole of the ninth transistor are integrally formed.
  • the second pole of the fifth transistor and the sixth transistor are integrally formed.
  • the second pole has a one-piece structure;
  • the orthographic projection of the first power line on the substrate and the orthographic projection of the signal output line on the substrate at least partially overlap;
  • the orthographic projection of the second power line on the substrate and the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor, the control electrode of the tenth transistor and the second capacitor connection portion of the second plate of the capacitor are on the substrate
  • the orthographic projection of the first clock signal line on the substrate partially overlaps with the orthographic projection of the control electrode of the tenth transistor and the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate;
  • the second clock signal line overlaps with the orthographic projection portion of the control electrode of the connected transistor on the substrate;
  • the orthographic projection of the integrated structure of the second pole of the first transistor and the first pole of the second transistor on the substrate overlaps with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate;
  • the orthographic projection of the integrated structure of the second electrode of the third transistor and the second electrode of the fourth transistor on the substrate partially overlaps with the orthographic projection of the control electrode of the sixth transistor and the control electrode of the fifth transistor on the substrate;
  • the orthographic projection of the integrated structure of the second pole of the fifth transistor and the second pole of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line on the substrate;
  • the orthographic projection of the integrated structure of the second electrode of the second transistor, the second electrode of the eighth transistor and the first electrode of the ninth transistor on the substrate and the control electrode of the third transistor and the control electrode of the fourth transistor on the substrate The orthographic projections partially overlap;
  • the orthographic projection of the first connection signal line on the substrate partially overlaps the orthographic projection of the control electrode of the ninth transistor on the substrate;
  • the orthographic projection of the second connection signal line on the substrate partially overlaps the orthographic projection of the control electrode of the eighth transistor on the substrate;
  • the orthographic projection of the third connection signal line on the substrate overlaps with the orthographic projection of the control electrode of the second transistor and the control electrode of the tenth transistor on the substrate.
  • the first pole and the second pole of the third transistor are connected to the active layer of the third transistor through the third third via hole and the fourth third via hole respectively;
  • the first connection signal line is connected to the active layer of the third transistor through the first third via hole;
  • the second connection signal line is connected to the active layer of the third transistor through the second third via hole;
  • the third connection signal line is connected to the control electrode of the tenth transistor through the first 22nd via hole;
  • One of the first clock signal line and the second clock signal line is connected to the control electrode of the tenth transistor through the second twenty-second via hole.
  • the present disclosure also provides a display device, including: the above display substrate.
  • the present disclosure also provides a driving method of a shift register, which is configured to drive the above-mentioned shift register.
  • the method includes:
  • the storage sub-circuit stores the voltage difference between the signal of the first node and the signal of the first power terminal
  • the node control subcircuit provides the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and provides the signal of the first node to the second node under the control of the second clock signal terminal;
  • the output control subcircuit provides the signal of the first power terminal or the second power terminal to the signal output terminal under the control of the second node.
  • Figure 1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of an output control subcircuit provided in an exemplary embodiment
  • Figure 3 is a schematic structural diagram of a shift register provided in an exemplary embodiment
  • Figure 4 is an equivalent circuit diagram of a memory subcircuit provided by an exemplary embodiment
  • Figure 5 is an equivalent circuit diagram of a node control subcircuit provided by an exemplary embodiment
  • Figure 6 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment
  • Figure 7 is an equivalent circuit diagram of a noise reduction subcircuit provided by an exemplary embodiment
  • Figure 8 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment
  • Figure 9 is an equivalent circuit diagram of a shift register provided by another exemplary embodiment.
  • Figure 10 is an operating timing diagram of a shift register provided in an exemplary embodiment
  • Figure 11 is an operating timing diagram of a shift register provided by another exemplary embodiment
  • Figure 12 is a schematic structural diagram of a display substrate provided in an exemplary embodiment
  • Figure 13 is a schematic diagram after forming the first semiconductor layer pattern
  • Figure 14A is a schematic diagram of the first conductive layer pattern
  • Figure 14B is a schematic diagram after forming the first conductive layer pattern
  • Figure 15A is a schematic diagram of the second conductive layer pattern
  • Figure 15B is a schematic diagram after the second conductive layer pattern is formed
  • Figure 16A is a schematic diagram of the second semiconductor layer pattern
  • Figure 16B is a schematic diagram after the second semiconductor layer pattern is formed
  • Figure 17A is a schematic diagram of the third conductive layer pattern
  • Figure 17B is a schematic diagram after forming the third conductive layer pattern
  • Figure 18 is a schematic diagram after the fifth insulating layer pattern is formed
  • Figure 19A is a schematic diagram of the fourth conductive layer pattern
  • Figure 19B is a schematic diagram after the fourth conductive layer pattern is formed.
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • components with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the "same layer arrangement" used refers to structures formed by patterning two (or more than two) structures through the same patterning process, and their materials may be the same or different.
  • the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • the display substrate includes: a pixel circuit, a light-emitting element and a gate driving circuit, wherein the gate driving circuit is configured to provide a gate signal to the pixel circuit so that the pixel circuit can drive the light-emitting element to emit light.
  • the gate drive circuit occupies a relatively large area and consumes a large amount of power.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register provided by the embodiment of the present disclosure may include: a storage sub-circuit, a node control sub-circuit and an output control sub-circuit.
  • the storage subcircuit is electrically connected to the first node N1 and the first power terminal VGH respectively, and is configured to store the voltage difference between the signal of the first node N1 and the signal of the first power terminal VGH; node control The sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first node N1 and the second node N2 respectively, and is configured to control the first clock signal terminal CK under the control of the first clock signal terminal CK.
  • the signal of the signal input terminal IN is provided to the first node N1, and under the control of the second clock signal terminal CB, the signal of the first node N1 is provided to the second node N2; the output control subcircuit is respectively connected with the second node N2,
  • the first power terminal VGH, the second power terminal VGL and the signal output terminal OUT are electrically connected, and are configured to provide the signal output terminal OUT with a signal of the first power terminal VGH or the second power terminal VGL under the control of the second node N2.
  • the first power terminal VGH continuously provides a high-level signal
  • the second power terminal VGL continuously provides a low-level signal
  • the signals of the first clock signal terminal CK and the second clock signal terminal CB may be periodic pulse signals.
  • the shift register provided by the embodiment of the present disclosure includes: a storage sub-circuit, a node control sub-circuit and an output control sub-circuit; the storage sub-circuit is electrically connected to the first node and the first power supply terminal respectively, and is configured to store the signal of the first node and the voltage difference between the signal at the first power supply terminal; the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node and the second node respectively, and is configured to operate at the first Under the control of the clock signal terminal, the signal of the signal input terminal is provided to the first node, and under the control of the second clock signal terminal, the signal of the first node is provided to the second node; the output control subcircuit is respectively connected with the second node and the second node.
  • a power supply terminal, a second power supply terminal and a signal output terminal are electrically connected and configured to provide a signal from the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.
  • the shift register provided by the present disclosure can reduce the area occupied by the shift register and the power consumption through the cooperation of the storage sub-circuit, the node control sub-circuit and the output control sub-circuit.
  • FIG. 2 is a schematic structural diagram of an output control subcircuit provided in an exemplary embodiment.
  • the output control subcircuit may include: a first output control subcircuit and a second output control subcircuit.
  • the first output control sub-circuit is electrically connected to the second node N2, the third node N3, the first power terminal VGH and the second power terminal VGL respectively, and is configured to be under the control of the second node N2.
  • the second output control sub-circuit is respectively connected to the third node N3, the first power terminal VGH, the second power terminal VGL and the signal output terminal OUT.
  • the electrical connection is configured to provide the signal of the first power terminal VGH or the second power terminal VGL to the signal output terminal OUT under the control of the third node N3.
  • FIG. 3 is a schematic structural diagram of a shift register provided in an exemplary embodiment.
  • the shift register may further include: a noise reduction subcircuit.
  • the noise reduction sub-circuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first power terminal VGH, the second power terminal VGL, the second node N2 and the third node N3, and is set to Under the control of the first clock signal terminal CK, the second clock signal terminal CB and the third node N3, a signal of the first power terminal VGH or the second power terminal VGL is provided to the second node N2.
  • the present disclosure can maintain the voltage value of the signal of the second node N2 by setting the noise reduction sub-circuit, so that the signal of the second node N2 is in a stable state, preventing the voltage value of the signal from being changed due to floating of the second node N2, and improving the shift. Register reliability.
  • FIG. 4 is an equivalent circuit diagram of a memory subcircuit provided by an exemplary embodiment.
  • the storage subcircuit may include a capacitor C, and the capacitor C includes a first plate C1 and a second plate C2.
  • the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power terminal VGH.
  • FIG. 4 An exemplary structure of the memory subcircuit is shown in FIG. 4 . Those skilled in the art can easily understand that the implementation of the memory subcircuit is not limited to this.
  • FIG. 5 is an equivalent circuit diagram of a node control subcircuit provided by an exemplary embodiment.
  • the node control sub-circuit may include: a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first clock signal terminal IN.
  • the node N1 is electrically connected;
  • the control electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node. N2 electrical connection.
  • FIG. 5 An exemplary structure of the node control subcircuit is shown in FIG. 5 . Those skilled in the art can easily understand that the implementation of the node control subcircuit is not limited to this.
  • FIG. 6 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment.
  • the first output control sub-circuit in the output control sub-circuit may include: a third transistor T3 and a fourth transistor T4;
  • the second output control sub-circuit may include: a fifth transistor. transistor T5 and sixth transistor T6.
  • control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VGH, and the second electrode of the third transistor T3 is electrically connected to the third node.
  • N3 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3.
  • control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT;
  • the control electrode of the sixth transistor T6 is electrically connected to the third node N3, the first electrode of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT.
  • the transistor types of the third transistor T3 and the fourth transistor T4 are opposite, that is, the first output control sub-circuit is equivalent to a set of inverters.
  • the transistor types of the fifth transistor T5 and the sixth transistor T6 are opposite, that is, the second output control sub-circuit is equivalent to a set of inverters.
  • the output control subcircuit in this disclosure is equivalent to two series-connected inverters.
  • FIG. 6 An exemplary structure of the output control subcircuit is shown in FIG. 6 . Those skilled in the art can easily understand that the implementation of the output control sub-circuit is not limited to this.
  • FIG. 7 is an equivalent circuit diagram of a noise reduction subcircuit provided by an exemplary embodiment.
  • the noise reduction sub-circuit may include: a seventh transistor T7 , an eighth transistor T8 , a ninth transistor T9 and a tenth transistor T10 .
  • the control electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CK
  • the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VGH
  • the second electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CK.
  • the first electrode of the eighth transistor T8 is electrically connected;
  • the control electrode of the eighth transistor T8 is electrically connected to the third node N3;
  • the second electrode of the eighth transistor T8 is electrically connected to the second node N2;
  • the control electrode of the ninth transistor T9 is electrically connected to the third node N3.
  • the three nodes N3 are electrically connected, the first pole of the ninth transistor T9 is electrically connected to the second node N2, the second pole of the ninth transistor T9 is electrically connected to the second pole of the tenth transistor T10; the control pole of the tenth transistor T10 is electrically connected to The second clock signal terminal CB is electrically connected, and the first pole of the tenth transistor T10 is electrically connected to the second power supply terminal VGL.
  • the seventh transistor T7 and the eighth transistor T8 may have the same transistor type.
  • the ninth transistor T9 and the tenth transistor T10 may be of the same type.
  • the transistor types of the seventh transistor T7 and the ninth transistor T9 may be opposite.
  • FIG. 7 An exemplary structure of the noise reduction subcircuit is shown in FIG. 7 . Those skilled in the art can easily understand that the implementation of the noise reduction sub-circuit is not limited to this.
  • transistors can be divided into N-type transistors and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) ).
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) ).
  • FIG. 8 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment.
  • the storage sub-circuit in the shift register may include: a capacitor C, the capacitor C includes: a first plate C1 and a second plate C2; the node control sub-circuit may include: : a first transistor T1 and a second transistor T2; the output control subcircuit may include: a third transistor T3, a fourth transistor T4, a fifth transistor and a sixth transistor T6.
  • the first plate C1 of the capacitor C is electrically connected to the first node N1, the second plate C2 of the capacitor C is electrically connected to the first power terminal VGH; the control electrode of the first transistor T1 is connected to the first clock
  • the signal terminal CK is electrically connected, the first pole of the first transistor T1 is electrically connected to the signal input terminal IN, the second pole of the first transistor T1 is electrically connected to the first node N1; the control pole of the second transistor T2 is electrically connected to the second clock signal
  • the terminal CB is electrically connected, the first pole of the second transistor T2 is electrically connected to the first node N1, the second pole of the second transistor T2 is electrically connected to the second node N2; the control pole of the third transistor T3 is electrically connected to the second node N2.
  • the first electrode of the third transistor T3 is electrically connected to the first power terminal VGH, the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, The first pole of the fourth transistor T4 is electrically connected to the second power terminal VGL, the second pole of the fourth transistor T4 is electrically connected to the third node N3; the control pole of the fifth transistor T5 is electrically connected to the third node N3, and the fifth transistor T4 is electrically connected to the third node N3.
  • the first pole of the transistor T5 is electrically connected to the first power terminal VGH, and the second pole of the fifth transistor T5 is electrically connected to the signal output terminal OUT; the control pole of the sixth transistor T6 is electrically connected to the third node N3, and the sixth transistor T6 The first pole of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and the second pole of the sixth transistor T6 is electrically connected to the signal output terminal OUT.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5 may be P-type transistors.
  • the fourth transistor T4 and the sixth transistor T6 may be N-type transistors and be oxide transistors. Oxide transistors can reduce leakage current, improve the performance of the shift register, and reduce the power consumption of the shift register.
  • FIG. 9 is an equivalent circuit diagram of a shift register provided by another exemplary embodiment.
  • the shift register may also include: a noise reduction subcircuit
  • the storage subcircuit may include: a capacitor C, and the capacitor C includes: a first plate C1 and a second plate C2.
  • the node control subcircuit may include: a first transistor T1 and a second transistor T2;
  • the output control subcircuit may include: a third transistor T3, a fourth transistor T4, a fifth transistor, and a sixth transistor T6;
  • the noise reduction subcircuit may include: The seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10.
  • the first plate C1 of the capacitor C is electrically connected to the first node N1, the second plate C2 of the capacitor C is electrically connected to the first power terminal VGH; the control electrode of the first transistor T1 is connected to the first clock
  • the signal terminal CK is electrically connected, the first pole of the first transistor T1 is electrically connected to the signal input terminal IN, the second pole of the first transistor T1 is electrically connected to the first node N1; the control pole of the second transistor T2 is electrically connected to the second clock signal
  • the terminal CB is electrically connected, the first pole of the second transistor T2 is electrically connected to the first node N1, the second pole of the second transistor T2 is electrically connected to the second node N2; the control pole of the third transistor T3 is electrically connected to the second node N2.
  • the first electrode of the third transistor T3 is electrically connected to the first power terminal VGH, the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, The first pole of the fourth transistor T4 is electrically connected to the second power terminal VGL, the second pole of the fourth transistor T4 is electrically connected to the third node N3; the control pole of the fifth transistor T5 is electrically connected to the third node N3, and the fifth transistor T4 is electrically connected to the third node N3.
  • the first pole of the transistor T5 is electrically connected to the first power terminal VGH, and the second pole of the fifth transistor T5 is electrically connected to the signal output terminal OUT; the control pole of the sixth transistor T6 is electrically connected to the third node N3, and the sixth transistor T6
  • the first pole of the seventh transistor T6 is electrically connected to the second power terminal VGL, the second pole of the sixth transistor T6 is electrically connected to the signal output terminal OUT;
  • the control pole of the seventh transistor T7 is electrically connected to the first clock signal terminal CK, and the seventh transistor T7
  • the first pole of the seventh transistor T7 is electrically connected to the first power terminal VGH, the second pole of the seventh transistor T7 is electrically connected to the first pole of the eighth transistor T8; the control pole of the eighth transistor T8 is electrically connected to the third node N3.
  • the second electrode of the transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the third node N3; the first electrode of the ninth transistor T9 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the second node N2.
  • the second electrode of the tenth transistor T10 is electrically connected to the second electrode of the tenth transistor T10; the control electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VGL.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 may be P-type transistors.
  • the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 may be N-type transistors and be oxide transistors. Oxide transistors can reduce leakage current, improve the performance of the shift register, and reduce the power consumption of the shift register.
  • the clock signal of the first clock signal terminal CK and the clock signal of the second clock signal terminal CB are inverse signals of each other.
  • the signal at the signal input terminal IN may be a first pulse signal
  • the signal at the signal output terminal OUT may be a second pulse signal
  • the duration of the first pulse signal is equal to the clock at the first clock signal terminal CK.
  • the period of the signal, the duration of the second pulse signal is equal to the duration of the first pulse signal, and the start time of the second pulse signal is the end time of the first pulse signal.
  • the signal at the signal input terminal IN may be a third pulse signal, the duration of the third pulse signal is equal to N times the period of the clock signal at the first clock signal terminal CK, and N is greater than or equal to A positive integer of 2;
  • the signal at the signal output terminal OUT can be the fourth pulse signal, the duration of the fourth pulse signal is equal to the duration of the third pulse signal, and the start time of the fourth pulse signal is the same as the start time of the third pulse signal The difference is equal to the period of the clock signal of the first clock signal terminal CK.
  • the shift register provided by the present disclosure only includes one capacitor and has a small number of transistors, which reduces the area occupied by the shift register and reduces power consumption.
  • the shift register provided by the present disclosure can not only output pulse signals with a short duration, but also output signals with a longer duration, that is, it has a variety of waveform outputs and has a wide applicable range.
  • FIG. 10 is a working timing diagram of a shift register provided by an exemplary embodiment
  • FIG. 11 is a working timing diagram of a shift register provided by another exemplary embodiment. Both Figures 10 and 11 can be applied to the shift registers shown in Figures 8 and 9.
  • Figure 10 takes the shift register to output a pulse signal with a shorter duration as an example.
  • Figure 11 takes the shift register to output A pulse signal with a long duration is taken as an example for illustration.
  • the shift register in Figure 8 includes first to sixth transistors T1 to T6, 1 capacitor (capacitor C) and 4 signal terminals (first clock signal terminal CK, second clock signal terminal CB, signal input terminal IN and Signal output terminal OUT).
  • the working process of the shift register provided in Figure 8 may include:
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the signal input terminal IN and the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal
  • the second transistor T2 is turned off, the signal of the second node N2 remains a high-level signal
  • the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL passes through the turned-on third transistor.
  • the four transistors T4 are transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the signals of the signal input terminal IN and the second clock signal terminal CB are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 is turned off.
  • the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the high-level signal in the previous stage.
  • the signal at the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the high-level signal at the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2
  • the fourth transistor T4 is turned on
  • the low-level signal of the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4
  • the fifth transistor T5 is turned on
  • the high-level signal of the first power supply terminal VGH is transmitted through the turned-on third node N3.
  • Five transistors T5 transmit to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signals of the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal, the second transistor T2 is turned off, the second node N2 maintains the high-level signal of the previous stage, the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL passes through the turned-on
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 is turned off.
  • the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the low-level signal in the previous stage.
  • the signal at the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the low-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2
  • the third transistor T3 is turned on
  • the high-level signal of the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3
  • the sixth transistor T6 is turned on
  • the low-level signal of the second power supply terminal VGL is transmitted through the turned-on third transistor T3.
  • Six transistors T6 transmit to the signal output terminal OUT.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal, the second transistor T2 is turned off, the second node N2 maintains the low-level signal of the previous stage, the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH passes through the turned-on
  • the third transistor T3 is transmitted to the third node N3, the sixth transistor T6 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is low-level. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the first transistor T1 is turned off, the first node N1 maintains the high-level signal of the previous stage, the signal of the second clock signal terminal CB is a low-level signal, and the second
  • the transistor T2 is turned on, and the high-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2.
  • the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted through the turned-on second transistor T2.
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the working process of the shift register provided in Figure 8 may include:
  • the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signals at the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal
  • the second transistor T2 is turned off, the signal of the second node N2 remains a low-level signal
  • the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH passes through the turned-on third transistor.
  • the three transistors T3 are transmitted to the third node N3, the sixth transistor T6 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal. Signal.
  • the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals at the second clock signal terminal CB are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 is turned off.
  • the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the low-level signal in the previous stage.
  • the signal at the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the low-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2
  • the third transistor T3 is turned on
  • the high-level signal of the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3
  • the sixth transistor T6 is turned on
  • the low-level signal of the second power supply terminal VGL is transmitted through the turned-on third transistor T3.
  • Six transistors T6 transmit to the signal output terminal OUT.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal, the second transistor T2 is turned off, the second node N2 maintains the low-level signal of the previous stage, the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH passes through the turned-on
  • the third transistor T3 is transmitted to the third node N3, the sixth transistor T6 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is low-level. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the first transistor T1 is turned off, the first node N1 maintains the high-level signal of the previous stage, the signal of the second clock signal terminal CB is a low-level signal, and the second
  • the transistor T2 is turned on, and the high-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2.
  • the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted through the turned-on second transistor T2.
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal, the second transistor T2 is turned off, the second node N2 maintains the high-level signal of the previous stage, the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL passes through the turned-on
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the first transistor T1 is turned off, the first node N1 maintains the high-level signal of the previous stage, the signal of the second clock signal terminal CB is a low-level signal, and the second
  • the transistor T2 is turned on, and the high-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2.
  • the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted through the turned-on second transistor T2.
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal, the second transistor T2 is turned off, the second node N2 maintains the high-level signal of the previous stage, the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL passes through the turned-on
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 is turned off.
  • the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the high-level signal in the previous stage.
  • the signal at the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the high-level signal at the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2
  • the fourth transistor T4 is turned on
  • the low-level signal of the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4
  • the fifth transistor T5 is turned on
  • the high-level signal of the first power supply terminal VGH is transmitted through the turned-on third node N3.
  • Five transistors T5 transmit to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signals of the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal.
  • the first transistor T1 is turned on.
  • the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the second clock signal terminal The signal of CB is a high-level signal, the second transistor T2 is turned off, the second node N2 maintains the high-level signal of the previous stage, the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL passes through the turned-on
  • the fourth transistor T4 is transmitted to the third node N3, the fifth transistor T5 is turned on, and the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the first transistor T1 is turned off
  • the first node N1 maintains the low-level signal of the previous stage
  • the signal of the second clock signal terminal CB is a low-level signal
  • the second The transistor T2 is turned on, and the low-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2.
  • the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted through the turned-on second transistor T2.
  • the third transistor T3 is transmitted to the third node N3, the sixth transistor T6 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal. Signal.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 in the shift register provided in FIG. 9 are P-type transistors, and the fourth transistor T4 and the eighth transistor T8 are P-type transistors.
  • the six transistors T6, the ninth transistor T9 and the tenth transistor T10 are N-type transistors as an example.
  • the shift register in Figure 9 includes the first transistor T1 to the tenth transistor T10, 1 capacitor (capacitor C) and 4 signal terminals. (The first clock signal terminal CK, the second clock signal terminal CB, the signal input terminal IN and the signal output terminal OUT).
  • the working process of the shift register provided in Figure 9 may include:
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the signal input terminal IN and the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off
  • the tenth transistor T10 is turned on
  • the signal at the second node N2 remains a high-level signal
  • the fourth transistor T4 is turned on
  • the second power supply The low-level signal at terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 is turned off, the second power supply
  • the low-level signal at terminal VGL cannot be written to the second node N2.
  • the signal at the first power terminal VGH can be transmitted to the second node N2 through the seventh transistor T7 and the eighth transistor T8 that are turned on.
  • the signal at the second node N2 remains As a high-level signal, the high-level signal of the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the signals of the signal input terminal IN and the second clock signal terminal CB are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 and the seventh transistor T7 are turned off.
  • the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the previous stage.
  • the high-level signal of the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the tenth transistor T10 is turned off
  • the high-level signal of the first node N1 passes through the turned-on second transistor T2 is transmitted to the second node N2
  • the fourth transistor T4 is turned on
  • the low-level signal of the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4, and the fifth transistor T5 and the eighth transistor T8 are turned on.
  • the ninth transistor T9 is turned off.
  • the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal of the second power supply terminal VGL cannot be written to the second node N2, and the signal of the second node N2 remains a high-level signal.
  • the high-level signal of the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signals of the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off, the tenth transistor T10 is turned on, the fourth transistor T4 is turned on, and the low-level signal of the second power supply terminal VGL passes through the turned-on fourth transistor T10 .
  • the transistor T4 is transmitted to the third node N3, the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 is turned off, the low level signal of the second power supply terminal VGL cannot be written to the second node. N2, the signal of the first power terminal VGH can be transmitted to the second node N2 through the turned-on seventh transistor T7 and the eighth transistor T8. The signal of the second node N2 remains a high-level signal, and the high-level signal of the first power terminal VGH The level signal is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 and the seventh transistor T7 are turned off.
  • the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the previous stage.
  • the low-level signal of the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the tenth transistor T10 is turned off
  • the low-level signal of the first node N1 passes through the turned-on second transistor T2 is transmitted to the second node N2
  • the third transistor T3 is turned on
  • the high-level signal of the first power terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3, and the sixth transistor T6 and the ninth transistor T9 are turned on.
  • the eighth transistor T8 is turned off.
  • the seventh transistor T7 and the eighth transistor T8 are both turned off, the high-level signal of the first power supply terminal VGH cannot be written to the second node N2, and the signal of the second node N2 remains a low-level signal.
  • the low-level signal of the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal. Signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off
  • the tenth transistor T10 is turned on
  • the second node N2 maintains the low-level signal of the previous stage
  • the third transistor T3 is turned on
  • the first The high-level signal of the power terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3.
  • the sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. Since the ninth transistor T9 and the tenth transistor T10 is turned on, and the low-level signal of the second power supply terminal VLG is transmitted to the second node N2 through the turned-on ninth transistor T9 and the tenth transistor T10.
  • the signal of the second node N2 remains a low-level signal, and the second power supply terminal T10 is turned on.
  • the low-level signal at terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is low-level. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the high-level signal of the previous stage, and the signal of the second clock signal terminal CB is a low-level signal.
  • the second transistor T2 is turned on, the tenth transistor T10 is turned off, the high level signal of the first node N1 is transmitted to the second node N2 through the turned on second transistor T2, the fourth transistor T4 is turned on, and the second power supply
  • the low-level signal at terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off.
  • the ninth transistor T9 and the tenth transistor T10 are all cut off, the low-level signal of the second power terminal VLG cannot be transmitted to the second node N2, the signal of the second node N2 remains a high-level signal, and the high-level signal of the first power terminal VGH passes through the conductive fifth node.
  • Transistor T5 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the working process of the shift register provided in Figure 9 may include:
  • the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signals at the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off
  • the tenth transistor T10 is turned on
  • the signal at the second node N2 remains a low-level signal
  • the third transistor T3 is turned on
  • the first power terminal The high-level signal of VGH is transmitted to the third node N3 through the turned-on third transistor T3, the sixth transistor T6 and the ninth transistor T9 are turned on, the eighth transistor T8 is turned off, and the low-level signal of the second power supply terminal VGL passes through
  • the turned-on ninth transistor T9 and the tenth transistor T10 are transmitted to the second node N2.
  • the signal of the second node N2 remains a low-level signal.
  • the low-level signal of the second power supply terminal VGL passes through the turned-on sixth transistor T6. Transmitted to the signal output terminal OUT.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal. Signal.
  • the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals at the second clock signal terminal CB are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 and the seventh transistor T7 are turned off.
  • the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the previous stage.
  • the low-level signal of the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the tenth transistor T10 is turned off
  • the low-level signal of the first node N1 passes through the turned-on second transistor T2 is transmitted to the second node N2
  • the third transistor T3 is turned on
  • the high-level signal of the first power terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3, and the sixth transistor T6 and the ninth transistor T9 are turned on.
  • the eighth transistor T8 is turned off.
  • the seventh transistor T7 and the eighth transistor T8 are both turned off, the high-level signal of the first power supply terminal VGH cannot be transmitted to the second node N2, and the signal of the second node N2 remains a low-level signal.
  • the low-level signal of the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal. Signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off
  • the tenth transistor T10 is turned on
  • the second node N2 maintains the low-level signal of the previous stage
  • the third transistor T3 is turned on
  • the first The high-level signal of the power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3, the sixth transistor T6 and the ninth transistor T9 are turned on, the eighth transistor T8 is turned off, and the low-level signal of the second power supply terminal VGL
  • the signal is transmitted to the second node N2 through the turned-on ninth transistor T9 and the tenth transistor T10.
  • the signal at the second node N2 remains a low-level signal.
  • the low-level signal of the second power supply terminal VGL passes through the turned-on sixth transistor T10.
  • Transistor T6 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is low-level. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the high-level signal of the previous stage, and the signal of the second clock signal terminal CB is a low-level signal.
  • the second transistor T2 is turned on, the tenth transistor T10 is turned off, the high level signal of the first node N1 is transmitted to the second node N2 through the turned on second transistor T2, the fourth transistor T4 is turned on, and the second power supply
  • the low-level signal at terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off.
  • the ninth transistor T9 and the tenth transistor T10 are all cut off, the low-level signal of the second power supply terminal VGL cannot be transmitted to the second node N2, the signal of the second node N2 remains a high-level signal, and the high-level signal of the first power supply terminal VGH passes through the conductive fifth node.
  • Transistor T5 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off
  • the tenth transistor T10 is turned on
  • the signal at the second node N2 remains the high-level signal in the previous stage
  • the fourth transistor T4 is turned on.
  • the low-level signal of the second power terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on, the fifth transistor T5 and the eighth transistor T8 are turned on, the ninth transistor T9 is turned off, and the first power terminal VGH
  • the high-level signal is transmitted to the second node N2 through the turned-on seventh transistor T7 and the eighth transistor T8.
  • the signal at the second node N2 remains a high-level signal.
  • the high-level signal of the first power supply terminal VGH is passed through the turned-on seventh transistor T7 and the eighth transistor T8.
  • the fifth transistor T5 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signals of the second clock signal terminal CB are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the high-level signal of the previous stage, and the signal of the second clock signal terminal CB is a low-level signal.
  • the second transistor T2 is turned on, the tenth transistor T10 is turned off, the high level signal of the first node N1 is transmitted to the second node N2 through the turned on second transistor T2, the fourth transistor T4 is turned on, and the second power supply
  • the low-level signal at terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off.
  • the ninth transistor T9 and the tenth transistor T10 are all cut off, the low-level signal of the second power supply terminal VGL cannot be transmitted to the second node N2, the signal of the second node N2 remains a high-level signal, and the high-level signal of the first power supply terminal VGH passes through the conductive fifth node.
  • Transistor T5 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a low-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off
  • the tenth transistor T10 is turned on
  • the second node N2 maintains the high-level signal of the previous stage
  • the fourth transistor T4 is turned on
  • the second transistor T10 is turned on.
  • the low level signal of the power supply terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, the ninth transistor T9 is turned off, and the high level of the first power supply terminal VGH
  • the signal is transmitted to the second node N2 through the seventh transistor T7 and the eighth transistor T8 that are turned on.
  • the signal at the second node N2 remains a high-level signal.
  • the high-level signal of the first power supply terminal VGH passes through the turned-on fifth transistor T8.
  • Transistor T5 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are low-level signals.
  • the signal at the first clock signal terminal CK is a high-level signal.
  • the first transistor T1 and the seventh transistor T7 are turned off.
  • the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1.
  • the first node N1 maintains the previous stage.
  • the high-level signal of the second clock signal terminal CB is a low-level signal
  • the second transistor T2 is turned on
  • the tenth transistor T10 is turned off
  • the high-level signal of the first node N1 passes through the turned-on second transistor T2 is transmitted to the second node N2
  • the fourth transistor T4 is turned on
  • the low-level signal of the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4, and the fifth transistor T5 and the eighth transistor T8 are turned on.
  • the ninth transistor T9 is turned off.
  • the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal of the second power supply terminal VGL cannot be transmitted to the second node N2, and the signal of the second node N2 remains a high-level signal.
  • the high-level signal of the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5.
  • the signal of the first node N1 is a high-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signals of the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signals of the second clock signal terminal CB are high-level signals.
  • the signal at the first clock signal terminal CK is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1.
  • the signal at the second clock signal terminal CB is a high-level signal
  • the second transistor T2 is turned off, the tenth transistor T10 is turned on, the second node N2 maintains the high-level signal of the previous stage, the fourth transistor T4 is turned on, and the second transistor T10 is turned on.
  • the low-level signal of the power supply terminal VGL is transmitted to the third node N3 through the fourth transistor T4 that is turned on.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 is turned off, the second transistor T9 is turned off.
  • the low-level signal of the power terminal VGL cannot be transmitted to the second node N2.
  • the signal of the second node N2 remains a high-level signal.
  • the high-level signal of the first power terminal VGH is transmitted to the signal through the turned-on fifth transistor T5. Output terminal OUT.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a high-level signal
  • the signal of the third node N3 is a low-level signal
  • the signal of the signal output terminal OUT is a high-level signal. Signal.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the signals of the second clock signal terminal CB and the signal input terminal IN are low-level signals.
  • the signal of the first clock signal terminal CK is a high-level signal
  • the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the low-level signal of the previous stage, and the signal of the second clock signal terminal CB is a low-level signal.
  • the second transistor T2 is turned on, the tenth transistor T10 is turned off, the low-level signal of the first node N1 is transmitted to the second node N2 through the turned-on second transistor T2, the third transistor T3 is turned on, and the first power supply
  • the high-level signal at terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3.
  • the sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off.
  • the seventh transistor T7 and the eighth transistor T8 are all cut off, the high-level signal of the first power supply terminal VGH cannot be transmitted to the second node N2, the signal of the second node N2 remains a low-level signal, and the low-level signal of the second power supply terminal VGL passes through the conductive sixth node.
  • Transistor T6 transmits to the signal output terminal OUT.
  • the signal of the first node N1 is a low-level signal
  • the signal of the second node N2 is a low-level signal
  • the signal of the third node N3 is a high-level signal
  • the signal of the signal output terminal OUT is a low-level signal. Signal.
  • Embodiments of the present disclosure also provide a display substrate, including: a display area and a non-display area.
  • the display substrate includes: a substrate and a circuit structure layer provided on the substrate.
  • the circuit structure layer includes: located in the non-display area.
  • the gate drive circuit includes: multiple cascaded shift registers.
  • the pixel circuit includes: a light-emitting signal line, a scanning signal line and a reset signal line;
  • the signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the i+1-th stage shift register, 1 ⁇ i ⁇ M-1, and M is the total number of stages of the shift register.
  • the gate driving circuit may be electrically connected to at least one of a light-emitting signal line, a scanning signal line, and a reset signal line.
  • the pixel circuit may be a 7T1C or 8T1C circuit structure, which is not limited in this disclosure.
  • the shift register can be a shift register provided in any of the foregoing embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.
  • each shift register drives several rows of sub-pixels, as long as a large-area device like this is changed, and after this change creates additional space, a simple translation of the small device is possible , stretching are all within the protection scope of the present disclosure.
  • the display substrate of the present disclosure can be applied to a display device with a gate driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot luminescence. Diode display (QDLED), etc., this disclosure is not limited here.
  • a gate driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot luminescence. Diode display (QDLED), etc., this disclosure is not limited here.
  • the circuit structure layer may further include: a pixel circuit and a reset signal line, a light emitting signal line and a scanning signal line connected to the pixel circuit.
  • the gate driving circuit may provide a signal for at least one of a reset signal line, a light emitting signal line, or a scanning signal line.
  • the display substrate may further include: a light-emitting structure layer disposed on a side of the circuit structure layer away from the substrate.
  • the light-emitting structure layer includes: light-emitting elements arranged in an array in the display area.
  • the light-emitting element may be an organic electroluminescent diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic electroluminescent diode
  • QLED quantum dot light-emitting diode
  • the OLED may include a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode).
  • the display substrate may also include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • FIG. 12 is a schematic structural diagram of a display substrate according to an exemplary embodiment.
  • the display substrate may further include: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VHL and a second power supply line extending along the first direction.
  • the line VLL, the first power line VHL, the second power line VLL, the first clock signal line CLK1 and the second clock signal line CLK2 are arranged along the second direction, and the first direction intersects the second direction.
  • the first power terminals of all shift registers are electrically connected to the first power line
  • the second power terminals of all shift registers are electrically connected to the second power line
  • the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock
  • the signal lines are electrically connected.
  • the second clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal line.
  • the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line.
  • the second clock signal terminal of the i+1 stage shift register is electrically connected to the first clock signal line.
  • the shift register includes: first to tenth transistors T1 to T10 and a capacitor C.
  • the capacitor C includes: a first plate and a second plate.
  • the circuit structure layer may include: a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the substrate. layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer;
  • the first semiconductor layer includes: an active layer of the first transistor, an active layer of the second transistor, an active layer of the third transistor, an active layer of the fifth transistor, an active layer of the seventh transistor, and an active layer of the eighth transistor. active layer;
  • the first conductive layer includes: the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, the control electrode of the fifth transistor, the control electrode of the seventh transistor, the control electrode of the eighth transistor, the control electrode of the capacitor.
  • the second conductive layer includes: a second plate of the capacitor
  • the second semiconductor layer includes: an active layer of the fourth transistor, an active layer of the sixth transistor, an active layer of the ninth transistor, and an active layer of the tenth transistor;
  • the third conductive layer includes: a control electrode of the fourth transistor, a control electrode of the sixth transistor, a control electrode of the ninth transistor and a control electrode of the tenth transistor;
  • the fourth conductive layer includes: a first clock signal line, a second clock signal line, a first power line, a second power line, first and second poles of the first transistor to first and second poles of the sixth transistor. pole, the first pole of the seventh transistor, the second pole of the eighth transistor, the first pole of the ninth transistor, the first pole of the tenth transistor, the first connection signal line, the second connection signal line and the third connection signal Wire;
  • the signal output line is respectively connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor; the first connection signal line is connected to the active layer of the third transistor and the control electrode of the ninth transistor respectively; the second connection signal line They are respectively connected to the active layer of the third transistor and the control electrode of the eighth transistor; the third connection signal line is respectively connected to the control electrode of the tenth transistor and the control electrode of the second transistor.
  • the fifth transistor T5 and the sixth transistor T6 are located on the same side of the first power line VHL, and the fifth transistor T5 and the sixth transistor T6 are arranged along the first direction. ;
  • the third transistor T3 is located on the side of the fifth transistor T5 away from the first power line VHL, the fourth transistor T4 is located on the side of the sixth transistor T6 away from the first power line VHL, the third transistor T3 and the fourth transistor T4 are located along the first power line VHL.
  • the third transistor T3 and the fifth transistor T5 are arranged in the second direction, the fourth transistor T4 and the sixth transistor T6 are arranged in the second direction; the eighth transistor T8 is located away from the third transistor T3 and the fifth transistor On one side of T5, the ninth transistor T9 is located on the side of the fourth transistor T4 away from the sixth transistor T6.
  • the eighth transistor T8 and the ninth transistor T9 are arranged along the first direction, and the third transistor T3 and the eighth transistor T8 are arranged along the first direction.
  • the fourth transistor T4 and the ninth transistor T9 are arranged along the second direction; the seventh transistor T7 is located on the side of the eighth transistor T8 away from the third transistor T3, and the tenth transistor T10 is located on the side away from the ninth transistor T9.
  • the seventh transistor T7 and the tenth transistor T10 are arranged along the first direction
  • the seventh transistor Y7 and the eighth transistor T8 are arranged along the second direction
  • the ninth transistor T9 and the tenth transistor T10 are arranged along the second direction.
  • the second transistor T2 is located between the seventh transistor T7 and the tenth transistor T10, the first transistor T1 is located on the side of the seventh transistor T7 away from the eighth transistor T8, and the capacitor C is located on the side of the tenth transistor T10 away from the ninth transistor.
  • One side of the transistor T9; the second power line VLL is located on the side of the capacitor C away from the tenth transistor T10, the first clock signal line CLK1 is located on the side of the second power line VLL away from the capacitor C, and the second clock signal line CLK2 is located on the side of the second power line VLL away from the tenth transistor T10.
  • a clock signal line CLK1 is on a side away from the second power line VLL.
  • the active layer of the first transistor and the active layer of the second transistor are an integrally formed structure, and the active layer of the seventh transistor and the active layer of the eighth transistor are an integrally formed structure;
  • the active layer of the third transistor includes: a first active connection part, a second active connection part and a third active connection part; the first active connection part and the third active connection part extend along the first direction, and the The two active connection parts extend along the second direction and are respectively connected to the first active connection part and the third active connection part;
  • the first active connection part is located on a side of the second active connection part close to the integrated structure of the active layer of the seventh transistor and the active layer of the eighth transistor, and the third active connection part is located on the second active connection part A side of the integrated structure away from the active layer of the seventh transistor and the active layer of the eighth transistor;
  • a straight line extending in the second direction passes through the first active connection and the active layer of the second transistor
  • a straight line extending in the second direction passes through the third active connection and the active layer of the first transistor.
  • the first plate of the capacitor includes: a first capacitor body part and a first capacitor connection part that are connected to each other;
  • the control electrode of the first transistor and the control electrode of the seventh transistor have an integrated structure and are located on the side of the first capacitor connection part away from the first capacitor main part;
  • the virtual straight line extending along the second direction passes through the control electrode of the eighth transistor and the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the virtual straight line extending along the second direction passes through the control electrode of the third transistor and the control electrode of the eighth transistor;
  • the virtual straight line extending in the second direction passes through the control electrode of the fifth transistor and the control electrode of the third transistor.
  • the virtual straight line extending in the second direction passes through the signal output line and the control electrode of the second transistor.
  • the second plate of the capacitor includes: a second capacitor body part and a second capacitor connection part that are connected to each other, and the second capacitor connection part is located on one side of the second capacitor body part;
  • the area of the first capacitor body part of the first plate of the capacitor is larger than the area of the second capacitor body part of the second plate of the capacitor;
  • the orthographic projection of the second capacitor main body part and the second capacitor connection part on the substrate at least partially overlaps with the orthographic projection of the first capacitor main body part of the first plate of the capacitor on the substrate, and overlaps with the orthographic projection of the first capacitor plate of the capacitor on the substrate. Orthographic projections of the first capacitor connecting portion on the substrate do not overlap.
  • the orthographic projection of the active layer of the sixth transistor on the substrate and the orthographic projection of the active layer of the fifth transistor on the substrate are respectively located opposite to the orthographic projection of the signal output line on the substrate. on both sides, and a straight line extending along the first direction passes through the active layer of the fifth transistor and the active layer of the sixth transistor;
  • a straight line extending in the first direction passes through the active layer of the fourth transistor and the third active connection portion of the active layer of the third transistor;
  • the straight line extending along the first direction passes through the active layer of the ninth transistor and the active layer of the eighth transistor, and the straight line extending along the first direction passes through the active layer of the tenth transistor and the active layer of the seventh transistor.
  • the virtual straight line extending in the second direction passes through the control electrode of the fourth transistor, the control electrode of the sixth transistor, and the control electrode of the ninth transistor;
  • the control electrode of the tenth transistor includes: a first electrode connection part, a second electrode connection part and a third electrode connection part.
  • the first electrode connecting part and the third electrode connecting part extend along the second direction, and the second electrode connecting part extends along the first direction and are connected to the first electrode connecting part and the third electrode connecting part respectively;
  • the first electrode connection part is located on a side of the second electrode connection part close to the control electrode of the ninth transistor, and the third electrode connection part is located on a side of the second electrode connection part away from the control electrode of the ninth transistor;
  • the virtual straight line extending in the second direction passes through the orthographic projection of the first electrode connection portion of the control electrode of the tenth transistor on the substrate and the orthographic projection of the first capacitor main body portion of the first plate of the capacitor on the substrate;
  • the orthographic projection of the third electrode connecting portion of the control electrode of the tenth transistor on the substrate is located at the orthographic projection of the first plate of the capacitor on the substrate and is far away from the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the side of the orthographic projection on the base is located at the orthographic projection of the first plate of the capacitor on the substrate and is far away from the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the fifth insulating layer is provided with a plurality of via hole patterns
  • the plurality of via hole patterns include: first via holes to The sixth via hole is the seventh to thirteenth via hole opened in the second to fifth insulating layers, the fourteenth via hole is opened in the third to fifth insulating layer, and the fourth via hole is opened in the fourth insulating layer.
  • the number of third via holes is four.
  • a virtual straight line extending along the first direction passes through the first third via hole and the second third via hole, and the first third via hole and the second third via hole
  • the via hole exposes the first active connection portion of the active layer of the third transistor
  • a virtual straight line extending in the first direction passes through the third third via hole and the fourth third via hole
  • the third third via hole The three via holes and the fourth third via hole expose the third active connection portion of the active layer of the third transistor
  • a virtual straight line extending in the second direction passes through the second third via hole and the third third via hole.
  • the number of the twenty-second via holes is two.
  • the first twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor.
  • the second twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor.
  • the first pole of the third transistor, the first pole of the fifth transistor, the first pole of the seventh transistor and the first power line are an integrally formed structure
  • the first pole of the fourth transistor The first pole of the sixth transistor, the first pole of the tenth transistor and the second power line have an integrally formed structure
  • the second pole of the first transistor and the first pole of the second transistor have an integrally formed structure
  • the second pole of the third transistor has an integrally formed structure
  • the second pole of the second transistor, the second pole of the eighth transistor, and the first pole of the ninth transistor are integrally formed, and the second pole of the fifth transistor and the sixth transistor are integrally formed.
  • the second pole of the transistor has an integrated structure
  • the orthographic projection of the first power line on the substrate at least partially overlaps the orthographic projection of the signal output line on the substrate; the orthographic projection of the second power line on the substrate overlaps with the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the orthographic projection of the integrated structure, the control electrode of the tenth transistor and the second capacitor connection portion of the second plate of the capacitor on the substrate overlap; the orthographic projection of the first clock signal line on the substrate and the control of the tenth transistor
  • the orthographic projection portion of the integrated structure of the control electrode of the first transistor and the control electrode of the seventh transistor overlaps on the substrate; the second clock signal line intersects the orthographic projection portion of the control electrode of the connected transistor on the substrate.
  • the orthographic projection of the integrated structure of the second pole of the first transistor and the first pole of the second transistor on the substrate overlaps with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate;
  • the orthographic projection of the integrated structure of the second electrode of the third transistor and the second electrode of the fourth transistor on the substrate partially overlaps with the orthographic projection of the control electrode of the sixth transistor and the control electrode of the fifth transistor on the substrate;
  • the orthographic projection of the integrated structure of the second pole of the five transistors and the second pole of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line on the substrate;
  • the second pole of the second transistor and the eighth transistor The orthographic projection of the integrated structure of the second electrode and the first electrode of the ninth transistor on the substrate partially overlaps the orthographic projection of the control electrode of the third transistor and the control electrode of the fourth transistor on the substrate; the first connection signal line
  • the orthographic projection on the substrate overlaps with the orthographic projection of the control electrode of the ninth transistor on the substrate; the orthographic
  • the first pole and the second pole of the third transistor are respectively connected to the active layer of the third transistor through the third third via hole and the fourth third via hole;
  • the first connection The signal line is connected to the active layer of the third transistor through the first third via hole;
  • the second connection signal line is connected to the active layer of the third transistor through the second third via hole;
  • the third connection signal line is connected to the active layer of the third transistor through the second third via hole.
  • a twenty-second via hole is connected to the control electrode of the tenth transistor; one of the first clock signal line and the second clock signal line is connected to the control electrode of the tenth transistor through the second twenty-second via hole. connect.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • FIGS. 13 to 18 illustrate using the example that the display substrate includes the shift register provided in FIG. 9 , that is, the shift register includes: the first transistor T1 to the tenth transistor T10 .
  • Forming a first semiconductor layer pattern on a substrate includes: depositing a first semiconductor film on the substrate, patterning the first semiconductor film through a patterning process, and forming a first semiconductor layer pattern. As shown in FIG. 13 , FIG. 13 is a schematic diagram after the first semiconductor layer pattern is formed.
  • the first semiconductor layer pattern may include: an active layer T11 of the first transistor, an active layer T21 of the second transistor, an active layer T31 of the third transistor, The active layer T51 of the fifth transistor, the active layer T71 of the seventh transistor, and the active layer T81 of the eighth transistor.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal chips; the flexible substrate may be, but is not limited to, polyparaphenylene.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
  • the first and second flexible material layers can be made of polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., used to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the materials of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the preparation process may include: first coating a layer of polyimide on a glass substrate, and then curing to form a film.
  • a first flexible (PI1) layer then deposit a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then deposit a layer of amorphous silicon on the first barrier layer Thin film to form an amorphous silicon (a-si) layer covering the first barrier layer; then apply a layer of polyimide on the amorphous silicon layer, and solidify the film to form a second flexible (PI2) layer; then Deposit a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, completing the preparation of the substrate.
  • the first semiconductor layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a -Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene and other various materials, that is, the present disclosure is applicable to transistors manufactured based on oxide Oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a -Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other various materials
  • the active layer T11 of the first transistor and the active layer T21 of the second transistor may be an integrally formed structure, and the active layer T71 of the seventh transistor and the eighth transistor The active layer T81 may be an integrally formed structure.
  • the active layer T11 of the first transistor extends along the first direction and may be in a strip structure
  • the active layer T21 of the second transistor extends along the second direction, And it can be in strip structure.
  • the integrated structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor may be an inverted "L" shape, and the opening of the inverted "L” shape faces the active layer T71 of the seventh transistor and the eighth transistor.
  • the active layer T71 of the seventh transistor may be of "n" type, and the active layer T81 of the eighth transistor may be of "L” type.
  • the integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor may be an "S-shape" rotated 90 degrees.
  • the active layer T31 of the third transistor may be located in the integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor, away from the first transistor.
  • the active layer T31 of the third transistor may include: a first active connection portion T31A, a second active connection portion T31B, and a third active connection portion T31C.
  • the first active connection part T31A and the third active connection part T31C extend along the first direction
  • the second active connection part T31B extends along the second direction, and are respectively connected with the first active connection part T31A and the third active connection part T31B.
  • the source connection part T31C is connected.
  • the first active connection part T31A and the third active connection part T31C are respectively located on opposite sides of the second active connection part T31B.
  • the first active connection part T31A is located on a side of the second active connection part T31B close to the integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor
  • the third active connection part T31C The second active connection portion T31B is located on a side away from the integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor.
  • a straight line extending in the second direction passes through the first active connection portion T31A and the active layer T21 of the second transistor.
  • a straight line extending in the second direction passes through the third active connection part T31C and the active layer T11 of the first transistor.
  • the active layer T51 of the fifth transistor is located away from the active layer T31 of the third transistor and away from the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor. one side of the integrally formed structure and extending along the first direction.
  • the active layer T51 of the fifth transistor may be square.
  • Figure 14A is a schematic diagram of the first conductive layer pattern
  • Figure 14B is a diagram of forming the first conductive layer pattern. Schematic diagram after.
  • the first conductive layer pattern may include: a control electrode T12 of the first transistor, a control electrode T22 of the second transistor, a control electrode T32 of the third transistor, The control electrode T52 of the fifth transistor, the control electrode T72 of the seventh transistor, the control electrode T82 of the eighth transistor, the first plate C1 of the capacitor and the signal output line OUTL.
  • the first conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a first gate insulating layer.
  • the first plate C1 of the capacitor may include: a first capacitor body part C11 and a first capacitor connection part C12 that are connected to each other.
  • the first capacitor connection part C12 is located on one side of the first capacitor main body part C11.
  • the area of the first capacitor connection part C12 is smaller than the area of the first capacitor main part C11 .
  • control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor are integrally formed structures.
  • the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor extends along the second direction and may be in a strip shape.
  • the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor may be located at the first capacitor connection portion C12 away from the first capacitor body. side of part C11.
  • control electrode T22 of the second transistor and the first plate C1 of the capacitor are located between the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor.
  • the control electrode T22 of the second transistor is located on the side of the first plate C1 of the capacitor close to the signal output line.
  • the control electrode T22 of the second transistor may be in an "L" shape rotated 90 degrees.
  • control electrode T82 of the eighth transistor may be located on one side of the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, And the virtual straight line extending along the second direction passes through the control electrode T82 of the eighth transistor and the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor.
  • control electrode T82 of the eighth transistor extends along the second direction and may be in a strip shape.
  • control electrode T32 of the third transistor may be located away from the control electrode T82 of the eighth transistor and away from the control electrode T12 of the first transistor and the control electrode of the seventh transistor.
  • One side of the integrated structure of T72, and the virtual straight line extending in the second direction passes through the control electrode T32 of the third transistor and the control electrode T82 of the eighth transistor.
  • control electrode T32 of the third transistor extends along the second direction and may be in a strip shape.
  • control electrode T52 of the fifth transistor may be located on a side of the control electrode T32 of the third transistor away from the control electrode T82 of the eighth transistor, and along the second The virtual straight line extending in the direction passes through the control electrode T52 of the fifth transistor and the control electrode T32 of the third transistor.
  • control electrode T52 of the fifth transistor extends along the second direction and may be in a strip shape.
  • the signal output line OUTL may be located on a side of the control electrode T22 of the second transistor away from the first plate C1 of the capacitor and extends in the second direction.
  • the virtual straight line passes through the signal output line OUTL and the control electrode T22 of the second transistor.
  • the signal output line OUTL extends along the second direction and may be in a strip shape.
  • the control electrode T12 of the first transistor is disposed across the active layer of the first transistor
  • the control electrode T22 of the second transistor is disposed across the active layer of the second transistor.
  • the control electrode T32 of the third transistor is disposed across the active layer of the third transistor
  • the control electrode T52 of the fifth transistor is disposed across the active layer of the fifth transistor
  • the control electrode T52 of the seventh transistor is disposed across the active layer of the third transistor.
  • T72 is disposed across the active layer of the seventh transistor
  • the control electrode T82 of the eighth transistor is disposed across the active layer of the eighth transistor. That is to say, the extension direction of the control electrode of at least one transistor is in line with the direction of the active layer. The extension directions are perpendicular to each other.
  • this process also includes a conductorization process.
  • the conductorization process is to use the semiconductor layer in the control electrode shielding area of multiple transistors (that is, the area where the semiconductor layer and the control electrode overlap) after forming the first conductive layer as the channel area of the transistor, which is not blocked by the first conductive layer.
  • the semiconductor layer in the area is processed into a conductive layer, forming the electrode connection portion of the transistor.
  • the interconnected electrode connection portions of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor in the present disclosure are processed into conductive layers to form a conductive layer that can be multiplexed as the seventh transistor.
  • the conductive structure of the second pole and the first pole of the eighth transistor are processed into conductive layers to form a conductive layer that can be multiplexed as the seventh transistor.
  • Figure 15A is a schematic diagram of the second conductive layer pattern.
  • Figure 15B after forming the second conductive layer pattern schematic diagram.
  • the second conductive layer pattern may include: a second plate C2 of the capacitor.
  • the second conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a second gate insulating layer.
  • the second plate C2 of the capacitor may include: a second capacitor body part C21 and a second capacitor connection part C22 that are connected to each other.
  • the second capacitor connecting portion C22 is located on one side of the second capacitor main body portion C21.
  • the shape of the second plate C2 of the capacitor may be "L" shaped.
  • the second capacitor main part C21 may be in a strip shape and extend along the second direction
  • the second capacitor connection part C22 may be in a strip shape and extend along the first direction.
  • the area of the first capacitor body part C11 of the first plate of the capacitor is larger than the area of the second capacitor body part C21 of the second plate of the capacitor.
  • the orthographic projection of the second capacitor main part C21 and the second capacitor connection part C22 on the substrate is consistent with the first capacitor main part of the first plate of the capacitor.
  • the orthographic projection on the substrate at least partially overlaps and does not overlap with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate.
  • Forming the second semiconductor layer pattern includes: depositing a third insulating film and a second semiconductor film on the substrate forming the aforementioned pattern, patterning the third insulating film and the second semiconductor film through a patterning process, and forming a third insulating film and a second semiconductor film.
  • FIGS. 16A and 16B FIG. 16A is a schematic diagram of the second semiconductor layer pattern.
  • FIG. 16B is a schematic diagram after the second semiconductor layer pattern is formed.
  • the second semiconductor layer pattern may include: an active layer T41 of the fourth transistor, an active layer T61 of the sixth transistor, an active layer T61 of the ninth transistor. layer T91 and the active layer T101 of the tenth transistor.
  • the second semiconductor layer may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, or an oxide containing titanium, indium and tin. oxides containing indium and zinc, oxides containing silicon and indium and tin, or oxides containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, or may be a double layer, or may be multiple layers.
  • the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the active layer T91 of the ninth transistor and the active layer T101 of the tenth transistor are an integrally formed structure.
  • the active layer T61 of the sixth transistor extends along the first direction and may be in a strip structure.
  • the orthographic projection of the active layer T61 of the sixth transistor on the substrate and the orthographic projection of the active layer T51 of the fifth transistor on the substrate are respectively located on opposite sides of the orthographic projection of the signal output line OUTL on the substrate, and along the The straight line extending in the first direction passes through the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor.
  • the orthographic projection of the active layer T51 of the fifth transistor on the substrate and the orthographic projection of the active layer T61 of the sixth transistor on the substrate may be arranged symmetrically along a virtual straight line extending in the second direction.
  • the active layer T41 of the fourth transistor extends along the first direction and may be in a strip structure.
  • the straight line extending in the first direction passes through the active layer T41 of the fourth transistor and the third active connection portion of the active layer T31 of the third transistor.
  • the orthographic projection of the active layer T41 of the fourth transistor on the substrate and the orthographic projection of the third active connection portion of the active layer T31 of the third transistor on the substrate may be along the second direction. Extended virtual straight line symmetry set.
  • the active layer T91 of the ninth transistor may be an inverted "L" type, and the active layer T101 of the tenth transistor may be an "n" type.
  • the straight line extending along the first direction passes through the active layer T91 of the ninth transistor and the active layer T81 of the eighth transistor, and the straight line extending along the first direction passes through the active layer T101 of the tenth transistor and the active layer of the seventh transistor. T71.
  • the orthographic projection of the active layer T91 of the ninth transistor on the substrate and the orthographic projection of the active layer T81 of the eighth transistor on the substrate may be arranged symmetrically along a virtual straight line extending in the second direction.
  • FIG. 17A is a schematic diagram of the third conductive layer pattern
  • Figure 17B is a diagram of forming the third conductive layer pattern. Schematic diagram after.
  • the third conductive layer pattern may include: a control electrode T42 of the fourth transistor, a control electrode T62 of the sixth transistor, a control electrode T92 of the ninth transistor, and The control electrode of the tenth transistor T102.
  • the third conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo) or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo) or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor extend along the second direction and may be strip-shaped.
  • the control electrode T42 of the fourth transistor is located on one side of the control electrode T62 of the sixth transistor, and the virtual straight line extending in the second direction passes through the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor.
  • the control electrode T92 of the ninth transistor extends along the second direction and may be in a strip shape.
  • the control electrode T92 of the ninth transistor may be located on a side of the control electrode T42 of the fourth transistor away from the control electrode T62 of the sixth transistor, and a virtual straight line extending in the second direction passes through the control electrode T42 of the fourth transistor and the control electrode T42 of the ninth transistor. Control pole T92.
  • control electrode T102 of the tenth transistor may be located on a side of the control electrode T92 of the ninth transistor away from the control electrode T42 of the fourth transistor.
  • the control electrode T102 of the tenth transistor may include: a first electrode connection part T102A, a second electrode connection part T102B, and a third electrode connection part T102C.
  • the first electrode connection part T102A and the third electrode connection part T102C extend along the second direction, and the second electrode connection part T102B extends along the first direction and are connected to the first electrode connection part T102A and the third electrode connection part T102C respectively.
  • the first electrode connection part T102A and the third electrode connection part T102C are respectively located on opposite sides of the second electrode connection part T102B, and the first electrode connection part The portion T102A may be located on a side of the second electrode connection portion T102B close to the control electrode T92 of the ninth transistor, and the third electrode connection portion T102C may be located on a side of the second electrode connection portion T102B away from the control electrode T92 of the ninth transistor.
  • a virtual straight line extending in the second direction passes through the orthographic projection of the first electrode connection portion T102A of the control electrode T102 of the tenth transistor on the substrate and the capacitance.
  • the orthographic projection of the third electrode connection portion T102C of the control electrode T102 of the tenth transistor on the substrate is located at the orthographic projection of the first plate of the capacitor on the substrate and is far away from the control electrode of the first transistor and the control electrode of the seventh transistor.
  • the side of the orthographic projection of the structure on the substrate is provided.
  • the control electrode T42 of the fourth transistor is disposed across the active layer T41 of the fourth transistor
  • the control electrode T62 of the sixth transistor is disposed across the sixth transistor.
  • the control electrode T92 of the ninth transistor is arranged across the active layer T91 of the ninth transistor
  • the control electrode T102 of the tenth transistor is arranged across the active layer T101 of the tenth transistor, that is, That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.
  • this process also includes a conductorization process.
  • the conductorization process is to use the second semiconductor layer in the control electrode shielding area of multiple transistors (that is, the area where the semiconductor layer and the control electrode overlap) after forming the third conductive layer as the channel area of the transistor, which is not covered by the third conductive layer.
  • the semiconductor layer in the layer shielding area is processed into a conductive layer to form the electrode connection portion of the transistor.
  • the interconnected electrode connection portions of the active layer T91 of the ninth transistor and the active layer T101 of the tenth transistor in the present disclosure are processed into conductive layers, forming a conductive layer that can be multiplexed as a ninth transistor.
  • the conductive structure of the second pole and the second pole of the tenth transistor are processed into conductive layers, forming a conductive layer that can be multiplexed as a ninth transistor.
  • Forming a fifth insulating layer pattern including: depositing a third insulating film on the substrate with the aforementioned pattern, patterning the fifth insulating film through a patterning process, and forming a fifth insulating layer pattern covering the aforementioned structure,
  • the fifth insulating layer is provided with a plurality of via hole patterns, as shown in Figure 18.
  • Figure 18 is a schematic diagram after forming the fifth insulating layer pattern.
  • the plurality of via hole patterns may include: first to sixth via holes V1 opened in the first insulating layer, the second insulating layer and the fifth insulating layer.
  • V6 the seventh via hole V7 to the thirteenth via hole V13 opened in the second to fifth insulating layers
  • the fourteenth via hole V14 opened in the third to fifth insulating layers
  • the fourth via V14 in the fourth insulating layer.
  • the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a second gate insulating layer.
  • the first via V1 exposes the active layer T11 of the first transistor
  • the second via V2 exposes the active layer T21 of the second transistor
  • the third via V3 exposes the active layer T21 of the third transistor.
  • Source layer T31, the fourth via V4 exposes the active layer T51 of the fifth transistor
  • the fifth via V5 exposes the active layer T71 of the seventh transistor
  • the sixth via V6 exposes the active layer of the eighth transistor.
  • the seventh via V7 exposes the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor
  • the eighth via V8 exposes the control electrode T22 of the second transistor
  • the ninth via V9 exposes The control electrode T32 of the third transistor is exposed
  • the tenth via hole V10 exposes the control electrode T52 of the fifth transistor
  • the eleventh via hole V11 exposes the control electrode T82 of the eighth transistor
  • the twelfth via hole V12 exposes the control electrode T82 of the capacitor.
  • the first plate C1, the thirteenth via V13 exposes the signal output line OUTL, the fourteenth via V14 exposes the second plate C2 of the capacitor; the fifteenth via V15 exposes the active layer of the fourth transistor T41, the sixteenth via V16 exposes the active layer T61 of the sixth transistor, the seventeenth via V17 exposes the active layer T91 of the ninth transistor, and the eighteenth via V18 exposes the active layer T91 of the tenth transistor.
  • the nineteenth via V19 exposes the control electrode T42 of the fourth transistor, the twentieth via V20 exposes the control electrode T62 of the sixth transistor, and the twenty-first via V21 exposes the control electrode of the ninth transistor.
  • T92, the twenty-second via V22 exposes the control electrode T102 of the tenth transistor.
  • the number of third vias V3 is four, and a virtual straight line extending in the first direction passes through the first third via and the second third via. hole, and the first third via hole and the second third via hole expose the first active connection portion of the active layer T31 of the third transistor, and a virtual straight line extending in the first direction passes through the third third via hole.
  • An extended virtual straight line passes through the second tertiary via and the third tertiary via.
  • the number of fourth via holes V4 is multiple, and the plurality of fourth via holes V4 are arranged in an array.
  • the number of the thirteenth via holes V13 may be multiple, and the plurality of the thirteenth via holes V13 are arranged along the second direction.
  • the number of sixteenth via holes V16 is multiple, and the plurality of sixteenth via holes V16 are arranged in an array.
  • the number of the twenty-second via hole V22 may be two, and the first twenty-second via hole exposes the second part of the control electrode T102 of the tenth transistor.
  • the second twenty-two via holes expose the third electrode connection part of the control electrode T102 of the tenth transistor.
  • Forming a fourth conductive layer pattern includes: depositing a fourth metal film on the substrate on which the foregoing pattern is formed, patterning the fourth metal film through a patterning process, and forming a fourth metal layer pattern, as shown in Figure 19A and Figure 19A.
  • FIG. 19A is a schematic diagram of the fourth conductive layer pattern
  • FIG. 19B is a schematic diagram after the fourth conductive layer pattern is formed.
  • the fourth conductive layer pattern may include: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VHL, a second power line VLL, the first pole T13 and the second pole T14 of the first transistor to the first pole T63 and the second pole T64 of the sixth transistor, the first pole T73 of the seventh transistor, the second pole T84 of the eighth transistor, the ninth The first pole T93 of the transistor, the first pole T103 of the tenth transistor, the first connection signal line L1, the second connection signal line L2 and the third connection signal line L3.
  • the fourth conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the first pole T33 of the third transistor, the first pole T53 of the fifth transistor, the first pole T73 of the seventh transistor and the first power line VHL It is an integrally formed structure.
  • the first electrode T43 of the fourth transistor, the first electrode T63 of the sixth transistor, the first electrode T103 of the tenth transistor and the second power line VLL are an integrally formed structure.
  • the second electrode T14 of the first transistor The first electrode T23 of the second transistor is an integrally formed structure.
  • the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor are integrally formed.
  • the second electrode T24 of the second transistor and the third electrode of the eighth transistor are integrally formed.
  • the diode T84 and the first pole T93 of the ninth transistor have an integrally formed structure
  • the second pole T54 of the fifth transistor and the second pole T64 of the sixth transistor have an integrally formed structure.
  • the first power line VHL is located at the second pole T54 of the fifth transistor and the integrated structure of the second pole T64 of the sixth transistor is away from the second power line.
  • the second power line VLL is located on the side of the integrated structure of the second pole T14 of the first transistor and the first pole T23 of the second transistor away from the first power line VHL
  • the first clock signal line CLK1 is located on the side of the integrated structure of the first transistor T14 and the first pole T23 of the second transistor.
  • the second power line VLL is located on a side away from the first power line VHL
  • the second clock signal line CLK2 is located on a side of the first clock signal line CLK1 away from the second power line VLL.
  • the first power line VHL extends along the first direction and may be in a strip shape.
  • the orthographic projection of the first power line VHL on the substrate at least partially overlaps the orthographic projection of the signal output line OUTL on the substrate.
  • the first electrode T33 of the third transistor, the first electrode T53 of the fifth transistor, and the first electrode T73 of the seventh transistor extend along the second direction, And the first pole T33 of the third transistor, the first pole T53 of the fifth transistor, and the first pole T73 of the seventh transistor are located on the side of the first power line VHL close to the second power line VLL.
  • the second power line VLL extends along the first direction and may be in a strip shape.
  • the orthographic projection of the second power line VLL on the substrate is integrated with the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, the control electrode of the tenth transistor, and the second capacitor of the second plate C2 of the capacitor.
  • the orthographic projections of the connections on the base partially overlap.
  • the first electrode T43 of the fourth transistor, the first electrode T63 of the sixth transistor, and the first electrode T103 of the tenth transistor extend along the second direction, And the first pole T43 of the fourth transistor, the first pole T63 of the sixth transistor, and the first pole T103 of the tenth transistor are located on the side of the second power line VLL close to the first power line VHL.
  • the first clock signal line CLK1 extends along the first direction and may be in a strip shape.
  • the orthographic projection of the first clock signal line CLK1 on the substrate overlaps with the orthographic projection of the control electrode T102 of the tenth transistor and the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor on the substrate.
  • the second clock signal line CLK2 extends along the first direction and may be in a strip shape.
  • the second clock signal line CLK2 overlaps with the orthographic projection portion of the control electrode T102 of the tenth transistor or the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor on the substrate.
  • the orthographic projection of the second clock signal line CLK2 on the substrate partially overlaps the orthographic projection of the control electrode T102 of the tenth transistor on the substrate.
  • the orthographic projection of the second clock signal line CLK2 on the substrate is in contact with the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor.
  • the one-piece structure partially overlaps the orthographic projection on the base.
  • 19A and 19B illustrate using an example where the orthographic projection of the second clock signal line CLK2 on the substrate overlaps with the orthographic projection of the control electrode T102 of the tenth transistor on the substrate.
  • the integrated structure of the second pole T14 of the first transistor and the first pole T23 of the second transistor may be an "L" shape, and the first transistor
  • the orthographic projection of the integrated structure of the second pole T14 and the first pole T23 of the second transistor on the substrate overlaps with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate.
  • the integrated structure of the second pole T34 of the third transistor and the second pole T44 of the fourth transistor may be an "I" shape rotated 90 degrees.
  • the orthographic projection of the integrated structure of the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor on the substrate is the same as the orthographic projection of the control electrode T62 of the sixth transistor and the control electrode T52 of the fifth transistor on the substrate. The projections partially overlap.
  • the integrated structure of the second pole T54 of the fifth transistor and the second pole T64 of the sixth transistor extends along the first direction and may be strip-shaped.
  • the orthographic projection of the integrated structure of the second pole T54 of the fifth transistor and the second pole T64 of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line OUTL on the substrate.
  • the integrated structure of the second pole T24 of the second transistor, the second pole T84 of the eighth transistor, and the first pole T93 of the ninth transistor may be
  • the "earth" shape is rotated 90 degrees, and the orthographic projection of the integrated structure of the second pole T24 of the second transistor, the second pole T84 of the eighth transistor, and the first pole T93 of the ninth transistor on the substrate is the same as the third
  • the control electrode T32 of the transistor and the control electrode T42 of the fourth transistor overlap in their orthographic projections on the substrate.
  • the first connection signal line L1 extends along the first direction and may be in a strip shape.
  • the orthographic projection of the first connection signal line L1 on the substrate partially overlaps the orthographic projection of the control electrode T92 of the ninth transistor on the substrate.
  • the second connection signal line L2 extends along the first direction and may be in a strip shape.
  • the orthographic projection of the second connection signal line L2 on the substrate partially overlaps the orthographic projection of the control electrode T82 of the eighth transistor on the substrate.
  • the third connection signal line L3 extends along the first direction and may be in a strip shape.
  • the orthographic projection of the third connection signal line L3 on the substrate partially overlaps with the orthographic projection of the control electrode T22 of the second transistor and the control electrode T102 of the tenth transistor on the substrate.
  • the first electrode T13 and the second electrode T14 of the first transistor are connected to the active layer of the first transistor through the first via hole, and the second electrode of the second transistor is connected to the active layer of the first transistor.
  • the first pole T23 and the second pole T24 of the second transistor are connected to the active layer of the second transistor through the second via hole, and the first pole T33 and the second pole T34 of the third transistor are respectively connected through the third third via hole.
  • the fourth third via hole is connected to the active layer of the third transistor, and the first electrode T43 and the second electrode T44 of the fourth transistor are connected to the exposed active layer of the fourth transistor through the fifteenth via hole.
  • the first pole T53 and the second pole T55 of the fifth transistor are connected to the active layer of the fifth transistor through the fourth via hole, and the first pole T63 and the second pole T65 of the sixth transistor are connected to the sixth transistor through the sixteenth via hole.
  • the active layer of the seventh transistor is connected, the first electrode T73 of the seventh transistor is connected to the active layer of the seventh transistor through the fifth via hole, and the second electrode T84 of the eighth transistor is connected to the active layer of the eighth transistor through the sixth via hole.
  • connection, the first pole T93 of the ninth transistor is connected to the active layer of the ninth transistor through the seventeenth via hole, and the first pole T103 of the tenth transistor is connected to the active layer of the tenth transistor through the eighteenth via hole.
  • the integrated structure of the second pole T14 of the first transistor and the first pole T23 of the second transistor is connected to the first plate C1 of the capacitor through the twelfth via hole.
  • the integrated structure of the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor is connected to the control electrode T62 of the sixth transistor through the twentieth via hole, and is connected to the control electrode T62 of the fifth transistor through the tenth via hole. T52 connection.
  • the second electrode T24 of the second transistor, the second electrode T84 of the eighth transistor, and the first electrode T93 of the ninth transistor are integrally formed structures and are connected to the control electrode T42 of the fourth transistor through the nineteenth via hole. , and passes through the ninth via hole and the control electrode T32 of the third transistor.
  • the integrated structure of the second pole T54 of the fifth transistor and the second pole T64 of the sixth transistor is connected to the signal output line OUTL through the thirteenth via hole.
  • the first connection signal line L1 is connected to the active layer of the third transistor through the first third via hole, and is connected to the control electrode T92 of the ninth transistor through the twenty-first via hole.
  • the second connection signal line L2 is connected to the active layer of the third transistor through the second third via hole, and is connected to the control electrode T82 of the eighth transistor through the eleventh via hole V11.
  • the third connection signal line L3 is connected to the control electrode T102 of the tenth transistor through the first 22nd via hole, and is connected to the control electrode T22 of the second transistor through the eighth via hole.
  • One of the first clock signal line and the second clock signal line CLK2 is connected to the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor through a seventh via hole.
  • the other signal line among the first clock signal line and the second clock signal line CLK2 is connected to the control electrode T102 of the tenth transistor through the second twenty-second via hole.
  • the second power line VLL is connected to the second plate C2 of the capacitor through the fourteenth via hole.
  • control electrode T92 of the ninth transistor is connected to the second electrode and the second electrode of the third transistor through the first connection signal line L1 and the active layer of the third transistor.
  • the second pole of the four transistors is connected in a monolithic structure.
  • control electrode T82 of the eighth transistor is connected to the second electrode and the second electrode of the third transistor through the second connection signal line L2 and the active layer of the third transistor.
  • the second pole of the four transistors is connected in a monolithic structure.
  • An embodiment of the present disclosure also provides a display device, which may include a display substrate.
  • the display substrate is the display substrate provided in any of the foregoing embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.
  • the display device may be a Liquid Crystal Display (LCD for short) or an Organic Light Emitting Diode (OLED for short) display device.
  • the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED for short) panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, and a digital photo frame. , navigator and other products or components with display functions.
  • Embodiments of the present disclosure also provide a method for driving a shift register, which is configured to drive the shift register.
  • the method includes the following steps:
  • Step 100 The storage sub-circuit stores the voltage difference between the signal of the first node and the signal of the first power terminal;
  • Step 200 The node control subcircuit provides the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and provides the signal of the first node to the second node under the control of the second clock signal terminal;
  • Step 300 The output control subcircuit provides the signal of the first power terminal or the second power terminal to the signal output terminal under the control of the second node.
  • the shift register is a shift register provided in any of the foregoing embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.

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Abstract

一种移位寄存器及其驱动方法、显示基板、显示装置，移位寄存器包括：存储子电路、节点控制子电路和输出控制子电路；存储子电路，分别与第一节点和第一电源端电连接，设置为存储第一节点的信号和第一电源端的信号之间的电压差；节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一节点和第二节点电连接，设置为在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；输出控制子电路，分别与第二节点、第一电源端、第二电源端和信号输出端电连接，设置为在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。

Description

移位寄存器及其驱动方法、显示基板、显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种移位寄存器及其驱动方法、显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种移位寄存器，包括：存储子电路、节点控制子电路和输出控制子电路；
所述存储子电路，分别与第一节点和第一电源端电连接，设置为存储第一节点的信号和第一电源端的信号之间的电压差；
所述节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一节点和第二节点电连接，设置为在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；
所述输出控制子电路，分别与第二节点、第一电源端、第二电源端和信号输出端电连接，设置为在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
在一些可能的实现方式中，所述输出控制子电路包括：第一输出控制子电路和第二输出控制子电路；
所述第一输出控制子电路，分别与第二节点、第三节点、第一电源端和第二电源端电连接，设置为在第二节点的控制下，向第三节点提供第一电源端或第二电源端的信号；
所述第二输出控制子电路，分别与第三节点、第一电源端、第二电源端和信号输出端电连接，设置为在第三节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
在一些可能的实现方式中，还包括：降噪子电路；
所述降噪子电路，分别与第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、第二节点和第三节点电连接，设置为在第一时钟信号端、第二时钟信号端和第三节点的控制下，向第二节点提供第一电源端或第二电源端的信号。
在一些可能的实现方式中，所述存储子电路包括：电容，电容包括：第一极板和第二极板；
电容的第一极板与第一节点电连接，电容的第二极板与第一电源端电连接。
在一些可能的实现方式中，所述节点控制子电路包括：第一晶体管和第二晶体管；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第二时钟信号端电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第二节点电连接。
在一些可能的实现方式中，所述第一输出控制子电路包括：第三晶体管和第四晶体管，所述第二输出控制子电路包括：第五晶体管和第六晶体管；
第三晶体管的控制极与第二节点电连接，第三晶体管的第一极与第一电源端电连接，第三晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电 源端电连接，第四晶体管的第二极与第三节点电连接；
第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与信号输出端电连接；
第六晶体管的控制极与第三节点电连接，第六晶体管的第一极与第二电源端电连接，第六晶体管的第二极与信号输出端电连接；
所述第三晶体管和所述第四晶体管的晶体管类型相反，所述第五晶体管和第六晶体管的晶体管类型相反。
在一些可能的实现方式中，所述降噪子电路包括：第七晶体管、第八晶体管、第九晶体管和第十晶体管；
第七晶体管的控制极与第一时钟信号端电连接，第七晶体管的第一极与第一电源端电连接，第七晶体管的第二极与第八晶体管的第一极电连接；
第八晶体管的控制极与第三节点电连接，第八晶体管的第二极与第二节点电连接；
第九晶体管的控制极与第三节点电连接，第九晶体管的第一极与第二节点电连接，第九晶体管的第二极与第十晶体管的第二极电连接；
第十晶体管的控制极与第二时钟信号端电连接，第十晶体管的第一极与第二电源端电连接；
第七晶体管和第八晶体管的晶体管类型相同，第九晶体管和第十晶体管的晶体管类型相同，第七晶体管和第九晶体管的晶体管类型相反。
在一些可能的实现方式中，所述存储子电路包括：电容，电容包括：第一极板和第二极板；所述节点控制子电路包括：第一晶体管和第二晶体管；所述输出控制子电路包括：第三晶体管、第四晶体管、五晶体管和第六晶体管
电容的第一极板与第一节点电连接，电容的第二极板与第一电源端电连接；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第二时钟信号端电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第二节点电连接，第三晶体管的第一极与第一电源端电连接，第三晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第三节点电连接；
第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与信号输出端电连接；
第六晶体管的控制极与第三节点电连接，第六晶体管的第一极与第二电源端电连接，第六晶体管的第二极与信号输出端电连接；
第一晶体管、第二晶体管、第三晶体管和第五晶体管为P型晶体管，第四晶体管和第六晶体管为N型晶体管，且为氧化物晶体管。
在一些可能的实现方式中，还包括：降噪子电路，所述存储子电路包括：电容，电容包括：第一极板和第二极板；所述节点控制子电路包括：第一晶体管和第二晶体管；所述输出控制子电路包括：第三晶体管、第四晶体管、五晶体管和第六晶体管；所述降噪子电路包括：第七晶体管、第八晶体管、第九晶体管和第十晶体管；
电容的第一极板与第一节点电连接，电容的第二极板与第一电源端电连接；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第二时钟信号端电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第二节点电连接，第三晶体管的第一极与第一电源端电连接，第三晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第三节点电连接；
第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第一电 源端电连接，第五晶体管的第二极与信号输出端电连接；
第六晶体管的控制极与第三节点电连接，第六晶体管的第一极与第二电源端电连接，第六晶体管的第二极与信号输出端电连接；
第七晶体管的控制极与第一时钟信号端电连接，第七晶体管的第一极与第一电源端电连接，第七晶体管的第二极与第八晶体管的第一极电连接；
第八晶体管的控制极与第三节点电连接，第八晶体管的第二极与第二节点电连接；
第九晶体管的控制极与第三节点电连接，第九晶体管的第一极与第二节点电连接，第九晶体管的第二极与第十晶体管的第二极电连接；
第十晶体管的控制极与第二时钟信号端电连接，第十晶体管的第一极与第二电源端电连接；
第一晶体管、第二晶体管、第三晶体管、第五晶体管、第七晶体管和第八晶体管为P型晶体管，第四晶体管、第六晶体管、第九晶体管和第十晶体管为N型晶体管，且为氧化物晶体管。
在一些可能的实现方式中，所述第一时钟信号端的时钟信号和所述第二时钟信号端的时钟信号互为反相信号；
所述信号输入端的信号为第一脉冲信号，所述第一脉冲信号的持续时间等于所述第一时钟信号端的时钟信号的周期，
所述信号输出端的信号为第二脉冲信号，所述第二脉冲信号的持续时间等于所述第一脉冲信号的持续时间，且所述第二脉冲信号的开始时间为所述第一脉冲信号的结束时间。
在一些可能的实现方式中，所述第一时钟信号端的时钟信号和所述第二时钟信号端的时钟信号互为反相信号；
所述信号输入端的信号为第三脉冲信号，所述第三脉冲信号的持续时间等于所述第一时钟信号端的时钟信号的周期的N倍，N为大于或者等于2的正整数；
所述信号输出端的信号为第四脉冲信号，所述第四脉冲信号的持续时间等于所述第三脉冲信号的持续时间，且所述第四脉冲信号的开始时间与所述 第三脉冲信号的开始时间之差等于所述第一时钟信号端的时钟信号的周期。
第二方面，本公开还提供了一种显示基板，包括：显示区域和非显示区域，所述显示基板包括：基底以及设置在所述基底上的电路结构层，所述电路结构层包括：位于非显示区域的栅极驱动电路和位于显示区域的阵列排布的像素电路，栅极驱动电路包括：多个级联的上述移位寄存器，像素电路包括：发光信号线、扫描信号线和复位信号线；
第i级移位寄存器的信号输出端与第i+1级移位寄存器的信号输入端电连接，1≤i≤M-1，M为移位寄存器的总级数；
所述栅极驱动电路与发光信号线、扫描信号线和复位信号线中的至少一种信号线电连接。
在一些可能的实现方式中，还包括：沿第一方向延伸的第一时钟信号线、第二时钟信号线、第一电源线和第二电源线，第一电源线、第二电源线、第一时钟信号线和第二时钟信号线沿第二方向排布，所述第一方向与所述第二方向相交；
所有移位寄存器的第一电源端与第一电源线电连接，所有移位寄存器的第二电源端与第二电源线电连接，第i级移位寄存器的第一时钟信号端与第一时钟信号线电连接，第i级移位寄存器的第二时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第一时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第二时钟信号端与第一时钟信号线电连接。
在一些可能的实现方式中，所述移位寄存器包括：第一晶体管至第十晶体管以及电容，电容包括：第一极板和第二极板；所述电路结构层包括：依次叠设在基底上的第一半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第二半导体层、第四绝缘层、第三导电层、第五绝缘层和第四导电层；
所述第一半导体层包括：第一晶体管的有源层、第二晶体管的有源层、第三晶体管的有源层、第五晶体管的有源层、第七晶体管的有源层和第八晶体管的有源层；
所述第一导电层包括：第一晶体管的控制极、第二晶体管的控制极、第 三晶体管的控制极、第五晶体管的控制极、第七晶体管的控制极、第八晶体管的控制极、电容的第一极板和信号输出线；
所述第二导电层包括：电容的第二极板；
所述第二半导体层包括：第四晶体管的有源层、第六晶体管的有源层、第九晶体管的有源层和第十晶体管的有源层；
所述第三导电层包括：第四晶体管的控制极、第六晶体管的控制极、第九晶体管的控制极和第十晶体管的控制极；
所述第四导电层包括：第一时钟信号线、第二时钟信号线、第一电源线、第二电源线、第一晶体管的第一极和第二极至第六晶体管的第一极和第二极、第七晶体管的第一极、第八晶体管的第二极、第九晶体管的第一极、第十晶体管的第一极、第一连接信号线、第二连接信号线和第三连接信号线；
信号输出线分别与第五晶体管的第二极和第六晶体管的第二极连接；
第一连接信号线分别与第三晶体管的有源层和第九晶体管的控制极连接；
第二连接信号线分别与第三晶体管的有源层和第八晶体管的控制极连接；
第三连接信号线分别与第十晶体管的控制极和第二晶体管的控制极连接。
在一些可能的实现方式中，第五晶体管和第六晶体管位于第一电源线的同一侧，且第五晶体管和第六晶体管沿第一方向排布；
第三晶体管位于第五晶体管远离第一电源线的一侧，第四晶体管位于第六晶体管远离第一电源线的一侧，第三晶体管和第四晶体管沿第一方向排布。第三晶体管和第五晶体管沿第二方向排布，第四晶体管和第六晶体管沿第二方向排布；
第八晶体管位于第三晶体管远离第五晶体管的一侧，第九晶体管位于第四晶体管远离第六晶体管的一侧，第八晶体管和第九晶体管沿第一方向排布，第三晶体管和第八晶体管沿第二方向排布，第四晶体管和第九晶体管沿第二方向排布；
第七晶体管位于第八晶体管远离第三晶体管的一侧，第十晶体管位于第九晶体管远离第四晶体管的一侧，第七晶体管和第十晶体管沿第一方向排布，第七晶体管和第八晶体管沿第二方向排布，第九晶体管和第十晶体管沿第二 方向排布；
第二晶体管位于第七晶体管和第十晶体管之间，第一晶体管位于第七晶体管远离第八晶体管的一侧，电容位于第十晶体管远离第九晶体管的一侧；
第二电源线位于电容远离第十晶体管的一侧，第一时钟信号线位于第二电源线远离电容的一侧，第二时钟信号线位于第一时钟信号线远离第二电源线的一侧。
在一些可能的实现方式中，第一晶体管的有源层和第二晶体管的有源层为一体成型结构，第七晶体管的有源层与第八晶体管的有源层为一体成型结构；
第三晶体管的有源层包括：第一有源连接部、第二有源连接部和第三有源连接部；第一有源连接部和第三有源连接部沿第一方向延伸，第二有源连接部沿第二方向延伸，且分别与第一有源连接部和第三有源连接部连接；
第一有源连接部位于第二有源连接部靠近第七晶体管的有源层与第八晶体管的有源层的一体成型结构的一侧，第三有源连接部位于第二有源连接部远离第七晶体管的有源层与第八晶体管的有源层的一体成型结构的一侧；
沿第二方向延伸的直线经过第一有源连接部和第二晶体管的有源层；
沿第二方向延伸的直线经过第三有源连接部和第一晶体管的有源层。
在一些可能的实现方式中，电容的第一极板包括：相互连接的第一电容主体部和第一电容连接部；
第一晶体管的控制极和第七晶体管的控制极为一体成型结构，且位于第一电容连接部远离第一电容主体部的一侧；
沿第二方向延伸的虚拟直线经过第八晶体管的控制极以及第一晶体管的控制极和第七晶体管的控制极的一体成型结构。
沿第二方向延伸的虚拟直线经过第三晶体管的控制极和第八晶体管的控制极；
沿第二方向延伸的虚拟直线经过第五晶体管的控制极和第三晶体管的控制极。
沿第二方向延伸的虚拟直线经过信号输出线和第二晶体管的控制极。
在一些可能的实现方式中，电容的第二极板包括：相互连接的第二电容主体部和第二电容连接部，第二电容连接部位于第二电容主体部的一侧；
电容的第一极板的第一电容主体部的面积大于电容的第二极板的第二电容主体部的面积；
第二电容主体部和第二电容连接部在基底上的正投影与电容的第一极板的第一电容主体部在基底上的正投影至少部分交叠，且与电容的第一极板的第一电容连接部在基底上的正投影不交叠。
在一些可能的实现方式中，第六晶体管的有源层在基底上的正投影与第五晶体管的有源层在基底上的正投影分别位于信号输出线在基底上的正投影的相对设置的两侧，且沿第一方向延伸的直线经过第五晶体管的有源层和第六晶体管的有源层；
沿第一方向延伸的直线经过第四晶体管的有源层和第三晶体管的有源层的第三有源连接部；
沿第一方向延伸的直线经过第九晶体管的有源层和第八晶体管的有源层，沿第一方向延伸的直线经过第十晶体管的有源层和第七晶体管的有源层。
在一些可能的实现方式中，沿第二方向延伸的虚拟直线经过第四晶体管的控制极、第六晶体管的控制极和第九晶体管的控制极；
第十晶体管的控制极包括：第一电极连接部、第二电极连接部和第三电极连接部。第一电极连接部和第三电极连接部沿第二方向延伸，第二电极连接部沿第一方向延伸，且分别与第一电极连接部和第三电极连接部连接；
第一电极连接部位于第二电极连接部靠近第九晶体管的控制极的一侧，第三电极连接部位于第二电极连接部远离第九晶体管的控制极的一侧；
沿第二方向延伸的虚拟直线经过第十晶体管的控制极的第一电极连接部在基底上的正投影和电容的第一极板的第一电容主体部在基底上的正投影；
第十晶体管的控制极的第三电极连接部在基底上的正投影位于电容的第一极板在基底上的正投影远离第一晶体管的控制极和第七晶体管的控制极的 一体成型结构在基底上的正投影的一侧。
在一些可能的实现方式中，第五绝缘层开设有多个过孔图案，多个过孔图案包括：开设在第一绝缘层、第二绝缘层和第五绝缘层的第一过孔至第六过孔，开设在第二绝缘层至第五绝缘层的第七过孔至第十三过孔、开设在第三绝缘层至第五绝缘层的第十四过孔、开设在第四绝缘层至第五绝缘层的第十五过孔至第十八过孔以及开设在第五绝缘层的第十九过孔至第二十二过孔；
第三过孔暴露出第三晶体管的有源层，第二十二过孔暴露出第十晶体管的控制极；
第三过孔的数量为四个，沿第一方向延伸的虚拟直线穿过第一个第三过孔和第二个第三过孔，且第一个第三过孔和第二个第三过孔暴露出第三晶体管的有源层的第一有源连接部，沿第一方向延伸的虚拟直线穿过第三个第三过孔和第四个第三过孔，且第三个第三过孔和第四个第三过孔暴露出第三晶体管的有源层的第三有源连接部，沿第二方向延伸的虚拟直线穿过第二个第三过孔和第三个第三过孔；
第二十二过孔的数量为两个，第一个第二十二过孔暴露出第十晶体管的控制极的第二电极连接部，第二个二十二过孔暴露出第十晶体管的控制极的第三电极连接部。
在一些可能的实现方式中，第三晶体管的第一极、第五晶体管的第一极、第七晶体管的第一极和第一电源线为一体成型结构，第四晶体管的第一极、第六晶体管的第一极、第十晶体管的第一极和第二电源线为一体成型结构，第一晶体管的第二极和第二晶体管的第一极为一体成型结构，第三晶体管的第二极和第四晶体管的第二极为一体成型结构，第二晶体管的第二极、第八晶体管的第二极和第九晶体管的第一极为一体成型结构，第五晶体管的第二极和第六晶体管的第二极为一体成型结构；
第一电源线在基底上的正投影与信号输出线在基底上的正投影至少部分交叠；
第二电源线在基底上的正投影与第一晶体管的控制极和第七晶体管的控制极的一体成型结构、第十晶体管的控制极以及电容的第二极板的第二电容连接部在基底上的正投影部分交叠；
第一时钟信号线在基底上的正投影与第十晶体管的控制极以及第一晶体管的控制极和第七晶体管的控制极的一体成型结构在基底上的正投影部分交叠；
第二时钟信号线与所连接的晶体管的控制极在基底上的正投影部分交叠；
第一晶体管的第二极和第二晶体管的第一极的一体成型结构在基底上的正投影与电容的第一极板的第一电容连接部在基底上的正投影部分交叠；
第三晶体管的第二极和第四晶体管的第二极的一体成型结构在基底上的正投影与第六晶体管的控制极和第五晶体管的控制极在基底上的正投影部分交叠；
第五晶体管的第二极和第六晶体管的第二极的一体成型结构在基底上的正投影与信号输出线在基底上的正投影部分交叠；
第二晶体管的第二极、第八晶体管的第二极和第九晶体管的第一极的一体成型结构在基底上的正投影与第三晶体管的控制极和第四晶体管的控制极在基底上的正投影部分交叠；
第一连接信号线在基底上的正投影与第九晶体管的控制极在基底上的正投影部分交叠；
第二连接信号线在基底上的正投影与第八晶体管的控制极在基底上的正投影部分交叠；
第三连接信号线在基底上的正投影与第二晶体管的控制极和第十晶体管的控制极在基底上的正投影部分交叠。
在一些可能的实现方式中，第三晶体管的第一极和第二极分别通过第三个第三过孔和第四个第三过孔与第三晶体管的有源层连接；
第一连接信号线通过第一个第三过孔与第三晶体管的有源层连接；
第二连接信号线通过第二个第三过孔与第三晶体管的有源层连接；
第三连接信号线通过第一个第二十二过孔与第十晶体管的控制极连接；
第一时钟信号线和第二时钟信号线中的一条信号线通过第二个第二十二过孔与第十晶体管的控制极连接。
第三方面，本公开还提供了一种显示装置，包括：上述显示基板。
第四方面，本公开还提供了一种移位寄存器的驱动方法，设置为驱动上述移位寄存器，所述方法包括：
存储子电路存储第一节点的信号和第一电源端的信号之间的电压差；
节点控制子电路在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；
输出控制子电路在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的移位寄存器的结构示意图；
图2为一种示例性实施例提供的输出控制子电路的结构示意图；
图3为一种示例性实施例提供的移位寄存器的结构示意图；
图4为一种示例性实施例提供的存储子电路的等效电路图；
图5为一种示例性实施例提供的节点控制子电路的等效电路图；
图6为一种示例性实施例提供的输出控制子电路的等效电路图；
图7为一种示例性实施例提供的降噪子电路的等效电路图；
图8为一种示例性实施例提供的移位寄存器的等效电路图；
图9为另一示例性实施例提供的移位寄存器的等效电路图；
图10为一种示例性实施例提供的移位寄存器的工作时序图；
图11为另一示例性实施例提供的移位寄存器的工作时序图；
图12为一种示例性实施例提供的显示基板的结构示意图；
图13为形成第一半导体层图案后的示意图；
图14A为第一导电层图案的示意图；
图14B为形成第一导电层图案后的示意图；
图15A为第二导电层图案的示意图；
图15B形成第二导电层图案后的示意图；
图16A为第二半导体层图案的示意图；
图16B为形成第二半导体层图案后的示意图；
图17A为第三导电层图案的示意图；
图17B为形成第三导电层图案后的示意图；
图18为形成第五绝缘层图案后的示意图；
图19A为第四导电层图案的示意图；
图19B形成第四导电层图案后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也 不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容 器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板包括：像素电路、发光元件和栅极驱动电路，其中，栅极驱动电路设置为向像素电路提供栅极信号，以使得像素电路可以驱动发光元件发光。栅极驱动电路所占用的面积以及功耗比较大。
图1为本公开实施例提供的移位寄存器的结构示意图。如图1所示，本公开实施例提供的移位寄存器可以包括：存储子电路、节点控制子电路和输出控制子电路。
如图1所示，存储子电路，分别与第一节点N1和第一电源端VGH电连接，设置为存储第一节点N1的信号和第一电源端VGH的信号之间的电压差；节点控制子电路，分别与信号输入端IN、第一时钟信号端CK、第二时钟信号端CB、第一节点N1和第二节点N2电连接，设置为在第一时钟信号端CK的控制下，将信号输入端IN的信号提供至第一节点N1，在第二时钟信号端CB的控制下，将第一节点N1的信号提供至第二节点N2；输出控制子电路， 分别与第二节点N2、第一电源端VGH、第二电源端VGL和信号输出端OUT电连接，设置为在第二节点N2的控制下，向信号输出端OUT提供第一电源端VGH或第二电源端VGL的信号。
在一种示例性实施例中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。
在一种示例性实施例中，第一时钟信号端CK和第二时钟信号端CB的信号可以为周期性脉冲信号。
本公开实施例提供的移位寄存器包括：存储子电路、节点控制子电路和输出控制子电路；存储子电路，分别与第一节点和第一电源端电连接，设置为存储第一节点的信号和第一电源端的信号之间的电压差；节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一节点和第二节点电连接，设置为在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；输出控制子电路，分别与第二节点、第一电源端、第二电源端和信号输出端电连接，设置为在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。本公开提供的移位寄存器通过存储子电路、节点控制子电路和输出控制子电路的配合，可以减少移位寄存器所占用的面积以及功耗。
图2为一种示例性实施例提供的输出控制子电路的结构示意图。如图2所示，一种示例性实施例中，输出控制子电路可以包括：第一输出控制子电路和第二输出控制子电路。
如图2所示，第一输出控制子电路，分别与第二节点N2、第三节点N3、第一电源端VGH和第二电源端VGL电连接，设置为在第二节点N2的控制下，向第三节点N3提供第一电源端VGH或第二电源端VGL的信号；第二输出控制子电路，分别与第三节点N3、第一电源端VGH、第二电源端VGL和信号输出端OUT电连接，设置为在第三节点N3的控制下，向信号输出端OUT提供第一电源端VGH或第二电源端VGL的信号。
图3为一种示例性实施例提供的移位寄存器的结构示意图。如图3所示，一种示例性实施例中，移位寄存器还可以包括：降噪子电路。其中，降噪子电路，分别与第一时钟信号端CK、第二时钟信号端CB、第一电源端VGH、 第二电源端VGL、第二节点N2和第三节点N3电连接，设置为在第一时钟信号端CK、第二时钟信号端CB和第三节点N3的控制下，向第二节点N2提供第一电源端VGH或第二电源端VGL的信号。
本公开通过设置降噪子电路可以维持第二节点N2的信号的电压值，使得第二节点N2的信号处于稳定状态，防止第二节点N2浮接而信号的电压值被改变，提升了移位寄存器的可靠性。
图4为一种示例性实施例提供的存储子电路的等效电路图。如图4所示，一种示例性实施例中，存储子电路可以包括：电容C，电容C包括：第一极板C1和第二极板C2。电容C的第一极板C1与第一节点N1电连接，电容C的第二极板C2与第一电源端VGH电连接。
图4中示出了存储子电路的一个示例性结构。本领域技术人员容易理解是，存储子电路的实现方式不限于此。
图5为一种示例性实施例提供的节点控制子电路的等效电路图。如图5所示，一种示例性实施例中，节点控制子电路可以包括：第一晶体管T1和第二晶体管T2。
如图5所示，第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第二时钟信号端CB电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第二节点N2电连接。
图5中示出了节点控制子电路的一个示例性结构。本领域技术人员容易理解是，节点控制子电路的实现方式不限于此。
图6为一种示例性实施例提供的输出控制子电路的等效电路图。如图6所示，一种示例性实施例中，输出控制子电路中的第一输出控制子电路可以包括：第三晶体管T3和第四晶体管T4，第二输出控制子电路可以包括：第五晶体管T5和第六晶体管T6。
如图6所示，第三晶体管T3的控制极与第二节点N2电连接，第三晶体管T3的第一极与第一电源端VGH电连接，第三晶体管T3的第二极与第三 节点N3电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第二电源端VGL电连接，第四晶体管T4的第二极与第三节点N3电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第一电源端VGH电连接，第五晶体管T5的第二极与信号输出端OUT电连接；第六晶体管T6的控制极与第三节点N3电连接，第六晶体管T6的第一极与第二电源端VGL电连接，第六晶体管T6的第二极与信号输出端OUT电连接。
在一种示例性实施例中，第三晶体管T3和第四晶体管T4的晶体管类型相反，即第一输出控制子电路相当于一组反相器。第五晶体管T5和第六晶体管T6的晶体管类型相反，即第二输出控制子电路相当于一组反相器。本公开中的输出控制子电路相当于两个串联的反相器。
图6中示出了输出控制子电路的一个示例性结构。本领域技术人员容易理解是，输出控制子电路的实现方式不限于此。
图7为一种示例性实施例提供的降噪子电路的等效电路图。如图7所示，一种示例性实施例中，降噪子电路可以包括：第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。
如图7所示，第七晶体管T7的控制极与第一时钟信号端CK电连接，第七晶体管T7的第一极与第一电源端VGH电连接，第七晶体管T7的第二极与第八晶体管T8的第一极电连接；第八晶体管T8的控制极与第三节点N3电连接，第八晶体管T8的第二极与第二节点N2电连接；第九晶体管T9的控制极与第三节点N3电连接，第九晶体管T9的第一极与第二节点N2电连接，第九晶体管T9的第二极与第十晶体管T10的第二极电连接；第十晶体管T10的控制极与第二时钟信号端CB电连接，第十晶体管T10的第一极与第二电源端VGL电连接。
在一种示例性实施例中，第七晶体管T7和第八晶体管T8的晶体管类型可以相同。
在一种示例性实施例中，第九晶体管T9和第十晶体管T10的晶体管可以类型相同。
在一种示例性实施例中，第七晶体管T7和第九晶体管T9的晶体管类型 可以相反。
图7中示出了降噪子电路的一个示例性结构。本领域技术人员容易理解是，降噪子电路的实现方式不限于此。
一种示例性实施例中，按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
图8为一种示例性实施例提供的移位寄存器的等效电路图。如图8所示，一种示例性实施例中，移位寄存器中的存储子电路可以包括：电容C，电容C包括：第一极板C1和第二极板C2；节点控制子电路可以包括：第一晶体管T1和第二晶体管T2；输出控制子电路可以包括：第三晶体管T3、第四晶体管T4、五晶体管和第六晶体管T6。
如图8所示，电容C的第一极板C1与第一节点N1电连接，电容C的第二极板C2与第一电源端VGH电连接；第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第二时钟信号端CB电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第二节点N2电连接，第三晶体管T3的第一极与第一电源端VGH电连接，第三晶体管T3的第二极与第三节点N3电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第二电源端VGL电连接，第四晶体管T4的第二极与第三节点N3电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第一电源端VGH电连接，第五晶体管T5的第二极与信号输出端OUT电连接；第六晶体管T6的控制极与第三节点N3电连接，第六晶体管T6的第一极与第二电源端VGL电连接，第六晶体管T6的第二极与信号输出端OUT电连接。
在一种示例性实施例中，第一晶体管T1、第二晶体管T2、第三晶体管 T3和第五晶体管T5可以为P型晶体管。
在一种示例性实施例中，第四晶体管T4和第六晶体管T6可以为N型晶体管，且为氧化物晶体管。氧化物晶体管可以减少漏电流，提升移位寄存器的性能，可以降低移位寄存器的功耗。
图9为另一示例性实施例提供的移位寄存器的等效电路图。如图9所示，一种示例性实施例中，移位寄存器还可以包括：降噪子电路，存储子电路可以包括：电容C，电容C包括：第一极板C1和第二极板C2；节点控制子电路可以包括：第一晶体管T1和第二晶体管T2；输出控制子电路可以包括：第三晶体管T3、第四晶体管T4、五晶体管和第六晶体管T6；降噪子电路可以包括：第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。
如图9所示，电容C的第一极板C1与第一节点N1电连接，电容C的第二极板C2与第一电源端VGH电连接；第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第二时钟信号端CB电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第二节点N2电连接，第三晶体管T3的第一极与第一电源端VGH电连接，第三晶体管T3的第二极与第三节点N3电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第二电源端VGL电连接，第四晶体管T4的第二极与第三节点N3电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第一电源端VGH电连接，第五晶体管T5的第二极与信号输出端OUT电连接；第六晶体管T6的控制极与第三节点N3电连接，第六晶体管T6的第一极与第二电源端VGL电连接，第六晶体管T6的第二极与信号输出端OUT电连接；第七晶体管T7的控制极与第一时钟信号端CK电连接，第七晶体管T7的第一极与第一电源端VGH电连接，第七晶体管T7的第二极与第八晶体管T8的第一极电连接；第八晶体管T8的控制极与第三节点N3电连接，第八晶体管T8的第二极与第二节点N2电连接；第九晶体管T9的控制极与第三节点N3电连接，第九晶体管T9的第一极与第二节点N2电连接，第九晶体管T9的第二极与第十 晶体管T10的第二极电连接；第十晶体管T10的控制极与第二时钟信号端CB电连接，第十晶体管T10的第一极与第二电源端VGL电连接。
在一种示例性实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5、第七晶体管T7和第八晶体管T8可以为P型晶体管。
在一种示例性实施例中，第四晶体管T4、第六晶体管T6、第九晶体管T9和第十晶体管T10可以为N型晶体管，且为氧化物晶体管。氧化物晶体管可以减少漏电流，提升移位寄存器的性能，可以降低移位寄存器的功耗。
在一种示例性实施例中，第一时钟信号端CK的时钟信号和第二时钟信号端CB的时钟信号互为反相信号。
在一种示例性实施例中，信号输入端IN的信号可以为第一脉冲信号，信号输出端OUT的信号为第二脉冲信号，第一脉冲信号的持续时间等于第一时钟信号端CK的时钟信号的周期，第二脉冲信号的持续时间等于第一脉冲信号的持续时间，且第二脉冲信号的开始时间为第一脉冲信号的结束时间。
在一种示例性实施例中，信号输入端IN的信号可以为第三脉冲信号，第三脉冲信号的持续时间等于第一时钟信号端CK的时钟信号的周期的N倍，N为大于或者等于2的正整数；信号输出端OUT的信号可以为第四脉冲信号，第四脉冲信号的持续时间等于第三脉冲信号的持续时间，且第四脉冲信号的开始时间与第三脉冲信号的开始时间之差等于第一时钟信号端CK的时钟信号的周期。
本公开提供的移位寄存器中仅包括一个电容，且晶体管的数量较少，减少了移位寄存器所占的面积，并降低了功耗。
本公开提供的移位寄存器不仅可以输出持续时间较短的脉冲信号，还可以输出持续时间较长的信号，即具有多种波形输出，可适用范围较大。
图10为一种示例性实施例提供的移位寄存器的工作时序图，图11为另一示例性实施例提供的移位寄存器的工作时序图。图10和图11均可以适用于图8和图9所示的移位寄存器，图10是以移位寄存器输出持续时间较短的脉冲信号为例进行说明的，图11是以移位寄存器输出持续时间较长的脉冲信号为例进行说明的。
下面通过图8示例的移位寄存器的工作过程说明本公开示例性实施例。以图8提供的移位寄存器中的第一晶体管T1、第二晶体管T2、第三晶体管T3和第五晶体管T5为P型晶体管，第四晶体管T4和第六晶体管T6为N型晶体管为例，图8中的移位寄存器包括第一晶体管T1到第六晶体管T6、1个电容(电容C)和4个信号端(第一时钟信号端CK、第二时钟信号端CB、信号输入端IN和信号输出端OUT)。
在一种示例性实施例中，如图10所示，图8提供的移位寄存器的工作过程可以包括：
第一阶段P1，第一时钟信号端CK的信号为低电平信号，信号输入端IN和第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2的信号保持为高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第二阶段P2，第一时钟信号端CK的信号为高电平信号，信号输入端IN和第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，信号输入端IN的低电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第三阶段P3，第一时钟信号端CK和信号输入端IN的信号为低电平信号，第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的低电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2保持上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第四阶段P4，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，信号输入端IN的高电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的低电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的低电平信号通过导通的第二晶体管T2传输至第二节点N2，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6导通，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第五阶段P5，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2保持上一阶段的低电平信号，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6导通，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1 的信号为高电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第六阶段P6，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
在一种示例性实施例中，如图11所示，图8提供的移位寄存器的工作过程可以包括：
第一阶段P1，第一时钟信号端CK和信号输入端IN的信号为低电平信号，第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的低电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2的信号保持为低电平信号，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6导通，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第二阶段P2，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，信号输入端IN的高电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的低电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的低电平信号 通过导通的第二晶体管T2传输至第二节点N2，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6导通，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第三阶段P3，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2保持上一阶段的低电平信号，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6导通，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第四阶段P4，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第五阶段P5，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的高电平信号经过导通的 第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2保持上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第六阶段P6，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第七阶段P7，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2保持上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第八阶段P8，第一时钟信号端CK的信号为高电平信号，第二时钟信号端CB和信号输入端IN的信号为低电平信号。第一时钟信号端CK的信号为 高电平信号，第一晶体管T1截止，信号输入端IN的低电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第九阶段P9，第一时钟信号端CK和信号输入端IN的信号为低电平信号，第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1导通，信号输入端IN的低电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第二节点N2保持上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5导通，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第十阶段P10，第一时钟信号端CK的信号为高电平信号，第二时钟信号端CB和信号输入端IN的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1截止，第一节点N1保持上一阶段的低电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第一节点N1的低电平信号通过导通的第二晶体管T2传输至第二节点N2，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6导通，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
下面通过图9示例的移位寄存器的工作过程说明本公开示例性实施例。以图9提供的移位寄存器中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5、第七晶体管T7和第八晶体管T8为P型晶体管，第四晶体管T4、第六晶体管T6、第九晶体管T9和第十晶体管T10为N型晶体管为例，图9中的移位寄存器包括第一晶体管T1到第十晶体管T10、1个电容(电容C)和4个信号端(第一时钟信号端CK、第二时钟信号端CB、信号输入端IN和信号输出端OUT)。
在一种示例性实施例中，如图10所示，图9提供的移位寄存器的工作过程可以包括：
第一阶段P1，第一时钟信号端CK的信号为低电平信号，信号输入端IN和第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2的信号保持为高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9截止，第二电源端VGL的低电平信号无法写入第二节点N2，第一电源端VGH的信号可以通过导通的第七晶体管T7和第八晶体管T8传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第二阶段P2，第一时钟信号端CK的信号为高电平信号，信号输入端IN和第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，信号输入端IN的低电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二 节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9和第十晶体管T10均截止，第二电源端VGL的低电平信号无法写入第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第三阶段P3，第一时钟信号端CK和信号输入端IN的信号为低电平信号，第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的低电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9截止，第二电源端VGL的低电平信号无法写入第二节点N2，第一电源端VGH的信号可以通过导通的第七晶体管T7和第八晶体管T8传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第四阶段P4，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，信号输入端IN的高电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的低电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的低电平信号通过导通的第二晶体管T2传输至第二节点N2，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的 第三晶体管T3传输至第三节点N3，第六晶体管T6和第九晶体管T9导通，第八晶体管T8截止，由于第七晶体管T7和第八晶体管T8均截止，第一电源端VGH的高电平信号无法写入第二节点N2，第二节点N2的信号保持为低电平信号，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第五阶段P5，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2保持上一阶段的低电平信号，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6和第九晶体管T9导通，第八晶体管T8截止，由于第九晶体管T9和第十晶体管T10导通，第二电源端VLG的低电平信号通过导通的第九晶体管T9和第十晶体管T10传输至第二节点N2，第二节点N2的信号保持为低电平信号，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第六阶段P6，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9和第十晶 体管T10均截止，第二电源端VLG的低电平信号无法传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
在一种示例性实施例中，如图11所示，图9提供的移位寄存器的工作过程可以包括：
第一阶段P1，第一时钟信号端CK和信号输入端IN的信号为低电平信号，第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的低电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2的信号保持低电平信号，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6和第九晶体管T9导通，第八晶体管T8截止，第二电源端VGL的低电平信号通过导通的第九晶体管T9和第十晶体管T10传输至第二节点N2，第二节点N2的信号保持为低电平信号，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第二阶段P2，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，信号输入端IN的高电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的低电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的低电平信号通过导通的第二晶体管T2传输至第二节点N2，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6和第九晶体管T9导通，第八晶体管T8截止，由于第七晶体管T7和第八晶体管T8均截止，第一电 源端VGH的高电平信号无法传输至第二节点N2，第二节点N2的信号保持为低电平信号，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第三阶段P3，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2保持上一阶段的低电平信号，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6和第九晶体管T9导通，第八晶体管T8截止，第二电源端VGL的低电平信号通过导通的第九晶体管T9和第十晶体管T10传输至第二节点N2，第二节点N2的信号保持为低电平信号，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
第四阶段P4，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9和第十晶体管T10均截止，第二电源端VGL的低电平信号无法传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1 的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第五阶段P5，第一时钟信号端CK的信号为低电平信号，第二时钟信号端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2的信号保持为上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，第一电源端VGH的高电平信号通过导通的第七晶体管T7和第八晶体管T8传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第六阶段P6，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第二时钟信号端CB的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9和第十晶体管T10均截止，第二电源端VGL的低电平信号无法传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第七阶段P7，第一时钟信号端CK的信号为低电平信号，第二时钟信号 端CB和信号输入端IN的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的高电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2保持上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，第一电源端VGH的高电平信号通过导通的第七晶体管T7和第八晶体管T8传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第八阶段P8，第一时钟信号端CK的信号为高电平信号，第二时钟信号端CB和信号输入端IN的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，信号输入端IN的低电平信号无法传输至第一节点N1，第一节点N1保持上一阶段的高电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的高电平信号通过导通的第二晶体管T2传输至第二节点N2，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9和第十晶体管T10均截止，第二电源端VGL的低电平信号无法传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为高电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第九阶段P9，第一时钟信号端CK和信号输入端IN的信号为低电平信号，第二时钟信号端CB的信号为高电平信号。第一时钟信号端CK的信号为低电平信号，第一晶体管T1和第七晶体管T7导通，信号输入端IN的低 电平信号经过导通的第一晶体管T1传输至第一节点N1，第二时钟信号端CB的信号为高电平信号，第二晶体管T2截止，第十晶体管T10导通，第二节点N2保持上一阶段的高电平信号，第四晶体管T4导通，第二电源端VGL的低电平信号通过导通的第四晶体管T4传输至第三节点N3，第五晶体管T5和第八晶体管T8导通，第九晶体管T9截止，由于第九晶体管T9截止，第二电源端VGL的低电平信号无法传输至第二节点N2，第二节点N2的信号保持为高电平信号，第一电源端VGH的高电平信号通过导通的第五晶体管T5传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为高电平信号，第三节点N3的信号为低电平信号，信号输出端OUT的信号为高电平信号。
第十阶段P10，第一时钟信号端CK的信号为高电平信号，第二时钟信号端CB和信号输入端IN的信号为低电平信号。第一时钟信号端CK的信号为高电平信号，第一晶体管T1和第七晶体管T7截止，第一节点N1保持上一阶段的低电平信号，第二时钟信号端CB的信号为低电平信号，第二晶体管T2导通，第十晶体管T10截止，第一节点N1的低电平信号通过导通的第二晶体管T2传输至第二节点N2，第三晶体管T3导通，第一电源端VGH的高电平信号通过导通的第三晶体管T3传输至第三节点N3，第六晶体管T6和第九晶体管T9导通，第八晶体管T8截止，由于第七晶体管T7和第八晶体管T8均截止，第一电源端VGH的高电平信号无法传输至第二节点N2，第二节点N2的信号保持为低电平信号，第二电源端VGL的低电平信号通过导通的第六晶体管T6传输至信号输出端OUT。本阶段中，第一节点N1的信号为低电平信号，第二节点N2的信号为低电平信号，第三节点N3的信号为高电平信号，信号输出端OUT的信号为低电平信号。
本公开实施例还提供了一种显示基板，包括：显示区域和非显示区域，显示基板包括：基底以及设置在所述基底上的电路结构层，所述电路结构层包括：位于非显示区域的栅极驱动电路和位于显示区域的阵列排布的像素电路，栅极驱动电路包括：多个级联的移位寄存器，像素电路包括：发光信号线、扫描信号线和复位信号线；
第i级移位寄存器的信号输出端与第i+1级移位寄存器的信号输入端电 连接，1≤i≤M-1，M为移位寄存器的总级数。
本公开中，栅极驱动电路可以与发光信号线、扫描信号线和复位信号线中的至少一种信号线电连接。
在一种示例性实施例中，像素电路可以为7T1C或者8T1C电路结构，本公开对此不作任何限定。
移位寄存器可以为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
对于不同显示产品，栅极驱动电路中多个移位寄存器的级联关系可能有所不同。无论多个移位寄存器的级联关系如何，每个移位寄存器驱动几行子像素，只要是类似这种大面积的器件发生改变，以及这种改变产生额外空间以后，小器件可能的简单平移、拉伸都在本公开的保护范围内。
在一种示例性实施例中，本公开显示基板可以应用于具有栅极驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
在一种示例性实施例中，电路结构层还可以包括：像素电路以及与像素电路连接的复位信号线、发光信号线和扫描信号线。栅极驱动电路可以为复位信号线、发光信号线或者扫描信号线中的至少一种信号线提供信号。
在一种示例性实施例中，显示基板还可以包括：设置在电路结构层远离基底一侧的发光结构层。发光结构层包括：位于显示区域的阵列排布的发光元件。
在一种示例性实施例中，发光元件可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。其中，OLED可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在一种示例性实施例中，显示基板还可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
图12为一种示例性实施例提供显示基板的结构示意图。如图12所示，在一种示例性实施例中，显示基板还可以包括：沿第一方向延伸的第一时钟 信号线CLK1、第二时钟信号线CLK2、第一电源线VHL和第二电源线VLL，第一电源线VHL、第二电源线VLL、第一时钟信号线CLK1和第二时钟信号线CLK2沿第二方向排布，第一方向与第二方向相交。
所有移位寄存器的第一电源端与第一电源线电连接，所有移位寄存器的第二电源端与第二电源线电连接，第i级移位寄存器的第一时钟信号端与第一时钟信号线电连接，第i级移位寄存器的第二时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第一时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第二时钟信号端与第一时钟信号线电连接。
如图12所示，移位寄存器包括：第一晶体管T1至第十晶体管T10以及电容C，电容C包括：第一极板和第二极板。
在一种示例性实施例中，电路结构层可以包括：依次叠设在基底上的第一半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第二半导体层、第四绝缘层、第三导电层、第五绝缘层和第四导电层；
第一半导体层包括：第一晶体管的有源层、第二晶体管的有源层、第三晶体管的有源层、第五晶体管的有源层、第七晶体管的有源层和第八晶体管的有源层；
第一导电层包括：第一晶体管的控制极、第二晶体管的控制极、第三晶体管的控制极、第五晶体管的控制极、第七晶体管的控制极、第八晶体管的控制极、电容的第一极板和信号输出线；
第二导电层包括：电容的第二极板；
第二半导体层包括：第四晶体管的有源层、第六晶体管的有源层、第九晶体管的有源层和第十晶体管的有源层；
第三导电层包括：第四晶体管的控制极、第六晶体管的控制极、第九晶体管的控制极和第十晶体管的控制极；
第四导电层包括：第一时钟信号线、第二时钟信号线、第一电源线、第二电源线、第一晶体管的第一极和第二极至第六晶体管的第一极和第二极、第七晶体管的第一极、第八晶体管的第二极、第九晶体管的第一极、第十晶体管的第一极、第一连接信号线、第二连接信号线和第三连接信号线；
信号输出线分别与第五晶体管的第二极和第六晶体管的第二极连接；第一连接信号线分别与第三晶体管的有源层和第九晶体管的控制极连接；第二连接信号线分别与第三晶体管的有源层和第八晶体管的控制极连接；第三连接信号线分别与第十晶体管的控制极和第二晶体管的控制极连接。
如图12所示，在一种示例性实施例中，第五晶体管T5和第六晶体管T6位于第一电源线VHL的同一侧，且第五晶体管T5和第六晶体管T6沿第一方向排布；第三晶体管T3位于第五晶体管T5远离第一电源线VHL的一侧，第四晶体管T4位于第六晶体管T6远离第一电源线VHL的一侧，第三晶体管T3和第四晶体管T4沿第一方向排布，第三晶体管T3和第五晶体管T5沿第二方向排布，第四晶体管T4和第六晶体管T6沿第二方向排布；第八晶体管T8位于第三晶体管T3远离第五晶体管T5的一侧，第九晶体管T9位于第四晶体管T4远离第六晶体管T6的一侧，第八晶体管T8和第九晶体管T9沿第一方向排布，第三晶体管T3和第八晶体管T8沿第二方向排布，第四晶体管T4和第九晶体管T9沿第二方向排布；第七晶体管T7位于第八晶体管T8远离第三晶体管T3的一侧，第十晶体管T10位于第九晶体管T9远离第四晶体管T4的一侧，第七晶体管T7和第十晶体管T10沿第一方向排布，第七晶体管Y7和第八晶体管T8沿第二方向排布，第九晶体管T9和第十晶体管T10沿第二方向排布；第二晶体管T2位于第七晶体管T7和第十晶体管T10之间，第一晶体管T1位于第七晶体管T7远离第八晶体管T8的一侧，电容C位于第十晶体管T10远离第九晶体管T9的一侧；第二电源线VLL位于电容C远离第十晶体管T10的一侧，第一时钟信号线CLK1位于第二电源线VLL远离电容C的一侧，第二时钟信号线CLK2位于第一时钟信号线CLK1远离第二电源线VLL的一侧。
在一种示例性实施例中，第一晶体管的有源层和第二晶体管的有源层为一体成型结构，第七晶体管的有源层与第八晶体管的有源层为一体成型结构；
第三晶体管的有源层包括：第一有源连接部、第二有源连接部和第三有源连接部；第一有源连接部和第三有源连接部沿第一方向延伸，第二有源连接部沿第二方向延伸，且分别与第一有源连接部和第三有源连接部连接；
第一有源连接部位于第二有源连接部靠近第七晶体管的有源层与第八晶 体管的有源层的一体成型结构的一侧，第三有源连接部位于第二有源连接部远离第七晶体管的有源层与第八晶体管的有源层的一体成型结构的一侧；
沿第二方向延伸的直线经过第一有源连接部和第二晶体管的有源层；
沿第二方向延伸的直线经过第三有源连接部和第一晶体管的有源层。
在一种示例性实施例中，电容的第一极板包括：相互连接的第一电容主体部和第一电容连接部；
第一晶体管的控制极和第七晶体管的控制极为一体成型结构，且位于第一电容连接部远离第一电容主体部的一侧；
沿第二方向延伸的虚拟直线经过第八晶体管的控制极以及第一晶体管的控制极和第七晶体管的控制极的一体成型结构。
沿第二方向延伸的虚拟直线经过第三晶体管的控制极和第八晶体管的控制极；
沿第二方向延伸的虚拟直线经过第五晶体管的控制极和第三晶体管的控制极。
沿第二方向延伸的虚拟直线经过信号输出线和第二晶体管的控制极。
在一种示例性实施例中，电容的第二极板包括：相互连接的第二电容主体部和第二电容连接部，第二电容连接部位于第二电容主体部的一侧；
电容的第一极板的第一电容主体部的面积大于电容的第二极板的第二电容主体部的面积；
第二电容主体部和第二电容连接部在基底上的正投影与电容的第一极板的第一电容主体部在基底上的正投影至少部分交叠，且与电容的第一极板的第一电容连接部在基底上的正投影不交叠。
在一种示例性实施例中，第六晶体管的有源层在基底上的正投影与第五晶体管的有源层在基底上的正投影分别位于信号输出线在基底上的正投影的相对设置的两侧，且沿第一方向延伸的直线经过第五晶体管的有源层和第六晶体管的有源层；
沿第一方向延伸的直线经过第四晶体管的有源层和第三晶体管的有源层 的第三有源连接部；
沿第一方向延伸的直线经过第九晶体管的有源层和第八晶体管的有源层，沿第一方向延伸的直线经过第十晶体管的有源层和第七晶体管的有源层。
在一种示例性实施例中，沿第二方向延伸的虚拟直线经过第四晶体管的控制极、第六晶体管的控制极和第九晶体管的控制极；
第十晶体管的控制极包括：第一电极连接部、第二电极连接部和第三电极连接部。第一电极连接部和第三电极连接部沿第二方向延伸，第二电极连接部沿第一方向延伸，且分别与第一电极连接部和第三电极连接部连接；
第一电极连接部位于第二电极连接部靠近第九晶体管的控制极的一侧，第三电极连接部位于第二电极连接部远离第九晶体管的控制极的一侧；
沿第二方向延伸的虚拟直线经过第十晶体管的控制极的第一电极连接部在基底上的正投影和电容的第一极板的第一电容主体部在基底上的正投影；
第十晶体管的控制极的第三电极连接部在基底上的正投影位于电容的第一极板在基底上的正投影远离第一晶体管的控制极和第七晶体管的控制极的一体成型结构在基底上的正投影的一侧。
在一种示例性实施例中，第五绝缘层开设有多个过孔图案，多个过孔图案包括：开设在第一绝缘层、第二绝缘层和第五绝缘层的第一过孔至第六过孔，开设在第二绝缘层至第五绝缘层的第七过孔至第十三过孔、开设在第三绝缘层至第五绝缘层的第十四过孔、开设在第四绝缘层至第五绝缘层的第十五过孔至第十八过孔以及开设在第五绝缘层的第十九过孔至第二十二过孔；第三过孔暴露出第三晶体管的有源层，第二十二过孔暴露出第十晶体管的控制极；
第三过孔的数量为四个，沿第一方向延伸的虚拟直线穿过第一个第三过孔和第二个第三过孔，且第一个第三过孔和第二个第三过孔暴露出第三晶体管的有源层的第一有源连接部，沿第一方向延伸的虚拟直线穿过第三个第三过孔和第四个第三过孔，且第三个第三过孔和第四个第三过孔暴露出第三晶体管的有源层的第三有源连接部，沿第二方向延伸的虚拟直线穿过第二个第三过孔和第三个第三过孔；
第二十二过孔的数量为两个，第一个第二十二过孔暴露出第十晶体管的控制极的第二电极连接部，第二个二十二过孔暴露出第十晶体管的控制极的第三电极连接部。
在一种示例性实施例中，第三晶体管的第一极、第五晶体管的第一极、第七晶体管的第一极和第一电源线为一体成型结构，第四晶体管的第一极、第六晶体管的第一极、第十晶体管的第一极和第二电源线为一体成型结构，第一晶体管的第二极和第二晶体管的第一极为一体成型结构，第三晶体管的第二极和第四晶体管的第二极为一体成型结构，第二晶体管的第二极、第八晶体管的第二极和第九晶体管的第一极为一体成型结构，第五晶体管的第二极和第六晶体管的第二极为一体成型结构；
第一电源线在基底上的正投影与信号输出线在基底上的正投影至少部分交叠；第二电源线在基底上的正投影与第一晶体管的控制极和第七晶体管的控制极的一体成型结构、第十晶体管的控制极以及电容的第二极板的第二电容连接部在基底上的正投影部分交叠；第一时钟信号线在基底上的正投影与第十晶体管的控制极以及第一晶体管的控制极和第七晶体管的控制极的一体成型结构在基底上的正投影部分交叠；第二时钟信号线与所连接的晶体管的控制极在基底上的正投影部分交叠；第一晶体管的第二极和第二晶体管的第一极的一体成型结构在基底上的正投影与电容的第一极板的第一电容连接部在基底上的正投影部分交叠；第三晶体管的第二极和第四晶体管的第二极的一体成型结构在基底上的正投影与第六晶体管的控制极和第五晶体管的控制极在基底上的正投影部分交叠；第五晶体管的第二极和第六晶体管的第二极的一体成型结构在基底上的正投影与信号输出线在基底上的正投影部分交叠；第二晶体管的第二极、第八晶体管的第二极和第九晶体管的第一极的一体成型结构在基底上的正投影与第三晶体管的控制极和第四晶体管的控制极在基底上的正投影部分交叠；第一连接信号线在基底上的正投影与第九晶体管的控制极在基底上的正投影部分交叠；第二连接信号线在基底上的正投影与第八晶体管的控制极在基底上的正投影部分交叠；第三连接信号线在基底上的正投影与第二晶体管的控制极和第十晶体管的控制极在基底上的正投影部分交叠。
在一种示例性实施例中，第三晶体管的第一极和第二极分别通过第三个第三过孔和第四个第三过孔与第三晶体管的有源层连接；第一连接信号线通过第一个第三过孔与第三晶体管的有源层连接；第二连接信号线通过第二个第三过孔与第三晶体管的有源层连接；第三连接信号线通过第一个第二十二过孔与第十晶体管的控制极连接；第一时钟信号线和第二时钟信号线中的一条信号线通过第二个第二十二过孔与第十晶体管的控制极连接。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。图13至图18是以显示基板包括图9提供的移位寄存器，即移位寄存器包括：第一晶体管T1至第十晶体管T10为例进行说明的。
(1)在基底上形成第一半导体层图案，包括：在基底上沉积第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成第一半导体层图案。如图13所示，图13为形成第一半导体层图案后的示意图。
在一种示例性实施例中，如图13所示，第一半导体层图案可以包括：第一晶体管的有源层T11、第二晶体管的有源层T21、第三晶体管的有源层T31、第五晶体管的有源层T51、第七晶体管的有源层T71和第八晶体管的有源层 T81。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在一种示例性实施例中，第一半导体层层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
在一种示例性实施例中，如图13所示，第一晶体管的有源层T11和第二晶体管的有源层T21可以为一体成型结构，第七晶体管的有源层T71与第八晶体管的有源层T81可以为一体成型结构。
在一种示例性实施例中，如图13所示，第一晶体管的有源层T11沿第一方向延伸，且可以为条状结构，第二晶体管的有源层T21沿第二方向延伸，且为可以条状结构。第一晶体管的有源层T11和第二晶体管的有源层T21的 一体成型结构可以为倒“L”型，且倒“L”型的开口朝向第七晶体管的有源层T71与第八晶体管的有源层T81的一体成型结构。
在一种示例性实施例中，如图13所示，第七晶体管的有源层T71可以为“n”型，第八晶体管的有源层T81可以为“L”型。第七晶体管的有源层T71与第八晶体管的有源层T81的一体成型结构可以为旋转90度的“S型”。
在一种示例性实施例中，如图13所示，第三晶体管的有源层T31可以位于第七晶体管的有源层T71与第八晶体管的有源层T81的一体成型结构远离第一晶体管的有源层T11和第二晶体管的有源层T21的一体成型结构的一侧。
在一种示例性实施例中，如图13所示，第三晶体管的有源层T31可以包括：第一有源连接部T31A、第二有源连接部T31B和第三有源连接部T31C。其中，第一有源连接部T31A和第三有源连接部T31C沿第一方向延伸，第二有源连接部T31B沿第二方向延伸，且分别与第一有源连接部T31A和第三有源连接部T31C连接。
在一种示例性实施例中，如
图13所示，第一有源连接部T31A和第三有源连接部T31C分别位于第二有源连接部T31B相对设置的两侧。其中，第一有源连接部T31A位于第二有源连接部T31B靠近第七晶体管的有源层T71与第八晶体管的有源层T81的一体成型结构的一侧，第三有源连接部T31C位于第二有源连接部T31B远离第七晶体管的有源层T71与第八晶体管的有源层T81的一体成型结构的一侧。
在一种示例性实施例中，如图13所示，沿第二方向延伸的直线经过第一有源连接部T31A和第二晶体管的有源层T21。
在一种示例性实施例中，如图13所示，沿第二方向延伸的直线经过第三有源连接部T31C和第一晶体管的有源层T11。
在一种示例性实施例中，如图13所示，第五晶体管的有源层T51位于第三晶体管的有源层T31远离第七晶体管的有源层T71与第八晶体管的有源层T81的一体成型结构的一侧，且沿第一方向延伸。其中，第五晶体管的有 源层T51可以为方形。
(2)形成第一导电层图案，包括：在形成有前述图案的基底上沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一绝缘薄膜和第一导电薄膜进行图案化，形成第一绝缘层图案以及设置在第一绝缘层图案上的第一导电层图案，如图14A和图14B所示，图14A为第一导电层图案的示意图，图14B为形成第一导电层图案后的示意图。
在一种示例性实施例中，如图14A和图14B所示，第一导电层图案可以包括：第一晶体管的控制极T12、第二晶体管的控制极T22、第三晶体管的控制极T32、第五晶体管的控制极T52、第七晶体管的控制极T72、第八晶体管的控制极T82、电容的第一极板C1和信号输出线OUTL。
在一种示例性实施例中，第一导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，第一绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第一栅绝缘层。
在一种示例性实施例中，如图14A和图14B所示，电容的第一极板C1可以包括：相互连接的第一电容主体部C11和第一电容连接部C12。第一电容连接部C12位于第一电容主体部C11的一侧。
在一种示例性实施例中，如图14A和图14B所示，第一电容连接部C12的面积小于第一电容主体部C11的面积。
在一种示例性实施例中，如图14A和图14B所示，第一晶体管的控制极T12和第七晶体管的控制极T72为一体成型结构。第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构沿第二方向延伸，且可以为条状。
在一种示例性实施例中，如图14A和图14B所示，第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构可以位于第一电容连接部C12远离第一电容主体部C11的一侧。
在一种示例性实施例中，如图14A和图14B所示，第二晶体管的控制极T22和电容的第一极板C1位于第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构的同一侧，且第二晶体管的控制极T22位于电容的第一极板C1靠近信号输出线的一侧。第二晶体管的控制极T22可以为旋转90度的“L”型。
在一种示例性实施例中，如图14A和图14B所示，第八晶体管的控制极T82可以位于第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构的一侧，且沿第二方向延伸的虚拟直线经过第八晶体管的控制极T82以及第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构。
在一种示例性实施例中，如图14A和图14B所示，第八晶体管的控制极T82沿第二方向延伸，且可以为条状。
在一种示例性实施例中，如图14A和图14B所示，第三晶体管的控制极T32可以为位于第八晶体管的控制极T82远离第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构的一侧，且沿第二方向延伸的虚拟直线经过第三晶体管的控制极T32和第八晶体管的控制极T82。
在一种示例性实施例中，如图14A和图14B所示，第三晶体管的控制极T32沿第二方向延伸，且可以为条状。
在一种示例性实施例中，如图14A和图14B所示，第五晶体管的控制极T52可以位于第三晶体管的控制极T32远离第八晶体管的控制极T82的一侧，且沿第二方向延伸的虚拟直线经过第五晶体管的控制极T52和第三晶体管的控制极T32。
在一种示例性实施例中，如图14A和图14B所示，第五晶体管的控制极T52沿第二方向延伸，且可以为条状。
在一种示例性实施例中，如图14A和图14B所示，信号输出线OUTL可以位于第二晶体管的控制极T22远离电容的第一极板C1的一侧，且沿第二方向延伸的虚拟直线经过信号输出线OUTL和第二晶体管的控制极T22。
在一种示例性实施例中，如图14A和图14B所示，信号输出线OUTL沿第二方向延伸，且可以为条状。
在一种示例性实施例中，如图14A和图14B所示，第一晶体管的控制极T12跨设在第一晶体管的有源层上，第二晶体管的控制极T22跨设在第二晶体管的有源层上，第三晶体管的控制极T32跨设在第三晶体管的有源层上，第五晶体管的控制极T52跨设在第五晶体管的有源层上，第七晶体管的控制极T72跨设在第七晶体管的有源层上，第八晶体管的控制极T82跨设在第八晶体管的有源层上，也就是说，至少一个晶体管的控制极的延伸方向与有源层的延伸方向相互垂直。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第一导电层后，利用多个晶体管的控制极遮挡区域的半导体层(即半导体层与控制极交叠的区域)作为晶体管的沟道区域，未被第一导电层遮挡区域的半导体层被处理成导体化层，形成晶体管的电极连接部。如图14B所示，本公开中的第七晶体管的有源层T71和第八晶体管的有源层T81的相互连接的电极连接部被处理成导体化层，形成可以复用为第七晶体管的第二极和第八晶体管的第一极的导体化结构。
(3)形成第二导电层图案，包括：在形成有前述图案的基底上，沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二绝缘薄膜和第二导电薄膜进行图案化，形成第二绝缘层图案和位于第二绝缘层图案上的第二导电层图案，如图15A和图15B所示，图15A为第二导电层图案的示意图，图15B形成第二导电层图案后的示意图。
在一种示例性实施例中，如图15A和图15B所示，第二导电层图案可以包括：电容的第二极板C2。
在一种示例性实施例中，第二导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
在一种示例性实施例中，如图15A和图15B所示，电容的第二极板C2可以包括：相互连接的第二电容主体部C21和第二电容连接部C22。第二电容连接部C22位于第二电容主体部C21的一侧。
在一种示例性实施例中，如图15A和图15B所示，电容的第二极板C2的形状可以为“L”型。其中，第二电容主体部C21的形状可以为条状，且沿第二方向延伸，第二电容连接部C22可以为条状，且沿第一方向延伸。
在一种示例性实施例中，如图15A和图15B所示，电容的第一极板的第一电容主体部C11的面积大于电容的第二极板的第二电容主体部C21的面积。
在一种示例性实施例中，如图15A和图15B所示，第二电容主体部C21和第二电容连接部C22在基底上的正投影与电容的第一极板的第一电容主体部在基底上的正投影至少部分交叠，且与电容的第一极板的第一电容连接部在基底上的正投影不交叠。
(4)形成第二半导体层图案，包括：在形成前述图案的基底上沉积第三绝缘薄膜和第二半导体薄膜，通过图案化工艺对第三绝缘薄膜和第二半导体薄膜进行图案化，形成第三绝缘层图案以及设置在第三绝缘层图案上的第二半导体层图案。如图16A和图16B所示，图16A为第二半导体层图案的示意图图16B为形成第二半导体层图案后的示意图。
在一种示例性实施例中，如图16A和图16B所示，第二半导体层图案可以包括：第四晶体管的有源层T41、第六晶体管的有源层T61、第九晶体管的有源层T91和第十晶体管的有源层T101。
在一种示例示例性实施例中，第二半导体层可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在一种示例性实施例中，第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
在一种示例性实施例中，如图16A和图16B所示，第九晶体管的有源层T91和第十晶体管的有源层T101为一体成型结构。
在一种示例性实施例中，如图16A和图16B所示，第六晶体管的有源层T61沿第一方向延伸，且可以为条状结构。第六晶体管的有源层T61在基底上的正投影与第五晶体管的有源层T51在基底上的正投影分别位于信号输出线OUTL在基底上的正投影的相对设置的两侧，且沿第一方向延伸的直线经过第五晶体管的有源层T51和第六晶体管的有源层T61。
在一种示例性实施例中，第五晶体管的有源层T51在基底上的正投影与第六晶体管的有源层T61在基底上的正投影可以沿第二方向延伸的虚拟直线对称设置。
在一种示例性实施例中，如图16A和图16B所示，第四晶体管的有源层T41沿第一方向延伸，且可以为条状结构。沿第一方向延伸的直线经过第四晶体管的有源层T41和第三晶体管的有源层T31的第三有源连接部。
在一种示例性实施例中，第四晶体管的有源层T41在基底上的正投影与第三晶体管的有源层T31的第三有源连接部在基底上的正投影可以沿第二方向延伸的虚拟直线对称设置。
在一种示例性实施例中，如图16A和图16B所示，第九晶体管的有源层T91可以为倒“L”型，第十晶体管的有源层T101可以为“n”型。沿第一方向延伸的直线经过第九晶体管的有源层T91和第八晶体管的有源层T81，沿第一方向延伸的直线经过第十晶体管的有源层T101和第七晶体管的有源层T71。
在一种示例性实施例中，第九晶体管的有源层T91在基底上的正投影与第八晶体管的有源层T81在基底上的正投影可以沿第二方向延伸的虚拟直线对称设置。
(5)形成第三导电层图案，包括：在形成有前述图案的基底上沉积第四绝缘薄膜和第三导电薄膜，通过图案化工艺对第四绝缘薄膜和第三导电薄膜进行图案化，形成第四绝缘层图案以及设置在第四绝缘层图案上的第三导电层图案，如图17A和图17B所示，图17A为第三导电层图案的示意图，图 17B为形成第三导电层图案后的示意图。
在一种示例性实施例中，如图17A和图17B所示，第三导电层图案可以包括：第四晶体管的控制极T42、第六晶体管的控制极T62、第九晶体管的控制极T92和第十晶体管的控制极T102。
在一种示例性实施例中，第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
在一种示例性实施例中，如图17A和图17B所示，第四晶体管的控制极T42和第六晶体管的控制极T62沿第二方向延伸，且可以为条状。第四晶体管的控制极T42位于第六晶体管的控制极T62的一侧，且沿第二方向延伸的虚拟直线经过第四晶体管的控制极T42和第六晶体管的控制极T62。
在一种示例性实施例中，如图17A和图17B所示，第九晶体管的控制极T92沿第二方向延伸，且可以为条状。第九晶体管的控制极T92可以位于第四晶体管的控制极T42远离第六晶体管的控制极T62的一侧，且沿第二方向延伸的虚拟直线经过第四晶体管的控制极T42和第九晶体管的控制极T92。
在一种示例性实施例中，如图17A和图17B所示，第十晶体管的控制极T102可以位于第九晶体管的控制极T92远离第四晶体管的控制极T42的一侧。
在一种示例性实施例中，如图17A和图17B所示，第十晶体管的控制极T102可以包括：第一电极连接部T102A、第二电极连接部T102B和第三电极连接部T102C。第一电极连接部T102A和第三电极连接部T102C沿第二方向延伸，第二电极连接部T102B沿第一方向延伸，且分别与第一电极连接部T102A和第三电极连接部T102C连接。
在一种示例性实施例中，如图17A和图17B所示，第一电极连接部T102A 和第三电极连接部T102C分别位于第二电极连接部T102B的相对设置的两侧，第一电极连接部T102A可以位于第二电极连接部T102B靠近第九晶体管的控制极T92的一侧，第三电极连接部T102C可以位于第二电极连接部T102B远离第九晶体管的控制极T92的一侧。
在一种示例性实施例中，如图17A和图17B所示，沿第二方向延伸的虚拟直线经过第十晶体管的控制极T102的第一电极连接部T102A在基底上的正投影和电容的第一极板的第一电容主体部在基底上的正投影。第十晶体管的控制极T102的第三电极连接部T102C在基底上的正投影位于电容的第一极板在基底上的正投影远离第一晶体管的控制极和第七晶体管的控制极的一体成型结构在基底上的正投影的一侧。
在一种示例性实施例中，如图17A和图17B所示，第四晶体管的控制极T42跨设在第四晶体管的有源层T41上，第六晶体管的控制极T62跨设在第六晶体管的有源层T61上，第九晶体管的控制极T92跨设在第九晶体管的有源层T91上，第十晶体管的控制极T102跨设在第十晶体管的有源层T101上，也就是说，至少一个晶体管的控制极的延伸方向与有源层的延伸方向相互垂直。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第三导电层后，利用多个晶体管的控制极遮挡区域的第二半导体层(即半导体层与控制极交叠的区域)作为晶体管的沟道区域，未被第三导电层遮挡区域的半导体层被处理成导体化层，形成晶体管的电极连接部。如图17B所示，本公开中的第九晶体管的有源层T91和第十晶体管的有源层T101的相互连接的电极连接部被处理成导体化层，形成可以复用为第九晶体管的第二极和第十晶体管的第二极的导体化结构。
(6)形成第五绝缘层图案，包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行构图，形成覆盖前述结构的第五绝缘层图案，第五绝缘层开设有多个过孔图案，如图18所示，图18为形成第五绝缘层图案后的示意图。
在一种示例性实施例中，如图18所示，多个过孔图案可以包括：开设在第一绝缘层、第二绝缘层和第五绝缘层的第一过孔V1至第六过孔V6，开设 在第二绝缘层至第五绝缘层的第七过孔V7至第十三过孔V13、开设在第三绝缘层至第五绝缘层的第十四过孔V14、开设在第四绝缘层至第五绝缘层的第十五过孔V15至第十八过孔V18以及开设在第五绝缘层的第十九过孔V19至第二十二过孔V22。
在一种示例性实施例中，第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
如图18所示，第一过孔V1暴露出第一晶体管的有源层T11，第二过孔V2暴露出第二晶体管的有源层T21，第三过孔V3暴露出第三晶体管的有源层T31，第四过孔V4暴露出第五晶体管的有源层T51，第五过孔V5暴露出第七晶体管的有源层T71，第六过孔V6暴露出第八晶体管的有源层T81，第七过孔V7暴露出第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构，第八过孔V8暴露出第二晶体管的控制极T22，第九过孔V9暴露出第三晶体管的控制极T32，第十过孔V10暴露出第五晶体管的控制极T52，第十一过孔V11暴露出第八晶体管的控制极T82，第十二过孔V12暴露出电容的第一极板C1，第十三过孔V13暴露出信号输出线OUTL，第十四过孔V14暴露出电容的第二极板C2；第十五过孔V15暴露出第四晶体管的有源层T41，第十六过孔V16暴露出第六晶体管的有源层T61，第十七过孔V17暴露出第九晶体管的有源层T91，第十八过孔V18暴露出第十晶体管的有源层T101，第十九过孔V19暴露出第四晶体管的控制极T42，第二十过孔V20暴露出第六晶体管的控制极T62，第二十一过孔V21暴露出第九晶体管的控制极T92，第二十二过孔V22暴露出第十晶体管的控制极T102。
在一种示例性实施例中，如图18所示，第三过孔V3的数量为四个，沿第一方向延伸的虚拟直线穿过第一个第三过孔和第二个第三过孔，且第一个第三过孔和第二个第三过孔暴露出第三晶体管的有源层T31的第一有源连接部，沿第一方向延伸的虚拟直线穿过第三个第三过孔和第四个第三过孔，且第三个第三过孔和第四个第三过孔暴露出第三晶体管的有源层T31的第三有源连接部，沿第二方向延伸的虚拟直线穿过第二个第三过孔和第三个第三过孔。
在一种示例性实施例中，如图18所示，第四过孔V4的数量为多个，且多个第四过孔V4阵列排布。
在一种示例性实施例中，如图18所示，第十三过孔V13的数量可以为多个，且多个第十三过孔V13沿第二方向排布。
在一种示例性实施例中，如图18所示，第十六过孔V16的数量为多个，且多个第十六过孔V16阵列排布。
在一种示例性实施例中，如图18所示，第二十二过孔V22的数量可以为两个，第一个第二十二过孔暴露出第十晶体管的控制极T102的第二电极连接部，第二个二十二过孔暴露出第十晶体管的控制极T102的第三电极连接部。
(7)形成第四导电层图案，包括：在形成前述图案的基底上，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行构图，形成第四金属层图案，如图19A和图19B所示，图19A为第四导电层图案的示意图，图19B形成第四导电层图案后的示意图。
在一种示例性实施例中，如图19A和图19B所示，第四导电层图案可以包括：第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VHL、第二电源线VLL、第一晶体管的第一极T13和第二极T14至第六晶体管的第一极T63和第二极T64、第七晶体管的第一极T73、第八晶体管的第二极T84、第九晶体管的第一极T93、第十晶体管的第一极T103、第一连接信号线L1、第二连接信号线L2和第三连接信号线L3。
在一种示例性实施例中，第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，如图19A和图19B所示，第三晶体管的第一极T33、第五晶体管的第一极T53、第七晶体管的第一极T73和第一电源线VHL为一体成型结构，第四晶体管的第一极T43、第六晶体管的第一极T63、第十晶体管的第一极T103和第二电源线VLL为一体成型结构，第一晶体管的 第二极T14和第二晶体管的第一极T23为一体成型结构，第三晶体管的第二极T34和第四晶体管的第二极T44为一体成型结构，第二晶体管的第二极T24、第八晶体管的第二极T84和第九晶体管的第一极T93为一体成型结构，第五晶体管的第二极T54和第六晶体管的第二极T64为一体成型结构。
在一种示例性实施例中，如图19A和图19B所示，第一电源线VHL位于第五晶体管的第二极T54和第六晶体管的第二极T64的一体成型结构远离第二电源线VLL的一侧，第二电源线VLL位于第一晶体管的第二极T14和第二晶体管的第一极T23的一体成型结构远离第一电源线VHL的一侧，第一时钟信号线CLK1位于第二电源线VLL远离第一电源线VHL的一侧，第二时钟信号线CLK2位于第一时钟信号线CLK1远离第二电源线VLL的一侧。
在一种示例性实施例中，如图19A和图19B所示，第一电源线VHL沿第一方向延伸，且可以为条状。第一电源线VHL在基底上的正投影与信号输出线OUTL在基底上的正投影至少部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第三晶体管的第一极T33、第五晶体管的第一极T53、第七晶体管的第一极T73沿第二方向延伸，且第三晶体管的第一极T33、第五晶体管的第一极T53、第七晶体管的第一极T73位于第一电源线VHL靠近第二电源线VLL的一侧。
在一种示例性实施例中，如图19A和图19B所示，第二电源线VLL沿第一方向延伸，且可以为条状。第二电源线VLL在基底上的正投影与第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构、第十晶体管的控制极以及电容的第二极板C2的第二电容连接部在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第四晶体管的第一极T43、第六晶体管的第一极T63、第十晶体管的第一极T103沿第二方向延伸，且第四晶体管的第一极T43、第六晶体管的第一极T63、第十晶体管的第一极T103位于第二电源线VLL靠近第一电源线VHL的一侧。
在一种示例性实施例中，如图19A和图19B所示，第一时钟信号线CLK1沿第一方向延伸，且可以为条状。第一时钟信号线CLK1在基底上的正投影与第十晶体管的控制极T102以及第一晶体管的控制极T12和第七晶体管的 控制极T72的一体成型结构在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第二时钟信号线CLK2沿第一方向延伸，且可以为条状。第二时钟信号线CLK2与第十晶体管的控制极T102或者第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构在基底上的正投影部分交叠。当移位寄存器中的第二时钟信号端与第二时钟信号线电连接时，第二时钟信号线CLK2在基底上的正投影与第十晶体管的控制极T102在基底上的正投影部分交叠，当移位寄存器中的第一时钟信号端与第二时钟信号线电连接时，第二时钟信号线CLK2在基底上的正投影与第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构在基底上的正投影部分交叠。图19A和图19B是以第二时钟信号线CLK2在基底上的正投影与第十晶体管的控制极T102在基底上的正投影部分交叠为例进行说明的。
在一种示例性实施例中，如图19A和图19B所示，第一晶体管的第二极T14和第二晶体管的第一极T23的一体成型结构可以为“L”型，且第一晶体管的第二极T14和第二晶体管的第一极T23的一体成型结构在基底上的正投影与电容的第一极板的第一电容连接部在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第三晶体管的第二极T34和第四晶体管的第二极T44的一体成型结构可以为旋转90度的“工”字型，且第三晶体管的第二极T34和第四晶体管的第二极T44的一体成型结构在基底上的正投影与第六晶体管的控制极T62和第五晶体管的控制极T52在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第五晶体管的第二极T54和第六晶体管的第二极T64的一体成型结构沿第一方向延伸，且可以为条状。第五晶体管的第二极T54和第六晶体管的第二极T64的一体成型结构在基底上的正投影与信号输出线OUTL在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第二晶体管的第二极T24、第八晶体管的第二极T84和第九晶体管的第一极T93的一体成型结构可以为旋转90度的“土”字型，且第二晶体管的第二极T24、第八晶体管的第二极T84和第九晶体管的第一极T93的一体成型结构在基底上的正投影与 第三晶体管的控制极T32和第四晶体管的控制极T42在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第一连接信号线L1沿第一方向延伸，且可以为条状。第一连接信号线L1在基底上的正投影与第九晶体管的控制极T92在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第二连接信号线L2沿第一方向延伸，且可以为条状。第二连接信号线L2在基底上的正投影与第八晶体管的控制极T82在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第三连接信号线L3沿第一方向延伸，且可以为条状。第三连接信号线L3在基底上的正投影与第二晶体管的控制极T22和第十晶体管的控制极T102在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第一晶体管的第一极T13和第二极T14通过第一过孔与第一晶体管的有源层连接，第二晶体管的第一极T23和第二晶体管的第二极T24通过第二过孔与第二晶体管的有源层连接，第三晶体管的第一极T33和第二极T34分别通过第三个第三过孔和第四个第三过孔与第三晶体管的有源层连接，第四晶体管的第一极T43和第二极T44通过第十五过孔与暴露出第四晶体管的有源层连接，第五晶体管的第一极T53和第二极T55通过第四过孔与第五晶体管的有源层连接，第六晶体管的第一极T63和第二极T65通过第十六过孔与第六晶体管的有源层连接，第七晶体管的第一极T73通过第五过孔与第七晶体管的有源层连接，第八晶体管的第二极T84通过第六过孔与第八晶体管的有源层连接，第九晶体管的第一极T93通过第十七过孔与第九晶体管的有源层连接，第十晶体管的第一极T103通过第十八过孔与第十晶体管的有源层连接。第一晶体管的第二极T14和第二晶体管的第一极T23的一体成型结构通过第十二过孔与电容的第一极板C1连接。第三晶体管的第二极T34和第四晶体管的第二极T44的一体成型结构通过第二十过孔与第六晶体管的控制极T62连接，且通过第十过孔与第五晶体管的控制极T52连接。第二晶体管的第二极T24、第八晶体管的第二极T84和第九晶体管的第一极T93为一体成型结构通过第十九过孔与 第十九过孔第四晶体管的控制极T42连接，且通过第九过孔与第三晶体管的控制极T32。第五晶体管的第二极T54和第六晶体管的第二极T64的一体成型结构通过第十三过孔与信号输出线OUTL连接。第一连接信号线L1通过第一个第三过孔与第三晶体管的有源层连接，且通过第二十一过孔与第九晶体管的控制极T92连接。第二连接信号线L2通过第二个第三过孔与第三晶体管的有源层连接，且通过第十一过孔V11与第八晶体管的控制极T82连接。第三连接信号线L3通过第一个第二十二过孔与第十晶体管的控制极T102连接，且通过第八过孔与第二晶体管的控制极T22连接。第一时钟信号线和第二时钟信号线CLK2中的其中一条信号线通过第七过孔与第一晶体管的控制极T12和第七晶体管的控制极T72的一体成型结构连接。第一时钟信号线和第二时钟信号线CLK2中的另一条信号线通过第二个第二十二过孔与第十晶体管的控制极T102连接。第二电源线VLL通过第十四过孔与电容的第二极板C2连接。
在一种示例性实施例中，如图19A和图19B所示，第九晶体管的控制极T92通过第一连接信号线L1和第三晶体管的有源层与第三晶体管的第二极和第四晶体管的第二极的一体成型结构连接。
在一种示例性实施例中，如图19A和图19B所示，第八晶体管的控制极T82通过第二连接信号线L2和第三晶体管的有源层与第三晶体管的第二极和第四晶体管的第二极的一体成型结构连接。
本公开实施例还提供了一种显示装置，该显示装置可以包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为液晶显示装置(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置。该显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种移位寄存器的驱动方法，设置为驱动移位寄 存器，该方法包括以下步骤：
步骤100、存储子电路存储第一节点的信号和第一电源端的信号之间的电压差；
步骤200、节点控制子电路在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；
步骤300、输出控制子电路在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
移位寄存器为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
本发明实施例附图只涉及本发明实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本发明的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本发明所揭露的实施方式如上，但所述的内容仅为便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (25)

  1. 一种移位寄存器，包括：存储子电路、节点控制子电路和输出控制子电路；
    所述存储子电路，分别与第一节点和第一电源端电连接，设置为存储第一节点的信号和第一电源端的信号之间的电压差；
    所述节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一节点和第二节点电连接，设置为在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；
    所述输出控制子电路，分别与第二节点、第一电源端、第二电源端和信号输出端电连接，设置为在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述输出控制子电路包括：第一输出控制子电路和第二输出控制子电路；
    所述第一输出控制子电路，分别与第二节点、第三节点、第一电源端和第二电源端电连接，设置为在第二节点的控制下，向第三节点提供第一电源端或第二电源端的信号；
    所述第二输出控制子电路，分别与第三节点、第一电源端、第二电源端和信号输出端电连接，设置为在第三节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
  3. 根据权利要求1或2所述的移位寄存器，还包括：降噪子电路；
    所述降噪子电路，分别与第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、第二节点和第三节点电连接，设置为在第一时钟信号端、第二时钟信号端和第三节点的控制下，向第二节点提供第一电源端或第二电源端的信号。
  4. 根据权利要求1所述的移位寄存器，其中，所述存储子电路包括：电容，电容包括：第一极板和第二极板；
    电容的第一极板与第一节点电连接，电容的第二极板与第一电源端电连接。
  5. 根据权利要求1所述的移位寄存器，其中，所述节点控制子电路包括：第一晶体管和第二晶体管；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第二时钟信号端电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第二节点电连接。
  6. 根据权利要求2所述的移位寄存器，其中，所述第一输出控制子电路包括：第三晶体管和第四晶体管，所述第二输出控制子电路包括：第五晶体管和第六晶体管；
    第三晶体管的控制极与第二节点电连接，第三晶体管的第一极与第一电源端电连接，第三晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第三节点电连接；
    第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与信号输出端电连接；
    第六晶体管的控制极与第三节点电连接，第六晶体管的第一极与第二电源端电连接，第六晶体管的第二极与信号输出端电连接；
    所述第三晶体管和所述第四晶体管的晶体管类型相反，所述第五晶体管和第六晶体管的晶体管类型相反。
  7. 根据权利要求3所述的移位寄存器，其中，所述降噪子电路包括：第七晶体管、第八晶体管、第九晶体管和第十晶体管；
    第七晶体管的控制极与第一时钟信号端电连接，第七晶体管的第一极与第一电源端电连接，第七晶体管的第二极与第八晶体管的第一极电连接；
    第八晶体管的控制极与第三节点电连接，第八晶体管的第二极与第二节点电连接；
    第九晶体管的控制极与第三节点电连接，第九晶体管的第一极与第二节点电连接，第九晶体管的第二极与第十晶体管的第二极电连接；
    第十晶体管的控制极与第二时钟信号端电连接，第十晶体管的第一极与第二电源端电连接；
    第七晶体管和第八晶体管的晶体管类型相同，第九晶体管和第十晶体管的晶体管类型相同，第七晶体管和第九晶体管的晶体管类型相反。
  8. 根据权利要求1所述的移位寄存器，其中，所述存储子电路包括：电容，电容包括：第一极板和第二极板；所述节点控制子电路包括：第一晶体管和第二晶体管；所述输出控制子电路包括：第三晶体管、第四晶体管、五晶体管和第六晶体管
    电容的第一极板与第一节点电连接，电容的第二极板与第一电源端电连接；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第二时钟信号端电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第二节点电连接，第三晶体管的第一极与第一电源端电连接，第三晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第三节点电连接；
    第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与信号输出端电连接；
    第六晶体管的控制极与第三节点电连接，第六晶体管的第一极与第二电源端电连接，第六晶体管的第二极与信号输出端电连接；
    第一晶体管、第二晶体管、第三晶体管和第五晶体管为P型晶体管，第四晶体管和第六晶体管为N型晶体管，且为氧化物晶体管。
  9. 根据权利要求1所述的移位寄存器，还包括：降噪子电路，所述存储子电路包括：电容，电容包括：第一极板和第二极板；所述节点控制子电路 包括：第一晶体管和第二晶体管；所述输出控制子电路包括：第三晶体管、第四晶体管、五晶体管和第六晶体管；所述降噪子电路包括：第七晶体管、第八晶体管、第九晶体管和第十晶体管；
    电容的第一极板与第一节点电连接，电容的第二极板与第一电源端电连接；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第二时钟信号端电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第二节点电连接，第三晶体管的第一极与第一电源端电连接，第三晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第三节点电连接；
    第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与信号输出端电连接；
    第六晶体管的控制极与第三节点电连接，第六晶体管的第一极与第二电源端电连接，第六晶体管的第二极与信号输出端电连接；
    第七晶体管的控制极与第一时钟信号端电连接，第七晶体管的第一极与第一电源端电连接，第七晶体管的第二极与第八晶体管的第一极电连接；
    第八晶体管的控制极与第三节点电连接，第八晶体管的第二极与第二节点电连接；
    第九晶体管的控制极与第三节点电连接，第九晶体管的第一极与第二节点电连接，第九晶体管的第二极与第十晶体管的第二极电连接；
    第十晶体管的控制极与第二时钟信号端电连接，第十晶体管的第一极与第二电源端电连接；
    第一晶体管、第二晶体管、第三晶体管、第五晶体管、第七晶体管和第八晶体管为P型晶体管，第四晶体管、第六晶体管、第九晶体管和第十晶体管为N型晶体管，且为氧化物晶体管。
  10. 根据权利要求1所述的移位寄存器，其中，所述第一时钟信号端的时钟信号和所述第二时钟信号端的时钟信号互为反相信号；
    所述信号输入端的信号为第一脉冲信号，所述第一脉冲信号的持续时间等于所述第一时钟信号端的时钟信号的周期，
    所述信号输出端的信号为第二脉冲信号，所述第二脉冲信号的持续时间等于所述第一脉冲信号的持续时间，且所述第二脉冲信号的开始时间为所述第一脉冲信号的结束时间。
  11. 根据权利要求1所述的移位寄存器，其中，所述第一时钟信号端的时钟信号和所述第二时钟信号端的时钟信号互为反相信号；
    所述信号输入端的信号为第三脉冲信号，所述第三脉冲信号的持续时间等于所述第一时钟信号端的时钟信号的周期的N倍，N为大于或者等于2的正整数；
    所述信号输出端的信号为第四脉冲信号，所述第四脉冲信号的持续时间等于所述第三脉冲信号的持续时间，且所述第四脉冲信号的开始时间与所述第三脉冲信号的开始时间之差等于所述第一时钟信号端的时钟信号的周期。
  12. 一种显示基板，包括：显示区域和非显示区域，所述显示基板包括：基底以及设置在所述基底上的电路结构层，所述电路结构层包括：位于非显示区域的栅极驱动电路和位于显示区域的阵列排布的像素电路，栅极驱动电路包括：多个级联的如权利要求1至11任一项所述的移位寄存器，像素电路包括：发光信号线、扫描信号线和复位信号线；
    第i级移位寄存器的信号输出端与第i+1级移位寄存器的信号输入端电连接，1≤i≤M-1，M为移位寄存器的总级数；
    所述栅极驱动电路与发光信号线、扫描信号线和复位信号线中的至少一种信号线电连接。
  13. 根据权利要求12所述的显示基板，还包括：沿第一方向延伸的第一时钟信号线、第二时钟信号线、第一电源线和第二电源线，第一电源线、第二电源线、第一时钟信号线和第二时钟信号线沿第二方向排布，所述第一方向与所述第二方向相交；
    所有移位寄存器的第一电源端与第一电源线电连接，所有移位寄存器的第二电源端与第二电源线电连接，第i级移位寄存器的第一时钟信号端与第一时钟信号线电连接，第i级移位寄存器的第二时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第一时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第二时钟信号端与第一时钟信号线电连接。
  14. 根据权利要求13所述的显示基板，其中，所述移位寄存器包括：第一晶体管至第十晶体管以及电容，电容包括：第一极板和第二极板；所述电路结构层包括：依次叠设在基底上的第一半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第二半导体层、第四绝缘层、第三导电层、第五绝缘层和第四导电层；
    所述第一半导体层包括：第一晶体管的有源层、第二晶体管的有源层、第三晶体管的有源层、第五晶体管的有源层、第七晶体管的有源层和第八晶体管的有源层；
    所述第一导电层包括：第一晶体管的控制极、第二晶体管的控制极、第三晶体管的控制极、第五晶体管的控制极、第七晶体管的控制极、第八晶体管的控制极、电容的第一极板和信号输出线；
    所述第二导电层包括：电容的第二极板；
    所述第二半导体层包括：第四晶体管的有源层、第六晶体管的有源层、第九晶体管的有源层和第十晶体管的有源层；
    所述第三导电层包括：第四晶体管的控制极、第六晶体管的控制极、第九晶体管的控制极和第十晶体管的控制极；
    所述第四导电层包括：第一时钟信号线、第二时钟信号线、第一电源线、第二电源线、第一晶体管的第一极和第二极至第六晶体管的第一极和第二极、第七晶体管的第一极、第八晶体管的第二极、第九晶体管的第一极、第十晶体管的第一极、第一连接信号线、第二连接信号线和第三连接信号线；
    信号输出线分别与第五晶体管的第二极和第六晶体管的第二极连接；
    第一连接信号线分别与第三晶体管的有源层和第九晶体管的控制极连接；
    第二连接信号线分别与第三晶体管的有源层和第八晶体管的控制极连接；
    第三连接信号线分别与第十晶体管的控制极和第二晶体管的控制极连接。
  15. 根据权利要求14所述的显示基板，其中，第五晶体管和第六晶体管位于第一电源线的同一侧，且第五晶体管和第六晶体管沿第一方向排布；
    第三晶体管位于第五晶体管远离第一电源线的一侧，第四晶体管位于第六晶体管远离第一电源线的一侧，第三晶体管和第四晶体管沿第一方向排布，第三晶体管和第五晶体管沿第二方向排布，第四晶体管和第六晶体管沿第二方向排布；
    第八晶体管位于第三晶体管远离第五晶体管的一侧，第九晶体管位于第四晶体管远离第六晶体管的一侧，第八晶体管和第九晶体管沿第一方向排布，第三晶体管和第八晶体管沿第二方向排布，第四晶体管和第九晶体管沿第二方向排布；
    第七晶体管位于第八晶体管远离第三晶体管的一侧，第十晶体管位于第九晶体管远离第四晶体管的一侧，第七晶体管和第十晶体管沿第一方向排布，第七晶体管和第八晶体管沿第二方向排布，第九晶体管和第十晶体管沿第二方向排布；
    第二晶体管位于第七晶体管和第十晶体管之间，第一晶体管位于第七晶体管远离第八晶体管的一侧，电容位于第十晶体管远离第九晶体管的一侧；
    第二电源线位于电容远离第十晶体管的一侧，第一时钟信号线位于第二电源线远离电容的一侧，第二时钟信号线位于第一时钟信号线远离第二电源线的一侧。
  16. 根据权利要求14或15所述的显示基板，其中，第一晶体管的有源层和第二晶体管的有源层为一体成型结构，第七晶体管的有源层与第八晶体管的有源层为一体成型结构；
    第三晶体管的有源层包括：第一有源连接部、第二有源连接部和第三有源连接部；第一有源连接部和第三有源连接部沿第一方向延伸，第二有源连接部沿第二方向延伸，且分别与第一有源连接部和第三有源连接部连接；
    第一有源连接部位于第二有源连接部靠近第七晶体管的有源层与第八晶体管的有源层的一体成型结构的一侧，第三有源连接部位于第二有源连接部 远离第七晶体管的有源层与第八晶体管的有源层的一体成型结构的一侧；
    沿第二方向延伸的直线经过第一有源连接部和第二晶体管的有源层；
    沿第二方向延伸的直线经过第三有源连接部和第一晶体管的有源层。
  17. 根据权利要求16所述的显示基板，其中，电容的第一极板包括：相互连接的第一电容主体部和第一电容连接部；
    第一晶体管的控制极和第七晶体管的控制极为一体成型结构，且位于第一电容连接部远离第一电容主体部的一侧；
    沿第二方向延伸的虚拟直线经过第八晶体管的控制极以及第一晶体管的控制极和第七晶体管的控制极的一体成型结构；
    沿第二方向延伸的虚拟直线经过第三晶体管的控制极和第八晶体管的控制极；
    沿第二方向延伸的虚拟直线经过第五晶体管的控制极和第三晶体管的控制极；
    沿第二方向延伸的虚拟直线经过信号输出线和第二晶体管的控制极。
  18. 根据权利要求17所述的显示基板，其中，电容的第二极板包括：相互连接的第二电容主体部和第二电容连接部，第二电容连接部位于第二电容主体部的一侧；
    电容的第一极板的第一电容主体部的面积大于电容的第二极板的第二电容主体部的面积；
    第二电容主体部和第二电容连接部在基底上的正投影与电容的第一极板的第一电容主体部在基底上的正投影至少部分交叠，且与电容的第一极板的第一电容连接部在基底上的正投影不交叠。
  19. 根据权利要求18所述的显示基板，其中，第六晶体管的有源层在基底上的正投影与第五晶体管的有源层在基底上的正投影分别位于信号输出线在基底上的正投影的相对设置的两侧，且沿第一方向延伸的直线经过第五晶体管的有源层和第六晶体管的有源层；
    沿第一方向延伸的直线经过第四晶体管的有源层和第三晶体管的有源层 的第三有源连接部；
    沿第一方向延伸的直线经过第九晶体管的有源层和第八晶体管的有源层，沿第一方向延伸的直线经过第十晶体管的有源层和第七晶体管的有源层。
  20. 根据权利要求18或19所述的显示基板，其中，沿第二方向延伸的虚拟直线经过第四晶体管的控制极、第六晶体管的控制极和第九晶体管的控制极；
    第十晶体管的控制极包括：第一电极连接部、第二电极连接部和第三电极连接部，第一电极连接部和第三电极连接部沿第二方向延伸，第二电极连接部沿第一方向延伸，且分别与第一电极连接部和第三电极连接部连接；
    第一电极连接部位于第二电极连接部靠近第九晶体管的控制极的一侧，第三电极连接部位于第二电极连接部远离第九晶体管的控制极的一侧；
    沿第二方向延伸的虚拟直线经过第十晶体管的控制极的第一电极连接部在基底上的正投影和电容的第一极板的第一电容主体部在基底上的正投影；
    第十晶体管的控制极的第三电极连接部在基底上的正投影位于电容的第一极板在基底上的正投影远离第一晶体管的控制极和第七晶体管的控制极的一体成型结构在基底上的正投影的一侧。
  21. 根据权利要求20所述的显示基板，其中，第五绝缘层开设有多个过孔图案，多个过孔图案包括：开设在第一绝缘层、第二绝缘层和第五绝缘层的第一过孔至第六过孔，开设在第二绝缘层至第五绝缘层的第七过孔至第十三过孔、开设在第三绝缘层至第五绝缘层的第十四过孔、开设在第四绝缘层至第五绝缘层的第十五过孔至第十八过孔以及开设在第五绝缘层的第十九过孔至第二十二过孔；
    第三过孔暴露出第三晶体管的有源层，第二十二过孔暴露出第十晶体管的控制极；
    第三过孔的数量为四个，沿第一方向延伸的虚拟直线穿过第一个第三过孔和第二个第三过孔，且第一个第三过孔和第二个第三过孔暴露出第三晶体管的有源层的第一有源连接部，沿第一方向延伸的虚拟直线穿过第三个第三过孔和第四个第三过孔，且第三个第三过孔和第四个第三过孔暴露出第三晶 体管的有源层的第三有源连接部，沿第二方向延伸的虚拟直线穿过第二个第三过孔和第三个第三过孔；
    第二十二过孔的数量为两个，第一个第二十二过孔暴露出第十晶体管的控制极的第二电极连接部，第二个二十二过孔暴露出第十晶体管的控制极的第三电极连接部。
  22. 根据权利要求21所述的显示基板，其中，第三晶体管的第一极、第五晶体管的第一极、第七晶体管的第一极和第一电源线为一体成型结构，第四晶体管的第一极、第六晶体管的第一极、第十晶体管的第一极和第二电源线为一体成型结构，第一晶体管的第二极和第二晶体管的第一极为一体成型结构，第三晶体管的第二极和第四晶体管的第二极为一体成型结构，第二晶体管的第二极、第八晶体管的第二极和第九晶体管的第一极为一体成型结构，第五晶体管的第二极和第六晶体管的第二极为一体成型结构；
    第一电源线在基底上的正投影与信号输出线在基底上的正投影至少部分交叠；
    第二电源线在基底上的正投影与第一晶体管的控制极和第七晶体管的控制极的一体成型结构、第十晶体管的控制极以及电容的第二极板的第二电容连接部在基底上的正投影部分交叠；
    第一时钟信号线在基底上的正投影与第十晶体管的控制极以及第一晶体管的控制极和第七晶体管的控制极的一体成型结构在基底上的正投影部分交叠；
    第二时钟信号线与所连接的晶体管的控制极在基底上的正投影部分交叠；
    第一晶体管的第二极和第二晶体管的第一极的一体成型结构在基底上的正投影与电容的第一极板的第一电容连接部在基底上的正投影部分交叠；
    第三晶体管的第二极和第四晶体管的第二极的一体成型结构在基底上的正投影与第六晶体管的控制极和第五晶体管的控制极在基底上的正投影部分交叠；
    第五晶体管的第二极和第六晶体管的第二极的一体成型结构在基底上的正投影与信号输出线在基底上的正投影部分交叠；
    第二晶体管的第二极、第八晶体管的第二极和第九晶体管的第一极的一体成型结构在基底上的正投影与第三晶体管的控制极和第四晶体管的控制极在基底上的正投影部分交叠；
    第一连接信号线在基底上的正投影与第九晶体管的控制极在基底上的正投影部分交叠；
    第二连接信号线在基底上的正投影与第八晶体管的控制极在基底上的正投影部分交叠；
    第三连接信号线在基底上的正投影与第二晶体管的控制极和第十晶体管的控制极在基底上的正投影部分交叠。
  23. 根据权利要求22所述的显示基板，其中，第三晶体管的第一极和第二极分别通过第三个第三过孔和第四个第三过孔与第三晶体管的有源层连接；
    第一连接信号线通过第一个第三过孔与第三晶体管的有源层连接；
    第二连接信号线通过第二个第三过孔与第三晶体管的有源层连接；
    第三连接信号线通过第一个第二十二过孔与第十晶体管的控制极连接；
    第一时钟信号线和第二时钟信号线中的一条信号线通过第二个第二十二过孔与第十晶体管的控制极连接。
  24. 一种显示装置，包括：如权利要求12至23任一项所述的显示基板。
  25. 一种移位寄存器的驱动方法，设置为驱动如权利要求1至11任一项所述的移位寄存器，所述方法包括：
    存储子电路存储第一节点的信号和第一电源端的信号之间的电压差；
    节点控制子电路在第一时钟信号端的控制下，将信号输入端的信号提供至第一节点，在第二时钟信号端的控制下，将第一节点的信号提供至第二节点；
    输出控制子电路在第二节点的控制下，向信号输出端提供第一电源端或第二电源端的信号。
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CN114512084A (zh) * 2022-03-03 2022-05-17 北京京东方技术开发有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示面板

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