WO2023221390A1 - Anti-fuse circuit and method for real-time verification of burning state of anti-fuse unit - Google Patents
Anti-fuse circuit and method for real-time verification of burning state of anti-fuse unit Download PDFInfo
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- WO2023221390A1 WO2023221390A1 PCT/CN2022/126177 CN2022126177W WO2023221390A1 WO 2023221390 A1 WO2023221390 A1 WO 2023221390A1 CN 2022126177 W CN2022126177 W CN 2022126177W WO 2023221390 A1 WO2023221390 A1 WO 2023221390A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- Figure 2 is a signal timing diagram of the antifuse circuit provided by the first embodiment of the present disclosure
- the input signal EFDAT at the input end of unit 30 is inverted, and in the second embodiment, due to the existence of the first inverter P1, the output signal of the latch 32 is inverted by the first inverter P1 Finally, as the output signal EFOUT of the output terminal OUT, the output signal EFOUT of the output terminal OUT is in the same phase as the input signal EFDAT of the input terminal of the reading unit 30 .
- the programming signal Data is 0 (that is, indicating breakdown of the anti-fuse unit 10 )
- the first transistor of the verification control unit 40 is turned off, and the reading unit 30
- the input terminal IN is disconnected from the ground terminal GND.
- the anti-fuse unit programming status verification method provided by the embodiment of the present disclosure can verify whether the anti-fuse unit 10 is programmed correctly according to the data signal and the programming signal Data, without the need to read the data signal to test The machine then verifies the programming status of the anti-fuse unit 10, which can quickly verify whether the anti-fuse unit 10 has been burned through by mistake, saving time and having a high verification accuracy.
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Abstract
Description
相关申请引用说明Related application citations
本申请要求于2022年05月19日递交的中国专利申请号202210545449.0、申请名为“反熔丝电路及反熔丝单元烧写状态实时验证方法”的优先权，其全部内容以引用的形式附录于此。This application claims priority to the Chinese patent application number 202210545449.0 submitted on May 19, 2022, titled "Anti-fuse circuit and anti-fuse unit programming status real-time verification method", the entire content of which is appended in the form of a reference. Here it is.
本发明涉及集成电路领域，尤其涉及一种反熔丝电路及反熔丝单元烧写状态实时验证方法。The invention relates to the field of integrated circuits, and in particular to an antifuse circuit and a method for real-time verification of the programming status of an antifuse unit.
在半导体工业中，熔丝元件由于具有多种用途而被广泛使用在集成电路中。例如，在集成电路中设计多个具有相同功能的电路模块作为备份，当发现其中一个电路模块失效时，通过熔丝元件将电路模块和集成电路中的其它功能电路烧断，而使用具有相同功能的另一个电路模块取代失效的电路模块。In the semiconductor industry, fuse components are widely used in integrated circuits due to their various uses. For example, multiple circuit modules with the same function are designed in an integrated circuit as backup. When one of the circuit modules is found to be faulty, the circuit module and other functional circuits in the integrated circuit are blown out through the fuse element, and the circuit module with the same function is used. Another circuit module replaces the failed circuit module.
随着半导体技术的不断发展，反熔丝(Anti-fuse)技术已经吸引了很多发明者和制造商的关注。反熔丝元件通过从绝缘状态变为导电状态来存储信息。通过施加高压导致的介质击穿来执行向反熔丝元件写入信息。反熔丝存储单元在编程前呈电容特性，无导通沟道形成；当发生编程击穿后，在单元两端会形成导通沟道，可以通过电流，导通电流的大小与编程效果相关。With the continuous development of semiconductor technology, anti-fuse (Anti-fuse) technology has attracted the attention of many inventors and manufacturers. Antifuse elements store information by changing from an insulating state to a conducting state. Writing information to the antifuse element is performed by dielectric breakdown caused by application of high voltage. The antifuse memory cell has capacitive characteristics before programming, and no conduction channel is formed; when programming breakdown occurs, conduction channels will be formed at both ends of the cell, allowing current to pass through. The size of the conduction current is related to the programming effect. .
然而，现有的反熔丝电路无法实现反熔丝单元的实时验证，无法满足需求。However, the existing antifuse circuit cannot realize real-time verification of the antifuse unit and cannot meet the demand.
发明内容Contents of the invention
本公开实施例所要解决的技术问题是，提供一种反熔丝电路及反熔丝单元烧写状态实时验证方法，其能够对反熔丝单元的烧写状态进行实时验证。The technical problem to be solved by the embodiments of the present disclosure is to provide an anti-fuse circuit and a method for real-time verification of the programming status of the anti-fuse unit, which can perform real-time verification of the programming status of the anti-fuse unit.
为了解决上述问题，本公开实施例提供了一种反熔丝电路，其包括：反熔丝单元；读取单元，用于对所述反熔丝单元进行读取获得数据信号；验证控制单元，设置在所述读取单元的输入端与地端之间，所述验证控制单元接收所述反熔丝单元的烧写信号，用于在验证所述反熔丝单元的烧写状态时，根据所述烧写信号控制所述读取单元的输入端与地端断开连接，所述烧写信号表征所述反熔丝单元击穿。In order to solve the above problems, embodiments of the present disclosure provide an anti-fuse circuit, which includes: an anti-fuse unit; a reading unit for reading the anti-fuse unit to obtain a data signal; a verification control unit, Disposed between the input end of the reading unit and the ground end, the verification control unit receives the programming signal of the anti-fuse unit and is used to verify the programming status of the anti-fuse unit according to The programming signal controls the input terminal of the reading unit to be disconnected from the ground terminal, and the programming signal indicates breakdown of the antifuse unit.
在一实施例中，所述验证控制单元包括：第一晶体管，具有第一端、第二 端及控制端，所述第一晶体管的第一端与所述读取单元的输入端电连接，所述第一晶体管的第二端与所述地端电连接，所述第一晶体管的控制端用于接收所述烧写信号。In one embodiment, the verification control unit includes: a first transistor having a first terminal, a second terminal and a control terminal, the first terminal of the first transistor is electrically connected to the input terminal of the reading unit, The second terminal of the first transistor is electrically connected to the ground terminal, and the control terminal of the first transistor is used to receive the programming signal.
在一实施例中，所述第一晶体管为NMOS晶体管。In one embodiment, the first transistor is an NMOS transistor.
在一实施例中，所述反熔丝电路还包括验证开关单元，设置在所述验证控制单元与所述读取单元的输入端之间，用于响应于所述验证使能信号导通。In one embodiment, the anti-fuse circuit further includes a verification switch unit, which is disposed between the verification control unit and the input end of the reading unit and is configured to be turned on in response to the verification enable signal.
在一实施例中，所述验证开关单元包括第二晶体管，所述第二晶体管的第一端与所述读取单元的输入端电连接，所述第二晶体管的第二端与所述验证控制单元电连接，所述第二晶体管的的控制端用于接收所述验证使能信号。In one embodiment, the verification switch unit includes a second transistor, a first end of the second transistor is electrically connected to the input end of the reading unit, and a second end of the second transistor is electrically connected to the verification unit. The control unit is electrically connected, and the control end of the second transistor is used to receive the verification enable signal.
在一实施例中，所述反熔丝单元包括第一端及第二端，所述反熔丝单元的第一端接地，所述反熔丝单元的第二端与所述读取单元的输入端电连接。In one embodiment, the anti-fuse unit includes a first end and a second end, the first end of the anti-fuse unit is grounded, and the second end of the anti-fuse unit is connected to the reading unit. The input terminals are electrically connected.
在一实施例中，所述读取单元包括：预充电单元，用于根据预充电控制信号向所述读取单元的输入端进行预充电；锁存器，所述锁存器的输入端与所述读取单元的输入端电连接，所述锁存器的输出端与所述读取单元的输出端电连接。In one embodiment, the reading unit includes: a precharge unit for precharging an input terminal of the reading unit according to a precharge control signal; a latch, the input terminal of the latch is connected to The input terminal of the reading unit is electrically connected, and the output terminal of the latch is electrically connected to the output terminal of the reading unit.
在一实施例中，所述预充电单元包括第三晶体管，所述第三晶体管的第一端连接电源电压，所述第三晶体管的第二端连接所述读取单元的输入端，所述第二晶体管的控制端接收所述预充电控制信号。In one embodiment, the precharging unit includes a third transistor, a first terminal of the third transistor is connected to the power supply voltage, a second terminal of the third transistor is connected to the input terminal of the reading unit, and the The control terminal of the second transistor receives the precharge control signal.
在一实施例中，所述反熔丝电路还包括读开关单元，所述读开关单元用于根据读使能信号控制所述读取单元的输入端与所述反熔丝单元的第二端电连接。In one embodiment, the anti-fuse circuit further includes a read switch unit configured to control the input end of the read unit and the second end of the anti-fuse unit according to a read enable signal. Electrical connection.
在一实施例中，所述读开关单元包括第四晶体管，所述第四晶体管的第一端连接所述反熔丝单元的第二端，所述第四晶体管的第二端连接所述读取单元的输入端，所述第三晶体管的控制端接收所述读使能信号NMOS晶体管。In one embodiment, the read switch unit includes a fourth transistor, a first terminal of the fourth transistor is connected to the second terminal of the antifuse unit, and a second terminal of the fourth transistor is connected to the read switch unit. The input terminal of the unit is taken, and the control terminal of the third transistor receives the read enable signal NMOS transistor.
在一实施例中，所述读取单元还包括第一反相器，所述第一反相器设置在所述锁存器与所述输出端之间。In one embodiment, the reading unit further includes a first inverter, and the first inverter is disposed between the latch and the output terminal.
本公开实施例还提供一种反熔丝单元烧写状态实时验证方法，采用上述的反熔丝电路，所述方法包括：输入烧写信号，根据所述烧写信号对所述反熔丝单元进行烧写，所述烧写信号表征所述反熔丝单元击穿；根据所述烧写信号和 验证使能信号控制读取单元的输入端与地端断开连接；所述读取单元对所述反熔丝单元进行读取获得数据信号；根据所述数据信号和所述烧写信号验证所述反熔丝单元是否烧写正确。Embodiments of the present disclosure also provide a method for real-time verification of the programming status of an anti-fuse unit, using the above-mentioned anti-fuse circuit. The method includes: inputting a programming signal, and verifying the anti-fuse unit according to the programming signal. Perform programming, and the programming signal represents the breakdown of the anti-fuse unit; control the input terminal of the reading unit to disconnect from the ground terminal according to the programming signal and the verification enable signal; the reading unit The anti-fuse unit reads and obtains a data signal; and verifies whether the anti-fuse unit is programmed correctly according to the data signal and the programming signal.
在一实施例中，所述根据所述数据信号和所述烧写信号验证所述反熔丝单元是否烧写正确的步骤还包括：比较所述数据信号和所述烧写信号，根据所述数据信号和所述烧写信号的比较结果确定所述反熔丝单元是否烧写正确。In one embodiment, the step of verifying whether the anti-fuse unit is programmed correctly according to the data signal and the programming signal further includes: comparing the data signal and the programming signal, and according to the The comparison result between the data signal and the programming signal determines whether the anti-fuse unit is programmed correctly.
在一实施例中，根据所述数据信号和所述烧写信号的比较结果确定所述反熔丝单元是否烧写正确的步骤还包括：所述数据信号和所述烧写信号一致，所述反熔丝单元烧写错误；所述数据信号和所述烧写信号不一致，所述反熔丝单元烧写正确。In one embodiment, the step of determining whether the anti-fuse unit is correctly programmed based on the comparison result between the data signal and the programming signal further includes: the data signal is consistent with the programming signal, and the The anti-fuse unit is programmed incorrectly; the data signal and the programming signal are inconsistent, and the anti-fuse unit is programmed correctly.
本公开实施例提供的反熔丝电路当在反熔丝单元完成击穿烧写进入验证(verify)模式时，所述验证控制单元能够控制所述读取单元与地端断开连接，所述读取单元读取所述反熔丝单元的数据信号，所述数据信号经所述读取单元的输出端以输出信号的形式输出，利用所述烧写信号与反熔丝单元的数据信号实时验证所述反熔丝单元是否烧写正确，从而能够实现实时对反熔丝单元进行验证的目的。In the anti-fuse circuit provided by the embodiment of the present disclosure, when the anti-fuse unit completes breakdown and programming and enters the verification mode, the verification control unit can control the reading unit to disconnect from the ground terminal. The reading unit reads the data signal of the anti-fuse unit, and the data signal is output in the form of an output signal through the output end of the reading unit. The programming signal and the data signal of the anti-fuse unit are used in real time. Verify whether the anti-fuse unit is programmed correctly, thereby achieving the purpose of verifying the anti-fuse unit in real time.
图1是本公开第一实施例提供的反熔丝电路的示意图；Figure 1 is a schematic diagram of an antifuse circuit provided by a first embodiment of the present disclosure;
图2是本公开第一实施例提供的反熔丝电路的信号时序图；Figure 2 is a signal timing diagram of the antifuse circuit provided by the first embodiment of the present disclosure;
图3是本公开第二实施例提供的反熔丝电路的示意图；Figure 3 is a schematic diagram of an antifuse circuit provided by a second embodiment of the present disclosure;
图4是本公开第二实施例提供的反熔丝电路的信号时序图；Figure 4 is a signal timing diagram of the antifuse circuit provided by the second embodiment of the present disclosure;
图5是本公开第三实施例提供的反熔丝单元烧写状态验证方法的步骤示意图；Figure 5 is a schematic diagram of the steps of the antifuse unit programming status verification method provided by the third embodiment of the present disclosure;
图6是信号真值表。Figure 6 is the signal truth table.
下面结合附图对本发明提供的反熔丝电路及反熔丝单元烧写状态实时验证方法的具体实施方式做详细说明。The specific implementation of the anti-fuse circuit and the anti-fuse unit programming status real-time verification method provided by the present invention will be described in detail below with reference to the accompanying drawings.
图1是本公开第一实施例提供的反熔丝电路的示意图，请参阅图1，所述反熔丝电路包括反熔丝单元10、读取单元30、验证控制单元40；所述读取单 元30用于对反熔丝单元10进行读取并获得数据信号；所述验证控制单元40设置在所述读取单元30的输入端与地端之间，所述验证控制单元40接收所述反熔丝单元10的烧写信号Data，用于在验证所述反熔丝单元10的烧写状态时，根据所述烧写信号Data控制所述读取单元30的输入端与地端断开连接，所述烧写信号Data表征所述反熔丝单元10击穿。在本实施例中，所述反熔丝电路还包括烧写电路20，所述烧写电路20用于对所述反熔丝单元10进行烧写。Figure 1 is a schematic diagram of an anti-fuse circuit provided by the first embodiment of the present disclosure. Please refer to Figure 1. The anti-fuse circuit includes an
在本实施例中，所述反熔丝单元10包括第一端10A及第二端10B。所述第一端10A接地GND，所述第二端10B能够与所述读取单元30的输入端IN及烧写电路20电连接。在所述反熔丝单元10的第一端10A与第二端10B之间施加高压，高压能够击穿反熔丝单元10的介质，使所述反熔丝单元10从断路状态变为导电状态，实现信息的存储。在对反熔丝单元10执行烧写操作后，若所述反熔丝单元10为导通状态说明所述反熔丝单元10击穿，若所述反熔丝单元10为断路状态说明所述反熔丝单元10未击穿。在本实施例中，采用烧写信号Data表征所述反熔丝单元10击穿，例如，烧写信号Data的真值为“0”，表征所述反熔丝单元10击穿。In this embodiment, the
在本实施例中，所述烧写电路20与所述反熔丝单元10连接，用于根据烧写控制信号BlowEn对所述反熔丝单元10进行烧写，即所述烧写控制信号BlowEn作为所述烧写电路20的使能信号。当需要对所述反熔丝单元10进行烧写时，所述烧写控制信号BlowEn使能所述烧写电路20，对所述反熔丝单元10执行烧写操作。In this embodiment, the
作为示例，本实施例还提供一种烧写电路20的结构。所述烧写电路20包括烧写控制单元21及信号转换单元22。As an example, this embodiment also provides a structure of the
所述烧写控制单元21以烧写控制信号BlowEn作为使能信号，将烧写信号Data传输至信号转换单元22。例如，在本实施例中，所述烧写控制单元包括一个第一NMOS晶体管MN1，所述第一NMOS晶体管MN1的控制端连接烧写控制信号BlowEn，所述第一NMOS晶体管MN1的一端连接烧写信号Data，另一端连接信号转换单元22。当需要进行烧写时，所述烧写控制信号BlowEn置为1，以使所述第一NMOS晶体管MN1导通，所述烧写信号Data传输至所述信号转换单元22。The
所述信号转换单元22一端连接至编程电压VPP，另一端连接至反熔丝单元10，并以所述烧写信号Data作为控制信号，实现对反熔丝单元10的烧写。例如，在本实施例中，所述信号转换单元22包括第一PMOS晶体管MP1及第二PNOS晶体管MP2，所述第一PMOS晶体管MP1的一端与编程电压VPP连接，另一端与反熔丝单元10连接，所述第一PMOS晶体管MP1的控制端接收所述烧写信号Data。所述第二PNOS晶体管MP2的一端与编程电压VPP连接，另一端与所述第一PMOS晶体管MP1的控制端连接，所述第二PNOS晶体管MP2的控制端接收偏置信号，其中，所述偏置信号的电压Vbias小于所述编程电压VPP。One end of the
当需要对所述反熔丝单元10进行烧写时，所述烧写信号Data置为0，所述烧写控制信号BlowEn置为1，所述第一NMOS晶体管MN1导通，所述烧写信号Data控制所述第一PMOS晶体管MP1导通，所述反熔丝单元10两端的电压差为编程电压VPP与接地端GND之间的电压差，从而实现对反熔丝单元10的编写。若所述烧写信号Data置为1，则所述第一PMOS晶体管MP1不导通，所述烧写电路20不对所述反熔丝单元10进行烧写。When the
在本实施例中，所述烧写电路20还包括放大单元23，所述烧写控制单元21输出的烧写信号Data经所述放大单元23后传输至信号转换单元22。In this embodiment, the
在上述示例中，所述反熔丝单元10的第一端10A接地GND，第二端10B与所述读取单元30的输入端IN及烧写电路20电连接，可以理解的是，在另一些示例中，所述反熔丝单元10的第一端与编程电压VPP连接，第二端与所述读取单元30的输入端IN及烧写电路连接，所述烧写电路连接至接地端GND。In the above example, the
请继续参阅图1，所述读取单元30的输入端IN与反熔丝单元10的第二端10B连接，所述读取单元30的输出端OUT输出信号EFOUT，所述输出信号EFOUT即为从所述反熔丝单元10读取的数据信号。所述读取单元30输入端的输入信号EFDAT受到所述反熔丝单元10的击穿状态的影响，所述读取单元30根据所述反熔丝单元的击穿状态输出输出信号EFOUT至所述输出端OUT。在本实施例中，若所述反熔丝单元10击穿，所述反熔丝单元10导通，则所述读取单元30的输入端IN通过所述反熔丝单元10连接至接地端GND， 所述读取单元30的输入端输入信号EFDAT被拉低，置为0；若所述反熔丝单元10未击穿，所述反熔丝单元10不导通，则所述读取单元30未通过反熔丝单元10与接地端GND连接，所述读取单元30的输入端的输入信号EFDAT维持1。Please continue to refer to FIG. 1 . The input terminal IN of the
作为示例，本实施例提供一种读取单元30的电路结构。所述读取单元30包括预充电单元31及锁存器32。As an example, this embodiment provides a circuit structure of the
所述预充电单元31用于根据预充电控制信号pre向读取单元30的输入端进行预充电，即向所述锁存器32充电。在一些实施例中，所述预充电单元31包括第三晶体管，所述第三晶体管的第一端连接电源电压VDD，所述第三晶体管的第二端连接所述读取单元30的输入端IN，所述第二晶体管的控制端接收所述预充电控制信号pre。具体地说，请参阅图1，在本实施例中，所述第三晶体管为第三PMOS晶体管MP3，所述第三PMOS晶体管MP3的第一端连接电源电压VDD，所述第三PMOS晶体管MP3的第二端连接所述读取单元30的输入端IN，所述第三PMOS晶体管MP3的控制端接收所述预充电控制信号pre。当所述预充电控制信号pre置为0时，所述第三PMOS晶体管MP3导通，所述读取单元30的输入端IN与电源电压VDD连接，所述预充电单元31向所述读取单元30的输入端IN充电，拉高所述读取单元30的输入端IN电压，使所述输入信号EFDAT置为1。The
所述锁存器32的输入端与所述读取单元30的输入端IN电连接，输出端与所述读取单元30的输出端OUT电连接。所述锁存器32能够锁存读取单元30输入端IN的输入信号EFDAT。在本实施例中，所述锁存器包括第二反相器P2及第三反相器P3，第二反相器P2及第三反相器P3首尾相连，其中，第二反相器P2的输入端与读取单元30的输入端IN电连接，第二反相器P2的输出端与所述读取单元30的输出端OUT电连接，所述第三反相器P3的输入端与所述第二反相器P2的输出端电连接，所述第三反相器P3的输出端与所述第二反相器P2的输入端电连接，实现锁存器的功能。The input terminal of the
在本实施例中，所述读反熔丝结构还包括读开关单元S1，所述读开关单元S1用于根据读使能信号discharge控制所述读取单元30的输入端IN与所述反熔丝单元10的第二端10B的电连接。在一些实施例中，所述读开关单元S1 包括第四晶体管，所述第四晶体管的第一端连接所述反熔丝单元10的第二端10B，所述第四晶体管的第二端连接所述读取单元30的输入端IN，所述第三晶体管的控制端接收所述读使能信号。具体地说，请参阅图1，在本实施例中，所述第四晶体管为第二NMOS晶体管MN2。当读使能信号discharge置为1时，所述第二NMOS晶体管MN2导通，所述读取单元30与所述反熔丝单元10电连接，所述读取单元30能够对所述反熔丝单元10进行读取获得数据信号。可以理解的是，在烧写电路20对所述反熔丝单元10进行烧写时，读使能信号discharge置为0，所述读开关单元S1断开，所述读取单元30与所述反熔丝单元10不连通。In this embodiment, the read antifuse structure also includes a read switch unit S1, which is used to control the input terminal IN of the
在本实施例中，在对所述反熔丝单元10进行读写放大时，读使能信号discharge置为0，所述读开关单元S1断开，所述预充电单元31对所述读取单元30的输入端IN充电，使所述读取单元30的输入端IN置为1；读使能信号discharge置为1，所述读开关单元S1导通，所述读取单元输入端IN与所述反熔丝单元10的第二端10B连接，若所述反熔丝单元10击穿，则所述读取单元30的输入端IN变为0，所述输出端OUT输出1，若所述反熔丝单元10未击穿，则所述读取单元30的输入端IN保持1，所述输出端OUT输出0。In this embodiment, when the
所述验证控制单元40接收所述反熔丝单元10的烧写信号Data，用于在验证所述反熔丝单元10的烧写状态时，根据所述烧写信号Data控制所述读取单元30的输入端与地端断开连接。The
在本实施例中，所述验证控制单元40包括第一晶体管。所述第一晶体管用于接收所述烧写信号Data。所述第一晶体管的第一端40A与所述读取单元30的输入端IN电连接，所述第一晶体管的第二端410B与所述地端GND电连接，所述第一晶体管的控制端40C用于接收所述烧写信号Data。In this embodiment, the
在一些实施例中，所述第一晶体管为NMOS晶体管，具体地说，请参阅图1，在本实施例中，所述第一晶体管为第三MNOS晶体管MN3。当所述烧写信号Data表征所述反熔丝单元10击穿时，所述烧写信号Data的真值为“0”，则所述第三NMOS晶体管MN3断开，所述读取单元30的输入端IN与地端GND断开连接。In some embodiments, the first transistor is an NMOS transistor. Specifically, please refer to FIG. 1 . In this embodiment, the first transistor is a third MNOS transistor MN3. When the programming signal Data represents the breakdown of the
所述反熔丝电路还包括验证开关单元42，设置在所述验证控制单元40与 所述读取单元30的输入端IN之间，用于响应于验证使能信号VerifyEn导通。The anti-fuse circuit also includes a
在一些实施例中，所述验证开关单元42包括第二晶体管，所述第二晶体管的第一端42A与所述读取单元30的输入端IN电连接，所述第二晶体管的第二端42B与所述第一晶体管的第一端41A电连接，所述第二晶体管的控制端42C用于接收验证使能信号VerifyEn。In some embodiments, the
一些实施例中，所述第二晶体管为NMOS晶体管。具体地说，请参阅图1，在本实施例中，所述第二晶体管为第四NMOS晶体管MN4。当所述验证使能信号VerifyEn置为1时，所述第四NMOS晶体管MN4导通，所述读取单元30的输入端IN与所述第一晶体管的第一端41A连接，而此时所述第一晶体管不导通，则所述读取单元30的输入端与所述地端GND断开连接。In some embodiments, the second transistor is an NMOS transistor. Specifically, please refer to FIG. 1. In this embodiment, the second transistor is a fourth NMOS transistor MN4. When the verification enable signal VerifyEn is set to 1, the fourth NMOS transistor MN4 is turned on, and the input terminal IN of the
在另一些实施例中，所述第二晶体管为PMOS晶体管。可以理解的是，所述第二晶体管为PMOS晶体管时，所述验证使能信号VerifyEn置为0时，所述PMOS晶体管导通，所述读取单元30的输入端IN与所述第一晶体管的第一端41A连接，而此时所述第一晶体管不导通，则所述读取单元30的输入端与所述地端GND断开连接。In other embodiments, the second transistor is a PMOS transistor. It can be understood that when the second transistor is a PMOS transistor, when the verification enable signal VerifyEn is set to 0, the PMOS transistor is turned on, and the input terminal IN of the
本公开实施例提供的反熔丝电路当在反熔丝单元10完成击穿烧写进入验证(verify)模式时，所述验证控制单元40能够控制所述读取单元30与地端断开连接，所述读取单元30对所述反熔丝单元10进行读取获得数据信号，所述数据信号经所述读取单元30的输出端OUT以输出信号EFOUT的形式输出，利用所述烧写信号Data与反熔丝单元10的数据信号实时验证所述反熔丝单元是否烧写正确，从而能够实现实时对反熔丝单元10进行验证的目的。可以理解的是，在一些实施例中，在所述读取单元30执行读写放大操作时，而并非是验证模式时，所述验证控制单元40的第二单元42保持断开状态，以避免影响所述反熔丝单元10与所述读取单元30的连通。In the anti-fuse circuit provided by the embodiment of the present disclosure, when the
图2是本公开第一实施例提供的反熔丝电路的信号时序图，在反熔丝单元10完成击穿烧写后，进入验证(verify)模式。FIG. 2 is a signal timing diagram of the antifuse circuit provided by the first embodiment of the present disclosure. After the
请参阅图2，在验证模式下，烧写电路20的烧写控制信号BlowEn置为0，所述预充电控制信号pre置为0，所述读取单元30的预充电单元31向所述锁存器32充电，所述读取单元30的输入端IN的输入信号EFDAT置为1，读取 单元30输出端OUT的输出信号EFOUT输出0。充电结束后，所述预充电控制信号pre置为1，验证使能信号VerifyEn置为1，验证控制单元40被使能，读使能信号discharge置为1，读开关单元S1导通，所述读取单元30与所述反熔丝单元10导通。当所述烧写信号Data为0(即表征所述反熔丝单元10击穿)，所述验证控制单元40的第一晶体管断开，所述读取单元30的输入端IN与地端GND断开连接，此时，若所述读取单元30输出端OUT的输出信号EFOUT为1(如图2中虚线所示)，说明所述反熔丝单元10的真实状态是击穿，该真实状态与烧写信号Data一致，反熔丝单元10烧写正确，若所述读取单元30输出端OUT的输出信号EFOUT为0(如图2中实线所示)，说明所述反熔丝单元10的真实状态是未击穿，该真实状态与烧写信号Data不一致，反熔丝单元10误烧写。Please refer to Figure 2. In the verification mode, the programming control signal BlowEn of the
可以理解的是，当所述烧写信号Data表征所述反熔丝单元10未击穿时，例如，所述烧写信号Data的真值为“1”时，所述验证使能信号VerifyEn不使能所述验证开关单元42。具体地说，若所述使能开关单元42的第二晶体管为NMOS晶体管，则当所述烧写信号Data表征所述反熔丝单元10未击穿时，所述验证使能信号VerifyEn置为0；若所述使能开关单元42的第二晶体管为PMOS晶体管，则当所述烧写信号Data表征所述反熔丝单元10未击穿时，所述验证使能信号VerifyEn置为1，以避免所述验证控制单元40被使能。It can be understood that when the programming signal Data indicates that the
本公开反熔丝电路不需要将数据信号读出到测试机台再对反熔丝单元10的烧写状态进行验证，而是能够实时验证所述反熔丝单元10的烧写状态，能够快速地验证反熔丝单元10是否被误烧穿，节约时间，并且验证准确率高。The anti-fuse circuit of the present disclosure does not need to read the data signal to the test machine and then verify the programming status of the
作为示例，本公开第二实施例还提供一种反熔丝电路，请参阅图3，其为本公开第二实施例提供的反熔丝电路的电路图，第二实施例与第一实施例的区别在于，在第三实施例中，所述读取单元30还包括第一反相器P1，所述第一反相器P1设置在所述锁存器32与所述读取单元30的输出端OUT之间，以对所述锁存器32输出的信号进行整形。As an example, the second embodiment of the present disclosure also provides an anti-fuse circuit. Please refer to FIG. 3, which is a circuit diagram of the anti-fuse circuit provided by the second embodiment of the present disclosure. The difference between the second embodiment and the first embodiment is The difference is that in the third embodiment, the
图4是本公开第二实施例提供的反熔丝电路的信号时序图，请参阅图4，第二实施例反熔丝电路的时序图与第一实施例反熔丝电路提供的时序图的区别在于，读取单元30的输出端OUT的输出信号EFOUT的时序不同。具体地 说，请参阅图2，在第一实施例中，所述锁存器32的输出信号直接作为所述输出端OUT的输出信号EFOUT，则所述输出端OUT的输出信号EFOUT与读取单元30输入端的输入信号EFDAT反相，而在第二实施例中，由于所述第一反相器P1的存在，所述锁存器32的输出信号经所述第一反相器P1反相后作为输出端OUT的输出信号EFOUT，则所述输出端OUT的输出信号EFOUT与读取单元30输入端的输入信号EFDAT同相。在第二实施例中，若所述烧写信号Data为0(即表征所述反熔丝单元10击穿)，所述验证控制单元40的第一晶体管断开，所述读取单元30的输入端IN与地端GND断开连接，若所述读取单元30输出端OUT的输出信号EFOUT为0(如图4中虚线所示)，说明所述反熔丝单元10的真实状态是击穿，该真实状态与烧写信号Data一致，反熔丝单元10烧写正确；若所述烧写信号Data为0(即表征所述反熔丝单元10击穿)，而所述读取单元30输出端OUT的输出信号EFOUT为1(如图2中实线所示)，说明所述反熔丝单元10的真实状态是未击穿，该真实状态与烧写信号Data不一致，反熔丝单元10误烧写。Figure 4 is a signal timing diagram of the anti-fuse circuit provided by the second embodiment of the present disclosure. Please refer to Figure 4. The timing diagram of the anti-fuse circuit of the second embodiment is different from the timing diagram provided by the anti-fuse circuit of the first embodiment. The difference lies in that the timing of the output signal EFOUT of the output terminal OUT of the
本公开实施例还提供一种反熔丝单元烧写状态实时验证方法，采用上述的反熔丝电路。图5是本公开第三实施例提供的反熔丝单元烧写状态验证方法的步骤示意图，请参阅图1及图5，所述方法包括：Embodiments of the present disclosure also provide a method for real-time verification of the programming status of an anti-fuse unit, using the above-mentioned anti-fuse circuit. Figure 5 is a schematic diagram of the steps of a method for verifying the programming status of an antifuse unit provided by the third embodiment of the present disclosure. Please refer to Figures 1 and 5. The method includes:
步骤S501，输入烧写信号Data，根据所述烧写信号Data对所述反熔丝单元10进行烧写，所述烧写信号Data表征所述反熔丝单元击穿。Step S501: input a programming signal Data, and perform programming on the
具体地说，在本实施例中，烧写控制信号BlowEn使能所述反熔丝电路的烧写电路20，使所述烧写电路29能够根据烧写信号Data确定是否对反熔丝单元10执行烧写操作。例如，在本实施例中，所述烧写信号Data经所述烧写控制单元21输入后作为所述信号转换单元22的控制信号，若所述烧写信号Data表征所述反熔丝单元10击穿，则所述烧写信号Data为0，若所述烧写信号Data表征所述反熔丝单元10未击穿，则所述烧写信号Data为1。在本实施例中，所述烧写信号Data表征所述反熔丝单元10击穿。Specifically, in this embodiment, the programming control signal BlowEn enables the
步骤S502，根据所述烧写信号Data和验证使能信号VerifyEn控制读取单元30的输入端IN与地端GND断开连接。Step S502: Control the input terminal IN of the
在该步骤中，所述验证控制单元40接收所述反熔丝单元10的烧写信号 Data和验证使能信号VerifyEn，用于在验证所述反熔丝单元10的烧写状态时，根据所述烧写信号Data和所述验证使能信号VerifyEn控制所述读取单元30的输入端与地端断开连接。In this step, the
当进入验证模式时，所述验证使能信号VerifyEn使能所述验证控制单元40，所述烧写信号Dat,作为所述验证控制单元40的输入信号控制读取单元30的输入端IN与地端GND断开连接。具体地说，当进入验证模式时，所述验证使能信号VerifyEn控制所述第二单元42导通，当所述烧写信号Data表征所述反熔丝单元10击穿时，所述烧写信号Data置为0，所述烧写信号Data的真值为“0”，则所述第一晶体管断开，所述读取单元30的输入端IN与地端GND断开连接。When entering the verification mode, the verification enable signal VerifyEn enables the
可以理解的是，在一些实施例中，在所述读取单元30执行读写放大操作时，而并非是验证模式时，所述验证控制单元40的第二单元42保持断开状态，以避免影响所述反熔丝单元10与所述读取单元30的连通。It can be understood that in some embodiments, when the
步骤S503，所述读取单元30对所述反熔丝单元10进行读取获得数据信号。In step S503, the
在该步骤中，若所述反熔丝单元10击穿，则所述反熔丝单元10导通，所述读取单元30的输入端IN与接地端GAD连接，所述输入端IN的输入信号EFDAT也变为0，若所述反熔丝单元10未击穿，则所述反熔丝单元10未导通，所述读取单元30不与接地端GND连接，所述输入端IN的输入信号EFDAT维持1，所述读取单元30根据所述输入信号EFDAT形成输出信号EFOUT，所述输出信号EFOUT表征对所述反熔丝单元10读取获得的数据信号，从而实现所述读取单元30对所述反熔丝单元10的读取。In this step, if the
在该实施例中，所述读取单元的输出信号EFOUT与所述反熔丝单元10的烧写状态反相，即所述反熔丝单元10未击穿，所述读取单元的输出信号EFOUT为0，所述反熔丝单元10击穿，所述读取单元的输出信号EFOUT为1。可以理解的是，在本公开其他实施例中，所述读取单元的输出信号EFOUT与所述反熔丝单元10的烧写状态也可一致(例如本公开第二实施例)，即所述反熔丝单元10未击穿，所述读取单元的输出信号EFOUT为1，所述反熔丝单元10击穿，所述读取单元的输出信号EFOUT为0。In this embodiment, the output signal EFOUT of the reading unit is inverse phase with the programming state of the
步骤S504，根据所述数据信号和所述烧写信号Data验证所述反熔丝单元10是否烧写正确。Step S504: Verify whether the
在本实施例中，比较所述数据信号和所述烧写信号Data，根据所述数据信号和所述烧写信号Data的比较结果确定所述反熔丝单元10是否烧写正确，若所述数据信号和所述烧写信号Data一致，所述反熔丝单元10烧写错误；若所述数据信号和所述烧写信号Data不一致，所述反熔丝单元10烧写正确。即比较所述读取单元30的输入端的输出信号EFOUT，根据所述输出信号EFOUT和所述烧写信号Data的比较结果确定所述反熔丝单元10是否烧写正确，若所述输出信号EFOUT和所述烧写信号Data一致，所述反熔丝单元10烧写错误；若所述输出信号EFOUT和所述烧写信号Data不一致，所述反熔丝单元10烧写正确。In this embodiment, the data signal and the programming signal Data are compared, and whether the
具体地说，请参阅图6，其为信号真值表，所述烧写信号Data为0(表征所述反熔丝单元10击穿)，其真值为“0”。若所述读取单元30输入端IN的输入信号EFDAT为1，其真值为“1”，则所述读取单元30的输出端OUT的输出信号EFOUT(相当于所述反熔丝单元10的数据信号)为0，其真值为“0”，所述反熔丝单元10的真实状态为未击穿，与所述烧写信号Data表征不一致，即所述数据信号和所述烧写信号Data不一致，所述反熔丝单元10烧写错误。若所述读取单元30输入端IN的输入信号EFDAT为0，其真值为“0”，则所述读取单元30的输出端OUT的输出信号EFOUT(相当于所述反熔丝单元10的数据信号)为1，其真值为“1”，说明所述反熔丝单元10的真实状态为击穿，所述反熔丝单元10的真实状态与所述烧写信号Data表征一致，即所述数据信号和所述烧写信号Data一致，所述反熔丝单元10烧写正确。Specifically, please refer to FIG. 6 , which is a signal truth table. The programming signal Data is 0 (indicating the breakdown of the anti-fuse unit 10 ), and its true value is “0”. If the input signal EFDAT at the input terminal IN of the
在本公开另一实施例中，请参阅图3及图4，比较所述数据信号和所述烧写信号Data，根据所述数据信号和所述烧写信号Data的比较结果确定所述反熔丝单元10是否烧写正确，若所述数据信号和所述烧写信号Data不一致，所述反熔丝单元10烧写错误；若所述数据信号和所述烧写信号Data一致，所述反熔丝单元10烧写正确。即比较所述读取单元30的输入端的输出信号EFOUT，根据所述输出信号EFOUT和所述烧写信号Data的比较结果确定所述反熔丝单元10是否烧写正确，若所述输出信号EFOUT和所述烧写信号Data 不一致，所述反熔丝单元10烧写错误；若所述输出信号EFOUT和所述烧写信号Data一致，所述反熔丝单元10烧写正确。In another embodiment of the present disclosure, please refer to FIG. 3 and FIG. 4 to compare the data signal and the programming signal Data, and determine the anti-melt according to the comparison result of the data signal and the programming signal Data. Whether the
可以理解的是，若所述烧写信号Data为1(即表征所述反熔丝单元10未击穿)，其真值为“1”，所述验证使能信号VerifyEn置为0，其真值为“0”，所述验证控制单元40未被使能，即无法进入验证模式。It can be understood that if the programming signal Data is 1 (that is, indicating that the
本公开实施例提供的反熔丝单元烧写状态验证方法能够根据所述数据信号和所述烧写信号Data验证所述反熔丝单元10是否烧写正确，不需要将数据信号读出到测试机台再对反熔丝单元10的烧写状态进行验证，能够快速地验证反熔丝单元10是否被误烧穿，节约时间，并且验证准确率高。The anti-fuse unit programming status verification method provided by the embodiment of the present disclosure can verify whether the
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above are only preferred embodiments of the present invention. It should be noted that those of ordinary skill in the art can also make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as It is the protection scope of the present invention.
Claims (15)
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| CN202210545449.0A CN117133341A (en) | 2022-05-19 | 2022-05-19 | Anti-fuse circuit and anti-fuse unit programming state real-time verification method |
| CN202210545449.0 | 2022-05-19 |
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| PCT/CN2022/126177 Ceased WO2023221390A1 (en) | 2022-05-19 | 2022-10-19 | Anti-fuse circuit and method for real-time verification of burning state of anti-fuse unit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373771B1 (en) * | 2001-01-17 | 2002-04-16 | International Business Machines Corporation | Integrated fuse latch and shift register for efficient programming and fuse readout |
| CN1362741A (en) * | 2000-12-27 | 2002-08-07 | 株式会社东芝 | Fuse-wire circuit |
| CN112582013A (en) * | 2019-09-29 | 2021-03-30 | 长鑫存储技术有限公司 | Anti-fuse memory cell circuit, array circuit and read-write method thereof |
| CN114373497A (en) * | 2022-01-10 | 2022-04-19 | 北京昂瑞微电子技术股份有限公司 | Fuse burning circuit |
-
2022
- 2022-05-19 CN CN202210545449.0A patent/CN117133341A/en active Pending
- 2022-10-19 WO PCT/CN2022/126177 patent/WO2023221390A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1362741A (en) * | 2000-12-27 | 2002-08-07 | 株式会社东芝 | Fuse-wire circuit |
| US6373771B1 (en) * | 2001-01-17 | 2002-04-16 | International Business Machines Corporation | Integrated fuse latch and shift register for efficient programming and fuse readout |
| CN112582013A (en) * | 2019-09-29 | 2021-03-30 | 长鑫存储技术有限公司 | Anti-fuse memory cell circuit, array circuit and read-write method thereof |
| CN114373497A (en) * | 2022-01-10 | 2022-04-19 | 北京昂瑞微电子技术股份有限公司 | Fuse burning circuit |
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