WO2023211613A1 - Adaptive data encoding for memory systems - Google Patents

Abstract

Systems and methods for adaptive data encoding for memory systems are disclosed. In one aspect, a memory bus replaces a data bus inversion encoding technique with a more flexible encoding scheme which periodically calculates cluster centers based on pending data transactions. The dynamic cluster centers are used with an exclusive OR (XOR) function to minimize the number of bits that consume power sent over a memory bus. For example, in some standards, sending a one involves a state transition and consumes power. In other standards, sending a zero involves a state transition and consumes power. The present disclosure is applicable to both situations. By minimizing the power consuming bits sent over the memory bus, less power is consumed.

Description

ADAPTIVE DATA ENCODING FOR MEMORY SYSTEMS

PRIORITY APPLICATION

[0001] The present application claims priority to U.S. Patent Application Serial No. 17/661,084, filed April 28, 2022 and entitled “ADAPTIVE DATA ENCODING FOR MEMORY SYSTEMS,” which is incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

[0002] The technology of the disclosure relates generally to sending and receiving data to and from a memory device and, particularly, to an encoding scheme for the same.

II. Background

[0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to reduce power consumption. Memory systems that support the processing capabilities provide opportunities for innovation and power consumption reduction.

SUMMARY

[0004] Aspects disclosed in the detailed description include systems and methods for adaptive data encoding for memory systems. In particular, exemplary aspects of the present disclosure contemplate replacing a data bus inversion encoding technique with a more flexible encoding scheme which periodically calculates cluster centers based on pending data transactions. The dynamic cluster centers are used with an exclusive OR (XOR) function to minimize the number of bits that consume power sent over a memory bus. For example, in some standards, sending a one involves a state transition and consumes power. In other standards, sending a zero involves a state transition and consumes power. The present disclosure is applicable to both situations. By minimizing the power consuming bits sent over the memory bus, less power is consumed.

[0005] In this regard in one aspect, an integrated circuit (IC) is disclosed. The IC includes a bus interface configured to be coupled to a memory bus. The IC also includes a memory controller coupled to the bus interface. The memory controller is configured to send one or more data masks from a plurality of data masks to a memory device through the bus interface. The one or more data masks comprise respective patterns to be used in decoding encoded data sent to the memory device.

[0006] In another aspect, an IC is disclosed. The IC includes a bus interface configured to be coupled to a memory bus. The IC also includes a memory controller coupled to the bus interface. The memory controller is configured to send one or more data masks from a plurality of data masks to a memory device through the bus interface. The one or more data masks include an encoding mask used by the memory device to encode data sent to the memory controller.

[0007] In another aspect, an IC is disclosed. The IC includes a bus interface configured to be coupled to a memory bus. The IC also includes a mode register including a plurality of data masks stored therein. The IC also includes an encoding circuit configured to encode data to be sent to a memory controller through the bus interface using at least one data mask of the plurality of data masks.

[0008] In another aspect, an IC is disclosed. The IC includes a bus interface configured to be coupled to a memory bus. The IC also includes a mode register configured to have one or more data masks stored therein for decoding data sent from a memory controller.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure l is a block diagram of an exemplary memory system that may benefit from the adaptive encoding techniques of the present disclosure;

[0010] Figure 2 is a block diagram of a mobile terminal that may include the memory system of Figure 1;

[0011] Figure 3 is a flowchart illustrating an exemplary process for adaptively encoding data transmissions according to exemplary aspects of the present disclosure; and [0012] Figures 4A-4F illustrate the steps of the process of Figure 3.

DETAILED DESCRIPTION

[0013] With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0014] Aspects disclosed in the detailed description include systems and methods for adaptive data encoding for memory systems. In particular, exemplary aspects of the present disclosure contemplate replacing a data bus inversion encoding technique with a more flexible encoding scheme which periodically calculates cluster centers based on pending data transactions. The dynamic cluster centers are used with an exclusive OR (XOR) function to minimize bits that consume power sent over a memory bus. For example, in some standards, sending a one involves a state transition and consumes power. In other standards, sending a zero involves a state transition and consumes power. The present disclosure is applicable to both situations. By minimizing the power consuming bits sent over the memory bus, less power is consumed

[0015] Before addressing particulars of the present disclosure, a brief overview of an exemplary environment that may benefit from the present disclosure is provided with reference to Figures 1 and 2. A discussion of the adaptive encoding techniques begins below with reference to Figure 3.

[0016] In this regard, Figure 1 is a block diagram of a memory system 100 that includes a host 102 and a plurality of memory devices 104(l)-104(N) coupled by one or more memory buses 106 (only one shown). In an exemplary aspect, the host 102 may be an integrated circuit (IC) that performs as a system on a chip (SoC), application processor, main modem, or other control circuit that is designed to access the memory devices 104(l)-104(N). The host 102 may include a neural processing unit 108, a graphics processing unit (GPU) and multimedia engine 110, and/or a multi-core central processing unit (CPU) 112. The neural processing unit 108, the GPU and multimedia engine 110, and/or the multi-core CPU 112 may communicate with a memory controller 114 through a system bus 116. The memory controller 114 may send data to a physical layer (PHY) 118 across a data line 120. The PHY 118 is a memory bus interface and may include an encoding logic 122 that routes the data from the data line 120 to appropriate pins (e.g., data pins) coupled to the memory bus 106.

[0017] The memory devices 104(l)-104(N) may be identical, and accordingly, a discussion of a generic memory device 104 is provided. The memory device 104 may include an input-output (I/O) block 124. The I/O block 124 is a memory bus interface and communicates with banks 126 of data cell arrays 128 using read and write commands as is well understood. The I/O block 124 may also include an encoding logic 130 that routes the data from the data line to appropriate pins coupled to the memory bus 106. The memory bus 106 may include twenty-four data conductors, four clock conductors, and four read clock strobe (RDQS) conductors. Accordingly, the memory bus interfaces 118, 124 may include twenty-four pins (e.g., data pins) corresponding to the data conductors, four pins (e.g., clock pins) corresponding to the clock conductors, and four pins corresponding to the RDQS conductors. Additional conductors may be provided for command and address signals, an additional clock signal, a chip select signal, and/or a reset signal.

[0018] In an exemplary aspect, the conductors of the memory bus 106 are arranged in a specific layout. Namely, from a first edge moving inwards, there are data conductors (DQ0), a differential clock channel having two conductors (WCKO t, WCKO c), a differential RDQS channel having two conductors (RDQSO t, RDQSO c) and more data conductors (DQ0) shown generally as a first group 132. In a center section of the memory bus 106, a command and address (CA[0:k]) channel conductor, a differential command clock channel having two conductors (CK_t, CK_c), a chip select channel conductor, and a reset channel conductor may be positioned shown generally as a middle group 134. Then, moving outwards toward a second edge of the memory bus 106, there are data conductors (DQ1) a differential clock channel having two conductors (WCKl t, WCKl c), a differential RDQS channel having two conductors (RDQSl t, RDQSl c) and more data conductors (DQ1) shown generally as a second group 136. While there are reasons for this arrangement in terms of ease of routing, electromagnetic interference (EMI), and/or electromagnetic compatibility (EMC), it should be appreciated that other arrangements may also be used.

[0019] Further, as an additional feature, the memory controller 114 may include an error correcting code (ECC) circuit 140, which may encode and decode ECC signals. Further, the data cell arrays 128 may include an ECC cell 142 that stores parity bits and works with the ECC circuit 140 for error correction. In an exemplary aspect, ECC parity bits (p, as opposed to data 2*n) may be transmitted over an RDQS pin (e.g., RDQS t, RDQS c, or both) from the host 102 to the memory device 104 such as during a write operation. For the reverse direction, the ECC parity bits may be transmitted over data mask slots during a read operation. Alternatively, instead of using the RDQS signals, the host 102 may use the data mask slots (e.g., M[0:31]) for a write operation.

[0020] Each memory device 104(l)-104(N) may have a mode register 146 and encoding circuit (not shown), which will be used to identify whether aspects of the present disclosure are in use as explained in greater detail below.

[0021] For further context, Figure 2 is a system-level block diagram of an exemplary mobile communication device or mobile terminal 200 such as a smart phone, mobile computing device tablet, or the like in which a memory system such the memory system 100 of Figure 1 may be found. While a mobile terminal is particularly contemplated as being capable of benefiting from exemplary aspects of the present disclosure, it should be appreciated that the present disclosure is not so limited and may be useful in any system having a memory bus that will be compliant with existing or emerging memory standards. [0022] With continued reference to Figure 2, the mobile terminal 200 includes an application processor 204 (sometimes referred to as a host or an SoC) that communicates with a mass storage element 206 through a universal flash storage (UFS) bus 208. More relevantly, the application processor 204 may communicate with a double data rate (DDR) memory device 104 through a memory bus 106 according to exemplary aspects of the present disclosure. The application processor 204 may further be connected to a display 210 through a display serial interface (DSI) bus 212 and a camera 214 through a camera serial interface (CSI) bus 216. Various audio elements such as a microphone 218, a speaker 220, and an audio codec 222 may be coupled to the application processor 204 through a serial low-power interchip multimedia bus (SLIMbus) 224. Additionally, the audio elements may communicate with each other through a SOUNDWIRE bus 226. A modem 228 may also be coupled to the SLIMbus 224 and/or the SOUND WIRE bus 226. The modem 228 may further be connected to the application processor 204 through a peripheral component interconnect (PCI) or PCI express (PCIe) bus 230 and/or a system power management interface (SPMI) bus 232. [0023] With continued reference to Figure 2, the SPMI bus 232 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 234, a power management integrated circuit (PMIC) 236, a companion IC (sometimes referred to as a bridge chip) 238, and a radio frequency IC (RFIC) 240. It should be appreciated that separate PCI buses 242 and 244 may also couple the application processor 204 to the companion IC 238 and the WLAN IC 234. The application processor 204 may further be connected to sensors 246 through a sensor bus 248. The modem 228 and the RFIC 240 may communicate using a bus 250.

[0024] With continued reference to Figure 2, the RFIC 240 may couple to one or more RFFE elements, such as an antenna tuner 252, a switch 254, and a power amplifier 256 through a radio frequency front end (RFFE) bus 258. Additionally, the RFIC 240 may couple to an envelope tracking power supply (ETPS) 260 through a bus 262, and the ETPS 260 may communicate with the power amplifier 256. Collectively, the RFFE elements, including the RFIC 240, may be considered an RFFE system 264. It should be appreciated that the RFFE bus 258 may be formed from a clock line and a data line (not illustrated).

[0025] In the past, data communication between the memory controller 114 and the memory device 104 may be one of the largest power consumers. Specifically, in a low power double data rate (LPDDR) system, power is consumed when a logical high or logical one is sent. In an effort to reduce power consumption, existing LPDDR systems may use a data bus inversion (DBI) encoding scheme where if there are more ones than zeros in a block of eight bits, then the data is inverted and sent to the memory device with a signal in the data mask inversion (DMI) bits to indicate to the memory device that an inversion has occurred. While DBI does provide some power savings over non-encoded signaling, the granularity of DBI encoding is relatively coarse and may not optimally encode ones and zeros. Note that DBI may also be used in other systems such as a normal DDR memory, graphical DDR (GDDR) memory, high bandwidth memory (HBM) and the like. It is also possible that DBI may be used outside memory configurations. Further, while many systems are designed such that sending a logical one involves a logical high or state transition on the line that consumes power, some systems may consume power when sending a zero. The present disclosure works in either event with the substitution of the zeros for ones. Accordingly, all such environments may benefit from aspects of the present disclosure.

[0026] As a note nomenclature, double data rate (DDR) is a term of art within the JEDEC specifications and the memory world in general. As used herein, DDR is defined to be a signaling technique that uses both the falling and rising edges of the clock signal. This use of both edges is independent of frequency, and changes (e.g., doubling) in frequency do not fall within DDR unless both edges are used. Also contrast DDR with single data rate (SDR), which can transfer data on a rising edge or a falling edge, but not both.

[0027] Exemplary aspects of the present disclosure provide an adaptive encoding scheme that provides greater granularity by allowing for better data masks to be used to encode the data. The DMI bits may be repurposed to indicate which data mask is being used so that the memory device may decode using the correct data mask.

[0028] The techniques of the present disclosure are readily expressed as a process and specifically as a process 300 illustrated in Figure 3, with additional explanation of the steps provided with reference to Figures 4A-4F. In this regard, the process 300 begin by calculating optimum masks based on observed traffic (block 302). That is, the memory controller 114 knows the data contained in any write command and is likely to know certain types of read data (e.g., weights in a machine learning system). Thus, as illustrated in Figure 4A, the memory controller 114 may have a plurality of write transactions in a queue 400 and periodically, (e.g., every sixty-four (64) transactions) the memory controller 114 may calculate a set of cluster centers 402(0)-402(N) (where, as illustrated, N is 3) based on the transactions in the queue. This calculation may be done by having an up/down counter 408 (see Figure 4C) representing each cluster center (e.g., one counter per data line per cluster for sixty -four counters in an exemplary system). For each sixteen- bit chunk of data 404, the memory controller 114 may find the closest cluster center 402(0) based on finding a minimum Hamming distance 406(0)-406(3), see also Figure 4B where cluster center 402(0) is identified. Note that other cluster sizes may be chosen. Thus, for example, instead of sixteen-bit chunks of data, four, eight, thirty-two, sixty- four, or more may be used. Likewise, while powers of two are contemplated, other values are possible. [0029] Note that because in some instances the memory controller 114 may know what the pattern is within data that is being read, the memory controller 114 may instruct the memory device 104 to encode data using the data masks. That is, the data mask may act as an encoding mask comprising values inserted into a function (e.g., XOR) that encodes the data to be sent to the memory device 104.

[0030] As illustrated in Figure 4C, the corresponding counters 408 for the found cluster center 402(0) is incremented if a one is indicated and decremented if a zero is indicated in the data 404. Based on the results for the counters 408, a new cluster 410 is calculated as shown in Figure 4D. In a specific aspect, the new cluster 410 is chosen based on whether the updated counters are greater than five. So, for example, as illustrated in Figure 4D, elements 412(1)-412(2), 412(4)-412(6), 412(9)-412(14), and 412(16) are less than five, so those bits are 0, whereas elements 412(3), 412(7), 412(8), and 412(15) are more than five and those bits are 1. It should be appreciated that at start up or configuration, a set of default cluster centers may initially be provided.

[0031] Returning to Figure 3, the memory controller 114 communicates the new data masks based on the updated clusters 410 to the memory device 104 and particularly to the mode register 146 (block 304, see also Figure 4E). For subsequent write commands, the memory controller 114 may XOR data bits with the mask that minimizes the Hamming distance (block 306), see also Figure 4F where a DMI signal that is used for DBI may be used to communicate which cluster center is to be used by the memory device 104 by repurposing pins to indicate the selected mask (block 308).

[0032] The memory device 104 will then XOR the received bits with the identified mask to recover the data and perform the write command (block 310).

[0033] In this fashion, the number of ones communicated over the memory bus 106 is minimized, which results in power savings. At worst, the masks occasionally end up identical to DBI and there is no power savings for that window, but over a sufficiently large window of time, the power savings may be substantial approximating almost fifty percent savings for CPU write traffic and approximately ten percent savings for other forms of write traffic.

[0034] The adaptive data encoding for memory systems according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter. [0035] Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium wherein any such instructions are executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0036] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0037] The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0038] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0039] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0040] Implementation examples are described in the following numbered clauses:

1. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; and a memory controller coupled to the bus interface and configured to: send one or more data masks from a plurality of data masks to a memory device through the bus interface, wherein the one or more data masks comprise respective patterns to be used in decoding encoded data sent to the memory device.

2. The IC of clause 1, wherein the one or more data masks comprise values to be exclusive OR’d (XOR) with data to be sent to the memory device through the bus interface when the memory device decodes the encoded data.

3. The IC of clause 2, wherein the memory controller is further configured to XOR outgoing data with at least one data mask to encode the data to be sent to the memory device.

4. The IC of clause 3, wherein the memory controller is further configured to send the encoded data through the bus interface to the memory device.

5. The IC of any preceding clause, wherein the memory controller is further configured to write the one or more data masks to a mode register in the memory device.

6. The IC of any preceding clause, wherein the memory controller is further configured to send an identifier indicating which of the one or more data masks is used to encode data sent to the memory device.

7. The IC of any preceding clause, wherein the memory controller is further configured to determine the one or more data masks to be sent. 8. The IC of clause 7, wherein the one or more data masks are based on cluster centers associated with patterns in data to be sent to the memory device.

9. The IC of clause 8, wherein the memory controller is further configured to calculate new cluster centers based on a Hamming distance of bits in the data to be sent to the memory device to existing cluster centers.

10. The IC of clause 9, wherein the memory controller is further configured to calculate the new cluster centers periodically.

11. The IC of clause 9, wherein the memory controller is further configured to calculate the new cluster centers every sixty-four transactions.

12. The IC of clause 9, wherein the memory controller is further configured to calculate the new cluster centers based on sixteen-bit chunks in the data to be sent to the memory device.

13. The IC of any preceding clause, wherein the bus interface comprises a low power double data rate (LPDDR) bus interface.

14. The IC of any preceding clause, wherein the memory controller is further configured to decode data sent from the memory device using one of the plurality of data masks.

15. The IC of any of clauses 9, 13 or 14, wherein the memory controller is further configured to calculate the new cluster centers based on eight-bit chunks in the data to be sent to the memory device.

16. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; and a memory controller coupled to the bus interface and configured to: send one or more data masks from a plurality of data masks to a memory device through the bus interface, wherein the one or more data masks comprise an encoding mask used by the memory device to encode data sent to the memory controller. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; a mode register comprising a plurality of data masks stored therein; and an encoding circuit configured to encode data to be sent to a memory controller through the bus interface using at least one data mask of the plurality of data masks. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; and a mode register configured to have one or more data masks stored therein for decoding data sent from a memory controller.

Claims

What is claimed is:

1. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; and a memory controller coupled to the bus interface and configured to: send one or more data masks from a plurality of data masks to a memory device through the bus interface, wherein the one or more data masks comprise respective patterns to be used in decoding encoded data sent to the memory device.

2. The IC of claim 1, wherein the one or more data masks comprise values to be exclusive OR’d (XOR) with data to be sent to the memory device through the bus interface when the memory device decodes the encoded data.

3. The IC of claim 2, wherein the memory controller is further configured to XOR outgoing data with at least one data mask to encode the data to be sent to the memory device.

4. The IC of claim 3, wherein the memory controller is further configured to send the encoded data through the bus interface to the memory device.

5. The IC of claim 1, wherein the memory controller is further configured to write the one or more data masks to a mode register in the memory device.

6. The IC of claim 1, wherein the memory controller is further configured to send an identifier indicating which of the one or more data masks is used to encode data sent to the memory device.

7. The IC of claim 1, wherein the memory controller is further configured to determine the one or more data masks to be sent.

8. The IC of claim 7, wherein the one or more data masks are based on cluster centers associated with patterns in data to be sent to the memory device.

9. The IC of claim 8, wherein the memory controller is further configured to calculate new cluster centers based on a Hamming distance of bits in the data to be sent to the memory device to existing cluster centers.

10. The IC of claim 9, wherein the memory controller is further configured to calculate the new cluster centers periodically.

11. The IC of claim 9, wherein the memory controller is further configured to calculate the new cluster centers every sixty-four transactions.

12. The IC of claim 9, wherein the memory controller is further configured to calculate the new cluster centers based on sixteen-bit chunks in the data to be sent to the memory device.

13. The IC of claim 1, wherein the bus interface comprises a low power double data rate (LPDDR) bus interface.

14. The IC of claim 1, wherein the memory controller is further configured to decode data sent from the memory device using one of the plurality of data masks.

15. The IC of claim 9, wherein the memory controller is further configured to calculate the new cluster centers based on eight-bit chunks in the data to be sent to the memory device.

16. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; and a memory controller coupled to the bus interface and configured to: send one or more data masks from a plurality of data masks to a memory device through the bus interface, wherein the one or more data masks comprise an encoding mask used by the memory device to encode data sent to the memory controller. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; a mode register comprising a plurality of data masks stored therein; and an encoding circuit configured to encode data to be sent to a memory controller through the bus interface using at least one data mask of the plurality of data masks. An integrated circuit (IC) comprising: a bus interface configured to be coupled to a memory bus; and a mode register configured to have one or more data masks stored therein for decoding data sent from a memory controller.