WO2023283886A1 - Register array circuit and method for accessing register array - Google Patents

Abstract

A register array circuit and a method for accessing a register array, relating to the technical field of chips, for use in solving the problem of useless flipping when the register array circuit is stored, thereby achieving the technical effects of decreasing useless flipping in the register array circuit and reducing power consumption. When registers in the register array circuit are rising-edge trigger registers, if a certain rising-edge trigger register is not subjected to write access, a gating clock clamped to a high level is output to the rising-edge trigger register by means of an OR gated clock circuit. When the registers in the register array circuit are falling-edge trigger registers, if a certain falling-edge trigger register is not subjected to write access, a gating clock clamped to a low level is output to the falling-edge trigger register by means of an AND gated clock circuit.

Description

Register array circuit and method for accessing register array technical field

The embodiments of the present application relate to the field of chip technology, and in particular, to a register array circuit and a method for accessing the register array.

Background technique

With the development of the digital society, the demand for storage in circuit design is increasing, such as small-capacity storage based on register arrays or random access memory (random access memory, RAM). When small-capacity storage is implemented based on a register array, registers can be used to temporarily store instructions and data.

For the register, the information is generally stored in the data-clock mode, that is, the data input terminal (data terminal) corresponds to the data information bit, and the clock input terminal corresponds to the control signal. Under the action of the control signal, the information is written into the register instantaneously. For the register array, the registers of all addresses share the write data bus. When there is data transmission on the write data bus, the write data bus will be flipped, and the flip will be transmitted to the data ends of all address registers, because there is only one address register in one cycle. Write data, so it will cause useless circuit flips inside the registers of the unselected addresses in the register array, and each flip in the circuit is accompanied by power consumption, so these useless flips in the internal circuits of the registers will cause Wasted power.

At present, on the basis of using the gated clock circuit to control the clock input end of the register, the data end of the register of the unselected address can also be turned off through the AND gate or the NAND gate device (the register of the unselected address The data ends of the registers are turned off separately or grouped according to the address), which can avoid invalid flipping of the internal circuit of the register of the unselected address. However, this method will increase the number of windings and circuit area, resulting in difficulties in physical implementation, and additional power consumption will be introduced when the AND gate or NAND gate is in operation.

Contents of the invention

Embodiments of the present application provide a register array circuit and a method for accessing the register array, which can reduce useless flipping in the register array circuit when the register array circuit performs storage, thereby reducing power consumption.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

In the first aspect, the embodiment of the present application provides a register array circuit. The register array circuit includes a plurality of registers and a plurality of gated clock circuits corresponding to the plurality of registers. The gated clock circuit is used to output the gated clock. The multiple registers include a first register, the first register is a rising edge trigger register, and the first clock gate circuit corresponding to the first register is an OR gate clock circuit. The first gating clock circuit is configured to output a gating clock clamped to a high level to the first register when the first register is not being accessed for writing. Therefore, when the rising-edge trigger register is not being written and accessed, the gating clock circuit corresponding to the rising-edge trigger register will output a gating clock clamped to a high level to the first register, that is, the clock of the rising-edge trigger register The input terminal is clamped to a high level, which will cause the rising edge to trigger the internal SI and D terminal selection circuit of the register and the low-pass circuit in the low-pass high-lock latch circuit to be non-conductive, so it will not cause flipping, thereby avoiding power consumption waste.

In a possible design, when the first register is accessed for writing, that is, when the address corresponding to the first register is selected, the first gating clock circuit is also used to switch the gating clock output to the first register from a high level to Transition to low level, that is, the clock input terminal of the first register transitions from high level to low level, and clamps to low level, and then the gating clock output to the first register transitions from low level is a high level, that is, the clock input end of the first register transitions from a low level to a high level. Wherein, when the gating clock output to the first register transitions from low level to high level, that is, when the clock input terminal of the first register transitions from low level to high level, the first register is written with data . Therefore, the rising edge triggers the internal SI and D terminal selection circuit of the register and the low-pass circuit in the low-pass high-lock latch circuit will only be turned on for a period of time when the write access is performed, and there is a phenomenon of circuit reversal until the data is written. After the high-pass low-lock latch circuit, that is, after the data is written into the rising-edge trigger register, when the rising-edge trigger register is not executed for write access, the rising-edge trigger register internal SI and D terminal selection circuit and low-pass high latch The low-pass circuit in the lock circuit will not be turned on, thereby avoiding waste of power consumption.

In a possible design, each of the plurality of gated clock circuits further includes a first input terminal (ie, a data input terminal) and a second input terminal (ie, a clock input terminal), and the first input terminal Coupled with the write address bus shared by each clock gating circuit, the second input end is used to receive the write clock signal shared by each clock gating circuit. Thus, each address has a corresponding clock gate circuit, and the output of the clock gate circuit is related to the address information indicated by the write address bus and the write clock signal. The output of the register is clamped to a high-level gating clock, that is, the clock input terminal of the register of the address is clamped to a high level, thereby avoiding waste of power consumption.

In a possible design, when the first register is not being accessed for writing, the signal at the first input terminal of the first gating clock circuit is used to indicate that the first address of the first register is not selected. Therefore, when the address is not selected, the gated clock circuit corresponding to the address does not perform a jump, and the register of the address is not accessed for writing, and the gated clock circuit corresponding to the address will clamp the output to the register of the address as A high-level gated clock will clamp the clock input terminal of the register at the address to a high level, thereby avoiding waste of power consumption.

In the second aspect, the embodiment of the present application provides a register array circuit, the register array circuit includes a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one by one, and the gating clock circuit is used to output gating to the register clock. The multiple registers include a first register, the first register is a falling edge trigger register, and the first clock gate circuit corresponding to the first register is an AND gate clock circuit. The first gating clock circuit is configured to output a gating clock clamped to a low level to the first register when the first register is not being accessed for writing. Thus, the gating clock circuit corresponding to the falling edge trigger register will output a gating clock clamped to a low level to the first register, that is, when the falling edge trigger register is not being written and accessed, the clock of the falling edge trigger register The input terminal is clamped to a low level, which will make the SI and D terminal selection circuits inside the falling edge trigger register and the high-pass circuit in the high-pass low-lock latch circuit non-conductive, so no flipping will be caused, thereby avoiding waste of power consumption.

In a possible design, when the first register is accessed for writing, that is, when the address corresponding to the first register is selected, the first gating clock circuit is also used to switch the gating clock output to the first register from a low level to Jump to high level, that is, the clock input terminal of the first register is changed from low level to high level, and clamped to high level, and then the gating clock output to the first register is changed from high level to high level is low level, that is, the clock input end of the first register transitions from high level to low level. Wherein, when the gating clock output to the first register transitions from a high level to a low level, that is, when the clock input terminal of the first register transitions from a high level to a low level, the first register is written into the data . Therefore, the falling edge triggers the internal SI and D terminal selection circuits of the register and the high-pass circuit in the high-pass low-lock latch circuit will only be turned on for a period of time when the write access is performed, and there is a phenomenon of circuit reversal. Wait until the data is written to the low After the high-pass latch circuit, that is, after the data is written into the falling-edge trigger register, when the falling-edge trigger register is not executed for write access, the falling-edge trigger register internal SI and D terminal selection circuit and high-pass low-lock latch circuit The high-pass circuit in the circuit will not conduct, thus avoiding waste of power consumption.

In a possible design, each of the plurality of gated clock circuits further includes a first input terminal (ie, a data input terminal) and a second input terminal (ie, a clock input terminal), and the first input terminal Coupled with the write address bus shared by each clock gating circuit, the second input end is used to receive the write clock signal shared by each clock gating circuit. Thus, each address has a corresponding clock gate circuit, and the output of the clock gate circuit is related to the address information indicated by the write address bus and the write clock signal. The output of the register is clamped to a low-level gated clock, that is, the clock input terminal of the register of the address is clamped to a low level, thereby avoiding waste of power consumption.

In a possible design, when the first register is not being accessed for writing, the signal at the first input terminal of the first gating clock circuit is used to indicate that the first address of the first register is not selected. Therefore, when the address is not selected, the gated clock circuit corresponding to the address does not perform a jump, and the register of the address is not accessed for writing, and the gated clock circuit corresponding to the address will clamp the output to the register of the address as A low-level gated clock will clamp the clock input terminal of the register of the address to a low level, thereby avoiding waste of power consumption.

In the third aspect, the embodiment of the present application provides a method for accessing a register array. The method is applied to a register array circuit. The register array circuit includes a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one by one. The controlled clock circuit is used to output the gated clock to the register. The multiple registers include a first register, the first register is a rising edge trigger register, and the first clock gate circuit corresponding to the first register is an OR gate clock circuit. When it is determined that the first register is not being accessed for writing, the first gating clock circuit outputs a gating clock clamped to a high level to the first register, that is, the clock input end of the first register is clamped to a high level. For the beneficial effects achieved in the third aspect, please refer to the beneficial effects in the first aspect.

In a possible design, when it is determined that the first register is being accessed for writing, the gating clock output to the first register through the first gating clock circuit jumps from a high level to a low level, that is, the first register The clock input end of the clock transitions from high level to low level and is clamped to low level, and then the gating clock output to the first register transitions from low level to high level, that is, the first register The clock input terminal transitions from low level to high level. Wherein, when the gating clock output to the first register transitions from low level to high level, that is, when the clock input end of the first register transitions from low level to high level, write data to the first register .

In a possible design, each clock gating circuit in the plurality of clock gating circuits further includes a first input terminal and a second input terminal, and the first input terminal shares the write address bus with each clock gating circuit Coupling, the second input terminal is used to receive the write clock signal shared with each gating clock circuit.

In a possible design, when it is determined that the first register is not being accessed for writing, the signal passing through the first input terminal of the first gating clock circuit indicates that the first address of the first register is not selected.

In the fourth aspect, the embodiment of the present application provides a method for accessing a register array, and the method is applied to a register array circuit. The register array circuit includes a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one-to-one. The controlled clock circuit is used to output the gated clock to the register. The multiple registers include a first register, the first register is a falling edge trigger register, and the first clock gate circuit corresponding to the first register is an AND gate clock circuit. When it is determined that the first register is not being accessed for writing, the first gating clock circuit outputs a gating clock clamped to a low level to the first register, that is, the clock input end of the first register is clamped to a low level. The beneficial effects achieved in the fourth aspect can be referred to the beneficial effects in the second aspect.

In a possible design, when it is determined that the first register is being accessed for writing, the gating clock output to the first register through the first gating clock circuit jumps from a low level to a high level, that is, the first register The clock input end of the clock transitions from low level to high level, and is clamped to high level, and then the gating clock output to the first register transitions from high level to low level, that is, the first register The clock input terminal transitions from high level to low level. Wherein, when the gating clock output to the first register transitions from high level to low level, that is, when the clock input terminal of the first register transitions from high level to low level, write data to the first register .

In a possible design, each clock gating circuit in the plurality of clock gating circuits further includes a first input terminal and a second input terminal, and the first input terminal shares the write address bus with each clock gating circuit Coupling, the second input terminal is used to receive the write clock signal shared with each gating clock circuit.

In a possible design, when it is determined that the first register is not being accessed for writing, the signal passing through the first input terminal of the first gating clock circuit indicates that the first address of the first register is not selected.

In the fifth aspect, a computer-readable storage medium includes computer instructions. When the computer instructions are run on the electronic device, the electronic device executes the method described in the third aspect and any possible design of the third aspect. .

In the sixth aspect, a computer-readable storage medium includes computer instructions, and when the computer instructions are run on the electronic device, the electronic device executes the method described in the fourth aspect and any possible design of the fourth aspect .

In a seventh aspect, a computer program product, when the computer program product is run on a computer, causes an electronic device to execute the method described in the above third aspect and any possible design of the third aspect.

In an eighth aspect, a computer program product, when the computer program product is run on a computer, causes an electronic device to execute the method described in the fourth aspect and any possible design of the fourth aspect.

For the beneficial effects corresponding to the above other aspects, refer to the description of the beneficial effects of the method, which will not be repeated here.

Description of drawings

Fig. 1 is a schematic diagram of a register array circuit;

FIG. 2 is a timing diagram of a register array circuit;

3 is a schematic diagram of another register array circuit;

FIG. 4A is a schematic diagram of a register array circuit provided by an embodiment of the present application;

FIG. 4B is a schematic diagram of another register array circuit provided by the embodiment of the present application;

FIG. 5 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application;

FIG. 6A is a schematic diagram of an internal circuit of a register;

FIG. 6B is a schematic diagram of another register internal circuit;

FIG. 7A is a schematic diagram of a register array circuit provided by an embodiment of the present application;

FIG. 7B is a schematic diagram of an internal structure of an OR-gated clock circuit provided in an embodiment of the present application;

FIG. 7C is a schematic timing diagram of an OR-gated clock circuit provided in an embodiment of the present application;

FIG. 7D is a schematic diagram of another register array circuit provided by the embodiment of the present application;

FIG. 7E is a schematic diagram of the internal structure of an AND-gated clock circuit provided in an embodiment of the present application;

FIG. 7F is a schematic timing diagram of an AND-gated clock circuit provided in the embodiment of the present application;

FIG. 8 is a schematic diagram of a method for accessing a register array provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of another method for accessing a register array provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of a register array circuit provided by an embodiment of the present application;

FIG. 11 is a schematic timing diagram of a register array circuit provided by an embodiment of the present application;

FIG. 12 is a schematic diagram of another register array circuit provided by the embodiment of the present application;

FIG. 13 is a schematic timing diagram of another register array circuit provided by an embodiment of the present application;

FIG. 14 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application.

detailed description

In order to facilitate understanding, descriptions of some concepts related to the embodiments of the present application are provided by way of example for reference. As follows:

Clock (clock): Each memory element in the circuit is controlled by the clock. Only when the clock signal arrives, the state of the memory element can change, so that the output of the sequential circuit changes, and each time a clock signal comes, the state of the memory element and The output state of the circuit can only be changed once. In the embodiment of the present application, when data is written to the register array, the clock signal is a write clock signal, and the write clock signal is periodically reversed, that is, a 0-1 level transition is performed, from a low level to a high level, Or perform a 1-0 level transition, from a high level to a low level.

Clock gating circuit (clock gating): By turning off the temporarily unused function on the chip and the corresponding clock of the function, the purpose of saving current consumption can be achieved. When there is no transition at the output terminal of the gated clock circuit, it means that the register corresponding to the gated clock circuit is not written with data; data is written. In the embodiment of the present application, when the output end of the clock gating circuit jumps, data is written into the register corresponding to the clock gating circuit.

Data bus (data bus): Carrying data information, the data information can be instructions, audio, video or pictures and other data. In the embodiment of the present application, when data is written to the register array, the data bus can be a write data bus (write data bus). When there is data transmission in the write data bus, the write data bus will perform a 0-1 level jump, that is A low level transition to a high level, or a 1-0 level transition, that is, a high level transition to a low level. The level transition of the write data bus can be understood as data inversion.

Address bus (address bus): Carrying address information, the address bus can be divided into a write address bus and a read address bus. The write address bus indicates that the data information on the data bus needs to be written into the address information of the corresponding cache (ie register), and the read address bus indicates that the address information of the corresponding cache needs to be read from the cache.

Register: used to store data information, divided into rising edge triggered registers and falling edge triggered registers according to different clock trigger edges. The rising edge trigger register performs data writing when its clock input terminal transitions from low level to high level, and the falling edge trigger register performs data writing when its clock input terminal transitions from high level to low level. For example, in the embodiment of the present application, when using a rising edge trigger register with a double latch (latch) structure as an example, the internal circuit of the rising edge trigger register may include a scan input (scan input, SI) and a data (data, D) terminal The three-part circuit is a selection circuit, a low-pass high-lock latch circuit and a high-pass low-lock latch circuit.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Among them, in the description of the embodiments of this application, unless otherwise specified, "/" means or means, for example, A/B can mean A or B; "and/or" in this article is only a description of associated objects The association relationship of indicates that there may be three kinds of relationships, for example, A and/or B may indicate: A exists alone, A and B exist simultaneously, and B exists independently. In addition, in the description of the embodiments of the present application, "plurality" refers to two or more than two.

In the prior art, the register array circuit is shown in Figure 1, and the register array circuit includes a register array composed of a plurality of registers (in the prior art, they are all rising-edge triggered registers) and an AND-gated clock corresponding to each register. Circuit (AND clock gating). Wherein, when the output end of the gate-controlled clock circuit does not make a transition, the output remains at a low level, and at this time, no data is written into the register corresponding to the gate-controlled clock circuit. The register array includes, for example, 0 address registers, 1 address registers, ..., n address registers, etc. (n is an integer greater than 1) shown in FIG. Registers, ..., registers of address n, that is, the addresses corresponding to each register are different. The clock input terminal a of each register is coupled to the corresponding output terminal b of the gating clock circuit, and the data input terminal c of each register shares the write data bus. Among the two input terminals of the gate-controlled clock circuit, one input terminal d is controlled by the write address bus (write address bus) shared by each gate-controlled clock circuit, and the other input terminal e is used to receive each gate-controlled clock circuit The write clock signal shared by the circuit. Wherein, the address of the write address bus may be different in different clock cycles. In different clock cycles, the address information indicated by the write address bus may be 0, 1, ..., n, respectively representing the selected address 0, address 1, ..., address n. When the address information=0 indicated by the write address bus, that is, when the 0 address was selected to write data, the output terminal corresponding to the 0 address register and the gate-controlled clock circuit carried out a rising edge jump (the output terminal of the gate-controlled clock circuit is determined by Low level transitions to high level), the other unselected address registers correspond to the output terminal of the gated clock circuit without jumping (the output terminal of the gated clock circuit remains low), write data The data information carried on the bus is written into the 0 address register when the output terminal of the gate-controlled clock circuit performs a rising edge transition.

As shown in FIG. 2 , it is a timing diagram of the register array circuit in FIG. 1 . The write clock signal is periodically flipped, and when the address information indicated by the write address bus = 0, address 0 is selected, and the register of address 0 is executed for write access, and the output terminal corresponding to the address register of 0 and the gate control clock circuit will perform a rising edge jump , at this time, data is written into the 0 address register, and the data in the write data bus is written into the 0 address register. When the address information indicated by the write address bus=0, the registers corresponding to the remaining unselected addresses are not accessed for writing, and the output terminals of the clock gate circuit corresponding to the registers not accessed for writing do not perform a transition. Taking the output terminal of the gated clock circuit corresponding to the 1 address register as an example, when the address information indicated by the write address bus=0, the output terminal of the gated clock circuit corresponding to the 1 address register remains at a low level without jumping, that is 1 The address register is not written with data. Wherein, the jump position corresponding to the output end of the gated clock circuit corresponding to the register shown in FIG. 2 can be adjusted according to the actual circuit, and the timing diagram is only an example.

Since the registers of all addresses share the write data bus, as long as the write data bus performs data reversal (that is, there is data transmission in the write data bus), the data terminals of all address registers (such as input c in Figure 1) will be reversed . When a certain address is selected, the outputs of the output terminals corresponding to the other unselected addresses and the gated clock circuit are kept low. The internal SI and D terminal selection circuit of the register, the low-pass circuit in the low-pass high-latch latch circuit, and the inverter flipping cause the unselected address. Since the output terminal corresponding to the unselected address and the gated clock circuit does not jump, the register of the unselected address is not written into data, so the SI and D terminal selection circuit inside the register, low-pass high-lock The low-pass circuit in the latch circuit and the inversion of the inverter are invalid, which can be understood as a flip, which will cause waste of power consumption.

At present, in order to solve the power consumption waste problem that the data terminal invalid flipping of the register of the unselected address introduces, as shown in Figure 3, on the basis of the register array circuit of Figure 1, an AND gate (AND) (OR and NOT Gate (NAND)), the data end of the register of the address that is not selected is turned off, and the data end of the register of the address that has not been executed write access is set to low level (or high level), that is, no transitions, thereby reducing invalid flips. However, the added AND gate (or NAND gate) will increase the number of windings and circuit area, making physical implementation difficult, and the AND gate (or NAND gate) will also introduce additional power consumption during operation.

Therefore, the present application proposes a register array circuit, which can be located in an electronic device, such as integrated in a chip. Considering the problems of many useless flips in the register array circuit in the prior art that lead to increased power consumption, in the register array circuit of the present application, when the register arrays are all rising-edge trigger registers, the registers of the addresses that are not accessed by write When the data end of the register is flipped, the clock input end of the register of each address is controlled by using the OR clock gating circuit (OR clock gating), wherein, the output end of the OR gating clock circuit remains high, that is, no write The clock input terminal of the accessed register is kept at a high level, and when the output terminal of the OR-gated clock circuit is kept at a high level, the SI and D terminal selection circuits inside the register and the low-pass circuit in the low-pass high-lock latch circuit It will not be turned on, so that it can reduce the flipping of the internal circuit of the register, avoid the waste of power consumption, and can also reduce the number of windings and circuit area, and reduce the complexity of physical implementation. When the register array circuits are all falling-edge trigger registers, when the data ends of the registers of the addresses that have not been performed write access are flipped, the clock input ends of the registers of each address are controlled by using the AND gating clock circuit, wherein, the AND gating The output terminal output of the clock circuit remains low level, that is, the clock input terminal input of the register that is not being written and accessed remains low level. When the output terminal of the gate-controlled clock circuit is maintained at low level, the SI and D The high-pass circuit in the terminal selection circuit and the high-pass low-lock latch circuit will not be turned on, thereby reducing the flipping of the internal circuit of the register, avoiding waste of power consumption, reducing the number of windings and circuit area, and reducing the complexity of physical implementation.

As shown in FIG. 4A and FIG. 4B , the embodiment of the present application may be applied to a register array circuit. The register array circuit includes devices such as a gate control clock unit and a register array. Wherein, as shown in FIG. 4A , when the registers in the register array are rising-edge-triggered registers, the clock gating unit is an OR gating clock circuit. As shown in FIG. 4B , when the registers in the register array are falling-edge-triggered registers, the clock gating unit is an AND gating clock circuit. One of the two input terminals of the clock gating unit receives the write clock signal, and the other is coupled to the write address bus to receive address information indicated by the write address bus. The output end of the clock gating unit is used to control whether data is written into the register corresponding to the clock gating unit, and the output end of the clock gating unit and the output end of the write data bus are coupled to the register array. When the output end of the clock gating unit jumps, the data information carried by the write data bus is written into the register corresponding to the clock gating unit. Wherein, each gated clock unit has its corresponding register, and each register corresponds to a different address, and the registers of all addresses are collectively referred to as a register array.

It should be noted that the embodiment of the present application can be applied to a register array composed of various types of registers. For example, the register can be a register with a rising edge trigger on the SI terminal, a register with a falling edge trigger on the SI terminal, or a register without a rising edge on the SI terminal. Flip-flops and flip-flops without SI terminal falling edge, etc., are not limited.

When the embodiment of the present application is applied to an electronic device, as shown in FIG. 5 , it shows a schematic diagram of the hardware structure of an electronic device. The electronic device may include the chip in the embodiment of the present application. In FIG. 5 , the chip 500 is exemplified. chip. The chip 500 may include a processor 501, a memory 502, a bus 503, and the like.

It can be understood that, the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the chip 500 . In other embodiments of the present application, the chip 500 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange different components. The illustrated components can be realized in hardware, software or a combination of software and hardware.

Wherein, the processor 501 may include one or more processing units. For example, the processor 501 may include a graphics processing unit (graphics processing unit, GPU), a central processing unit (central processing unit, CPU), and/or a neural network processing unit (neural network processing unit, NPU), etc. Wherein, different processing units may be independent components, or may be integrated in one or more processors. In some embodiments, chip 500 may also include one or more processors 501 .

The processor 501 can be understood as the nerve center and command center of the chip 500 . The operation control signal can be generated according to the instruction opcode and timing signal, and the control of fetching and executing instructions can be completed.

Memory 502 may be a cache unit for storing instructions and data. In some embodiments, the memory 502 includes the register array and the clock gating unit provided in the embodiments of the present application.

In a possible implementation manner, the memory 502 may be independent of the processor 501 . That is, the memory 502 may be connected to the processor 501 through the bus 503 and used for storing data, instructions or program codes. When the processor 501 calls and executes the instructions or program codes stored in the memory 502, it can be implemented by calling the register array circuit provided by the embodiment of the present application.

Using the above-mentioned chip provided by this application, in the register array circuit proposed by this application for the chip in conjunction with the accompanying drawings, for example, the data end of the register of the unselected address of the chip is flipped, and the gate clock input to the register is low. The scene that causes the internal circuit of the register to perform invalid inversion is introduced through the register array circuit that uses the gated clock circuit to control the level value of the gated clock input to the register corresponding to each address.

Before introducing the register array circuit provided by the embodiment of the present application, the internal circuit of the register is briefly introduced, as shown in FIG. 6A , where the register is a rising edge trigger register as an example. The ports of the register include a data input terminal (D terminal), a clock input terminal (CLK terminal), a scan input terminal (SI terminal), a scan enable signal input terminal (SE terminal) and a signal output terminal (Q terminal). The D terminal is coupled to the write data bus outside the register to receive data information, the CLK terminal is coupled to the output terminal of the gating clock unit outside the register to receive the gating clock, and the SI terminal is used to input the scan during the register test Signal, the SE terminal is used to control the working mode of the register. When the SE input is low, it is the normal working mode of the register (that is, data is written), and when the SE terminal is high, it is the register scan mode (that is, the register is tested). The Q terminal is used to transmit the output signal. The internal circuit of the register includes SI and D terminal selection circuits, low-pass high-lock latch circuit and high-pass low-lock latch circuit, etc. The CLK terminal is coupled to the SI and D terminal selection circuits, the low-pass high latch circuit and the high-pass low latch circuit, and the CLK terminal includes the CLK terminal and the CLK_bb terminal in FIG. 6A (the signal input to the CLK_bb terminal is opposite to that of the CLK terminal). SE end, SI end and D end are coupled to the input end of SI and D end selection circuit, and the output end of SI and D end selection circuit is coupled to the low-pass circuit in the low-pass high-lock latch circuit (that is, CLK0 among Fig. 6A and CLK0_b partial circuit), the output of the low-pass high latch latch circuit is coupled to the high-pass circuit in the high-pass low latch latch circuit (i.e. CLK2 and CLK2_b partial circuit in Figure 6A), the output of the high-pass low latch latch circuit The terminal is coupled to the Q terminal through the output inverter circuit. Among them, the low-pass high-lock latch circuit can be understood as temporarily storing the data information transmitted by the output terminals of the SI and D terminal selection circuits, and only when the data information is stored in the high-pass low-lock latch circuit, the register is completed data write.

When the register is a rising edge trigger register, when the SE terminal inputs a low level and is in the normal working mode, when the CLK terminal output is a low level, CLK0 and CLK0_b in Figure 6A are turned on. At this time, if the D terminal flips to a low level , then the circuits D0, SE0 and CLK0 are turned on to transmit the data information of the D terminal, and if the D terminal is flipped to a high level, the circuits D0_b, SE0_b and CLK0_b are turned on to transmit the data information of the D terminal. It is equivalent to that the SI and D terminal selection circuits and the low-pass circuit in the low-pass high-lock latch circuit are turned on, and the data information transmitted by the D terminal is output from the low-pass circuit in the low-pass high-lock latch circuit. However, when the output of the CLK terminal is low level, CLK1, CLK1_b, CLK2 and CLK2_b in Figure 6A are not conducting, so the data information output from the low-pass circuit in the low-pass high-lock latch circuit will directly pass through the inverter 1 Output, but not through the high-pass circuit of the high-pass low-lock latch circuit, which is equivalent to the data being temporarily stored in the low-pass high-lock latch circuit. Since the data information has not been stored in the high-pass low-lock latch circuit, it is equivalent to that the register has not been written into data, so the SI and D terminal selection circuit, the low-pass circuit in the low-pass high-lock latch circuit and the inverter 1 The jump generated during data transmission is invalid, which can be understood as a flip in the internal circuit of the register.

When the CLK terminal output is high level, CLK0 and CLK0_b in Figure 6A are not conducting, CLK1, CLK1_b, CLK2 and CLK2_b are conducting, and at the moment when the CLK terminal is flipped from low level to high level, the inverter 1 The output data information will be locked into the high-lock circuit in the low-pass high-lock latch circuit (that is, the CLK1 and CLK1_b part circuits in Figure 6A) through the feedback circuit, and will also pass through the high-pass circuit in the high-pass low-lock latch circuit, It is equivalent to that the data information stored in the low-pass high-latching latch circuit is stored in the high-pass low-latching latch circuit, that is, the data writing to the register is completed. Since the output of the CLK terminal is high level, CLK0 and CLK0_b are not conducted, which is equivalent to that the low-pass circuit in the SI and D terminal selection circuit and the low-pass high-lock latch circuit is not conducted, so the SI and D terminal selection circuit, The low-pass circuit in the low-pass high-lock latch circuit and the inverter 1 do not overturn, so that no waste of power consumption is caused.

When the register is a falling-edge trigger register, the internal circuit of the register is shown in Figure 6B. Unlike the rising-edge trigger register, the output terminals of the SI and D terminal selection circuits are coupled to the high-pass circuit in the high-pass low-lock latch circuit (that is, the high-pass circuit in Figure 6B CLK0 and CLK0_b part of the circuit), the output of the high-pass low-lock latch circuit is coupled to the low-pass circuit in the low-pass high-lock latch circuit (i.e. CLK2 and CLK2_b part of the circuit in Figure 6B), the low-pass high lock The output terminal of the latch circuit is coupled to the Q terminal through the output inverter circuit. Among them, the high-pass low-lock latch circuit can be understood as temporarily storing the data information transmitted by the output terminals of the SI and D terminal selection circuits. Only when the data information is stored in the low-pass high-lock latch circuit, the register is completed. data write.

When the register is a falling-edge trigger register, when the SE terminal inputs a low level and is in normal working mode, when the CLK output is a high level, CLK0 and CLK0_b in Figure 6B are turned on, and if the D terminal flips to a low level at this time, Then the circuits D0, SE0 and CLK0 are turned on to transmit the data information of the D terminal, and if the D terminal is flipped to a high level, the circuits D0_b, SE0_b and CLK0_b are turned on to transmit the data information of the D terminal. It is equivalent to the SI and D terminal selection circuits and the high-pass circuit in the high-pass low-latching latch circuit being turned on, and the data information transmitted by the D terminal is output from the high-pass circuit in the high-pass low-latching latch circuit. However, when the output of the CLK terminal is at a high level, CLK1, CLK1_b, CLK2 and CLK2_b in FIG. 6B are not conducting, so the data information output from the high-pass circuit in the high-pass low-lock latch circuit will be output directly through the inverter 1, But it cannot pass through the low-pass circuit of the low-pass high-lock latch circuit, which is equivalent to the data being temporarily stored in the high-pass low-lock latch circuit. Since the data information has not been stored in the low-pass high-lock latch circuit, it is equivalent to that the register has not been written into data, so the SI and D terminal selection circuit, the high-pass circuit in the high-pass low-lock latch circuit and the inverter 1 The jump generated during data transmission is invalid, and it can be understood that there is a flip in the internal circuit of the register.

When the output of the CLK terminal is low level, CLK0 and CLK0_b in Figure 6B are not conducting, and CLK1, CLK1_b, CLK2 and CLK2_b are conducting. The output data information will be locked into the low-lock circuit in the high-pass low-lock latch circuit (that is, the CLK1 and CLK1_b part circuits in Figure 6B) through the feedback circuit, and will also pass through the low-pass circuit in the low-pass high-lock latch circuit , which means that the data information stored in the high-pass low-lock latch circuit is stored in the low-pass high-lock latch circuit, that is, the data writing to the register is completed. Since the output of the CLK terminal is low level, CLK0 and CLK0_b are not turned on, which is equivalent to that the high-pass circuit in the SI and D terminal selection circuit and the high-pass low latch circuit is not turned on, so the SI and D terminal selection circuit, high-pass low The high-pass circuit and the inverter 1 in the latch circuit do not overturn, so there is no waste of power consumption.

As shown in FIG. 7A , it is a schematic diagram of a register array circuit provided by an embodiment of the present application, and the register array circuit includes: a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one by one.

Wherein, the gating clock circuit is used to output the gating clock to the register. Each of the multiple registers corresponds to a different address. Each register includes a data input terminal and a clock input terminal. The data input terminal of each register is coupled to the write data bus shared by each register. The clock input terminal of each register Both terminals are coupled with the output terminals of the corresponding gated clock circuit, the multiple registers include a first register, the first register is a rising edge trigger register, and the first gated clock circuit corresponding to the first register is an OR gated clock circuit.

Exemplarily, as shown in FIG. 7A , the multiple registers may include a first register, a second register, and an Nth register (N is an integer greater than 1), all of which are rising edge triggered registers. Each register corresponds to a gated clock circuit, the gated clock circuit corresponding to the first register is the first gated clock circuit, the gated clock circuit corresponding to the second register is the second gated clock circuit, and the Nth register corresponds to The gated clock circuit is the Nth gated clock circuit, etc., and each gated clock circuit is an OR gated clock circuit. Wherein, the data input end of the first register is the input end f, and the input end f is coupled to the write data bus. The clock input terminal of the first register is the input terminal g, and the input terminal g is coupled with the output terminal h of the first gating clock circuit. It can be understood that the inversion on the write data bus can invert some circuits inside the first register through the input terminal g, and the output terminal of the first gating clock circuit is used to output the gating clock to the first register to control whether the first register is data input.

In some embodiments, the first clock gating circuit is configured to output a clock gating clamped to a high level to the first register when no write access is performed on the first register.

Wherein, the first gated clock circuit is an OR-gated clock circuit, as shown in FIG. 7B , which is a schematic diagram of the internal structure of the OR-gated clock circuit, which is composed of a high-pass low-lock latch, an inverter, and an OR gate. The high-pass low-lock latch has two input terminals, an enable terminal (E terminal) and a clock input terminal (CLK terminal). The enable terminal is used to receive the address information indicated by the write address bus. When the address information indicated by the write address bus is the When the address of the register corresponding to the OR-gated clock circuit is selected, the enable terminal input is at a high level, which means that the address corresponding to the OR-gated clock circuit is selected, or the register corresponding to the OR-gated clock circuit is executed for write access. The clock input is used to receive the write clock signal shared by each OR-gated clock circuit. The output terminal (Q terminal) of the high-pass low-lock latch is coupled to one input terminal of the OR gate through an inverter, and the other input terminal of the OR gate is used to receive the write clock signal shared by each OR gate clock circuit, or the gate The signal output by the output terminal of the OR gate control clock circuit is the gate control clock output.

The timing diagram of the OR-gated clock circuit shown in FIG. 7B is shown in FIG. 7C , and the address corresponding to the OR-gated clock circuit shown in FIG. 7B is address 1 as an example. In Figure 7C, the write clock signal is flipped periodically, and when the address information indicated by the write address bus is not address 1, that is, when the address corresponding to the OR-gated clock circuit is not selected, the high-pass low-lock latch in Figure 7B is enabled terminal input is low level. After the low level input by the enable terminal and the write clock signal pass through the high-pass low-lock latch, the output terminal of the high-pass low-lock latch is low-level, and the low-level output of the output terminal of the high-pass low-lock latch passes through the inverter. The output terminal of the phaser outputs a high level, and after the high level output by the inverter and the write clock signal pass through the OR gate, the OR gate outputs a high level, that is, the output terminal of the OR gate control clock circuit outputs a high level. It can be understood that when a certain address is not selected, that is, when the register corresponding to a certain address is not accessed for writing, the output end of the clock gating circuit corresponding to the register outputs a high level.

Exemplarily, the write access to the first register is not performed, which can be understood as the address corresponding to the first register is not selected. At this time, the first gating clock circuit outputs a gating clock clamped to a high level to the first register , it can be understood that the first clock gating circuit clamps the clock input terminal of the first register to a high level. When the clock input terminal of the rising-edge trigger register remains high, the SI and D terminal selection circuits inside the rising-edge trigger register and the low-pass circuit in the low-pass high-lock latch circuit will not be turned on, thereby reducing the rising-edge trigger The internal circuit of the register flips over to avoid waste of power consumption.

In some embodiments, when the first register is accessed for writing, the first gating clock circuit is also used to transition the gating clock output to the first register from a high level to a low level, and clamp it to a low level level, and then the gating clock output to the first register jumps from low level to high level.

Wherein, when the gating clock output to the first register transitions from low level to high level, the first register is written with data. As shown in Figure 7C, taking the address corresponding to the OR-gated clock circuit shown in Figure 7B as address 1 as an example, when the address information indicated by the write address bus is address 1, that is, the address corresponding to the OR-gated clock circuit is When selected, the high-pass low-lock latch enable terminal input in FIG. 7B is at a high level. After the high level input by the enable terminal and the write clock signal pass through the high-pass low latch latch, the output terminal of the high-pass low latch latch is high level (the output high level does not necessarily align with the period of the write clock signal), and the high-pass low latch latch After the high level output from the lock output terminal passes through the inverter, the inverter output terminal outputs a low level, and after the low level output from the inverter and the write clock signal pass through the OR gate, the OR gate outputs a low level, that is, the OR The output terminal of the gating clock circuit outputs a low level. And after the output terminal of the OR-gated clock circuit outputs low level for a period of time, it will jump from low level to high level, and the output terminal of the OR-gated clock circuit will jump from low level to high level At the instant of , the data is written into the register corresponding to the OR-gated clock circuit. It can be understood that when a certain address is selected, that is, when a register corresponding to a certain address is accessed for writing, the gating clock corresponding to the register or output from the output terminal of the clock gating circuit will jump from high level to Low level, and continue to output low level for a period of time, then jump from low level to high level, and write data into the register at the moment of transition from low level to high level. Wherein, the jump position of the output terminal of the OR-gated clock circuit corresponding to the register shown in FIG. 7B can be adjusted according to the actual circuit, and the timing diagram is only an example.

Exemplarily, the write access of the first register can be understood as the address corresponding to the first register is selected, at this time, the first gating clock circuit will first output the gating clock to the first register from a high level transition is low level, that is, the first gating clock circuit jumps the clock input terminal of the first register from high level to low level, and clamps it to low level, which can be understood as the rising edge triggers the SI and The low-pass circuit in the D-terminal selection circuit and the low-pass high-lock latch circuit is turned from non-conductive to conductive, and the data information transmitted by the D-terminal is stored in the low-pass high-lock latch circuit. The gated clock output by the first gated clock circuit to the first register changes from a low level to a high level, that is, the first gated clock circuit changes the clock input terminal of the first register from a low level to a high level. high level. And, when the gating clock output to the first register transitions from low level to high level, that is, at the moment when the clock input terminal of the first register transitions from low level to high level, the first register is written It can be understood that the high-pass low-lock latch circuit inside the rising edge trigger register is turned on at the moment when the clock input terminal of the first register jumps from low level to high level. At this time, the low-pass high latch circuit The data information stored in the lock circuit is written into the high-pass low-lock latch circuit, which is equivalent to writing data into the first register.

In some embodiments, each clock gating circuit in the plurality of clock gating circuits further includes a first input terminal and a second input terminal, the first input terminal is coupled to a write address bus shared by each clock gating circuit, The first input terminal can be understood as the enable terminal in FIG. 7B , the second input terminal is used to receive the write clock signal shared with each gating clock circuit, and the second input terminal can be understood as the clock input terminal in FIG. 7B .

Exemplarily, as shown in FIG. 7A , the first gate-controlled clock circuit includes a first input terminal i and a second input terminal j, the first input terminal i of the first gate-controlled clock circuit is coupled to the write address bus, and the first gate The second input terminal j of the clock control circuit is used to receive the write clock signal.

In some embodiments, when the first register is not being accessed for writing, the signal at the first input terminal of the first gating clock circuit is used to indicate that the first address of the first register is not selected.

Exemplarily, the write access to the first register is not performed, which can be understood as the address corresponding to the first register is not selected. At this time, the signal at the first input end of the first gating clock circuit corresponding to the first register is used to indicate The first address of a register is not selected. For example, when the write address bus is the second address, the signal at the first input end of the first gating clock circuit is used to indicate that the first address is not selected.

Therefore, in the register array circuit provided by the embodiment of the present application, when the register array is a rising edge triggered register, the OR gate clock circuit outputs a gate that is clamped to a high level to a register that is not subjected to write access. Clock, that is, the clock input terminal of the register that is not being written and accessed is clamped to a high level, so that the SI and D terminal selection circuits inside the register and the low-pass circuit in the low-pass high-lock latch circuit are not turned on, and SI and D The D-terminal selection circuit, the low-pass circuit in the low-pass high-lock latch circuit, and the inverter do not flip over, thereby avoiding waste of power consumption, improving power consumption utilization, reducing the number of windings and circuit area, and at the same time Ease of physical realization.

As shown in FIG. 7D , it is a schematic diagram of another register array circuit provided by an embodiment of the present application. The register array circuit includes: a plurality of registers and a plurality of clock gating circuits corresponding to the plurality of registers one by one.

Wherein, the gating clock circuit is used to output the gating clock to the register. Each of the multiple registers corresponds to a different address. Each register includes a data input terminal and a clock input terminal. The data input terminal of each register is coupled to the write data bus shared by each register. The clock input terminal of each register Both terminals are coupled with the output terminals of the corresponding gated clock circuit, the multiple registers include a first register, the first register is a falling edge trigger register, and the first gated clock circuit corresponding to the first register is an AND gated clock circuit.

Exemplarily, as shown in FIG. 7D , the multiple registers may include a first register, a second register, and an Nth register (N is an integer greater than 1), all of which are falling edge triggered registers. Each register corresponds to a gated clock circuit, the gated clock circuit corresponding to the first register is the first gated clock circuit, the gated clock circuit corresponding to the second register is the second gated clock circuit, and the Nth register corresponds to The gated clock circuit is the Nth gated clock circuit, etc., and each gated clock circuit is an AND gated clock circuit. Wherein, the data input terminal of the first register is the input terminal k, and the input terminal k is coupled to the write data bus. The clock input end of the first register is the input end l, and the input end l is coupled to the output end m of the first gating clock circuit. It can be understood that the inversion on the write data bus can cause some internal circuits of the first register to invert through the input terminal 1, and the output terminal of the first gating clock circuit is used to output the gating clock to the first register to control whether the first register is data input.

In some embodiments, the first clock gating circuit is configured to output a clock gating clamped to a low level to the first register when no write access is performed on the first register.

Wherein, the first gated clock circuit is an AND-gated clock circuit, as shown in FIG. 7E , which is a schematic diagram of the internal structure of the AND-gated clock circuit, which is composed of a low-pass high-lock latch, an inverter and an AND gate. The low-pass high-lock latch has two input terminals, an enable terminal (E terminal) and a clock input terminal (CLK terminal). The enable terminal is used to receive the address information indicated by the write address bus. When the address information indicated by the write address bus is When the address of the register corresponding to the gated clock circuit is set, the input of the enable terminal is at a high level, which means that the address corresponding to the gated clock circuit is selected, and the register corresponding to the gated clock circuit is executed for write access. A clock input is used to receive each write clock signal shared with the clock gating circuit. The output terminal (Q terminal) of the low-pass high-lock latch is coupled with one input terminal of the AND gate, and the other input terminal of the AND gate is used to receive the write clock signal shared by each gate-controlled clock circuit, and the output terminal of the AND gate The output signal is the gate control clock output by the gate control clock circuit.

The timing diagram of the gated clock circuit shown in FIG. 7E is shown in FIG. 7F , and the address corresponding to the gated clock circuit shown in FIG. 7E is address 1 as an example. In Fig. 7F, the write clock signal is periodically reversed. When the address information indicated by the write address bus is not address 1, that is, when the address corresponding to the gated clock circuit is not selected, the low-pass high-lock latch in Fig. 7E enables The energy terminal input is low level. After the low level input from the enable port and the write clock signal pass through the low-pass high latch latch, the output terminal of the low-pass high-lock latch is low level, and the low-level output terminal of the high-pass low-lock latch output terminal and the write clock signal pass through and After the gate, the AND gate outputs a low level, that is, the output terminal of the AND gate control clock circuit outputs a low level. It can be understood that when a certain address is not selected, that is, when the register corresponding to a certain address is not accessed for writing, the output end of the clock gating circuit corresponding to the register outputs a low level.

Exemplarily, the write access to the first register is not performed, which can be understood as the address corresponding to the first register is not selected. At this time, the first clock gating circuit outputs a gating clock clamped to a low level to the first register , it can be understood that the first gating clock circuit clamps the clock input terminal of the first register to a low level. When the clock input terminal of the falling-edge trigger register remains low, the SI and D terminal selection circuits inside the falling-edge trigger register and the high-pass circuit in the high-pass low-lock latch circuit will not be turned on, thereby reducing the internal frequency of the falling-edge trigger register. The circuit flips over to avoid wasting power consumption.

In some embodiments, when the first register is accessed for writing, the first gating clock circuit is also used to transition the gating clock output to the first register from a low level to a high level, and clamp it to a high level level, and then the gating clock output to the first register jumps from high level to low level.

Wherein, when the gating clock output to the first register transitions from a high level to a low level, the first register is written with data. As shown in FIG. 7F, taking the address corresponding to the gated clock circuit shown in FIG. 7E as address 1 as an example, when the address information indicated by the write address bus is address 1, that is, the address corresponding to the gated clock circuit is When selected, the input of the low-pass high-lock latch enable terminal in FIG. 7E is at a high level. After the high level input by the enable terminal and the write clock signal pass through the low-pass high-lock latch, the output terminal of the low-pass high-lock latch is high level (the output high level does not necessarily align with the period of the write clock signal), and the low-pass After the high level output from the high-lock latch output terminal and the write clock signal pass through the AND gate, the AND gate outputs a high level, that is, the output terminal of the AND gate control clock circuit outputs a high level. And after the output terminal of the AND-gated clock circuit outputs a high level for a period of time, it will jump from a high level to a low level, and the output terminal of the AND-gated clock circuit will change from a high level to a low level At an instant, data is written into the register corresponding to the gated clock circuit. It can be understood that when a certain address is selected, that is, when the register corresponding to a certain address is accessed for writing, the gating clock corresponding to the register and the output terminal of the clock gating circuit will jump from low level to High level, and continue to output high level for a period of time, then jump from high level to low level, and write data into the register at the moment of transition from high level to low level. Wherein, the jump position corresponding to the output end of the gated clock circuit corresponding to the register shown in FIG. 7E can be adjusted according to the actual circuit, and the timing diagram is only an example.

Exemplarily, the write access of the first register can be understood as the address corresponding to the first register is selected, at this time, the first gating clock circuit will first output the gating clock to the first register from a low level transition is a high level, that is, the first gating clock circuit jumps the clock input terminal of the first register from a low level to a high level, and clamps it to a high level, which can be understood as a falling edge triggering the SI and The high-pass circuit in the D-terminal selection circuit and the high-pass low-lock latch is changed from being turned on to being turned on, and the data information transmitted by the D-terminal is stored in the high-pass low-lock latch circuit. The gated clock output by the first gated clock circuit to the first register changes from a high level to a low level, that is, the first gated clock circuit changes the clock input terminal of the first register from a high level to a low level. low level. And, when the gating clock output to the first register transitions from a high level to a low level, that is, at the moment when the clock input terminal of the first register transitions from a high level to a low level, the first register is written It can be understood that the low-pass high-lock latch circuit inside the falling edge trigger register is turned on at the moment when the clock input terminal of the first register jumps from high level to low level. At this time, the high-pass low latch circuit The data information stored in the lock circuit is written into the low-pass high-lock latch circuit, which is equivalent to writing data into the first register.

In some embodiments, each clock gating circuit in the plurality of clock gating circuits further includes a first input terminal and a second input terminal, the first input terminal is coupled to a write address bus shared by each clock gating circuit, The first input terminal can be understood as the enable terminal in FIG. 7E , the second input terminal is used to receive the write clock signal shared with each gating clock circuit, and the second input terminal can be understood as the clock input terminal in FIG. 7E .

Exemplarily, as shown in FIG. 7D, the first clock gating circuit includes a first input terminal o and a second input terminal p, the first input terminal o of the first clock gating circuit is coupled to the write address bus, and the first gate The second input terminal p of the clock control circuit is used to receive the write clock signal.

In some embodiments, when the first register is not being accessed for writing, the signal at the first input terminal of the first gating clock circuit is used to indicate that the first address of the first register is not selected.

Exemplarily, the write access to the first register is not performed, which can be understood as the address corresponding to the first register is not selected. At this time, the signal at the first input end of the first gating clock circuit corresponding to the first register is used to indicate The first address of a register is not selected. For example, when the write address bus is the second address, the signal at the first input end of the first gating clock circuit is used to indicate that the first address is not selected.

Therefore, in the register array circuit provided by the embodiment of the present application, when the register array is a falling-edge trigger register, the AND gating clock circuit outputs a gate that is clamped to a low level to a register that is not subjected to write access. Clock, that is, the clock input terminal of the register that is not being written and accessed is clamped to a low level, so that the internal SI and D terminal selection circuit of the register and the high-pass circuit in the high-pass low-lock latch are not turned on, and the SI and D terminal selection The circuit, the high-pass circuit in the high-pass low-latch latch and the inverter do not flip over, thereby avoiding waste of power consumption, improving the utilization rate of power consumption, reducing the number of windings and circuit area, and at the same time facilitating physical implementation.

As shown in FIG. 8 , an embodiment of the present application provides a flow chart of a method for accessing a register array. Taking the register array circuit shown in FIG. 7A as an example, the register is a rising edge triggered register. That is, the gated clock unit of the OR clock gating circuit in FIG. 4A can be the first gated clock circuit in FIG. 7A, the write address bus in FIG. 4A is the write address bus in FIG. 7A, and the register array in FIG. 4A Including the first register in Fig. 7A and so on. This method is applied to the register array circuit shown in FIG. 7A . For the specific structure of the register array circuit, refer to the above description of FIG. 7A . The method includes:

Step 801 , when it is determined that the first register is not subject to write access, a signal through the first input terminal of the first gating clock circuit indicates that the first address of the first register is not selected.

Exemplarily, as shown in FIG. 7A, when it is determined that the first register is not subjected to write access, it can be understood that when it is determined that the address corresponding to the first register is not selected, the first gating clock circuit corresponding to the first register A signal at the first input of the first register indicates that the first address of the first register is not selected.

Step 802 , when it is determined that the first register is not subject to write access, output a gated clock clamped to a high level to the first register through the first gated clock circuit.

Exemplarily, as shown in FIG. 7A, when it is determined that the first register is not being accessed for write access, it can be understood that when it is determined that the address corresponding to the first register is not selected, the first register is sent to the first register through the first gating clock circuit. Outputting a gated clock clamped to a high level, that is, clamping the clock input terminal of the first register to a high level through the first gated clock circuit. When the clock input terminal of the rising-edge trigger register remains high, the SI and D terminal selection circuits inside the rising-edge trigger register and the low-pass circuit in the low-pass high-lock latch circuit will not be turned on, thereby reducing the rising-edge trigger The internal circuit of the register flips over to avoid waste of power consumption.

In some embodiments, when it is determined that the first register is accessed for writing, the gating clock output to the first register through the first gating clock circuit jumps from a high level to a low level, that is, the clock of the first register The input end transitions from high level to low level, and is clamped to low level, and then the gating clock output to the first register transitions from low level to high level, that is, the clock of the first register The input terminal transitions from low level to high level, and when the clock input terminal of the first register transitions from low level to high level, data is written into the first register.

Exemplarily, when it is determined that the first register is subjected to write access, the specific control process of the first clock gate circuit on the clock input terminal of the first register and the process of writing data to the first register can refer to the above description of FIG. 7A .

Therefore, in a method for accessing a register array provided by an embodiment of the present application, when the register array is a rising-edge-triggered register, an OR-gated clock circuit outputs a gated clock clamped to a high level to the first register, The clock input terminal of the register that is not being written and accessed is clamped to a high level, so that the SI and D terminal selection circuits inside the register and the low-pass circuit in the low-pass high-lock latch circuit are not turned on, and no flipping is performed. Furthermore, the waste of power consumption is avoided, the utilization rate of power consumption is improved, the number of winding wires and the circuit area are reduced, and at the same time, it is convenient for physical realization.

As shown in FIG. 9 , an embodiment of the present application provides a flow chart of a method for accessing a register array. Taking the register array circuit shown in FIG. 7D as an example, the register is a falling edge trigger register. That is, the gated clock unit comprising the clock gating circuit in FIG. 4B can be the first gated clock circuit in FIG. 7D, the write address bus in FIG. 4B is the write address bus in FIG. 7D, and the register array in FIG. 4B Including the first register in Fig. 7D and so on. This method is applied to the register array circuit shown in FIG. 7D . For the specific structure of the register array circuit, refer to the above description of FIG. 7D . The method includes:

Step 901. When it is determined that the first register is not subject to write access, a signal through the first input terminal of the first gating clock circuit indicates that the first address of the first register is not selected.

Exemplarily, as shown in FIG. 7D, when it is determined that the first register is not subjected to write access, it can be understood that when it is determined that the address corresponding to the first register is not selected, the first gating clock circuit corresponding to the first register A signal at the first input of the first register indicates that the first address of the first register is not selected.

Step 902: When it is determined that the first register is not being accessed for writing, output a gate clock clamped to a low level to the first register through the first gate clock circuit.

Exemplarily, as shown in FIG. 7D, when it is determined that the first register is not being accessed for writing, it can be understood that when it is determined that the address corresponding to the first register is not selected, the first register is sent to the first register through the first gating clock circuit. Outputting the gated clock clamped to a low level, that is, clamping the clock input end of the first register to a low level through the first gated clock circuit. When the clock input terminal of the falling-edge trigger register remains low, the SI and D terminal selection circuits inside the falling-edge trigger register and the high-pass circuit in the high-pass low-lock latch circuit will not be turned on, thereby reducing the internal frequency of the falling-edge trigger register. The circuit flips over to avoid wasting power consumption.

In some embodiments, when it is determined that the first register is to be accessed for writing, the gating clock output to the first register through the first gating clock circuit jumps from a low level to a high level, that is, the clock of the first register The input terminal transitions from low level to high level, and clamps to high level, and then the gating clock output to the first register transitions from high level to low level, that is, the clock of the first register The input terminal transitions from high level to low level, and when the clock input terminal of the first register transitions from high level to low level, data is written into the first register.

Exemplarily, when it is determined that the first register is subjected to write access, the specific control process of the first clock gate circuit on the clock input terminal of the first register and the process of writing data to the first register can refer to the above description of FIG. 7B .

Therefore, in a method for accessing a register array provided by an embodiment of the present application, when the register array is a falling-edge triggered register, the AND gate clock circuit outputs a gate clock clamped to a low level to the first register, The clock input terminal of the register that is not being written and accessed is clamped to a low level, so that the SI and D terminal selection circuits inside the register and the high-pass circuit in the high-pass low-lock latch circuit are not turned on, and no flipping is performed, thereby avoiding It causes waste of power consumption, improves the utilization rate of power consumption, reduces the number of winding wires and circuit area, and is convenient for physical realization at the same time.

The following uses FIG. 10 as an example to introduce a register array circuit provided by an embodiment of the present application, wherein the register array is a rising edge triggered register.

The register array includes, for example, 0 address registers, 1 address registers, and n address registers (n is an integer greater than 1) shown in FIG. The address corresponding to each register is different. The clock input terminal r of each register is coupled to the output terminal s of the corresponding OR-gated clock circuit, and the data input terminal q of each register shares the write data bus. Among the two input terminals of the OR-gated clock circuit, one input terminal t is controlled by the write address bus shared by each OR-gated clock circuit, and the other input terminal u is used to receive the write clock shared by each OR-gated clock circuit Signal. When the address information=0 indicated by the write address bus, that is, when the 0 address was selected to write data, the output terminal corresponding to the 0 address register or the gate-controlled clock circuit carried out a rising edge jump (or the output terminal of the gate-controlled clock circuit was controlled by Low level transitions to high level), and the output terminals of the other unselected address registers or the gate control clock circuit do not jump (or the output terminal of the gate control clock circuit remains high level), write data The data information carried on the bus is written into the 0 address register when the output terminal of the OR-gated clock circuit undergoes a rising edge transition. When the address information=0 indicated by the write address bus, all the other addresses were not selected (such as 1 address and n address were not selected), and the corresponding registers of the unselected addresses (such as 1 address register and n address register) were not executed Write access, the output terminal of the gate clock circuit corresponding to the register that has not been performed write access clamps the clock input terminal of the register to a high level, so that the internal SI and D terminal selection circuits of the register and the low-pass high latch The low-pass circuit in the lock is not turned on, and does not flip over, thereby avoiding waste of power consumption, improving the utilization rate of power consumption, reducing the number of winding wires and circuit area, and at the same time, it is convenient for physical realization.

As shown in FIG. 11 , it is a timing diagram of the register array circuit in FIG. 10 . The write clock signal is periodically flipped, and when the address information indicated by the write address bus = 0, address 0 is selected, and the register of address 0 is executed for write access, and the output terminal corresponding to address register 0 or the gate control clock circuit will perform a rising edge jump , at this time, data is written into the 0 address register, and the data in the write data bus is written into the 0 address register. When the address information indicated by the write address bus=0, the registers corresponding to the remaining unselected addresses are not accessed for writing, and the output terminals of the gate clock circuit corresponding to the registers not accessed for writing do not perform a transition. Taking the output terminal of the gated clock circuit corresponding to the 1 address register as an example, when the address information indicated by the write address bus=0, the output terminal of the gated clock circuit corresponding to the 1 address register remains at a high level without jumping, that is 1 The address register is not written with data. Wherein, the jump position of the output terminal of the OR-gated clock circuit corresponding to the register shown in FIG. 11 can be adjusted according to the actual circuit, and the timing diagram is only an example.

The following uses FIG. 12 as an example to introduce another register array circuit provided by the embodiment of the present application, wherein the register array is a falling edge trigger register.

The register array includes, for example, 0 address registers, 1 address registers, and n address registers (n is an integer greater than 1) shown in FIG. The address corresponding to each register is different. The clock input terminal w of each register is coupled to the corresponding output terminal x of the gating clock circuit, and the data input terminal v of each register shares the write data bus. Among the two input terminals of the gate-controlled clock circuit, one input terminal y is controlled by each write address bus shared with the gate-controlled clock circuit, and the other input terminal z is used to receive each write clock shared with the gate-controlled clock circuit Signal. When the address information=0 indicated by the write address bus, that is, when the 0 address was selected to write data, the output terminal corresponding to the 0 address register and the gate-controlled clock circuit carried out a falling edge jump (the output terminal of the gate-controlled clock circuit is determined by High level transitions to low level), the other unselected address registers correspond to the output terminal of the gated clock circuit without jumping (the output terminal of the gated clock circuit remains low), write data The data information carried on the bus is written into the 0 address register when the output end of the gate-controlled clock circuit performs a falling edge transition. When the address information=0 indicated by the write address bus, all the other addresses were not selected (such as 1 address and n address were not selected), and the corresponding registers of the unselected addresses (such as 1 address register and n address register) were not executed Write access, the output end of the gate control clock circuit corresponding to the register that has not been executed write access clamps the clock input end of the register to a low level, so that the internal SI and D end selection circuits of the register and the high-pass low-lock latch The high-pass circuit in the circuit is not turned on, and does not flip over, thereby avoiding waste of power consumption, improving the utilization rate of power consumption, reducing the number of windings and circuit area, and at the same time, it is convenient for physical realization.

As shown in FIG. 13 , it is a timing diagram of the register array circuit in FIG. 12 . The write clock signal is periodically flipped, and when the address information indicated by the write address bus = 0, address 0 is selected, and the register of address 0 is executed for write access, and the output of the address register 0 corresponding to the gated clock circuit will perform a falling edge jump , at this time, data is written into the 0 address register, and the data in the write data bus is written into the 0 address register. When the address information indicated by the write address bus=0, the registers corresponding to the remaining unselected addresses are not accessed for writing, and the output terminals of the clock gate circuit corresponding to the registers not accessed for writing do not perform a transition. Taking the output terminal of the gated clock circuit corresponding to the 1 address register as an example, when the address information indicated by the write address bus=0, the output terminal of the gated clock circuit corresponding to the 1 address register remains at a low level without jumping, that is 1 The address register is not written with data. Wherein, the jump position corresponding to the output end of the gated clock circuit corresponding to the register shown in FIG. 13 can be adjusted according to the actual circuit, and the timing diagram is only an example.

It can be understood that, in order to realize the above-mentioned functions, the above-mentioned electronic device includes corresponding hardware structures and/or software modules for performing each function. Those skilled in the art should easily realize that the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software in combination with the example units and algorithm steps described in the embodiments disclosed herein. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the embodiments of the present application.

The embodiments of the present application may divide the above-mentioned electronic device into functional modules according to the above-mentioned method examples. For example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.

In the case of using an integrated unit, as shown in FIG. 14 , the embodiment of the present application discloses an electronic device 1400 , and the electronic device 1400 may be the chip in the above embodiment. The electronic device 1400 may include a processing module and a memory module. Wherein, the processing module can be used to determine the address information indicated by the write address bus, and send the address information of the register to be accessed to the storage module through the write address bus, and send the data to be written to the storage module through the write data bus. The storage module can be used to support the electronic device 1400 to store program codes and data, and can also be used to support the electronic device 1400 to execute the above steps 801 , 802 , 901 and 902 .

Certainly, the unit modules in the above electronic device 1400 include but not limited to the above processing module and storage module.

Wherein, the processing module may be a processor 1401 (such as the processor 501 shown in FIG. 5 ), and the storage module may be a memory 1402 (such as the memory 502 shown in FIG. 5 ). The electronic device 1400 provided in the embodiment of the present application may be the chip 500 shown in FIG. 5 . Wherein, the processor and the memory may be coupled together, for example, the processor is coupled to the memory through a write address bus and a write data bus.

The embodiment of the present application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled with one or more processors, the one or more memories are used to store computer program codes, the computer program codes include computer instructions, and when the one or more processors execute the computer instructions, the electronic device performs The above related method steps implement the method for limiting power consumption in the above embodiments.

The embodiment of the present application also provides a computer-readable storage medium, in which computer program code is stored. When the processor executes the computer program code, the electronic device executes the method for accessing the register array in the above-mentioned embodiment.

Embodiments of the present application also provide a computer program product, which, when running on a computer, causes the computer to execute the above-mentioned related steps, so as to implement the method for accessing the register array performed by the electronic device in the above-mentioned embodiments.

Wherein, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is all used to execute the corresponding method provided above, therefore, the beneficial effects it can achieve can refer to the corresponding method provided above The beneficial effects in the method will not be repeated here.

Through the description of the above embodiments, those skilled in the art can understand that for the convenience and brevity of the description, only the division of the above functional modules is used as an example for illustration. In practical applications, the above functions can be assigned by different Completion of functional modules means that the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation or may be integrated into another device, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium Among them, several instructions are included to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes such as U disk, mobile hard disk, read only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk.

The above content is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should covered within the scope of protection of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (20)

A register array circuit, characterized in that the register array circuit includes a plurality of registers and a plurality of gate-controlled clock circuits corresponding to the plurality of registers one-to-one, and the gate-controlled clock circuit is used to output to the registers Gated clock; the multiple registers include a first register, the first register is a rising edge trigger register; the first gated clock circuit corresponding to the first register is an OR gated clock circuit; The first gating clock circuit is configured to output a gating clock clamped to a high level to the first register when the first register is not being accessed for writing. The register array circuit according to claim 1, wherein, When the first register is accessed for writing, the first gating clock circuit is also used to transition the gating clock output to the first register from high level to low level, and clamp it to low level, and then the gating clock output to the first register jumps from low level to high level; Wherein, when the gating clock output to the first register transitions from low level to high level, the first register is written with data. The register array circuit according to claim 1 or 2, wherein each clock gate circuit in the plurality of clock gate circuits further includes a first input terminal and a second input terminal, and the first input terminal The terminal is coupled to the write address bus shared by each clock gating circuit, and the second input terminal is used to receive the write clock signal shared by each clock gating circuit. The register array circuit according to claim 3, wherein when the first register is not being accessed for writing, the signal at the first input end of the first gating clock circuit is used to indicate the The first address is not selected. A register array circuit, characterized in that the register array circuit includes a plurality of registers and a plurality of gate-controlled clock circuits corresponding to the plurality of registers one-to-one, and the gate-controlled clock circuit is used to output to the registers Gated clock; the multiple registers include a first register, the first register is a falling edge trigger register; the first gated clock circuit corresponding to the first register is an AND gated clock circuit; The first gating clock circuit is configured to output a gating clock clamped to a low level to the first register when the first register is not being accessed for writing. The register array circuit according to claim 5, wherein, When the first register is accessed for writing, the first gating clock circuit is also used to transition the gating clock output to the first register from low level to high level, and clamp it to high level, and then the gating clock output to the first register jumps from a high level to a low level; Wherein, when the gating clock output to the first register transitions from a high level to a low level, the first register is written with data. The register array circuit according to claim 5 or 6, wherein each clock gate circuit in the plurality of clock gate circuits further includes a first input terminal and a second input terminal, and the first input terminal The terminal is coupled to the write address bus shared by each clock gating circuit, and the second input terminal is used to receive the write clock signal shared by each clock gating circuit. The register array circuit according to claim 7, wherein when the first register is not being accessed for writing, the signal at the first input end of the first gating clock circuit is used to indicate the The first address is not selected. A method for accessing a register array, the method being applied to a register array circuit, characterized in that the register array circuit includes a plurality of registers and a plurality of gated clock circuits corresponding to the plurality of registers one-to-one, the The gated clock circuit is used to output the gated clock to the register; the multiple registers include a first register, and the first register is a rising edge trigger register; the first gated clock circuit corresponding to the first register Or gate the clock circuit; When it is determined that the first register is not being accessed for writing, outputting a gated clock clamped to a high level to the first register through the first gated clock circuit. The method according to claim 9, characterized in that the method further comprises: When it is determined that the first register is being written and accessed, the gating clock output to the first register through the first gating clock circuit jumps from a high level to a low level, and is clamped to a low level level, and then the gating clock output to the first register jumps from a low level to a high level; Wherein, when the gating clock output to the first register transitions from low level to high level, data is written into the first register. The method according to claim 9 or 10, wherein each clock gating circuit in the plurality of clock gating circuits further comprises a first input terminal and a second input terminal, and the first input terminal and The write address bus shared by each clock gating circuit is coupled, and the second input end is used for receiving the write clock signal shared by each clock gating circuit. The method according to claim 11, further comprising: when it is determined that the first register is not being accessed for writing, indicating the The first address of the first register is not selected. A method for accessing a register array, the method being applied to a register array circuit, characterized in that the register array circuit includes a plurality of registers and a plurality of gated clock circuits corresponding to the plurality of registers one-to-one, the The gated clock circuit is used to output the gated clock to the register; the multiple registers include a first register, and the first register is a falling edge trigger register; the first gated clock circuit corresponding to the first register is an AND-gated clock circuit; When it is determined that the first register is not being accessed for writing, outputting a gate clock clamped to a low level to the first register through the first gate clock circuit. The method according to claim 13, further comprising: When it is determined that the first register is being written and accessed, the gating clock output to the first register through the first gating clock circuit jumps from a low level to a high level, and is clamped to a high level level, and then the gating clock output to the first register jumps from a high level to a low level; Wherein, when the gating clock output to the first register transitions from a high level to a low level, data is written into the first register. The method according to claim 13 or 14, wherein each clock gating circuit in the plurality of clock gating circuits further comprises a first input terminal and a second input terminal, and the first input terminal and The write address bus shared by each clock gating circuit is coupled, and the second input end is used for receiving the write clock signal shared by each clock gating circuit. The method according to claim 15, further comprising: when it is determined that the first register is not being accessed for writing, indicating the The first address of the first register is not selected. A computer-readable storage medium is characterized by comprising computer instructions, and when the computer instructions are run on the electronic device, the electronic device is made to execute the method described in any one of claims 9-12 above. A computer-readable storage medium is characterized by comprising computer instructions, and when the computer instructions are run on the electronic device, the electronic device is made to execute the method described in any one of claims 13-16. A computer program product, characterized in that, when the computer program product is run on a computer, the electronic device is made to execute the method described in any one of claims 9-12. A computer program product, characterized in that, when the computer program product is run on a computer, the electronic device is made to execute the method described in any one of claims 13-16.

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