WO2023240841A1 - Chip-based image affine transformation method and chip - Google Patents

Abstract

A chip-based image affine transformation method and a chip. The method comprises: triggering the current input cache of a plurality of input caches and an intermediate cache to read, from an off-chip memory, current partial image data of an input image and parameter data required for calculation, and respectively writing said data into the current input cache and the intermediate cache; when reading the current partial data of the input image, actuating a calculation unit to perform, via the parameter data, affine transformation and interpolation calculation on historical partial image data of the input image acquired by a historical input cache of the plurality of input caches, so as to obtain a historical partial processing result of a target output image; and writing the historical partial processing result into an output cache, and performing affine transformation and interpolation calculation on the current partial data at the same time, so as to obtain a complete processing result of the target output image.

Description

A chip-based image affine transformation method and chip

This application claims priority to the Chinese patent application submitted to the China Patent Office on June 15, 2022, with the application number 202210684991.4, and the invention title is "A chip-based image affine transformation method and chip", the entire content of which is incorporated by reference incorporated in this application.

Technical field

The present application belongs to the field of image processing and chip technology, and in particular relates to a chip-based image affine transformation method and chip.

Background technique

In image recognition, in order to improve the accuracy of image recognition, it is often necessary to transform the image perspective. For example, the images of a painting on the wall taken by the camera from different distances and different angles are different. If these images taken from different distances and different angles are uniformly projected through the transformation matrix, the camera will be at a fixed distance directly in front of the painting. The images taken at different places can help improve the accuracy of image recognition. This transformation is called projective transformation. However, in practical applications, since parallel straight lines may become non-parallel under projective transformation, affine transformation is generally used to approximate the projective transformation, such as preprocessing for face recognition.

In the existing technology, the computer system of Central Processing Unit (CPU) and Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) are often used to implement affine transformation, but Directly performing affine transformation through the transformation matrix in this system will cause problems such as slow speed and long time consumption. Because DDR is a dynamic memory, read and write access to random addresses in DDR takes much longer than continuous reading. address to access.

Technical solutions

In view of this, embodiments of the present application provide a chip-based image affine transformation method and chip, which can solve one or more technical problems in related technologies.

In the first aspect, an embodiment of the present application provides a chip-based image affine transformation method. The digital chip includes multiple sets of input buffers, intermediate buffers, computing units and output buffers, wherein the image affine transformation method It includes: triggering the current group of input buffers and intermediate buffers in the multiple groups of input buffers to read the current part of the image data of the input image and the parameter data required for calculation from the off-chip memory, and write them into the current group of input buffers and all the parameter data respectively. The intermediate cache; wherein, the parameter data includes the target output image of the required viewing angle and the corresponding resolution; while reading the current part of the input image data, the actuating calculation unit uses the parameter data to calculate the history of multiple sets of input caches. Perform affine transformation and interpolation calculations on the historical partial image data of the input image obtained by the input cache to obtain the historical partial processing results of the target output image; write the historical partial processing results to the output cache and simultaneously perform affine transformation and interpolation on the current partial data Calculated to obtain the complete processing result of the target output image.

In a second aspect, an embodiment of the present application provides a chip, including: multiple sets of input buffers, used to read part of the image data of the input image from an off-chip memory in turn; an intermediate buffer, used to read according to the multiple sets of input buffers The timing of the data reads part of the parameter data of the input image from the off-chip memory; where the parameter data includes the starting address of the input image data in the off-chip memory, the resolution of the target output image, and the designated storage address of the output image. ; Calculation module, configured to use parameter data to obtain the current partial data of the input image from the off-chip memory while the current group of input caches in the multiple groups of input buffers obtains the current partial data of the input image from the chip. The historical partial data of the input image obtained from the external memory is interpolated to obtain partial processing results of the output image; the output cache is used to store the partial processing results.

In a third aspect, an embodiment of the present application provides a computer storage medium. The computer storage medium stores a computer program. When the computer program is executed by a processor, the method as described in the embodiment of the first aspect is implemented.

In a fourth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device implements the method described in the embodiment of the first aspect.

beneficial effects

The embodiment of the present application caches the partial image data (or partial image data) of the input image stored in the off-chip memory through several input buffers inside the chip, and calculates the affine transformed pixel values through the interpolation calculation method so that The interpolation calculation process and the image caching process can be performed in parallel, which not only controls the cost, but also greatly improves the calculation speed of image affine transformation.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of the present application. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a chip provided by an embodiment of the present application;

Figure 2 is a schematic flow chart of the implementation of a chip-based image affine transformation method provided by an embodiment of the present application;

Figure 3 is a schematic diagram of the mapping relationship between an input image and a target output image of a required field of view under affine transformation provided by an embodiment of the present application;

Figure 4 is a schematic flow chart of the implementation of step S120 in a chip-based image affine transformation method provided by an embodiment of the present application;

Figure 5 is a schematic diagram of the positions of vertices and main edges provided by an embodiment of the present application;

Figure 6 is a schematic diagram of a mapping image of a target output image in an input image according to an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a chip provided by an embodiment of the present application.

Embodiments of the invention

In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures and technologies are provided to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

As used in this specification and the appended claims, the term "and/or" means and includes any and all possible combinations of one or more of the associated listed items.

Reference in the specification of this application to "one embodiment" or "some embodiments" or the like means that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in other embodiments", etc. appearing in different places in this specification are not necessarily References are made to the same embodiment, but rather to "one or more but not all embodiments" unless specifically stated otherwise. The terms “including,” “includes,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

In addition, in the description of this application, "plurality" means two or more. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

It should also be understood that, unless otherwise expressly stipulated or limited, the term "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection or an intermediate connection. The medium is indirectly connected, which can be the internal connection between two components or the interaction between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

At present, image affine transformation is often used in CPU and DDR computer systems, which directly implements affine transformation through transformation matrices. However, this method is slow and time-consuming.

In view of this, embodiments of the present application provide a chip-based image affine transformation method and chip, which only cache partial image data (or partial image data) stored in DDR through several small-capacity SRAMs; and use When the interpolation calculation method calculates the pixel value after affine transformation, the interpolation calculation process and the image caching process are performed in parallel, which not only controls the cost, but also greatly improves the calculation speed of the image affine transformation.

In order to better illustrate the technical solution of the present application, the following examples will elaborate and illustrate the technical solution of the present application in combination with some specific parameters. It should be understood that these parameters are only preferred parameters for convenience of explanation and cannot be construed as specific limitations of the present application.

FIG. 1 is an architectural schematic diagram of a chip provided according to an embodiment of the present application. In order to better illustrate the chip of this embodiment, FIG. 1 shows an off-chip memory 23A coupled to the chip 23 . More specifically, the chip 23 includes multiple sets of input caches 231, computing modules 232, output caches 233 and intermediate caches 234, wherein:

Multiple sets of input buffers 231 are used to obtain partial data of the input image from the off-chip memory 23A in turn, and stop obtaining until all data of the input image is obtained.

The intermediate cache 234 is used to cache parameters required for calculation by the calculation module 232; the parameters include the target output image of the required field of view and the corresponding resolution.

The calculation module 232 is configured to use the parameters cached in the intermediate cache 234 to input historical groups in the multiple sets of input caches using the parameters cached in the intermediate cache 234 while the current set of input caches in the multiple sets of input caches 231 obtains the current partial data of the input image from the off-chip memory 23A. The cache performs interpolation calculation on the historical partial data of the input image obtained from the off-chip memory 23A to obtain partial processing results of the output image.

The output cache 233 is used to store partial processing results, and after the complete processing result of the output image is written into the output cache, the complete processing result of the output image is written into the corresponding address specified by the off-chip memory 23A.

In one embodiment, input image data is stored in off-chip memory 23A. Preferably, the off-chip memory 23A may be a DDR memory. In some other embodiments, the DDR memory can also use devices such as Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), or Pseudo static random access memory (Pseudo static random access memory). , PSRAM) and other substitutions, there are no restrictions here.

Figure 2 is a schematic flow chart of an implementation of an image affine transformation method based on a digital chip according to an embodiment of the present application. The image affine transformation method may include steps S110 to S130.

S110, trigger the current group of input buffers in the multiple groups of input buffers to obtain the current part of the input image data from the off-chip memory, and write it into the current group of input buffers and the intermediate buffer.

In one embodiment, the data for obtaining the input image includes image data and parameter data, wherein the image data is written into the input cache, and the parameter data is written into the intermediate cache; preferably, the image data includes the pixel values and pixel coordinates of the input image. The parameter data includes the target output image of the required viewing angle and the corresponding resolution, the specified address of the output image corresponding to the input image in the off-chip memory, etc.

Further, multiple groups of input buffers are switched to the current group of input buffers in turn and partial data of the input image is obtained from the off-chip memory. The acquisition is stopped until all data of the input image is obtained; preferably, the multiple groups of input buffers include at least two groups. Input cache, two sets of input cache ping-pong operations obtain part of the data of the input image from off-chip memory, that is, the current set of input cache is the input cache for the current cache operation, and the historical set of input cache mentioned below is the cache that has been executed The operation's input buffer, that is, the moment it reads the input image data, is before the current set of input buffers.

S120, while the current group of input caches obtains the current part of the input image data from the off-chip memory, use the data in the intermediate cache to compare the input images obtained from the off-chip memories by the historical group input caches in the multiple groups of input caches. The historical partial data undergoes affine transformation and interpolation calculations to obtain partial processing results of the target output image from the required perspective.

More specifically, when multiple groups of input buffers are switched to the current group of input buffers in turn and partial data of the input image is obtained from the off-chip memory, the partial data of the input image obtained by the historical group input buffer from the off-chip memory is simulated. Through radial transformation and interpolation calculation, a partial processing result of the target output image of the required viewing angle is obtained, until all or complete processing results of the target output image are obtained. At this time, since the interpolation calculation process and the image caching process are performed in parallel, the calculation speed of the image affine transformation is greatly improved.

Figure 3 is a schematic diagram of the mapping relationship between the input image and the target output image of the required field of view under affine transformation. As shown in Figure 3, if the target output image is a rectangular image, since the parallel lines remain parallel under affine transformation, the target output image is mapped to a parallelogram-shaped mapping image on the input image. In some embodiments, the coordinates of the four vertices of the target output image in the input image are calculated based on the affine transformation principle, thereby obtaining the mapping image of the target output image in the input image based on the vertex coordinates; in some other embodiments, The sub-pixel accuracy coordinates of the four vertices of the target output image in the input image can be calculated based on the resolution of the target output image and through the affine transformation principle, and then all pixels of the output image can be obtained through interpolation calculations. It should be noted that this application can preferably use sub-pixel precision coordinates to obtain a high-resolution output image.

In view of this, in one embodiment, step S120 is more specifically shown in FIG. 4 and may include steps S121 to S123.

S121. Based on the target output image from the required perspective and the affine transformation principle, obtain the mapping image of the target output image in the input image.

In one embodiment, affine transformation is a special case of projective transformation, and its formula is:

Among them, (x ₀ , y ₀ ) and (x ₁ , y ₁ ) represent the coordinates of the same point in images taken at two different viewing angles, and A ₁₁ to A ₂₃ are the parameters of the transformation matrix, that is, characterizing the input image and Transformation of the target output image, and based on this formula, the target output image can be transformed into the same coordinate system as the input image, and the mapping image of the target output image in the input image can be obtained.

S122. Define one side of any vertex in the mapping image as the primary side and the other side as the secondary side. Calculate the number of points and the coordinates of each point on the primary side and secondary side of the mapping image according to the resolution of the target output image.

In one embodiment, assume that the first vertex is any vertex of the mapped image. As shown in Figure 5, the first vertex is the main vertex of the mapped image, the main edge is the left side of the main vertex on the mapped image, and the right side of the main vertex is the secondary vertex. side. It should be noted that the main vertex can preferably be the highest point in the mapping image to facilitate subsequent calculations.

Further, in one embodiment, according to the resolution of the target output image and the sub-pixel precision coordinates of the vertices of the mapped image in the input image, starting from the main vertex along the main edge and the secondary edge of the mapped image to the other two sides of the mapped image. Calculate the number of points and coordinates of the primary and secondary edges respectively when moving forward each vertex, and use the number and coordinates of the primary and secondary edges to determine the forward step length during interpolation calculation. The position reached by each step length corresponds to a point in the output image. pixels. Therefore, there is a step length for each step along the primary edge and secondary edge of the mapped image. The step length on the primary edge is called the primary edge step length, and the step length on the secondary edge is called the secondary edge step length. Each step length has a It is directional, such as moving toward the lower left or toward the lower right as shown in the arrow arrangement path in Figure 5.

S123: Interpolate the historical partial data according to the coordinates of each point on the primary edge and the secondary edge to generate a partial processing result of the target output image.

In some embodiments, step S123 may include, based on the coordinates of each point on the primary edge spaced by the primary edge step, taking each point on the primary edge as the starting point, along the secondary edge direction parallel to the mapping image and with the secondary edge step. Go forward, perform interpolation calculations on each point that arrives and belongs to the historical part of the data to obtain the pixel value of each point, and generate a partial processing result of the target output image; for each point that arrives and does not belong to the historical part of the data, the relevant information of these points Write to the intermediate cache. When the current part of the data obtained by the current group of input caches includes these points, the data can be read directly from the intermediate cache to perform interpolation calculations on these points to generate the pixel values of each point to obtain partial processing of the output image. result.

More specifically, as shown in Figure 6, the parallelogram ABDC is the mapping image of the target output image in the input image, point C is the main vertex of the mapping image, CA is the main side of the mapping image, and CD is the secondary side of the mapping image. Calculate the points and coordinates of the primary edge CA and secondary edge CD of the mapped image according to the resolution of the target output image to obtain the primary edge step length and secondary edge step length, and then start from each point of the primary edge along the direction of the secondary edge in steps of the secondary edge Long forward (shown as the arrow path in Figure 6) interpolation calculates the pixel value of each point. When multiple groups of input caches perform ping-pong operations to read partial data of the input image in turn, it is assumed that the historical partial data covered by the mapped image at the top of the input image is stored in the historical group input cache, and the current partial data covered by the mapped image in the middle of the input image is stored to the current group input cache.

When the current group input cache reads the part of the input image that is covered by the mapped image, the computing unit reads the mapped image data from the historical group input cache, with point C as the main vertex, and each main edge step on the main edge CA. point is the starting point, proceed with the secondary side step length along the direction of the secondary side CD (i.e., the direction of the arrow shown in Figure 6), and perform operations on each point reached and belonging to the historical part of the data (the solid line of the arrow shown in Figure 6) The interpolation calculation obtains the pixel value of each point and generates partial processing results of the output image; for each point that arrives and does not belong to the historical part of the data (the dotted line of the arrow as shown in Figure 6), the relevant information of these points is written to the intermediate cache , when the current part of the data obtained by the current group of input caches includes these points, the data can be directly read from the intermediate cache, interpolation calculations are performed on these points to generate the pixel values of each point, and partial processing results of the output image are obtained.

In another embodiment, since the resolution of the target output image of the required field of view is limited by the output cache, there may be an actual required resolution of the target output image that is greater than the standard output image resolution preset by the output cache. Case. Therefore, before executing step S121, step S1201 is also included: determine the relationship between the resolution of the target output image and the resolution of the standard output image in the output buffer, and adaptively select whether to replace the target output image with the standard output image based on the judgment result. subsequent calculations. Preferably, it can be divided into three situations:

(1) First situation: If the resolution of the target output image is equal to the standard output image resolution in the output cache, directly execute the aforementioned steps S121, S122 and S123;

(2) The second case: If the resolution of the target output image is smaller than the resolution of the standard output image in the output cache, the resolution of the standard output image is still calculated, and the target is specified in the standard output image stored in the output cache. The area where the output image is located is used, and the standard output image is used to replace the aforementioned target output image and the aforementioned steps S121, S122 and S123 are continued.

In one embodiment, the upper left corner of the standard output image is designated as the target output image. After the chip calculates the final processing result, all or complete processing results of the standard output image are obtained, which can be stored from the output cache according to the specified area. Only the upper left corner part of the complete processing result is read, thereby writing the target output image to the corresponding address specified by an off-chip memory such as DDR.

(3) Third scenario: If the resolution of the target output image is greater than the resolution of the standard output image in the output buffer, step S120 may include: step S221 and step S222.

S221, determine that the resolution of the target output image is greater than the standard output image resolution, and divide the target output image into several output image blocks; wherein the resolution of each output image block is less than or equal to the standard output image resolution.

In one embodiment, step S222 may include one or more of the following two sub-scenarios.

(1) First sub-scenario: If the resolution of the output image block is equal to the standard output image resolution, use the output image block to replace the target output image in the aforementioned steps S121, S122 and S123 and continue to perform the aforementioned steps. Again.

(2) The second sub-case: If the resolution of the output image block is smaller than the resolution of the standard output image, the calculation is still based on the standard output image resolution, and the area where the output image block is located is specified in the standard output image output by the output cache. And use the standard output image to replace the aforementioned target output image and continue to execute the aforementioned steps S121, S122 and S123. It should be noted that the second sub-scenario can be analogous to the aforementioned second scenario.

S130: Write the historical partial processing results into the output cache and simultaneously perform affine transformation and interpolation calculations on the current partial data to obtain the complete processing results of the target output image.

After all the complete processing results of the target output image have been written into the output cache, the complete processing results of the output image are read from the output cache and written to the address specified in the off-chip memory.

As mentioned above, the embodiment of the present application provides an image affine transformation method based on a digital chip, which can cache the local image content stored in the DDR through several dedicated small-capacity SRAMs, and calculate the affine transformation method through interpolation. The interpolation calculation process is carried out in parallel with the image caching process, thus greatly improving the calculation speed of image affine transformation.

It should be understood that the sequence number of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

FIG. 7 is an architectural schematic diagram of another chip provided on the basis of FIG. 1 of the present application. Please refer to the foregoing content for details not described in the chip embodiment.

In some embodiments, the multiple sets of input caches 231 include at least a first set of input caches and a second set of input caches, and the chip further includes a scheduling module 235 for scheduling the first set of input caches and the second set of input caches in the multiple sets of input caches 231 . The group input cache is switched to the current group input cache in turn to read the image data of the input image and schedule the intermediate cache to read the parameter data of the input image. That is, when the current group input cache and the intermediate cache read the current part of the input image data, the history The group input cache and the intermediate cache have completed the steps of reading the historical partial data of the input image and are ready to transmit the data to the calculation module 232; the calculation module 232 is used to use the parameter data in the intermediate cache to calculate the history in the multiple sets of input cache 231. The group input buffer performs interpolation calculation on the historical partial data of the input image obtained from the off-chip memory 23A to obtain partial processing results of the output image. Among them, the scheduling module 235 and the calculation module 232 operate in parallel.

In some embodiments, continuing to refer to FIG. 6 , the scheduling module 235 includes a sending read data request sub-module 2351 and a receiving data sub-module 2352.

In one embodiment, the read data request sub-module 2351 is sent to determine the remaining amount of data in the input image that has not been read. If the remaining data amount is 0, after the current group of input cache reads is completed, multiple groups of The input caches 231 are all marked as unavailable; if the remaining data amount is not 0, then the available space of the current group of input caches is determined. If the available space can accommodate the preset length data amount, a read data request is sent; if the available space cannot To accommodate the amount of data of the preset length, the current group input buffer is switched.

The receiving data submodule 2352 is used to receive the current partial data of the input image sent by the off-chip memory in response to the read data request, and write the image data and parameter data of the current partial data into the current group input cache and the intermediate cache 234 respectively.

In some embodiments, the calculation module 232 includes a get main edge sub-module 2321 and an interpolation and write sub-module 2322, which are executed in series.

Among them, the main edge acquisition submodule 2321 is used to obtain the mapping image of the target output image in the input image based on the target output image and the affine transformation principle; and define one side of any vertex in the mapping image as the main edge, and the other side For the secondary side, use the resolution of the target output image to calculate the number of points and the coordinates of each point on the primary and secondary sides of the mapped image, and write the number of points and coordinates of each point on the primary and secondary sides of the mapped image into the intermediate cache 234 .

The interpolation and writing sub-module 2322 is used to read the number of points and the coordinates of each point on the primary and secondary sides of the mapped image from the intermediate cache 234, perform interpolation calculations on the historical partial data, generate partial processing results of the output image, and write the partial processing results. Input and output buffer 233.

An embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps in the foregoing method embodiments can be implemented.

An embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device can implement each step in the foregoing method embodiment.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not detailed or documented in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. Computer-readable media may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, mobile hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), RAM, electronic Carrier signals, telecommunications signals, and software distribution media, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include Electrical carrier signals and telecommunications signals.

The above embodiments are only used to illustrate the technical solutions of the present application, but are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments. Modifications are made to the recorded technical solutions, or equivalent substitutions are made to some of the technical features; these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and shall be included in this application. within the scope of protection.

Claims (11)

A chip-based image affine transformation method, characterized in that the chip includes multiple sets of input caches, intermediate caches, computing units and output caches, wherein the image affine transformation method includes: Triggering the current group of input buffers and intermediate buffers in the multiple groups of input buffers to read the current part of the image data of the input image and the parameter data required for calculation from the off-chip memory, and write them into the current group of input buffers and all the input buffers respectively. The intermediate cache; the parameter data includes the target output image of the required viewing angle and the corresponding resolution; While reading the current partial image data of the input image, the computing unit is actuated to use the parameter data to perform a calculation on the historical partial image data of the input image obtained by the historical group input cache in the multiple groups of input buffers. Affine transformation and interpolation calculations are performed to obtain the historical partial processing results of the target output image; wherein the time when the historical group input cache reads data is before the current group input cache; The historical partial processing results are written into the output cache and at the same time, affine transformation and interpolation calculations are performed on the current partial data to obtain the complete processing results of the target output image. The method of claim 1, wherein the actuation calculation unit uses the parameter data to affine the historical partial image data of the input image obtained by the historical group input buffer in the multiple groups of input buffers. Transformation and interpolation calculations are performed to obtain the historical partial processing results of the target output image; including: Based on the target output image of the required perspective and the principle of affine transformation, obtain the mapping image of the target output image in the input image; Define the edge where any vertex in the mapping image is located as a primary edge and a secondary edge respectively, and calculate the number of points and the coordinates of each point on the primary edge and secondary edge of the mapping image according to the resolution of the target output image; Interpolation calculation is performed on the historical partial image data based on the coordinates of each point on the primary edge and the secondary edge to obtain the historical partial processing result of the target output image. The method according to claim 2, characterized in that, based on the target output image of the required perspective and the principle of affine transformation, obtaining the mapping image of the target output image in the input image includes: The coordinates of the four vertices of the target output image mapped to the input image are calculated based on the affine transformation principle, thereby obtaining the mapping image of the target output image in the input image based on the vertex coordinates. The method according to any one of claims 1 to 3, characterized in that the actuation calculation unit uses the parameter data to buffer the historical part of the input image acquired by the historical group in the plurality of input buffers. The image data undergoes affine transformation and interpolation calculations to obtain the historical partial processing results of the target output image, including: Determine the relationship between the resolution of the target output image and the standard output image resolution in the output cache, and adaptively select whether to replace the target output image with the standard output image according to the judgment result before performing subsequent calculations. The method according to claim 2 or 3, characterized in that after obtaining the number of points and the coordinates of each point on the main and secondary sides of the mapping image, it further includes: The points and coordinates of the primary and secondary edges are used to determine the forward step length during the interpolation calculation, where the position reached by each step corresponds to a pixel of the target output image; wherein, the step length on the primary edge is the step size of the primary side, and the step size on the secondary side is the step size of the secondary side. The method of claim 5, wherein the historical partial image data is interpolated based on the coordinates of each point on the primary edge and the secondary edge to obtain the historical partial processing result of the target output image, include: According to the coordinates of each point on the main edge spaced by the main edge step, taking each point on the main edge as a starting point, along the direction of the secondary edge parallel to the mapping image and with the secondary edge Step forward, perform the interpolation calculation on each point that reaches and belongs to the historical partial data to obtain the pixel value of each point, and generate a partial processing result of the target output image; For each point that arrives but does not belong to the historical partial data, the relevant information of each point is written into the intermediate cache. When the current partial data obtained by the current group input cache includes the points, Each point can be read from the intermediate cache and interpolated to calculate the pixel value of each point to obtain the current partial processing result of the target output image. A chip is characterized by including: Multiple sets of input buffers are used to read part of the image data of the input image from the off-chip memory in turn; An intermediate cache, configured to read part of the parameter data of the input image from the off-chip memory according to the timing of reading data from the multiple sets of input caches; wherein the parameter data includes the target output image of the required field of view and Corresponding resolution; A calculation module configured to use the parameter data to calculate the current partial data of the input image from the off-chip memory while the current group of input buffers in the multiple groups of input buffers obtains the current partial data of the input image from the off-chip memory. The historical group input cache performs interpolation calculation on the historical partial data of the input image obtained from the off-chip memory to obtain partial processing results of the output image; wherein, the time when the historical group input cache reads the data is located The current group is input before caching; The output cache is used to store partial processing results of the output image. The chip of claim 7, further comprising a scheduling module for scheduling each group of input buffers in multiple groups of input buffers to switch to the current group of input buffers in turn to read the image data of the input image and schedule the The intermediate cache reads the parameter data of the input image; wherein the scheduling module and the computing module operate in parallel. The chip according to claim 8, characterized in that the scheduling module includes a sending read data request sub-module and a receiving data sub-module, The sending read data request sub-module is used to determine the amount of remaining data that has not been read in the input image. If the amount of remaining data is 0, after the current group of input cache reads is completed, the multiple groups of input The caches are all marked as unavailable; if the remaining data amount is not 0, determine the available space of the current group input cache, and if the available space can accommodate the preset length data amount, send a read data request; if the available space cannot To accommodate the preset length of data, switch the current group input buffer; The receiving data submodule is configured to receive the current partial data of the input image sent by the off-chip memory in response to the read data request, and write the current partial data into the current group input cache. The chip according to any one of claims 7 to 9, characterized in that the calculation module includes a main edge acquisition sub-module and an interpolation and writing sub-module, and the main edge acquisition sub-module and the interpolation and writing sub-module are Submodules operate in series; The main edge acquisition submodule is used to obtain the mapping image of the target output image in the input image based on the target output image and the affine transformation principle; and define the side where any vertex in the mapping image is located as the main edge, and the other side. One side is the secondary side, use the resolution of the target output image to calculate the number of points and the coordinates of each point on the primary and secondary sides of the mapping image, and write the number of points and coordinates of each point on the primary and secondary sides of the mapping image into the middle cache; The interpolation and writing sub-module is used to read the number of points and the coordinates of each point on the primary and secondary sides of the mapping image from the intermediate cache, perform interpolation calculations on the historical partial data, generate partial processing results of the output image, and The partial processing results are written into the output cache. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, characterized in that, when the computer program is executed by a processor, the method of any one of claims 1 to 6 is implemented. Graph affine transformation method.

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