WO2023240491A1

WO2023240491A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2023240491A1
Application number: PCT/CN2022/098966
Authority: WO
Inventors: Keping Wu; Qiyue Zhao; Xiao Zhang; Tinglin YOU; Xiaoqi Li
Original assignee: Innoscience Suzhou Semiconductor Co Ltd
Current assignee: Innoscience Suzhou Semiconductor Co Ltd
Priority date: 2022-06-15
Filing date: 2022-06-15
Publication date: 2023-12-21
Anticipated expiration: 2024-12-15
Also published as: CN117916866A

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, a passivation layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The first electrode and the second electrode are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and between the first and second electrodes. The passivation layer covers the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode. The field plate is disposed over the second nitride-based semiconductor layer. The field plate is free from overlapping with the gate electrode along a vertical direction.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Keping WU, Qiyue ZHAO, Xiao ZHANG, Tinglin YOU, and Xiaoqi LI

Field of the Invention:

The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a high electron mobility transistor (HEMT) semiconductor device having multi field plates over a gate electrode thereof for improving the performance thereof.

Background of the Invention:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. The HEMT utilizes a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) . At present, there is a need to improve the yield rate for HMET devices, thereby making them suitable for mass production.

Summary of the Invention:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, a passivation layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The first electrode and the second electrode are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and between the first and second electrodes. The passivation layer covers the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode. The field plate is disposed over the second nitride-based semiconductor layer and located between the gate electrode and the first electrode. The field plate abuts against a sidewall of the projection portion of the passivation layer and is free from overlapping with the gate electrode along a vertical direction.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A gate electrode is formed over the second nitride-based semiconductor layer. A first passivation layer is formed to cover the gate electrode. A conductive layer is formed on the first passivation layer. A second passivation layer is formed on the conductive layer. A first etching process is performed to thin down the second passivation layer so as to expose a portion of the conductive layer which is located above the gate electrode. A second etching process is performed to remove the exposed portion of the conductive layer so as to expose the first passivation layer. The conductive layer is patterned after performing the first etching process.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, a passivation layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The first electrode and the second electrode are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and between the first and second electrodes. The passivation layer covers the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode. The field plate is disposed over the second nitride-based semiconductor layer and located between the gate electrode and the first electrode. The field plate laterally extends to have an uniform thickness.

By applying the above configuration, the field plate is free from overlapping with the gate electrode so the field plate has no portion directly above or over the gate electrode. The reason for such the configuration is to reduce parasitic capacitance between the field plate and the gate electrode. Such the configuration is advantageous to formation of the field plate by applying a self-alignment process.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a cross-sectional view of the semiconductor device 1A according to some embodiments of the present disclosure;

FIG. 1B is an enlarged view of a zone 1B in FIG. 1A according to some embodiments of the present disclosure;

FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I illustrate different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 6 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a cross-sectional view of the semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A is a dual-gate device. The semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 14 and 16,

electrodes

20, 22, 24, doped nitride-based semiconductor layers 30, 40,

gate electrodes

32, 42, passivation layers 50, 52, 70, 76,

field plates

60, 62, contact vias 72, 78, patterned

conductive layers

74, 80, and a protection layer 82.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable semiconductor materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the bidirectional switching device 1A may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated) . The buffer layer can be disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. The nucleation layer may be formed between the substrate 10 and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III- nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 14 is disposed over the substrate 10. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1. The nitride-based semiconductor layer 16 is disposed on the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The doped nitride-based semiconductor layer 30 and the gate electrode 32 are stacked on the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 30 are between the nitride-based semiconductor layer 16 and the gate electrode 32. In some embodiments, the gate electrode 32 is narrower than the doped nitride-based semiconductor layer 30.

The doped nitride-based semiconductor layer 40 and the gate electrode 42 are stacked on the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 40 are between the nitride-based semiconductor layer 16 and the gate electrode 42. In some embodiments, the gate electrode 42 is narrower than the doped nitride-based semiconductor layer 40.

In the exemplary illustration of FIG. 1A, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the

gate electrodes

32 and 42 are at approximately zero bias. Specifically, the doped nitride-based semiconductor layers 30 and 40 may create at least one p-n junction with the nitride-based semiconductor layer 16 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure 110 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the semiconductor device 100A has a normally-off characteristic. In other words, when no voltage is applied to the

gate electrodes

32 and 42 or a voltage applied to the

gate electrode

32 and 42 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrodes 32 and 42) , the zone of the 2DEG region below the

gate electrodes

32 and 42 is kept blocked, and thus no current flows therethrough. Moreover, by providing the doped nitride-based semiconductor layers 30 and 40, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.

In some embodiments, the doped nitride-based semiconductor layers 30 and 40 can be omitted, such that the semiconductor device 1A is a depletion-mode device, which means the semiconductor device 1A in a normally-on state at zero gate-source voltage.

The exemplary materials of the doped nitride-based semiconductor layers 30 and 40 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.

In some embodiments, the

gate electrodes

32 and 42 may include metals or metal compounds. The

gate electrodes

32 and 42 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the

gate electrodes

32 and 42 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

The

electrodes

20, 22, 24 are disposed on the nitride-based semiconductor layer 16. Each of the

electrodes

20, 22, 24 can serve as a source electrode or a drain electrode. In some embodiments, each of the

electrodes

20, 22, 24 can be called a source/drain (S/D) electrode, which means they can serve as a source electrode or a drain electrode, depending on the device design.

The

electrodes

20 and 22 can be located at two opposite sides of the gate electrode 32. The doped nitride-based semiconductor layers 30 and the gate electrode 32 are located between the

electrodes

20 and 22. The

electrodes

22 and 24 can be located at two opposite sides of the gate electrode 42. The doped nitride-based semiconductor layers 40 and the gate electrode 42 are located between the

electrodes

22 and 24.

The

electrodes

20, 22, 24 and the

gate electrodes

32 and 42 can collectively act as at least one nitride-based/GaN-based dual-gate HEMT with the 2DEG region, which can be called a nitride-based/GaN-based dual-gate semiconductor device. In the exemplary illustration of FIG. 1A, the

electrodes

20, 22, 24 are symmetrical about the

gate electrode

32 or 42 therebetween. In some embodiments, the

electrodes

20, 22, 24 can be optionally asymmetrical about the

gate electrode

32 or 42 therebetween.

In some embodiments, the

electrodes

20, 22, 24 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20, 22, 24 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20, 22, 24 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

20, 22, 24 form ohmic contact with the nitride-based semiconductor layer 16. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20, 22, 24. In some embodiments, each of the

electrodes

20, 22, 24 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The passivation layer 50 is disposed over the nitride-based semiconductor layer 16. The passivation layer 50 covers the doped nitride-based semiconductor layers 30, 40 and the

gate electrodes

32 and 42. The passivation layer 50 can form projection portions conformal with profiles of the doped nitride-based semiconductor layers 30, 40 and the

gate electrodes

32 and 42. The projection portions of the passivation layer 50 align with the

gate electrodes

32 and 42, respectively.

The passivation layer 52 is disposed over the passivation layer 50. The passivation layer 52 covers the passivation layer 50. The passivation layer 52 can form projection portions conformal with profiles of the passivation layer 50. The

electrodes

20, 22, 24 can penetrate the passivation layers 50 and 52 to make contact with the nitride-based semiconductor layer 16.

The exemplary materials of the passivation layers 50 and 52 can include, for example but are not limited to, SiNx, SiOx, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof. In some embodiments, the passivation layers 50 or 52 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The passivation layer 70 is disposed above the

electrodes

20, 22, 24 and the passivation layer 52. The passivation layer 70 covers the

electrodes

20, 22, 24 and the passivation layer 52. The passivation layer 70 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer 70 can be formed as being thicker, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 70 to remove the excess portions, thereby forming a level top surface. The exemplary materials of the passivation layer 70 can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof. In some embodiments, the passivation layer 70 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The

field plates

60 and 62 are disposed over the nitride-based semiconductor layer 16 and the passivation layer 50. The

field plates

60 and 62 are located between the passivation layers 50 and 52.

FIG. 1B is an enlarged view of a zone 1B in FIG. 1A according to some embodiments of the present disclosure. The configuration among the field plate 60, the doped nitride-based semiconductor layer 30, the gate electrode 32, and the passivation layers 50 and 52 can be applied to the configuration with respect to the field plate 62 as well.

The field plate 60 abuts against a sidewall of the projection portion of the passivation layer 50. The field plate 60 is adjacent to the gate electrodes32 and is free from overlapping with the gate electrode 32 along a vertical direction. Herein, the phrase “the field plate 60 free from overlapping with the gate electrode 32” means the field plate 60 has no portion directly above or over the gate electrode 32. The reason for such the configuration is to reduce parasitic capacitance between the field plate 60 and the gate electrode 32. Specifically, the field plate 60 has an end portion 602 (e.g., a top-most end portion) over the gate electrode 32 and beneath a top surface of the projection portion of the passivation layer 50. Correspondingly, the field plate 60 has a L-shaped profile. Such the configuration is advantageous to formation of the field plate 60 by applying a self-alignment process.

The field plate 60 is in a position higher than the doped nitride-based semiconductor layer 30. The field plate 60 at least vertically overlaps with the doped nitride-based semiconductor layer 30. As such, the field plate 60 can still modulate electric field distribution near the edge side of the doped nitride-based semiconductor layer 30 and the gate electrode 32.

The field plate 60 is thinner than the gate electrode 32, which will be advantageous to form the field plate 60 by a self-alignment process. The field plate 60 can have one longitudinal extending portion and one lateral extending portion which is connected to the longitudinal extending portion so that an entirety of the field plate 60 is in a L-shaped profile. The field plate 60 with L-shaped profile is to make field plate 60 can be formed through facilitating the self-alignment process.

The exemplary materials of the field plate 60 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.

Referring back to FIG. 1A, the contact vias 72 are disposed within the passivation layer 70. The contact vias 72 penetrate the passivation layer 70. The contact vias 72 extend longitudinally to electrically couple with the

electrodes

20, 22, 24, respectively. The upper surfaces of the contact vias 72 are free from coverage of the passivation layer 70. The exemplary materials of the contact vias 72 can include, for example but are not limited to, conductive materials, such as metals or alloys.

A patterned conductive layer 74 is disposed on the passivation layer 70 and the contact vias 72. The patterned conductive layer 74 is in contact with the contact vias 72. The patterned conductive layer 74 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 74 can form at least one circuit. The exemplary materials of the patterned conductive layer 74 can include, for example but are not limited to, conductive materials. The patterned conductive layer 74 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The passivation layer 76 is disposed above the passivation layer 70 and the patterned conductive layer 74. The passivation layer 76 covers the passivation layer 70 and the patterned conductive layer 74. The exemplary materials of the passivation layer 76 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof. In some embodiments, the passivation layer 76 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The contact vias 78 are disposed within the passivation layer 76. The contact vias 78 penetrate the passivation layer 76. The contact vias 78 extend longitudinally to electrically couple with the patterned conductive layer 74. The upper surfaces of the contact vias 78 are free from coverage of the passivation layer 76. The exemplary materials of the contact vias 78 can include, for example, but are not limited to, conductive materials, such as metals or alloys.

A patterned conductive layer 80 is disposed on the passivation layer 76 and the contact vias 78. The patterned conductive layer 80 is in contact with the contact vias 78. The patterned conductive layer 80 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 80 can form at least one circuit. The exemplary materials of the patterned conductive layer 80 can include, for example but are not limited to, conductive materials. The patterned conductive layer 80 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The circuit of the patterned

conductive layer

74 or 80 can connect different layers/elements, making these layers or elements have the same electrical potential.

The protection layer 82 is disposed above the passivation layer 76 and the patterned conductive layer 80. The protection layer 82 covers the passivation layer 76 and the patterned conductive layer 80. The protection layer 82 can prevent the patterned conductive layer 80 from oxidizing. Some portions of the patterned conductive layer 80 can be exposed through openings in the protection layer 82, which are configured to electrically connect to external elements (e.g., an external circuit) .

Different stages of a method for manufacturing the semiconductor device 100A are shown in FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. Nitride-based semiconductor layers 14 and 16 can be formed over the substrate 10 in sequence by using the above-mentioned deposition techniques. A doped nitride-based semiconductor layer 30 and a gate electrode 32 can be formed and patterned over the nitride-based semiconductor layer 14. A doped nitride-based semiconductor layer 40 and a gate electrode 42 can be formed and patterned over the nitride-based semiconductor layer 14. A passivation layer can be formed over the nitride-based semiconductor layer 14 to cover the doped nitride-based semiconductor layer 30 and the gate electrode 32. The passivation layer can be formed over the nitride-based semiconductor layer 14 to cover the doped nitride-based semiconductor layer 40 and the gate electrode 42. A conductive layer 84 can be formed on the passivation layer 50.

Referring to FIG. 2B, a passivation layer 86 can be formed on the conductive layer 84. The passivation layer 86 is in contact with conductive layer 84. The conductive layer 84 is entirely covered by the passivation layer 86. The passivation layer 86 is conformal with the conductive layer 84 and thus has projections.

Referring to FIG. 2C, an etching process is performed to thin down the passivation layer 86. In the exemplary illustration of FIG. 2C, the thinning down includes make the passivation layer 86 have flat top surface.

Referring to FIG. 2D, the etching process is still performed to thin down the passivation layer 86 until a portion of the conductive layer 84 which is located above the gate electrode is exposed. In some embodiments, the etching process is performed for exposing the conductive layer 84 from the passivation layer 86. In some embodiments, the conductive layer 84 and the passivation layer 86 have different etching rates with respect to the same etchant used in the etching process. The etching rate of the conductive layer 84 can be less than the etching rate of the passivation layer 86 in the etching process as mentioned with respect to FIGS. 2C and 2D. In some embodiments, during the etching stage with respect to FIGS. 2C and 2D, the etching process has a high etching selectivity between the conductive layer 84 and the passivation layer 86.

In some embodiments, the etching stage with respect to FIGS. 2C and 2D is applied/performed by using an etching back process. Since the removal of the conductive layer 84 can be performed by the etching back process which results from the high etching selectivity, such the etching stage serve as a self-alignment process.

Referring to FIG. 2E, another etching process is performed. Herein, “another etching process” means the etching process in this stage may apply a different etchant as the previous one. In this etching stage, the conductive layer 84 and the passivation layer 86 have different etching rates with respect to the same etchant as well. The etching rate of the conductive layer 84 can be greater than the etching rate of the passivation layer 86 in this etching stage. Accordingly, during the etching process, the exposed portions of the conductive layer 84 are removed and then the passivation layer 50 is exposed from the conductive layer 84 and the passivation layer 86. In some embodiments, after the etching process, the conductive layer 84 is in a position lower than the passivation 50. After the etching stage with respect to FIG. 2E, the conductive layer can be divided into a plurality of sub-conductive layers. That is, the conductive layer 84 can become discontinuous from a continuous profile.

Referring to FIG. 2F, the passivation layer 86 is removed. Then, a mask layer 88 is formed over the conductive layer 84 and the passivation layer 50. Some portions of the conductive layer 84 are exposed from the mask layer 88. The mask layer 88 can define the profile of the conductive layer 84 in a subsequent etching process.

Referring to FIG. 2G, the conductive layer 84 is patterned so

field plates

60 and 62 are formed. Profiles of the

field plates

60 and 62 are defined by the mask layer 88. The profiles of the

field plates

60 and 62 can be defined as being L-shaped. In some embodiments, the patterning the conductive layer 84 may be performed by using an etching process.

Referring to FIG. 2H, the mask layer 88 is removed so the

field plates

60 and 62 are free from coverage. Each of the

field plates

60 and 62 has a L-shaped profile.

Referring to FIG. 2I,

electrodes

20, 22, and 24 and

passivation layer

52 and 70 are formed. Accordingly, a self-alignment process for field plates is achieved. Such the self-alignment process can be applied for obtaining desired profiles of field plates.

FIG. 3 is a cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the field plate 60 is replaced by a field plate 60B.

The field plate 60B plate has a left end portion 602B in a position higher than the gate electrode 32. The left end portion 602B of the field plate 60B is adjacent to the projection portion of the passivation layer 50. The left end portion 602B of the field plate 60B is in contact with the projection portion of the passivation layer 50. The left end portion 602B of the field plate 60B has a curved end surface facing upward. The curved end surface of the field plate 60B can receive a portion of the passivation layer 52. The curved end surface of the field plate 60B can distribute the stress from the portion of the passivation layer 52 well so as to avoid void or crack therebetween. The curved end surface of the field plate 60B can be formed by tuning recipes in the etching stage.

FIG. 4 is a cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the field plate 60 is replaced by a field plate 60C.

An entirety of the field plate 60C is in within a thickness of the gate electrode. More specifically,

opposite end portions

602C and 604C of the field plate 60C are located beneath top surfaces of the gate electrode 32 and the projection portion of the passivation layer 50. The left end portion 602C of the field plate 60C is in contact with the projection portion of the passivation layer 50. The left end portion 602C of the field plate 60C abuts against the projection portion of the passivation layer 50. The right end portion 604C of the field plate 60C is covered by the passivation layer 52. An entirety of the field plate 60C is in a linear shaped profile. In some embodiments, the field plate 60C laterally extends to have an uniform thickness. As such, parasitic capacitance between the gate electrode 32 and the field plate 60C can be further reduce.

FIG. 5 is a cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1C as described and illustrated with reference to FIG. 4, except that the field plate 60C is replaced by a field plate 60D.

The field plate 60D plate has a left end portion 602D. The left end portion 602D of the field plate 60D is in contact with the projection portion of the passivation layer 50. The left end portion 602D of the field plate 60D abuts against the projection portion of the passivation layer 50. The left end portion 602D of the field plate 60C has a recessed region R adjacent with the projection portion of the passivation layer 50. The recessed region R of the field plate 60D can receive a portion of the passivation layer 52. The recessed region R of the field plate 60D can distribute the stress from the portion of the passivation layer 52 well so as to avoid void or crack therebetween. The recessed region R of the field plate 60B can be formed by tuning recipes in the etching stage.

FIG. 6 is a cross-sectional view of a semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the semiconductor device 1 as described and illustrated with reference to FIGS. 1A and 1B, except that the field plate 60 is replaced by a field plate 60E.

The field plate 60E plate has a left end portion 602E. The left end portion 602E of the field plate 60E is located over the gate electrode 32 and the projection portion of the passivation layer 50. The left end portion 602E of the field plate 60E laterally extends along a distance but still keeps free from vertically overlapping with the gate electrode 32.

The embodiments show that the self-alignment process applied to formation of field plates is flexible, which means various profiles of field plates can be achieved, so as to satisfy different device requirements.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a first electrode and a second electrode disposed over the second nitride-based semiconductor layer;

a gate electrode disposed over the second nitride-based semiconductor layer and between the first and second electrodes;

a passivation layer covering the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode; and

a field plate disposed over the second nitride-based semiconductor layer and located between the gate electrode and the first electrode, wherein the field plate abuts against a sidewall of the projection portion of the passivation layer and is free from overlapping with the gate electrode along a vertical direction.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate has an end portion over the gate electrode and the projection portion of the passivation layer.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate has an end portion over the gate electrode and beneath a top surface of the projection portion of the passivation layer.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate has an end portion beneath top surfaces of the gate electrode and the projection portion of the passivation layer, and the end portion is in contact with the projection portion of the passivation layer.
The nitride-based semiconductor device according to any one of the proceeding claims wherein the field plate has a L-shaped profile.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein an entirety of the field plate is in a L-shaped profile.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate has an end portion in contact with the projection portion of the passivation layer and having a curved end surface.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein an entirety of the field plate is in a linear shaped profile.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate has a top surface which has a recessed region adjacent with the projection portion of the passivation layer.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate is thinner than the gate electrode.
The nitride-based semiconductor device of any one of the proceeding claims, wherein an entirety of the field plate is in within a thickness of the gate electrode.
The nitride-based semiconductor device of any one of the proceeding claims, further comprising a doped nitride-based semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the field plate is in a position higher than the doped nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the field plate at least vertically overlaps with the doped nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doped nitride-based semiconductor layer is wider than the gate electrode.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a gate electrode over the second nitride-based semiconductor layer;

forming a first passivation layer covering the gate electrode;

forming a conductive layer on the first passivation layer;

forming a second passivation layer on the conductive layer;

performing a first etching process to thin down the second passivation layer so as to expose a portion of the conductive layer which is located above the gate electrode;

performing a second etching process to remove the exposed portion of the conductive layer so as to expose the first passivation layer; and

patterning the conductive layer after performing the first etching process.
The method of any one of the proceeding claims, wherein the first etching process is performed by an etching back process.
The method of any one of the proceeding claims, wherein the first etching process has a high etching selectivity between the conductive layer and the second passivation layer.
The method of any one of the proceeding claims, wherein the conductive layer is divided into a plurality of sub-conductive layers after the second etching process.
The method of any one of the proceeding claims, wherein patterning the conductive layer is performed by using a third etching process.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a first electrode and a second electrode disposed over the second nitride-based semiconductor layer;

a gate electrode disposed over the second nitride-based semiconductor layer and between the first and second electrodes;

a passivation layer covering the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode; and

a field plate disposed over the second nitride-based semiconductor layer and located between the gate electrode and the first electrode, wherein the field plate laterally extends to have an uniform thickness.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein an entirety of the field plate is in a linear shaped profile.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the field plate has an end portion beneath top surfaces of the gate electrode and the projection portion of the passivation layer.
The nitride-based semiconductor device according to any one of the proceeding claims, wherein the end portion abuts against the projection portion of the passivation layer.
The nitride-based semiconductor device of any one of the proceeding claims, further comprising:

a doped nitride-based semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode, wherein the field plate is in a position higher than the doped nitride-based semiconductor layer, and the field plate vertically overlaps with the doped nitride-based semiconductor layer.