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WO2023136621A1 - Carte de circuit imprimé et son procédé de fabrication - Google Patents

Carte de circuit imprimé et son procédé de fabrication Download PDF

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Publication number
WO2023136621A1
WO2023136621A1 PCT/KR2023/000560 KR2023000560W WO2023136621A1 WO 2023136621 A1 WO2023136621 A1 WO 2023136621A1 KR 2023000560 W KR2023000560 W KR 2023000560W WO 2023136621 A1 WO2023136621 A1 WO 2023136621A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
build
recesses
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2023/000560
Other languages
English (en)
Korean (ko)
Inventor
정율교
김영헌
권종상
조형진
김병문
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KOREA CIRCUIT CO Ltd
Original Assignee
KOREA CIRCUIT CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020220179405A external-priority patent/KR102561794B1/ko
Application filed by KOREA CIRCUIT CO Ltd filed Critical KOREA CIRCUIT CO Ltd
Publication of WO2023136621A1 publication Critical patent/WO2023136621A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the embodiment relates to a printed circuit board and a manufacturing method thereof.
  • a printed circuit board is one in which circuit line patterns are formed on an electrically insulating substrate with a conductive material such as copper.
  • the printed circuit board refers to a board before a semiconductor device is mounted thereon.
  • the multi-layer printed circuit board forms a circuit pattern by sequentially stacking insulating layers and applying a semi-additive process (SAP) method or a modified semi-additive process (MSAP) method to the surface of the insulating layer. It is manufactured by At this time, the SAP method is mainly used to refine the line width of the circuit pattern.
  • SAP method refers to a method of forming a circuit pattern by forming a seed layer on the surface of an insulating layer and proceeding with electroplating based on the seed layer.
  • the thickness of the insulating layer becomes thinner, the content of the filler disposed therein increases, and it may be difficult to impart a uniform surface roughness to the surface of the insulating layer by the desmear process. Accordingly, adhesion between the insulating layer and the circuit pattern may deteriorate, and as a result, mechanical reliability and/or electrical reliability problems arise in that the circuit pattern is separated from the insulating layer.
  • Patent Document 1 KR 10-2010-0010169 A
  • a printed circuit board capable of imparting a uniform surface roughness to an upper surface of an insulating layer and a manufacturing method thereof are provided.
  • a printed circuit board capable of improving adhesion between an insulating layer and a wiring layer and a manufacturing method thereof are provided.
  • the embodiment is to provide a printed circuit board applicable to a communication system using a high frequency band and a manufacturing method thereof.
  • a printed circuit board includes a first build-up insulating layer; a first wiring layer disposed on the first build-up insulating layer; and a via layer penetrating the first buildup insulating layer and connected to the first wiring layer, wherein the first buildup insulating layer includes a resin and a plurality of pillars disposed in the resin, and the first wiring layer does not contact the plurality of pillars, and the via layer contacts at least one of the plurality of pillars.
  • first recesses are formed on an upper surface of the first build-up insulating layer.
  • the first wiring layer includes a plurality of first protrusions disposed in the plurality of first recesses, and each of a width, a thickness, and an interval of the plurality of first protrusions is a width of the plurality of first recesses; Corresponds to depth and spacing, respectively.
  • the printed circuit board further includes a second build-up insulating layer disposed on the first build-up insulating layer, and the first protrusion of the first wiring layer is disposed in a portion of the plurality of first recesses. and the second build-up insulating layer includes second protrusions disposed in remaining portions of the plurality of first recesses.
  • each of the plurality of first recesses, the thickness of each of the plurality of first projections, and the thickness of each of the plurality of second projections satisfy a range of 0.05 ⁇ m to 0.5 ⁇ m.
  • a width of each of the plurality of first recesses, the plurality of first protrusions, and the plurality of second protrusions satisfies a range of 0.05 ⁇ m to 0.5 ⁇ m.
  • a distance between each of the plurality of first recesses, the plurality of first protrusions, and the plurality of second protrusions satisfies a range of 0.05 ⁇ m to 0.5 ⁇ m.
  • the surface roughness of the side surface of the via layer is different from the surface roughness of the lower surface of the first wiring layer.
  • the printed circuit board further includes a second wiring layer disposed on a lower surface of the first build-up insulating layer, the second wiring layer includes a second recess vertically overlapping the via layer, and the via A layer is disposed within the second recess and includes an extension of increasing width.
  • a method of manufacturing a printed circuit board includes laminating a first build-up insulating layer on a first insulating layer; positioning a transfer layer including protrusions on the first build-up insulating layer; attaching the transfer layer to an upper surface of the first build-up insulating layer; and forming a plurality of first recesses corresponding to the protrusions of the transfer layer on an upper surface of the first build-up insulating layer by removing the transfer layer by etching.
  • a depth of each of the plurality of first recesses satisfies a range of 0.05 ⁇ m to 0.5 ⁇ m.
  • the manufacturing method of the printed circuit board may include forming a via hole penetrating the transfer layer and the first build-up insulating layer before removing the transfer layer by etching; forming a plating seed layer on an upper surface of the first build-up insulating layer and an inner wall of the via hole after removing the transfer layer; forming a dry film including an opening on the plating seed layer; forming an electrolytic plating layer filling the opening of the dry film and the via hole; removing the dry film; and forming a via layer disposed in the via hole and a first wiring layer disposed on the first buildup insulating layer by removing a portion of the plating seed layer that does not vertically overlap the electrolytic plating layer. do.
  • the plating seed layer is formed along the profile of the plurality of first recesses provided on the upper surface of the first build-up insulating layer, and the first wiring layer has a plurality of recesses corresponding to the plurality of first recesses. It includes a first protrusion.
  • the method of manufacturing the printed circuit board further includes forming a second wiring layer on the first insulating layer before laminating the first build-up insulating layer, and the transfer layer is formed on an upper surface of the second wiring layer.
  • a second recess is formed upon removal of the via layer, and the via layer includes an extension disposed in the second recess of the second wiring layer.
  • the method of manufacturing the printed circuit board may further include stacking a second buildup insulating layer on the first buildup insulating layer and the first wiring layer, wherein the second buildup insulating layer comprises the first buildup insulating layer. and a plurality of second protrusions contacting an upper surface of the build-up insulating layer and corresponding to the first recess of the first build-up insulating layer.
  • the first build-up insulating layer includes a resin and a plurality of pillars disposed in the resin, the first wiring layer does not contact the plurality of pillars, and the via layer has at least one of the plurality of pillars. Contact with one filler.
  • a plurality of first recesses having uniform widths, intervals, and depths are formed on the upper surface of the first build-up insulating layer.
  • the plurality of first recesses are provided on an upper surface of the first build-up insulating layer, and thus contact a lower surface of the first wiring layer and a lower surface of the second build-up insulating layer, respectively.
  • a first protrusion corresponding to the first recess is formed on a lower surface of the first wiring layer.
  • a second protrusion corresponding to the first recess is formed on a lower surface of the second build-up insulating layer.
  • the plurality of first recesses are uniformly formed on the upper surface of the first build-up insulating layer.
  • the first protrusions are uniformly formed on the lower surface of the first wiring layer.
  • the second protrusion is uniformly formed on the lower surface of the second build-up insulating layer.
  • the embodiment may improve adhesion between the first build-up insulating layer and the second build-up insulating layer.
  • the embodiment may improve adhesion between the first build-up insulating layer and the first wiring layer. Therefore, the embodiment can solve the problem that the first wiring layer and the second buildup insulating layer are separated from the first buildup insulating layer. Through this, the embodiment can improve physical reliability and electrical reliability of the printed circuit board.
  • the embodiment allows uniform first recesses to be formed on the upper surface of the first build-up insulating layer, and accordingly, the thickness of the plating seed layer formed on the upper surface of the first build-up insulating layer can be made uniform. there is.
  • the embodiment it is possible to minimize the plating deviation of the electrolytic plating layer formed on the plating seed layer, and through this, a plurality of wiring layers can have the same thickness as each other. Therefore, the embodiment can improve the electrical characteristics of the printed circuit board.
  • each of the depth of the first recess, the thickness of the first protrusion and the thickness of the second protrusion has a range of 0.05 ⁇ m to 0.5 ⁇ m. Accordingly, the embodiment can solve the problem that a part of the transfer layer used to form the first recess is not removed, and through this, electrical reliability such as an electrical short circuit can be improved.
  • surface roughness of the first wiring layer may be lowered to correspond to the thickness of the first protrusion, thereby minimizing transmission loss of a signal transmitted through the first wiring layer.
  • a second recess having a predetermined depth may be formed on the second wiring layer during etching of the transfer layer.
  • a portion of the via layer penetrating the first build-up insulating layer may be disposed in the second recess, thereby increasing the adhesion between the via layer and the first build-up insulating layer.
  • FIG. 1 is a cross-sectional view showing a manufacturing method of a printed circuit board of a comparative example in the order of steps.
  • FIG. 2 is a view for explaining the surface roughness of the build-up insulating layer of FIG. 1 .
  • FIG 3 is a cross-sectional view showing a printed circuit board according to an embodiment.
  • FIG. 4 is an enlarged view in which a partial area of FIG. 3 is enlarged.
  • FIG. 5 is a view showing a first interface and a second interface according to the first embodiment.
  • FIG. 6 is a view showing a first interface and a second interface according to a second embodiment.
  • FIG. 7 is a view showing a first interface and a second interface according to a third embodiment.
  • FIGS. 8 to 21 are diagrams showing a manufacturing method of a printed circuit board according to an embodiment in process order.
  • FIG. 1 is a cross-sectional view showing a manufacturing method of a printed circuit board of a comparative example in process order
  • FIG. 2 is a view for explaining the surface roughness of the build-up insulating layer of FIG. 1 .
  • the printed circuit board of the comparative example is a core type core board. Accordingly, the comparative example proceeds with a process of manufacturing the inner layer of the core substrate. Specifically, the comparative example includes a process of preparing the core layer 10, a process of forming a through hole penetrating the core layer 10, a process of forming a via layer 30 on the inner wall of the through hole, and a plugging ink A process of forming a filler 40 that fills the through hole while in contact with the via layer 30 using the via layer 30, and wiring layers 20 electrically connected to each other through the via layer 30 to form the core layer 10 The process of forming on the upper and lower surfaces of the
  • the comparative example proceeds with a desmear process to form a certain level on the surface 50S of the build-up insulating layer 50.
  • a process of imparting surface roughness is performed.
  • the process of imparting the surface roughness is performed to improve adhesion between the build-up insulating layer 50 and the seed metal layer.
  • the desmear process may be performed in an over-cured state or a pre-cured state of the build-up insulating layer 50 .
  • the desmear process proceeds in an overhardened state of the build-up insulating layer 50, the amount of etching of the build-up insulating layer 50 in the desmear process is reduced, whereby the build-up A surface roughness lower than a target range may be imparted to the surface of the insulating layer 50 .
  • adhesion between the buildup insulating layer 50 and the seed metal layer may decrease, and a problem in that the wiring layer including the seed metal layer may be separated from the buildup insulating layer 50 may occur.
  • the etching amount of the build-up insulating layer 50 increases in the desmear process, thereby increasing the build-up insulating layer A surface roughness exceeding a target range may be imparted to the surface of (50).
  • the surface roughness (Ra) given to the surface of the build-up insulating layer 50 in the pre-cured state is about 2 ⁇ m to 5 ⁇ m.
  • the surface roughness (Ra) given to the surface of the build-up insulating layer 50 exceeds 2 ⁇ m, a seed metal layer having a uniform thickness is formed over the entire surface of the build-up insulating layer 50. Accordingly, adhesion between the dry film formed on the seed metal layer and the seed metal layer may decrease.
  • the adhesion between the dry film and the seed metal layer is reduced, there is a limit to miniaturization of the wiring layer formed on the build-up insulating layer 50 due to a peeling problem of the dry film.
  • the surface roughness (Ra) given to the surface of the build-up insulating layer 50 exceeds 2 ⁇ m, it may be difficult to apply it to a product using a high frequency band. That is, a skin effect phenomenon in which current flows along the surface of the wiring layer occurs in a higher frequency band.
  • the transmission distance of a signal flowing along the surface increases, and as the transmission distance of the signal increases, there is a problem in that signal transmission loss increases.
  • the build-up insulating layer 50 of the comparative example is provided with a filler 50F, which is a reinforcing material for improving warpage characteristics of a printed circuit board. .
  • a filler 50F which is a reinforcing material for improving warpage characteristics of a printed circuit board.
  • Figure 2 (a) is a cross-sectional view showing the surface roughness given to the surface of the build-up insulating layer 50 of the comparative example
  • Figure 2 (b) is an electron microscope (SEM: Scanning Electron Microscope) of the build-up insulating layer of the comparative example ) is a plan view taken with
  • the desmear process of the build-up insulating layer 50 is performed using an etchant capable of selectively etching only the resin of the build-up insulating layer 50 .
  • the filler 50F provided in the build-up insulating layer 50 is not etched by the etchant. Accordingly, non-uniform surface roughness may be imparted to the surface of the build-up insulating layer 50 according to the position of the filler 50F in the build-up insulating layer 50 .
  • the surface of the build-up insulating layer 50 after the desmear process is a first portion 50S1 made of resin of the build-up insulating layer 50
  • a filler provided in the build-up insulating layer 50 50F includes an exposed second portion 50S2.
  • the surface of the build-up insulating layer 50 includes a third portion 50S3 corresponding to a space where the filler 50F provided in the build-up insulating layer 50 escapes by the desmear process. .
  • the wiring layer disposed on the second part 50S2 of the build-up insulating layer 50 contacts the pillar 50F provided in the build-up insulating layer 50 .
  • the adhesion between the wiring layer and the filler 50F is lower than the adhesion between the wiring layer and the resin of the build-up insulating layer 50, and accordingly, the wiring layer having a relatively fine pattern is the build-up insulating layer ( 50) may cause a problem of peeling off.
  • uniform surface roughness is provided to the surface of the build-up insulating layer to improve adhesion between the build-up insulating layer and the wiring layer. Furthermore, the embodiment provides a uniform surface roughness within a target range to the surface of the build-up insulating layer so that the line width and spacing of the wiring layer can be refined. Furthermore, the embodiment makes it applicable to products using a high frequency band.
  • FIG 3 is a cross-sectional view showing a printed circuit board according to an embodiment.
  • the printed circuit board has a multilayer structure. Accordingly, the printed circuit board includes a plurality of insulating layers, a plurality of wiring layers disposed on respective surfaces of the plurality of insulating layers, and a plurality of via layers penetrating each of the plurality of insulating layers. In addition, the printed circuit board includes a passivation layer disposed on the uppermost side and the lowermost side.
  • the printed circuit board includes the first insulating layer 110 .
  • the printed circuit board of the embodiment may be a core board.
  • the first insulating layer 110 may mean a core layer, but is not limited thereto.
  • the printed circuit board of the embodiment may be a coreless board.
  • the printed circuit board includes a build-up insulating layer.
  • the build-up insulating layer may refer to insulating layers respectively built up on and under the first insulating layer 110 .
  • the build-up insulating layer includes a second insulating layer 120 disposed above the first insulating layer 110 and a third insulating layer 130 disposed below the first insulating layer 110. .
  • Each of the second insulating layer 120 and the third insulating layer 130 may have a plurality of layers.
  • the second insulating layer 120 and the third insulating layer 130 may have the same number of layers, and thus may have a symmetrical structure with respect to the first insulating layer 110 .
  • the number of layers of the second insulating layer 120 and the third insulating layer 130 is not particularly limited, and each of the second insulating layer 120 and the third insulating layer 130 is provided as one layer. It can be, and can be provided in three or more layers. In addition, the number of layers of the second insulating layer 120 and the third insulating layer 130 may be different from each other, and thus may have an asymmetric structure with respect to the first insulating layer 110 .
  • the first insulating layer 110 an insulating material of copper clad laminate (CCL) may be used.
  • the first insulating layer 110 may be a core layer having a thickness greater than each of the second insulating layer 120 and the third insulating layer 130 .
  • Each of the second insulating layer 120 and the third insulating layer 130 is made of any one of epoxy, phenol, BCB (benzocyclobutene), PBO (polybenzoxazole), SFR, LCP, and PTFE. It can be done.
  • each of the second insulating layer 120 and the third insulating layer 130 may include a resin, and glass fibers and fillers provided in the resin.
  • each of the second insulating layer 120 and the third insulating layer 130 may include prepreg.
  • each of the second insulating layer 120 and the third insulating layer 130 may include a resin and a filler included in the resin. That is, each of the second insulating layer 120 and the third insulating layer 130 may not include glass fibers. Accordingly, it is possible to reduce the thickness of each of the second insulating layer 120 and the third insulating layer 130, and formed on the surface of each of the second insulating layer 120 and the third insulating layer 130. It is possible to miniaturize the line width and spacing of the wiring layer.
  • each of the second insulating layer 120 and the third insulating layer 130 may be ABF (Ajinomoto Build-up Film).
  • each of the second insulating layer 120 and the third insulating layer 130 may include a photo-imageable dielectric (PID) that is a photosensitive material.
  • PID photo-imageable dielectric
  • the printed circuit board includes a wiring layer 140 .
  • the wiring layer 140 is disposed on surfaces of the first insulating layer 110 , the second insulating layer 120 , and the third insulating layer 130 , respectively.
  • the wiring layer 140 may include an upper surface of the first insulating layer 110, a lower surface of the first insulating layer 110, an upper surface of each of the plurality of second insulating layers 120, and the plurality of second insulating layers 120.
  • the first to sixth wires 141 , 142 , 143 , 144 , 145 , and 146 are disposed on each lower surface of the third insulating layer 130 of the second insulating layer 130 .
  • the wiring layer 140 may be formed of a metal material, and examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead. (Pb), titanium (Ti), or an alloy thereof or the like can be used.
  • the wiring layer 140 may perform at least one of a signal transfer function, a power transfer function, a ground function, and a heat dissipation function according to a design design.
  • the printed circuit board includes a via layer 150 .
  • the via layer 150 penetrates each of the first insulating layer 110 , the second insulating layer 120 , and the third insulating layer 130 .
  • the via layer 150 includes a plurality of first to fifth vias 151 , 152 , 153 , penetrating each of the first insulating layer 110 , the second insulating layer 120 , and the third insulating layer 130 . 154, 155) may be included.
  • the via layer 150 may be formed of a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), or nickel (Ni). ), lead (Pb), titanium (Ti), or alloys thereof.
  • the via layer 150 may perform at least one of a signal transmission function, a power transmission function, a ground function, and a heat dissipation function according to the function of the connected wiring layer 140 .
  • the first via 151 penetrating the first insulating layer 110 is disposed penetrating the relatively thick first insulating layer 110, and accordingly, the first insulating layer 110 has the first A filling member 160 may be included inside the via 151 to partially fill the through hole.
  • the filling member 160 may include plugging ink, but is not limited thereto.
  • the printed circuit board includes a first passivation layer 170 disposed on the second insulating layer 120 .
  • the first passivation layer 170 is disposed on the second insulating layer 120 and covers an upper surface of the second insulating layer 120 .
  • the first passivation layer 170 covers at least a portion of the upper surface of the fourth wiring 144 disposed on the second insulating layer 120 .
  • the first passivation layer 170 may protect the surface of the fourth wire 144 .
  • the printed circuit board includes a second passivation layer 180 disposed under the third insulating layer 130 .
  • the second passivation layer 180 is disposed below the lower surface of the third insulating layer 130 and covers the lower surface of the third insulating layer 130 .
  • the second passivation layer 180 covers at least a portion of the lower surface of the sixth wiring 146 disposed on the lower surface of the third insulating layer 130 .
  • the second passivation layer 180 may protect the surface of the sixth wire 146 .
  • the first passivation layer 170 and the second passivation layer 180 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an insulating material in which these resins are mixed with an inorganic filler.
  • a thermosetting resin such as epoxy resin
  • a thermoplastic resin such as polyimide
  • an insulating material in which these resins are mixed with an inorganic filler.
  • each of the first passivation layer 170 and the second passivation layer 180 may use ABF, which is the same insulating material as the second insulating layer 120 and the third insulating layer 130 .
  • solder resist SR
  • FIG. 4 is an enlarged view in which a partial area of FIG. 3 is enlarged.
  • the printed circuit board includes a first build-up insulating layer 210, a second build-up insulating layer 220, a first wiring layer 230, a via layer 240, and a second wiring layer 250.
  • the first build-up insulating layer 210 and the second build-up insulating layer 220 are two layers of second insulating layers sequentially disposed on the first insulating layer 110 of FIG. 3 ( 120)
  • the first wiring layer 230 may mean the third wiring 143 disposed between the second insulating layer 120 of the second layer of FIG. 3
  • the via layer ( 240) may mean a second via 152 disposed penetrating through one layer of the second insulating layer 120 of FIG. 3
  • the second wiring layer 250 is the first insulating layer 110 of FIG. ) may refer to the first wiring 141 disposed on the upper surface.
  • the first build-up insulating layer 210 and the second build-up insulating layer 220 are two third insulating layers sequentially disposed under the first insulating layer 110 of FIG. 3 .
  • the first wiring layer 230 may mean the fifth wiring 145 disposed between the third insulating layer 130 of the second layer of FIG. 3, and the via
  • the layer 240 may mean a fourth via 154 disposed penetrating one layer of the third insulating layer 130 of FIG. 3
  • the second wiring layer 250 may be the first insulating layer of FIG. 3 ( 110) may refer to the second wiring 142 disposed on the lower surface.
  • the first build-up insulating layer 210 and the second build-up insulating layer 220 include the same insulating material.
  • the first build-up insulating layer 210 includes a resin and a plurality of first fillers 210F provided in the resin.
  • the second build-up insulating layer 220 includes resin and a plurality of second fillers 220F provided in the resin.
  • the first wiring layer 230 is partially disposed on the first build-up insulating layer 210 .
  • the second build-up insulating layer 220 is disposed on the first wiring layer 230 .
  • the second build-up insulating layer 220 is disposed on the first build-up insulating layer 210 .
  • a plurality of interfaces are provided between the first build-up insulating layer 210 , the second build-up insulating layer 220 and the first wiring layer 230 .
  • the interface means a surface where the first build-up insulating layer 210 and the first wiring layer 230 contact each other. Also, the interface means a surface where the first buildup insulating layer 210 and the second buildup insulating layer 220 contact each other.
  • the interface includes a first interface IS1 in which an upper surface of the first build-up insulating layer 210 and a lower surface of the first wiring layer 230 contact each other.
  • the interface includes a second interface IS2 in which an upper surface of the first build-up insulating layer 210 and a lower surface of the second build-up insulating layer 220 contact each other.
  • the first interface IS1 means a part of the upper surface of the first build-up insulating layer 210 and the lower surface of the first wiring layer 230 .
  • the second interface IS2 means the remaining part of the upper surface of the first build-up insulating layer 220 and the lower surface of the second build-up insulating layer 220 .
  • the first interface IS1 and the second interface IS2 have the same shape as each other.
  • the first interface IS1 and the second interface IS2 in the vertical cross section of the printed circuit board may have concave or convex shapes toward the bottom.
  • the first interface IS1 and the second interface IS2 are the same between the first build-up insulating layer 210, the second build-up insulating layer 220, and the first wiring layer 230. It includes concave or convex portions having a spacing, shape, and size.
  • the first interface IS1 and the second interface IS2 may have a concave shape based on the lower surface of the first build-up insulating layer 210 .
  • the first interface IS1 and the second interface IS2 may have a convex shape based on the lower surfaces of the second build-up insulating layer 220 and the first wiring layer 230 , respectively.
  • the first interface IS1 and the second interface IS2 do not contact the plurality of first pillars 210F provided on the first build-up insulating layer 210 .
  • the lowermost end of the first interface IS1 may be located higher than the first pillar disposed on the uppermost side among the plurality of first pillars 210F provided in the first build-up insulating layer 210.
  • the lowermost end of the second interface IS2 does not contact the plurality of first pillars 210F provided in the first build-up insulating layer 210 . That is, the lowermost end of the second interface IS2 may be located higher than the first pillar disposed on the uppermost side among the plurality of first pillars 210F included in the first build-up insulating layer 210 .
  • the first wiring layer 230 does not contact the plurality of first pillars 210F provided on the first build-up insulating layer 210 .
  • the second build-up insulating layer 220 does not contact the plurality of first pillars 210F provided on the first build-up insulating layer 210 .
  • the via layer 240 is disposed penetrating the first build-up insulating layer 210 .
  • the via layer 240 may be electrically connected to the first wiring layer 230 disposed on the first build-up insulating layer 210 .
  • the via layer 240 may be electrically connected to the second wiring layer 250 disposed under the second build-up insulating layer 220 . That is, the upper surface of the via layer 240 is electrically connected to the lower surface of the first wiring layer 230, and the lower surface of the via layer 240 is electrically connected to the upper surface of the second wiring layer 250.
  • the via layer 240 has a tapered shape in the thickness direction of the first build-up insulating layer 210 .
  • the via layer 240 has a shape in which the width of the upper surface is greater than the width of the lower surface. Accordingly, the side surface of the via layer 240 may be inclined with a predetermined inclination angle between the upper and lower surfaces of the first build-up insulating layer 210 .
  • the side surface of the via layer 240 is divided into a plurality of side surfaces according to contact materials.
  • the via layer 240 includes a first side surface 240S1 and a second side surface 240S2.
  • the first side surface 240S1 of the via layer 240 contacts the resin of the first build-up insulating layer 210 .
  • the second side surface IS2 of the via layer 240 contacts the first pillar 210F of the first build-up insulating layer 210 .
  • the first build-up insulating layer 210 includes through-holes penetrating upper and lower surfaces of the first build-up insulating layer 210 .
  • the via layer 240 is disposed in the through hole of the first build-up insulating layer 210 .
  • the embodiment applies different methods to the upper surface of the first build-up insulating layer 210 and the inner wall of the through hole to impart surface roughness.
  • a plurality of first recesses corresponding to a plurality of protrusions provided in a transfer layer are formed on the upper surface of the first build-up insulating layer 210, and thus the first build-up insulating layer 210 is formed.
  • the upper surface of the insulating layer 210 is given a surface roughness corresponding to the depth of the plurality of first recesses.
  • a desmear process is performed on the inner wall of the through hole. Accordingly, surface roughness is imparted to the inner wall of the through hole of the first build-up insulating layer 210 by the desmear process.
  • the surface roughness of the upper surface of the first build-up insulating layer 210 may be different from the surface roughness of the inner wall of the through hole of the first build-up insulating layer 210 .
  • a surface roughness is imparted to the inner wall of the through hole by a desmear process, and thus the surface roughness may be greater than that applied to the upper surface of the first build-up insulating layer 210 .
  • the surface roughness of the lower surface of the first wiring layer 230 and the surface roughness of the side surface of the via layer 240 may be different from each other.
  • the surface roughness of the side surface of the via layer 240 may be greater than the surface roughness of the lower surface of the first wiring layer 230 .
  • the via layer 240 includes an extension portion 240E.
  • the extension portion 240E of the via layer 240 is disposed on the second wiring layer 250 disposed on the lower surface of the first build-up insulating layer 210 .
  • the upper surface of the second wiring layer 250 is provided with a second recess 250R concave toward the lower surface of the second wiring layer 250 .
  • the second recess 250R of the second wiring layer 250 may be formed in a process of removing a transfer layer used to impart a uniform surface roughness to the upper surface of the first build-up insulating layer 210. there is. That is, in the process of removing the transfer layer, at least a portion of the second wiring layer 250 exposed through the through hole is also removed in the embodiment. Through this, a second recess 250R concave toward the lower surface may be formed on the upper surface of the second wiring layer 250 .
  • the depth H1 of the second recess 250R is the depth H2 of each of the plurality of first recesses 210R (refer to FIG. 5 ) provided on the upper surface of the first build-up insulating layer 210 . ) is greater than A depth H1 of the second recess 250R may be 2 ⁇ m to 4.5 ⁇ m. Preferably, the depth H1 of the second recess 250R may be 2.5 ⁇ m to 4.3 ⁇ m. More preferably, the depth H1 of the second recess 250R may be 3.0 ⁇ m to 4.0 ⁇ m.
  • a portion of the transfer layer may remain on the upper surface of the first build-up insulating layer 210 in the process of etching the transfer layer. .
  • uniform surface roughness may not be imparted to the upper surface of the first build-up insulating layer 210 . Failure to impart the uniform surface roughness may mean that the sizes and intervals of the plurality of first recesses 210R formed on the upper surface of the first build-up insulating layer 210 are non-uniform.
  • the thickness of the second wiring layer 250 in the region where the second recess 250R is formed may become too thin. Accordingly, electrical characteristics of the second wiring layer 250 may be deteriorated. For example, allowable current of a signal that can be transmitted through the second wiring layer 250 may be lowered.
  • the depth H1 of the second recess 250R exceeds 4.5 ⁇ m it means that the thickness of the transfer layer is correspondingly large, and accordingly, the top surface of the first build-up insulating layer 210 A problem in which a part of the transfer layer remains may occur.
  • the via layer 240 may include an extension 240E filling the second recess 250R of the second wiring layer 250 .
  • the via layer 240 may decrease in width from the upper surface to the lower surface of the via layer 240 and increase in width in the expansion portion 240E.
  • the expansion portion 240E of the via layer 240 may function as an anchor to improve adhesion between the first build-up insulating layer 210 and the via layer 240 . That is, the width of the via layer 240 gradually decreases with the miniaturization of the printed circuit board. Accordingly, a problem in that adhesion between the via layer 240 and the first build-up insulating layer 210 may decrease may occur.
  • the embodiment allows the via layer 240 to include the expansion portion 240E.
  • the expansion portion 240E of the via layer 240 increases the contact area between the via layer 240 and the first build-up insulation layer 210, thereby increasing the contact area between the via layer 240 and the first build-up insulation layer 210. It can function to improve the bonding strength between the layers 210. Therefore, the embodiment can further improve physical reliability and electrical reliability of the printed circuit board.
  • FIG. 5 is a view showing a first interface and a second interface according to a first embodiment
  • FIG. 6 is a view showing a first interface and a second interface according to a second embodiment
  • FIG. 7 is a view showing a third embodiment. It is a view showing the first interface and the second interface according to the
  • a plurality of first recesses 210R concave toward the lower surface of the first build-up insulating layer 210 are provided on the upper surface of the first build-up insulating layer 210 .
  • the plurality of first recesses 210R have a uniform size. That is, the depth H2, width W1, and spacing W2 of each of the plurality of first recesses 210R have the same range.
  • a vertical cross-sectional shape of the plurality of first recesses 210R may be circular. Accordingly, the width W1 of the first recess 210R may mean the diameter of the first recess 210R.
  • the depth H2 of the plurality of first recesses 210R may correspond to the surface roughness applied to the upper surface of the first build-up insulating layer 210 .
  • the plurality of first recesses 210R have depths H2 in the same range as each other.
  • the plurality of first recesses 210R correspond to a first group contacting the first wiring layer 230 while corresponding to the first interface IS1 and to correspond to the second interface IS2.
  • a second group contacting the second build-up insulating layer 220 is included.
  • the plurality of first recesses of the first group and the first recesses of the second group have a depth H2 in the same range.
  • the plurality of first recesses of the first group and the first recesses of the second group according to the embodiment may have the same depth H2 as each other.
  • a depth H2 of the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.5 ⁇ m.
  • the depth H2 of the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.45 ⁇ m. More preferably, the depth H2 of the plurality of first recesses 210R may have a range of 0.05 ⁇ m to 0.4 ⁇ m.
  • the depth H2 of the plurality of first recesses 210R is less than 0.05 ⁇ m, an excessively low surface roughness may be imparted to the top surface of the first build-up insulating layer 210, and thus the first build-up insulating layer 210 may have a low surface roughness. Adhesion between the build-up insulating layer 210 and the first wiring layer 230 and between the first build-up insulating layer 210 and the second build-up insulating layer 220 may decrease. Accordingly, a problem in which the second buildup insulating layer 220 or the first wiring layer 230 is separated from the first buildup insulating layer 210 may occur.
  • the seed metal layer of the first wiring layer 230 disposed on the first build-up insulating layer 210 has a uniform thickness. may not have, whereby the seed metal layer may not function as a seed layer.
  • the depth H2 of the plurality of first recesses 210R exceeds 0.5 ⁇ m, the surface roughness of the lower surface of the first wiring layer 230 may increase, and thus signal transmission by skin effect. losses may increase.
  • the depth H2 of the plurality of first recesses 210R exceeds 0.5 ⁇ m, a portion of the transfer layer used to form the plurality of first recesses 210R may be part of the first recess ( 210R), and thus a circuit short problem may occur.
  • the first build-up insulating layer 210 is disposed. At least a portion of the first pillar 210F may be exposed through the first recess 210R.
  • first pillar 210F when the first pillar 210F is exposed, it may be difficult to form a uniform first recess 210R on the upper surface of the first build-up insulating layer 210, and furthermore, the first build-up insulating layer 210 may be difficult to form. Adhesion between the layer 210 and the second build-up insulating layer 220 or the first wiring layer 230 may decrease.
  • a width W1 of the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.5 ⁇ m.
  • the width W1 of the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.45 ⁇ m. More preferably, the width W1 of the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.4 ⁇ m.
  • the thickness of the seed layer may not be uniform.
  • the seed metal layer is not plated on some of the inner surfaces 210RS of the plurality of first recesses 210R. problems may arise.
  • the width W1 of the plurality of first recesses 210R exceeds 0.5 ⁇ m, the first build-up insulating layer 210 and the second build-up insulating layer 220 or the first wiring layer 230 ), the contact area between them may be reduced, and thus a problem of deterioration in adhesion may occur.
  • the width W1 of the plurality of first recesses 210R exceeds 0.5 ⁇ m, the plurality of first recesses 210R formed on the upper surface of the first build-up insulating layer 210 Their density may be reduced.
  • the distance W2 between the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.5 ⁇ m.
  • the distance W2 between the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.45 ⁇ m. More preferably, the distance W2 between the plurality of first recesses 210R may range from 0.05 ⁇ m to 0.4 ⁇ m.
  • the plurality of first recesses 210R may not have a depth H2 and an interval W2 within the range.
  • the distance W2 between the plurality of first recesses 210R exceeds 0.5 ⁇ m, the plurality of first recesses 210R formed on the upper surface of the first build-up insulating layer 210 Density of them may decrease, and thus, adhesion between the first build-up insulating layer 210 and the second build-up insulating layer 220 or the first wiring layer 230 may decrease.
  • a width of the plurality of first recesses 210R may change from an upper surface to a lower surface of the first build-up insulating layer 210 .
  • the width W3 of the upper surface of the first build-up insulating layer 210 is the width W1 of the first recess 210R, for example , the maximum width).
  • the embodiment is not limited thereto, and the width W3 of the first recess 210 on the upper surface of the first build-up insulating layer 210 may be equal to the maximum width W1.
  • an interior angle ⁇ between the top surface of the first build-up insulating layer 210 and the inner surface 210RS of the first recess 210R may be less than 90 degrees.
  • an interior angle ⁇ between the top surface of the first build-up insulating layer 210 and the inner surface 210RS of the first recess 210R may be an acute angle.
  • the embodiment improves the adhesion between the first build-up insulating layer 210 and the first wiring layer 230 by the first recess 210R, and the first build-up insulating layer 210 and Improvement of adhesion between the second build-up insulating layers 220 may be maximized.
  • the interior angle ⁇ is an acute angle smaller than 90 degrees, an anchoring effect by the first recess 210R may be maximized.
  • the lower surface of the first wiring layer 230 corresponds to the first recess 210R of the first build-up insulating layer 210 at the first interface IS1.
  • a first protrusion 230P is provided.
  • a plurality of first protrusions 230P may be formed on the lower surface of the first wiring layer 230 to correspond to the plurality of first recesses 210R and have a predetermined width, thickness, and spacing.
  • the width of the plurality of first protrusions 230P may correspond to the width W1 of the first recess 210R.
  • the thickness of the plurality of first protrusions 230P may correspond to the depth H2 of the first recess 210R.
  • the distance between the plurality of first protrusions 230P may correspond to the distance W2 between the first recesses 210R.
  • the lower surface of the second build-up insulating layer 220 has a first recess 210R of the first build-up insulating layer 210 at the second interface IS2.
  • a second protrusion 220P corresponding to is provided.
  • a plurality of second protrusions 220P may be formed on the lower surface of the second build-up insulating layer 220 to correspond to the plurality of first recesses 210R with a predetermined width, thickness, and spacing.
  • the width of the plurality of second protrusions 220P may correspond to the width W1 of the first recess 210R.
  • the thickness of the plurality of second protrusions 220P may correspond to the depth H2 of the first recess 210R.
  • the distance between the plurality of second protrusions 220P may correspond to the distance W2 between the first recesses 210R.
  • the second protrusion 220P formed on the lower surface of the layer 220 may have a shape different from that of FIG. 5 .
  • the first recess 210R, the first protrusion 230P, and the second protrusion 220P are illustrated as having a circular shape, but are not limited thereto.
  • a vertical cross-sectional shape of each of the first recess 210R, the first protrusion 230P, and the second protrusion 220P may have a trapezoidal shape.
  • a vertical cross-sectional shape of each of the first recess 210R, the first protrusion 230P, and the second protrusion 220P may have a parallelogram shape.
  • first recess 210R, the first protrusion 230P, and the second protrusion 220P may have shapes other than circular, trapezoidal, and parallelogram shapes shown in the drawings.
  • a plurality of first recesses 210R formed on the upper surface of the first build-up insulating layer 210 may also be formed on the upper surface of the second build-up insulating layer 220 .
  • some of the plurality of first recesses formed on the upper surface of the second build-up insulating layer 220 may contact the wiring layer 230 formed on the upper surface of the second build-up insulating layer 220, The remaining part may contact the third build-up insulating layer or the first passivation layer 170 formed on the upper surface of the second build-up insulating layer 220 .
  • a process of attaching a transfer layer to the first build-up insulating layer 210 is performed in a state in which the first build-up insulating layer 210 is stacked, so that the first build-up insulating layer 210 A first recess 210R having a uniform size is formed on the upper surface of ).
  • the first recess 210R having a uniform depth H2 of 0.05 ⁇ m to 0.5 ⁇ m may be formed on the upper surface of the layer 210 .
  • a first recess may be formed on the upper surface of the insulating layer using the copper foil layer of the RCC type while using the insulating layer and the copper foil layer provided in the RCC (Resin Coated Copper) type as a build-up insulating layer.
  • RCC Resin Coated Copper
  • the copper foil layer disposed on the RCC type insulating layer has the following characteristics different from the transfer layer used in the embodiment.
  • the copper foil layer and the transfer layer will be described separately.
  • the copper foil layer is composed of a layer for imparting a pure copper foil thickness and surface roughness, and the outermost surface of the layer constituting the surface roughness is made of an alloy layer.
  • the alloy layer includes nickel, zinc and chromium.
  • the copper foil layer usually has a thickness of 2.5 ⁇ m or more including a layer providing surface roughness.
  • the protrusions formed on the copper foil layer are relatively large in size.
  • the depth of the recess formed in the laser via pad penetrating the build-up insulating layer is at least 2 ⁇ m or more by the copper foil etching process, and the build-up corresponding to the depth of the recess
  • the surface roughness (Ra) of the insulating layer is also usually 1 ⁇ m or more. Therefore, when using the RCC type copper foil layer, it may be difficult to apply to products using a high frequency band as the surface roughness increases.
  • the thickness of the copper foil layer exceeds 2 ⁇ m. Accordingly, an etching amount in an etching process for removing the copper foil layer may be increased. At this time, in the process of removing the copper foil layer, the wiring layer exposed through the via hole is also removed. Accordingly, the depth of the recess formed in the wiring layer also increases. When the depth of the recess is increased, the wiring layer including the recess may not function as a normal circuit wiring. In addition, the thickness of the wiring layer including the recess must be increased by reflecting the depth of the recess, which increases manufacturing cost.
  • the copper foil layer further includes nickel and chromium other than copper.
  • the etch rate of the nickel and chromium is different from the etch rate of the copper. Therefore, when removing the copper foil layer by etching, etching conditions should be determined based on a metal material having a relatively high etching rate, and accordingly, an etching time may increase. Furthermore, as the etching time increases, the depth of the recess formed in the wiring layer must be increased or the thickness of the wiring layer must be increased.
  • nickel and chromium included in the copper foil layer are less etched than the copper, and some may remain in the build-up insulating layer in the process of removing the copper foil layer. Therefore, a nickel element or a chromium element may be present on the surface of the build-up insulating layer. And, when a part of the copper foil layer remains in the build-up insulating layer, it may be difficult to form a seed metal layer having a uniform thickness accordingly. In addition, when a portion of the copper foil layer remains in the build-up insulating layer, a circuit short circuit problem may occur in which a plurality of wiring layers to be electrically separated from each other are connected to each other due to the copper foil layer.
  • a lamination process is performed in a state in which the copper foil layer is disposed on the build-up insulating layer.
  • gas may be generated inside the insulating layer.
  • the copper foil layer is already disposed on the build-up insulating layer, and thus the gas may not be discharged to the outside.
  • the gas may not be discharged, voids may be generated due to the gas or adhesion between the build-up insulating layer and the wiring layer may be deteriorated.
  • a process of forming a first recess and imparting surface roughness to the upper surface of the build-up insulating layer is performed using a transfer layer containing pure copper. Accordingly, the embodiment can solve problems occurring in the process of providing surface roughness in the RCC type.
  • a feature of the manufacturing method of the printed circuit board of the embodiment lies in the lamination process of the build-up insulating layer, and accordingly, hereinafter, the lamination process of the build-up insulating layer will be mainly described.
  • FIGS. 8 to 21 are diagrams showing a manufacturing method of a printed circuit board according to an embodiment in process order.
  • the embodiment prepares a first insulating layer or core layer 260 .
  • the first insulating layer or core layer 260 may use CCL (Copper Clad Laminate). Thereafter, in the embodiment, a process of forming the second wiring layer 250 on the first insulating layer or core layer 260 is performed.
  • CCL Copper Clad Laminate
  • a process of stacking the first build-up insulating layer 210 on the first insulating layer or core layer 260 is performed.
  • a protective film PF may be formed on the upper surface of the first build-up insulating layer 210, but is not limited thereto.
  • the protective film PF may be polyethylene terephthalate (PET), but is not limited thereto.
  • a process of removing the protective film PF disposed on the upper surface of the first build-up insulating layer 210 is performed.
  • the process of FIG. 10 may be omitted.
  • a process of placing a transfer layer 300 on the first build-up insulating layer 210 is performed.
  • a protrusion 310 is formed on the transfer layer 300 .
  • the protrusion 310 formed on the lower surface of the transfer layer 300 has substantially the same shape as the first recess 210R, the first protrusion 230P, and the second protrusion 220P described with reference to FIG. 5 . and, therefore, a detailed description thereof will be omitted.
  • the thickness H3 of the transfer layer 300 may have a range of 1.2 ⁇ m to 1.8 ⁇ m including the protrusion 130 .
  • the thickness H3 of the transfer layer 300 means the total thickness including the thickness of the protrusions 310 of the transfer layer 300 corresponding to the depth H2 of the first recess 210R.
  • the process time of the process of etching the transfer layer 300 may increase, and in the process of completely removing the transfer layer 300, the via As the etching amount of the pad increases, excessive recesses may be formed or defects such as loss of the bottom of the via pad may occur, and the alloy layer may remain on the insulating layer, resulting in electrical reliability and / or physical reliability problems may occur.
  • a process of attaching the transfer layer 300 to the upper surface of the first build-up insulating layer 210 is performed.
  • the process of attaching the transfer layer 300 may be performed by a hot press method or a vacuum compression method in which heat is applied to the first build-up insulating layer 210 and compressed.
  • the first build-up insulating layer 210 that has received the heat may be melted, and the transfer layer 300 may be attached to an upper surface of the melted first build-up insulating layer 210 .
  • the embodiment proceeds with the process of attaching the transfer layer 300 before the melted first build-up insulating layer 210 is cooled and completely hardened.
  • the embodiment proceeds with a vacuum lamination process to remove air bubbles between the first build-up insulating layer 210 and the transfer layer 300, and applies temperature and pressure through an isostatic press or vacuum lamination.
  • a process of attaching the transfer layer 300 may be performed.
  • a process of forming a via hole VH penetrating the attached transfer layer 300 and the first build-up insulating layer 210 is performed.
  • the process of forming the via hole VH may be performed through a laser process, but is not limited thereto.
  • a process of desmearing the inner wall VHS of the formed via hole VH may be performed.
  • the desmear process may be performed in a dry method using plasma or a wet method using chemicals.
  • the desmear process may be performed on the inner wall VHS of the via hole VH and the bottom surface of the via hole VH.
  • the transfer layer 300 is disposed on the upper surface of the first build-up insulating layer 210, and accordingly, the upper surface of the first build-up insulating layer 210 is not desmeared.
  • a process of etching the transfer layer 300 is performed.
  • the etching process of the transfer layer 300 may be performed under an etching condition of an etching amount greater than the thickness H3 of the transfer layer 300 . Accordingly, the transfer layer 300 disposed on the upper surface of the first build-up insulating layer 210 may be completely removed as a whole.
  • the second wiring layer 250 exposed through the via hole VH may also be etched. Accordingly, a second recess 250R may be formed on an upper surface of the second wiring layer 250 .
  • a first recess 210R corresponding to the protrusion 310 of the transfer layer 300 is formed on the upper surface of the first build-up insulating layer 210 by etching the transfer layer 300 .
  • the plating seed layer M1 may be formed through a chemical copper plating process, but is not limited thereto.
  • the plating seed layer M1 may be formed through a sputtering process.
  • the plating seed layer M1 may be formed on an inner surface of the first recess 210R, an inner wall VHS of the via hole VH, and an inner surface of the second recess 250R.
  • the plating seed layer M1 may be formed along the profile of the upper surface of the first build-up insulating layer 210 . That is, the plating seed layer M1 may be formed along the profile of the first recess 210R formed on the upper surface of the first build-up insulating layer 210 .
  • a process of forming a dry film DF on the plating seed layer M1 is performed.
  • the dry film DF includes an opening.
  • the dry film DF includes a region where the first wiring layer 230 is to be formed and an opening exposing the via hole VH.
  • an electrolytic plating layer M2 is formed by electroplating the plating seed layer M1 as a seed layer.
  • the electrolytic plating layer M2 is formed to fill openings of the first recess 210R, the second recess 250R, the via hole VH, and the dry film DF.
  • a process of removing the dry film DF is performed.
  • the plating seed layer M1 includes a first region overlapping the electrolytic plating layer M2 in a vertical direction and a second region not overlapping the electroplating layer M2 in a vertical direction. And, in the embodiment, a process of removing the second region of the plating seed layer M1 by etching is performed. Accordingly, among the first recesses 210R formed on the upper surface of the first build-up insulating layer 210, first recesses that do not vertically overlap the electrolytic plating layer M2 are exposed to the outside.
  • the first wiring layer 230 including the plating seed layer M1 and the electrolytic plating layer M2, the via layer 240, and the expansion portion 240E of the via layer 240 are formed.
  • the first wiring layer 230 may include a first protrusion 230P corresponding to the first recess 210R provided on the upper surface of the first build-up insulating layer 210 .
  • a second build-up insulating layer 220 is formed on the first build-up insulating layer 210 .
  • the second build-up insulating layer 220 may be provided while filling at least a portion of the first recess 210R disposed on the upper surface of the first build-up insulating layer 210 .
  • the second build-up insulating layer 220 may include a second protrusion 220P corresponding to the first recess 210R provided on the upper surface of the first build-up insulating layer 210 . .
  • a plurality of first recesses having uniform widths, intervals, and depths are formed on the upper surface of the first build-up insulating layer.
  • the plurality of first recesses are provided on an upper surface of the first build-up insulating layer, and thus contact a lower surface of the first wiring layer and a lower surface of the second build-up insulating layer, respectively.
  • a first protrusion corresponding to the first recess is formed on a lower surface of the first wiring layer.
  • a second protrusion corresponding to the first recess is formed on a lower surface of the second build-up insulating layer.
  • the plurality of first recesses are uniformly formed on the upper surface of the first build-up insulating layer.
  • the first protrusions are uniformly formed on the lower surface of the first wiring layer.
  • the second protrusion is uniformly formed on the lower surface of the second build-up insulating layer.
  • the embodiment may improve adhesion between the first build-up insulating layer and the second build-up insulating layer.
  • the embodiment may improve adhesion between the first build-up insulating layer and the first wiring layer. Therefore, the embodiment can solve the problem that the first wiring layer and the second buildup insulating layer are separated from the first buildup insulating layer. Through this, the embodiment can improve physical reliability and electrical reliability of the printed circuit board.
  • the embodiment allows uniform first recesses to be formed on the upper surface of the first build-up insulating layer, and accordingly, the thickness of the plating seed layer formed on the upper surface of the first build-up insulating layer can be made uniform. there is.
  • the embodiment it is possible to minimize the plating deviation of the electrolytic plating layer formed on the plating seed layer, and through this, a plurality of wiring layers can have the same thickness as each other. Therefore, the embodiment can improve the electrical characteristics of the printed circuit board.
  • each of the depth of the first recess, the thickness of the first protrusion and the thickness of the second protrusion has a range of 0.05 ⁇ m to 0.5 ⁇ m. Accordingly, the embodiment can solve the problem that a part of the transfer layer used to form the first recess is not removed, and through this, electrical reliability such as an electrical short circuit can be improved.
  • surface roughness of the first wiring layer may be lowered to correspond to the thickness of the first protrusion, thereby minimizing transmission loss of a signal transmitted through the first wiring layer.
  • a second recess having a predetermined depth may be formed on the second wiring layer during etching of the transfer layer.
  • a portion of the via layer penetrating the first build-up insulating layer may be disposed in the second recess, thereby increasing the adhesion between the via layer and the first build-up insulating layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention concerne, selon un mode de réalisation, une carte de circuit comprenant : une première couche d'isolation d'accumulation ; une première couche de câblage disposée sur la première couche d'isolation d'accumulation ; et une couche d'interconnexion qui pénètre dans la première couche d'isolation d'accumulation et qui est connectée à la première couche de câblage. La première couche d'isolation d'accumulation comprend une résine et une pluralité de charges disposées dans la résine ; la première couche de câblage n'est pas en contact avec la pluralité de charges, et la couche d'interconnexion est en contact avec au moins une des charges de la pluralité de charges.
PCT/KR2023/000560 2022-01-12 2023-01-12 Carte de circuit imprimé et son procédé de fabrication Ceased WO2023136621A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2022-0004661 2022-01-12
KR20220004661 2022-01-12
KR10-2022-0179405 2022-12-20
KR1020220179405A KR102561794B1 (ko) 2022-01-12 2022-12-20 인쇄회로기판 및 이의 제조 방법

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WO2023136621A1 true WO2023136621A1 (fr) 2023-07-20

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PCT/KR2023/000560 Ceased WO2023136621A1 (fr) 2022-01-12 2023-01-12 Carte de circuit imprimé et son procédé de fabrication

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TW (1) TW202335542A (fr)
WO (1) WO2023136621A1 (fr)

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CN117219710A (zh) * 2023-09-06 2023-12-12 广东中图半导体科技股份有限公司 一种图形化复合衬底及其制备方法、led外延片

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JP2011040728A (ja) * 2009-07-14 2011-02-24 Ajinomoto Co Inc 銅張積層板
JP2012004399A (ja) * 2010-06-18 2012-01-05 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
KR20170041544A (ko) * 2015-10-07 2017-04-17 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20180060687A (ko) * 2016-11-29 2018-06-07 삼성전기주식회사 인쇄회로기판 제조방법
KR20190044446A (ko) * 2017-10-20 2019-04-30 삼성전기주식회사 인쇄회로기판

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CN117219710A (zh) * 2023-09-06 2023-12-12 广东中图半导体科技股份有限公司 一种图形化复合衬底及其制备方法、led外延片
CN117219710B (zh) * 2023-09-06 2024-08-16 广东中图半导体科技股份有限公司 一种图形化复合衬底及其制备方法、led外延片

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