WO2023110048A1

WO2023110048A1 - Load circuit for use in an amplifier circuit, amplifier circuit and electro-optical transmitter

Info

Publication number: WO2023110048A1
Application number: PCT/EP2021/085342
Authority: WO
Inventors: Filippo SCHEMBARI; Claudio ASERO; Longfei ZHU
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2023-06-22
Anticipated expiration: 2024-06-13
Also published as: CN118402178A

Abstract

The present disclosure relates to a load circuit (3) for use in an amplifier circuit (1). The amplifier circuit (1) comprising a transconductance circuit (2). The load circuit (3) comprises one circuit branch (3a) or two circuit branches (3a, 3b). Each circuit branch comprises: two terminals (5a, 5a'; 5b, 5b'), N inductive elements (6) and N+1 nodes (7) and N+1 transistors (4), wherein N is one or more than one. The N inductive elements (6) and the N+1 nodes (7) are electrically connected in series between the two terminals (5a, 5a'; 5b, 5b'), wherein any two successive nodes of the N+1 nodes (7) are electrically connected to each other via a respective inductive element of the N inductive elements (6). Each of the N+1 nodes (7) is electrically connected to the supply terminal (8) via a respective transistor of the N+1 transistors (4).

Description

LOAD CIRCUIT FOR USE IN AN AMPLIFIER CIRCUIT, AMPLIFIER CIRCUIT AND ELECTRO-OPTICAL TRANSMITTER

TECHNICAL FIELD

The disclosure relates to a load circuit for use in an amplifier circuit, wherein the amplifier circuit comprises a transconductance circuit. The disclosure further relates to an amplifier circuit comprising such a load circuit and a transconductance circuit. Furthermore, the disclosure relates to an electro- optical transmitter comprising such an amplifier circuit.

BACKGROUND

The disclosure is in the field of amplifier circuits comprising a transconductance circuit and a load circuit. Such amplifier circuits may be used in electrical devices for amplifying signals (voltages).

SUMMARY

The following considerations are made by the inventors:

The main requirements for amplifier circuits for amplifying a signal may comprise introducing low distortion to the signal, providing a large output voltage swing, featuring a sufficiently wide bandwidth, featuring an impedance matched output so as to offer compatibility to a wide range of electrical loads. Typically, in the art an impedance matched output may mean that the output impedance of the amplifier is for example 50 Q for a single-ended topology or 100 Q for a differential topology.

Figure 1 shows two examples of an amplifier circuit. Each amplifier circuit 1 comprises a transconductance circuit 2 and a load circuit 3. In other words, an amplifier circuit (voltage amplifier) may conceptually comprise two parts: a transconductance and a load. Such amplifier circuits may be referred to as “transconductance amplifier circuits”. The transconductance circuit 2 may comprise in its simplest form a single transistor. Optionally, the single transistor may be cascoded. The load circuit 3 may be passive, e.g. comprising a resistor, or active, e.g. comprising a current source. The current source may be implemented by a transistor. With regard to a differential topology of the amplifier circuit comprising a pair of circuit branches, the aforementioned with regard to the transconductance circuit 2 and the load circuit 3 is valid for each circuit branch. The amplifier circuit 1 comprises an input, to which a signal to be amplified may be provided, an output for providing an amplified signal (i.e. the signal after being amplified) and a supply terminal 8 to which a supply voltage may be provided to the amplifier circuit 1. The supply voltage may be referred to as the supply voltage of the amplifier circuit 1. The amplifier circuit 1 on the left side of Figure 1 has a single-ended topology, i.e. it is a single-ended amplifier circuit 1. The single-ended amplifier circuit 1 may comprise an input terminal IN and an output terminal OUT. The amplifier circuit on the right side of Figure 1 has a differential topology, i.e. it is a differential amplifier circuit 1. The differential amplifier circuit 1 may comprise two input terminals IN_a, IN_b and two output terminals OUT_a, OUT_b.

In order to address the above-mentioned requirements for an amplifier circuit, the amplifier circuit may be implemented as exemplarily shown in Figure 2. The amplifier circuit of Figure 2 has a differential topology. This is only by way of example and, thus, the description with regard to Figure 2 is correspondingly valid for an amplifier circuit having a single-ended topology. Since the amplifier circuit 1 of Figure 2 has a differential topology it comprises two circuit branches. Thus, the transconductance circuit 2 and the load circuit 3 each have two circuit branches. As shown in Figure 2, each circuit branch of the load circuit 3 comprises a resistor RL and each circuit branch of the transconductance circuit 2 comprises two transistors T1 and T2 that are electrically connected in series. A first terminal of the first transistor T1 of a respective circuit branch of the transconductance circuit 2 is electrically connected to a first terminal of the resistor RL of the respective circuit branch of the load circuit 3. A second terminal of the resistor RL is electrically connected to a supply terminal of the load circuit 3 (and, thus, of the amplifier circuit 1). A supply voltage VDD may be supplied to the supply terminal for electrically supplying the amplifier circuit 1. The supply voltage VDD may be for example 3.3 V. A second terminal of the first transistor T1 of the respective circuit branch is electrically connected to a first terminal of the second transistor T2 of the respective circuit branch.

A third terminal of the first transistor T1 of a first circuit branch of the two circuit branches of the transconductance circuit 2 may be electrically connected to a third terminal of the first transistor T1 of a second circuit branch of the two circuit branches of the transconductance circuit 2. The third terminal of the first transistor T1 is a control terminal of the first transistor Tl. A second terminal of the second transistor T2 of the respective circuit branch may be electrically connected to ground. The third terminal of the second transistor T2 of the respective circuit branch may be connected to a respective input terminal of the amplifier circuit 1. The third terminal of the second transistor T2 is a control terminal. The node between the resistor RL and the first transistor Tl of the respective circuit branch may be electrically connected to a respective output terminal of the amplifier circuit 1. Thus, for amplifying a signal, the signal may be provided to the amplifier circuit 1 in the form of two input voltages VIN,P and VIN,M- The amplifier circuit 1 may provide the amplified signal in the form of two output voltages VO,M and Vo,p. As shown in Figure 2, the first transistors T1 may be implemented by bipolar junction transistor (BJTs), such as npn-type BJTs, and the second transistors T2 may be implemented by metal-oxide- semiconductor field-effect transistors (MOSFETs), such as n-channel MOSFETs. This is only by way of example and, thus, the transconductance circuit 2 may be implemented using different types of transistors.

Provided that the two second transistors T2 of the transconductance circuit 2 (i.e. the transistors T2 of the input differential pair) are sized and biased properly so as to introduce reasonably low g_m distortion (i.e. the distortion of the voltage-to-current conversion they exploit, where g_m denotes the transconductance of the FET transistors), the output DC common-mode voltage of the amplifier circuit 1 (VO.CM.DC) is dictated by the resistance of the resistor RL and the bias current (IBIAS/2) of each branch of the two circuit branches of the amplifier circuit 1 : (),CM,DC ⁼ ^DD ~ RL ■ IBIAS/ (1)

The resistance of the resistor RL of the respective circuit branch of the load circuit 3 and, thus, of the amplifier circuit 1 may be referred to as load resistance. The resistance of the resistor RL of each circuit branch of the load circuit 3 and, thus, of the amplifier circuit 1 may be set to e.g. 50 Q or close to 50 Q to ensure output impedance matching.

However, given that the output DC common-mode voltage depends on the resistors RL of the load circuit 3 and the bias current IBIAS flowing through the two branches of the amplifier circuit 1, the topology of the amplifier circuit 1 of Figure 2 is not suitable for large output voltage swings. This is due to the voltage headroom taken by the two second transistors T2 (i.e. voltage headroom taken by the input differential pair of the amplifier circuit 1) and the two first transistors T1 (which may be referred to as cascode transistors).

An improvement of the circuit topology of Figure 2 with regard to the output voltage swing is shown in Figure 3. The amplifier circuit 1 of Figure 3 differs from the amplifier circuit 1 of Figure 2 with regard to the load circuit 3. Thus, the above description with regard to Figure 2 is correspondingly valid for the amplifier circuit of Figure 3 and in the following mainly the difference between the amplifier circuit of Figure 2 and the amplifier circuit of Figure 3 is described.

The load circuit 3 of the amplifier circuit 1 of Figure 3 differs from the load circuit of Figure 2, in that the resistors RL are replaced by transistors T3. In other words, the passive load circuit 3 of Figure 2 is replaced by an active load circuit 3, as shown in Figure 3. The amplifier circuit 1 of Figure 3 offers a larger output voltage swing compared to the amplifier circuit 1 of Figure 2 because of replacing the passive load circuit 3 of the amplifier circuit 1 of Figure 2 with an active load circuit 3, as shown in Figure 3. The active load circuit 3 of the amplifier circuit 1 of Figure 3 may be referred to as lumped current generator or lumped current source. This current generator (current source) is provided by the transistors T3 of the load circuit 3.

The amplifier circuit 1 of Figure 3 offers a larger output voltage swing compared to the amplifier circuit 1 of Figure 2, because, to the first order, the output DC common-mode voltage is not dictated by resistors of the load circuit 3 and the bias current IBIAS of the two circuit branches. It is also not dictated by the resistor RTERM that may be electrically connected between the second terminals of the two first transistors T1 of the transconductance circuit 2 of the amplifier circuit 1. The resistor RTERM may be set to e.g. 100 Q or close to 100 Q to ensure output differential impedance matching. In contrast, the output DC common-mode voltage may be arbitrarily set to maximize the output voltage swing. The DC commonmode voltage may be set half-way between the minimum voltage, which is possible at the collector terminal of the first transistors T1 before the first transistors T1 enter into the saturation region, and the maximum voltage, which is possible at the drain terminal of the transistors T3 of the load circuit 3 before the transistors T3 of the load circuit 3 enter into the triode region. However, due to the large size of the transistors T3 of the load circuit 3 for ensuring sufficiently large voltage headroom towards the supply voltage VDD the output parasitic capacitance CPARI of the transistor T3 is rather big. Therefore, the amplifier circuit topology of Figure 3 exhibits worse bandwidth and worse output return loss compared to the amplifier circuit topology of Figure 2.

In view of the above, the present disclosure aims to provide an amplifier circuit that allows achieving a large output signal swing, a wide bandwidth, a low distortion and output impedance matching. A further objective may be to provide an amplifier circuit that allows operating under the nominal voltage supply offered by the technology used for implementing the amplifier circuit.

The objective is achieved by the subject matter of the enclosed independent claims. Advantageous implementations are further defined in the dependent claims.

A first aspect of the disclosure provides a load circuit for use in an amplifier circuit, wherein the amplifier circuit comprises a transconductance circuit. The load circuit comprises a supply terminal and one circuit branch or two circuit branches. Each circuit branch comprises two terminals. Further, each circuit branch comprises N inductive elements and N+l nodes, wherein N is one or more than one. The N inductive elements and the N+l nodes are electrically connected in series between the two terminals, wherein any two successive nodes of the N+l nodes are electrically connected to each other via a respective inductive element of the N inductive elements. Furthermore, each circuit branch comprises N+l transistors. Each of the N+l nodes is electrically connected to the supply terminal via a respective transistor of the N+l transistors.

With other words, the first aspect proposes replacing the single transistor of a respective circuit branch of the load circuit shown in Figure 3 by at least two transistors (i.e. N+l transistors). The at least two transistors may be decoupled by a respective inductive element. As a result, the load circuit of the first aspect allows achieving an amplifier circuit that has a large output signal swing, wide bandwidth, low distortion and output impedance matching, when the load circuit is used in the amplifier circuit. In addition, the first aspect provides the advantage that the amplifier circuit may be operated under nominal voltage supply offered by the technology used for the amplifier circuit, when the load circuit of the first aspect is provided in the amplifier circuit. In particular, the load circuit of the first aspect allows to improve the amplifier circuit of Figures 2 and 3 with regard to bandwidth and output return loss, when the load circuit is used in the amplifier circuit. Thus, when the load circuit of the first aspect replaces the load circuit of the amplifier circuit of Figure 3, the low bandwidth and poor output return loss of the amplifier circuit of Figure 3 may be overcome. Since the load circuit of the first aspect is an active load circuit, as it is the case for the active load circuit of the amplifier circuit of Figure 3, the load circuit of the first aspect achieves the same advantages as the load circuit of Figure 3, described above, while improving the bandwidth and output return loss of the amplifier circuit when being used in the amplifier circuit as the load circuit.

The amplifier circuit may be referred to as “transconductance amplifier circuit”. The amplifier circuit may be a driver amplifier. That is, the amplifier circuit may be configured to amplify a signal for driving another circuit, such as an optical modulator of an electro-optical transmitter.

The load circuit may be referred to as “active load circuit” or “active load”. The N+l transistors of the load circuit may be referred to as “active load transistors”. The N inductive elements may be referred to as “inductive decoupling elements”. Namely, a function of the N inductive elements is decoupling the N+l transistors.

Each transistor may act as or may be a current source. Thus, the N+l transistors of the respective circuit branch may act as or may be a distributed current source of the respective circuit branch. The N+l transistors of the respective circuit branch may act as or may be a distributed active load of the respective circuit branch. Since N is one or more than one, the N+l transistors may be referred to as two or more transistors. As mentioned, above N is one or more than one (N > 1). In other words, N is an integer that is greater or equal to one. The number of transistors of a respective circuit branch is one more than the number of inductive elements of the respective circuit branch.

In an implementation form of the first aspect, each respective transistor of the N+l transistors is dimensioned such that (N+l) * R1 = R2. R1 is a ratio between channel width and channel length of the respective transistor and R2 is a ratio between channel width and channel length of a virtual single transistor that is suited for a supply voltage of the amplifier circuit.

Therefore, a parasitic output capacitance of each transistor of the N+l transistors of the respective circuit branch may approximate to a parasitic output capacitance of the virtual single transistor divided by the number of the N+l transistors. For example, the above mentioned virtual single transistor may correspond to the single transistor (transistor T3) of a respective circuit branch of the load circuit of the amplifier circuit of Figure 3.

In other words, the virtual single transistor of a respective circuit branch of the load circuit may be split into N+l transistors. The virtual single transistor represents a main bottleneck for an amplifier circuit, such as the amplifier circuit of Figure 3 in terms of bandwidth and output return loss. Because of splitting the virtual single transistor into N+l transistors, each transistor of the N+l transistors may be of lower size and less weight compared to the virtual single transistor that may be heavy and of a larger size in order to be suited for the supply voltage of the amplifier circuit. Using an appropriate design, an output characteristic impedance of a respective circuit branch of the load circuit may be tuned to be as close as possible to a wanted impedance matching of for example 50 Q or close to 50 Q. In such way, both the bandwidth and output return loss of the amplifier circuit may be significantly improved.

In an implementation form of the first aspect, each of the N+l transistors comprises a first terminal which is electrically connected with the supply terminal, a second terminal which is electrically connected with the respective node, and a third terminal which is a control terminal.

In an implementation form of the first aspect, each respective transistor of the N+l transistors is one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate terminal as the third terminal; or a bipolar junction transistor (BJT) having a base terminal as the third terminal.

Thus, common transistor types may be used for implementing the load circuit. That is, common technologies may be used for implementing an amplifier circuit comprising the load circuit of the first aspect as the load circuit. This allows an easy and cheap production of the load circuit and, thus, amplifier circuit. Each respective transistor of the N+l transistors may be a p-channel metal -oxide-semiconductor fieldeffect transistor (p-channel MOSFET), having a source terminal as the first terminal, a drain terminal as the second terminal and a gate terminal as the third terminal. Alternatively, each respective transistor of the N+l transistors may be a pnp-type bipolar junction transistor (pnp-type BJT), having an emitter terminal as the first terminal, a collector terminal as the second terminal, and a base terminal as the third terminal.

In an implementation form of the first aspect, each of the N inductive elements comprises an inductor or a transmission line.

For example, the transmission line may be a micro-strip transmission line. Thus, common electrical components may be used for decoupling the N+l transistors of the load circuit. This allows an easy and cheap production of the load circuit and, thus, amplifier circuit.

In an implementation form of the first aspect, a characteristic impedance of a synthetic transmission line formed by the N inductive elements and parasitic capacitances of the N+l transistors is impedance matched to a load electrically connectable to a terminal of the two terminals. This allows achieving an amplifier circuit with a significantly improved bandwidth and output return loss, when the load circuit is used in the amplifier circuit. The bandwidth and output return loss is improved with regard to the amplifier circuit of Figure 3.

The parasitic capacitances of the N+l transistors may be parasitic capacitances that are present at the N+l nodes due to the N+l transistors. In other words, the parasitic capacitances may be parasitic capacitances asserting to each of the N+l nodes. The parasitic capacitances of the N+l transistors may be referred to as parasitic output capacitances.

In an implementation form of the first aspect, the transconductance circuit has a single-ended topology and the load circuit comprises the one circuit branch. Therefore, the load circuit may be used in a single- ended amplifier circuit and, thus, may improve bandwidth and output return loss of a single-ended topology.

In an implementation form of the first aspect, the transconductance circuit has a differential topology and the load circuit comprises the two circuit branches. Therefore, the load circuit may be used in a differential amplifier circuit and, thus, may improve bandwidth and output return loss of a differential topology. The load circuit may be integrated in different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN).

In order to achieve the load circuit according to the first aspect of the disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

A second aspect of the disclosure provides an amplifier circuit comprising a transconductance circuit and the load circuit according to the first aspect, as described above. The transconductance circuit and the load circuit are electrically connected with each other.

In an implementation form of the second aspect, the transconductance circuit comprises one circuit branch or two circuit branches. Each circuit branch of the transconductance circuit may comprise a first transistor and a second transistor electrically connected in series. A first terminal of the first transistor may be electrically connected with a terminal of the two terminals of a respective circuit branch of the one or two circuit branches of the load circuit. A second terminal of the first transistor may be electrically connected with a first terminal of the second transistor. A control terminal of the second transistor may be electrically connected with an input terminal of the circuit branch of the transconductance circuit.

In an implementation form of the second aspect, the first transistor of the circuit branch is one of the following: a bipolar junction transistor (BJT) having a base terminal as a third terminal, the base terminal being a control terminal; or a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate terminal as a third terminal, the gate terminal being a control terminal.

Thus, common transistor types may be used for implementing the transconductance circuit of the amplifier circuit. That is, common technologies may be used for implementing the amplifier circuit. This allows an easy and cheap production of the amplifier circuit.

The first transistor of the circuit branch may be an npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal and an emitter terminal as the second terminal. Alternatively, the first transistor of the circuit branch may be an n-channel metal-oxide-semiconductor field-effect transistor (n-channel MOSFET), having a drain terminal as the first terminal and a source terminal as the second terminal. In an implementation form of the second aspect, the second transistor of the circuit branch is one of the following: a bipolar junction transistor (BJT) having a base terminal as the control terminal; or a metal- oxide-semiconductor field-effect transistor (MOSFET) having a gate terminal as the control terminal.

The second transistor of the circuit branch may be an npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal and a base terminal as the control terminal. Alternatively, the second transistor of the circuit branch may be an n-channel metal-oxide- semiconductor field-effect transistor (n-channel MOSFET), having a drain as the first terminal and a gate terminal as the control terminal.

In an implementation form of the second aspect, the transconductance circuit comprises the one circuit branch of the transconductance circuit and the load circuit comprises the one circuit branch of the load circuit. A terminal of the two terminals of the circuit branch of the load circuit may be electrically connected with the first terminal of the first transistor of the circuit branch of the transconductance circuit, and a termination impedance may be electrically connected with the terminal of the two terminals of the circuit branch of the load circuit.

In an implementation form of the second aspect, the transconductance circuit comprises the two circuit branches of the transconductance circuit and the load circuit comprises the two circuit branches of the load circuit. A terminal of the two terminals of a first circuit branch of the two circuit branches of the load circuit may be electrically connected with the first terminal of the first transistor of a first circuit branch of the two circuit branches of the transconductance circuit. A terminal of the two terminals of a second circuit branch of the two circuit branches of the load circuit may be electrically connected with the first terminal of the first transistor of a second circuit branch of the two circuit branches of the transconductance circuit. A termination impedance may be electrically connected between the terminal of the two terminals of the first circuit branch of the load circuit and the terminal of the two terminals of the second circuit branch of the load circuit.

The amplifier circuit may be integrated in different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN). The above description with regard to the load circuit according to the first aspect is correspondingly valid for the amplifier circuit of the second aspect.

The amplifier circuit of the second aspect and its implementation forms and optional features achieve the same advantages as the load circuit of the first aspect and its respective implementation forms and respective optional features.

In order to achieve the amplifier circuit according to the second aspect of the disclosure, some or all of the implementation forms and optional features of the second aspect, as described above, may be combined with each other.

A third aspect of the disclosure provides an electro-optical transmitter comprising an optical modulator, and an amplifier circuit according to the second aspect, as described above. The amplifier circuit is configured to amplify a signal for driving the optical modulator.

The above description with regard to the load circuit according to the first aspect is correspondingly valid for the electro-optical transmitter of the third aspect.

The electro-optical transmitter of the third aspect and its implementation forms and optional features achieve the same advantages as the load circuit of the first aspect and its respective implementation forms and respective optional features.

In order to achieve the electro-optical transmitter according to the third aspect of the disclosure, some or all of the implementation forms and optional features of the third aspect, as described above, may be combined with each other.

It has to be noted that all devices, elements, units and means described in the present application could be implemented in software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms of the present disclosure will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Figure 1 shows two examples of an amplifier circuit;

Figure 2 shows an example of an amplifier circuit;

Figure 3 shows an example of an amplifier circuit;

Figure 4 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit;

Figure 5 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit;

Figure 6 shows an amplifier circuit according to an embodiment of the present disclosure;

Figure 7 shows an amplifier circuit according to an embodiment of the present disclosure;

Figure 8 shows an amplifier circuit according to an embodiment of the present disclosure;

Figure 9 shows an example of a part of a load circuit according to an embodiment of the present disclosure;

Figure 10 shows an example of an equivalent circuit for a load circuit according to an embodiment of the present disclosure;

Figure 11 shows an example of total harmonic distortion versus peak-to-peak differential output voltage for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and a differential amplifier circuit according the second aspect of the present disclosure; Figure 12 shows an example of normalized gain versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure;

Figure 13 shows an example of output return loss versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure; and

Figure 14 shows an example of an electro-optical transmitter according to an embodiment of the present disclosure.

In the Figures, corresponding elements are labeled with the same reference sign.

DETAILED DESCRIPTION OF EMBODIMENTS

Figure 4 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit. The load circuit of Figure 4 is an example of the load circuit according to the first aspect. Thus, the above description of the load circuit according to the first aspect is correspondingly valid for the load circuit of Figure 4.

As shown in Figure 4, the load circuit 3 comprises a supply terminal 8 and one circuit branch 3a. A supply voltage VDD may be provided to the supply terminal 8. The circuit branch 3 a comprises two terminals 5a and 5a’, N inductive elements 6, N+l nodes 7 and N+l transistors 4. N is one or more than one (N > 1). The N inductive elements 6 and N+l nodes 7 are electrically connected in series between the two terminals 5a and 5a’, wherein any two successive nodes of the N+l nodes are electrically connected to each other via a respective inductive element 6 of the N inductive elements 6. Each node of the N+l nodes 7 is electrically connected to the supply terminal 8 via a respective transistor of the N+l transistors 4. In the example of Figure 4 the number N is equal to two (N = 2). Thus, the circuit branch 3a comprises two inductive elements 6, three nodes 7 and three transistors 4. This is only by way of example and not limiting the present disclosure. The number N may equal to one (N = 1) or may be equal to or greater than two. In other words, the number N may be equal to or greater than one (N > 1).

As shown in Figure 4, the inductive elements 6 of the circuit branch 3a decouple the transistors 4 of the circuit branch 3 a. Each inductive element of the N inductive elements 6 may be or may comprise an inductor or a transmission line. For example, each inductive element may be or may comprise a microstrip transmission line.

Further, as shown in Figure 4, each transistor of the N+l transistors 4 comprises a first terminal 4a which is electrically connected with the supply terminal 8, a second terminal 4b which is electrically connected with the respective node 7 and a third terminal 4c which is a control terminal. According to the example of Figure 4, each transistor of the N+l transistors 4 is a p-channel metal-oxide-semiconductor fieldeffect transistor (p-channel MOSFET) having a source terminal as the first terminal 4a, a drain terminal as the second terminal 4b and a gate terminal as the third terminal (control terminal). This is only by way of example and does not limit the present disclosure. Thus, the transistors 4 may be implemented by a different transistor type. For example, each of the N+l transistors 4 may be a pnp-type bipolar junction transistor (pnp-type BJT), having an emitter terminal as the first terminal 4a, a collector terminal as the second terminal 4b, and a base terminal as the third terminal 4c. The transistors 4 may be implemented according to different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN). For example, this may be the case when implementing the load circuit 3 as part of an amplifier circuit comprising a transconductance circuit besides the load circuit 3. Examples of such an amplifier circuit are shown in Figures 6 to 8.

The load circuit 3 of Figure 4 is an active load circuit. The circuit branch 3a of the load circuit 3 of Figure 4 differs from each circuit branch of the active load circuit 3 of Figure 3 in that the single transistor T3 of the respective circuit branch of the load circuit 3 of Figure 3 is replaced by N+l transistors 4 that are decoupled from each other by N decoupling elements 6. As a result, a ratio R1 between channel width W and channel length L of each transistor of the N+l transistors 4 of the load circuit 3 of Figure 4 may equal to a ratio R2 between channel width W_s and channel length L_s of the single transistor T3 of each circuit branch of the load circuit of Figure 3 divided by the number N+l of the transistors 4 of the load circuit 3 of Figure 4 (R1 = (W/L); R2 = W_s/L_s and R1 = R2/(N+1), wherein N > 1). In other words, the ratio R2 is equal to the ratio R1 multiplied by N+l (R1*(N+1) = R2).

Each of the N+l transistors 4 contributes to a parasitic capacitance CPAR- In case the N+l transistors 4 are p-channel MOSFETs the parasitic capacitance CPAR of the respective transistor 4 comprises the intrinsic drain capacitance of the respective transistor 4, the capacitance between the drain and source terminal of the respective transistor 4, the capacitance between the drain and gate terminal of the respective transistor 4, and the parasitic capacitance of the layout interconnects of the respective transistor 4. The parasitic capacitance CPAR of the respective transistor 4 multiplied by the number N+l of transistors 4 of the load circuit 3 of Figure 4 may equal to the parasitic capacitance CPARI of the single transistor T3 of a respective circuit branch of the load circuit 3 of Figure 3 ((N+1)*CPAR = CPARI or CPAR = CPARI/(N+1)).

The load circuit of Figure 4 may be used in an amplifier circuit having a single-ended topology. An example of an amplifier circuit having a single-ended topology is shown in Figure 6.

Figure 5 shows a load circuit according to an embodiment of the present disclosure for an amplifier circuit. The load circuit 3 of Figure 5 differs from the load circuit 3 of Figure 4 in that the load circuit 3 of Figure 5 comprises two circuit branches 3a and 3b, whereas the load circuit 3 of Figure 4 comprises one circuit branch 3a. The above description of the load circuit 3 of Figure 4 is correspondingly valid for the load circuit 3 of Figure 5. In particular, the description of the circuit branch 3a of the load circuit 3 of Figure 4 is valid for each circuit branch 3a or 3b of the load circuit 3 of Figure 5.

Thus, as shown in Figure 5, a first circuit branch 3a of the two circuit branches 3a and 3b of the load circuit 3 comprises two terminals 5a and 5a’, N inductive elements 6, N+l nodes 7 and N+l transistors 4, wherein N is one or more than one. The N inductive elements 6 and the N+l nodes 7 are electrically connected in series between the two terminals 5a and 5a’, as shown in Figure 5. A second circuit branch 3b of the two circuit branches 3a and 3b of the load circuit 3 comprises two terminals 5b and 5b’, N inductive elements 6, N+l nodes 7 and N+l transistors 4, wherein N is one or more than one. The N inductive elements 6 and the N+l nodes 7 are electrically connected in series between the two terminals 5b and 5b’, as shown in Figure 5.

The load circuit of Figure 5 may be used in an amplifier circuit having a differential topology. Examples of an amplifier circuit having a differential topology are shown in Figures 7 and 8.

Figure 6 shows an amplifier circuit according to an embodiment of the present disclosure. The amplifier circuit of Figure 6 is an example of the amplifier circuit according to the second aspect. Thus, the above description of the amplifier circuit according to the second aspect is correspondingly valid for the amplifier circuit of Figure 6.

As shown in Figure 6, the amplifier circuit 1 comprises a transconductance circuit 2 and a load circuit 3 that are electrically connected with each other. The amplifier circuit 1 has a single-ended topology and, thus, the transconductance circuit 2 comprises one circuit branch 2a and the load circuit 3 comprises one circuit branch 3a. Thus, the amplifier circuit 1 comprises one circuit branch. The load circuit 3 of the amplifier circuit 1 of Figure 6 corresponds to the load circuit 3 of Figure 4 and, thus, the above description of Figure 4 is valid for the load circuit 3 of the amplifier circuit 1 of Figure 6. The circuit branch 2a of the transconductance circuit 2 may comprise a first transistor 9 and a second transistor 10 electrically connected in series. A first terminal 9a of the first transistor 9 is electrically connected with a terminal 5a’ of the two terminals 5a and 5a’ of the circuit branch 3a of the load circuit 3. A second terminal 9b of the first transistor 9 is electrically connected with a first terminal 10a of the second transistor 10. A control terminal 10c of the second transistor 10 is electrically connected with an input terminal I la of the circuit branch 2a of the transconductance circuit 2. The input terminal I la represents an input terminal of the amplifier circuit 1. A signal (voltage) may be applied to the input terminal I la in order to be amplified. The supply terminal 8 of the load circuit 3 represents a supply terminal of the amplifier 1. A supply voltage VDD may be applied to the supply terminal 8 in order to electrically supply the amplifier circuit 1 enabling the amplification function of the amplifier circuit 1. A second terminal 10b of the second transistor 10 may be electrically connected to ground. The terminal 5a of the two terminals 5a and 5a’ of the circuit branch 3a of the load circuit 3 may be electrically connected to or may represent an output terminal of the amplifier circuit 1. The terminal 5 a is a terminal of the two terminals 5a and 5a’ of the circuit branch 3a of the load circuit 3, to which the transconductance circuit 2 is not electrically connected. At the output terminal an amplified signal (amplified voltage) may be provided, which corresponds to the signal (voltage), applied to the input terminal of the amplifier circuit 1 , after being amplified by the amplifier circuit 1.

The amplification function of the amplifier circuit 1 may be controlled by applying control signals to the control terminals of the N+l transistors 4 of the load circuit 3 and a control terminal 9c of the first transistor T1 of the circuit branch 2a of the transconductance circuit 2. Such a control is known and, thus, not further described herein. The control terminal 9c of the first transistor T1 may be electrically connected to a DC bias voltage VCASC- The present disclosure focuses on the structure of the amplifier circuits enabling an amplifier circuit with the above described advantages. The control terminal 9c of the first transistor 9 is a third terminal of the first transistor 9. The control terminal 10c of the second transistor 10 is a third terminal of the second transistor 10.

According to the example of Figure 6, the first transistor 9 of the circuit branch 2a of the transconductance circuit 2 is a npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal 9a, an emitter terminal as the second terminal 9b, and a base terminal as the control terminal 9c (third terminal). This is only by way of example and does not limit the present disclosure. Thus, the first transistor 9 may be implemented by a different transistor type. For example, the first transistor 9 of the circuit branch 2a of the transconductance circuit 2 may be an n-channel metal- oxide-semiconductor field-effect transistor (n-channel MOSFET), having a drain terminal as the first terminal 9a, a source terminal as the second terminal 9b and a gate terminal as the control terminal 9c (third terminal). This is exemplarily shown in Figure 8 for a differential topology of the amplifier circuit, wherein the first transistor 9 of each circuit branch 2a and 2b of the transconductance circuit 2 is a n- channel MOSFET.

Further, according to the example of Figure 6, the second transistor 10 of the circuit branch 2a of the transconductance circuit 2 is an n-channel metal-oxide-semiconductor field-effect transistor (n-channel MOSFET), having a drain as the first terminal 10a, a source as the second terminal 10b and a gate terminal as the control terminal 10c (third terminal). This is only by way of example and does not limit the present disclosure. Thus, the second transistor 10 may be implemented by a different transistor type. For example, the second transistor 10 of the circuit branch 2a of the transconductance circuit 2 may be an npn-type bipolar junction transistor (npn-type BJT), having a collector terminal as the first terminal 10a, an emitter terminal as the second terminal 10b and a base terminal as the control terminal 10c (third terminal).

The first transistor 9 and the second transistor 10 of the circuit branch 2a of the transconductance circuit 2 may be implemented according to different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN). Thus, the transistors of the amplifier circuit 1 comprising the first transistor 9 and second transistor 10 of the circuit branch 2a and the N+l transistors 4 of the load circuit 3 may be implemented according to different integrated circuit (IC) complementary technologies including (but not limited to) the aforementioned technologies.

As shown in Figure 6, a termination impedance 12 may be electrically connected with the terminal 5a’ of the two terminals 5, 5a’of the circuit branch 3a of the load circuit 3. Optionally, a series connection of a capacitor 13 and the termination impedance 12 (as exemplarily shown in Figure 6) may be electrically connected to the terminal 5 a’ of the circuit branch 3 a of the load circuit 3.

Figure 7 shows an amplifier circuit according to an embodiment of the present disclosure. The amplifier circuit 1 of Figure 7 differs from the amplifier circuit 1 of Figure 6 in that the amplifier circuit 1 of Figure 7 has a differential topology, whereas the amplifier circuit 1 of Figure 6 has a single-ended topology. Therefore, the transconductance circuit 2 of the amplifier circuit 1 of Figure 7 comprises two circuit branches 2a and 2b, whereas the transconductance circuit 2 of the amplifier circuit 1 of Figure 6 comprises one circuit branch 2a. The above description of the transconductance circuit 2 of Figure 6 is correspondingly valid for the transconductance circuit 2 of Figure 7. In particular, the description of the circuit branch 2a of the transconductance circuit 2 of Figure 6 is valid for each circuit branch 2a and 2b of the transconductance circuit 2 of Figure 7. The load circuit 3 of Figure 7 corresponds to the load circuit 3 of Figure 5 and, thus, the above description of Figures 4 and 5 is valid for the load circuit 3 of the amplifier circuit 1 of Figure 7.

Thus, as shown in Figure 7, a first circuit branch 2a of the two circuit branches 2a and 2b of the transconductance circuit 2 comprises a first transistor 9 and a second transistor 10 electrically connected in series. The first terminal of the first transistor 9 of the first circuit branch 2a is electrically connected to a terminal 5a’ of the two terminals 5a, 5a’ of a first circuit branch 3a of the two circuit branches 3a and 3b of the load circuit 3. A second circuit branch 2b of the two circuit branches 2a and 2b of the transconductance circuit 2 comprises a first transistor 9 and a second transistor 10 electrically connected in series. The first terminal of the first transistor 9 of the second circuit branch 2b is electrically connected to a terminal 5b’ of the two terminals 5b and 5b’ of a second circuit branch 3b of the two circuit branches 3a and 3b of the load circuit 3.

A control terminal of the second transistor 10 of the first circuit branch 2a is electrically connected with an input terminal 1 la of the first circuit branch 2a of the transconductance circuit 2. A control terminal of the second transistor 10 of the second circuit branch 2b is electrically connected with an input terminal 11b of the second circuit branch 2b of the transconductance circuit 2. The two input terminals I la and 11b represent input terminals of the amplifier circuit 1 having a differential topology. A signal (voltage) may be applied to the amplifier circuit 1 for amplification by applying respective voltages to the input terminals I la and 11b. For example, the signal may be input to the amplifier circuit 1 by applying voltages VIN,P and VIN,M to the input terminals Ila and 11b, respectively. The terminal 5a of the first circuit branch 3 a of the load circuit 3 may be electrically connected with or may represent a first output terminal of the amplifier circuit 1. The terminal 5b of the second circuit branch 3b of the load circuit 3 may be electrically connected with or may represent a second output terminal of the amplifier circuit 1. The terminals 5a and 5b of the load circuit 3 are terminals to which the transconductance circuit 2 is not electrically connected. At the output terminals of the amplifier circuit 1 an amplified signal (amplified voltage) may be provided, which corresponds to the signal (voltage), applied to the input terminals I la and 11b of the amplifier circuit 1, after being amplified by the amplifier circuit 1. For example, the amplified signal may be provided at the output terminals of the amplifier circuit 1 by providing voltages VO,M and Vo,p at the terminals 5a and 5b of the load circuit 3, respectively.

As shown in Figure 7, a termination impedance 14 may be electrically connected between the terminal 5a’ of the first circuit branch 3a of the load circuit 3 and the terminal 5b’ of the second circuit branch 3b of the load circuit 3.

Further, each of the N inductance elements 6 of each circuit branch 3a and 3b of the load circuit 3 may comprise or may be a transmission line (not shown in Figure 7). For example, each of the N inductance elements 6 may comprise or may be a micro-strip transmission line. This is only by way of example and, thus, the N inductance elements 6 of each circuit branch 3a and 3b may be differently implemented. For example, each of the N inductance elements 6 of each circuit branch 3a and 3b of the load circuit 3 may comprise or may be an inductor.

Figure 8 shows an amplifier circuit according to an embodiment of the present disclosure. The amplifier circuit 1 of Figure 8 differs from the amplifier circuit 1 of Figure 7 in that the first transistor 9 of each circuit branch 2a and 2b of the transconductance circuit 2 is a MOSFET, whereas according to the example of Figure 7 the first transistor 9 of each circuit branch 2a and 2b of the transconductance circuit 2 is a BJT. Therefore, the above description of Figures 6 and 7 is correspondingly valid for the amplifier circuit 1 of Figure 8.

The circuit branch 2a of the transconductance circuit 2 of the amplifier circuit 1 of Figure 6 and each of the circuit branches 2a and 2b of the transconductance circuit 2 of the circuit amplifier circuit 1 of Figures 7 and 8 comprise cascoded transconductors in the form of the first transistor 9 and the second transistor 10. In the examples of Figures 7 and 8, an input differential pair of the amplifier circuit is formed by the second transistors 10, which are by way of example n-channel MOSFETs. The control terminals (e.g. gate terminals) of these second transistors 10 are connected to the input terminals I la and 11b of the transconductance circuit 2 and, thus, of the amplifier circuit 1. To these input terminals I la and 11b complementary input signals (voltages) for the amplifier circuit 1 may be applied. In Figures 7 and 8, IBIAS/2 represents the bias current of each of the two circuit branches 2a and 2b of the transconductance circuit 2. This bias current IBIAS/2 may be set by providing a proper input DC commonmode voltage to the amplifier circuit 1 (i.e. to the input terminals I la and 1 lb). The two first transistors 9 of the two circuit branches 2a and 2b of the transconductance circuit 2 of Figures 7 and 8 represent cascodes, whose control terminals 9c may be biased at a voltage VCASC- The termination impedance 14, which is differential in the examples of Figures 7 and 8, may be set to e.g. 100 Q or close to 100 Q in order to ensure differential output impedance matching from low frequency.

In Figures 7 and 8, each circuit branch 3a and 3b of the load circuit 3 (active load circuit) comprises N+l transistors 4, each of which is N+l -times smaller than the single transistor T3 of each circuit branch of the load circuit 3 of the amplifier circuit 1 of Figure 3. Each of the N+l transistors 4 of a respective circuit branch may comprise an aspect ratio of (W_S/L_S)/(N+1), where W_s and L_s denote the channel width and the channel length of the transistor T3 of the respective circuit branch of the amplifier circuit 1 of Figure 3, respectively. The total bias current carried by all of the N+l respective transistors 4 within each of the two circuit branches 3a and 3b of the load circuit 3 is equal to IBIAS/2. This bias current IBIAS/2 may be set by providing a proper DC voltage VGEN to the control terminals of the N+l transistors 4 of the circuit branches 3a and 3b of the load circuit 3. As outlined already above, the N+l transistors 4 of each circuit branch 3a and 3b of the load circuit 3 are separated or decoupled by inductive elements 6 (may be referred to as inductive decoupling elements), which may be for example transmission lines or inductors. The term “transmission line segment” may be used as a synonym for the term “transmission line”.

Figure 9 shows an example of a part of a load circuit according to an embodiment of the present disclosure. Especially, Figure 9 exemplarily shows the part of the N inductive elements and N+l nodes of a circuit branch of a load circuit according to an embodiment of the disclosure. This circuit branch may correspond to the circuit branch 3a of the load circuit 3 of Figures 4 and 6 or each of the two circuit branches 3a and 3b of the load circuit 3 of Figures 5, 7 and 8. Thus, the number N of inductive elements 6 equaling to two (N = 2) in the example of Figure 9 is only by way of example. N may be one or greater than one (N > 1).

In the example of Figure 9 it is assumed (only by way of example and, thus, not limiting the present disclosure) that the inductive elements 6 are transmission lines, each with length f and specific inductance L’ (i.e. inductance per unit length). In Figure 9 only the parasitic capacitance CPAR of each of the N+l transistors 4 is shown. The parasitic capacitance CPAR of each of the N+l transistors 4 equals to the parasitic capacitance CPARI of a single transistor (virtual transistor), such as the single transistor T3 of a respective circuit branch of the amplifier circuit 1 of Figure 3, divided by the number N+l of transistors 4 that are used instead of the single transistor (CPAR = CPARI/(N+1)). Together, as exemplified by Figure 9, the N+l transistors 4 and the transmission lines 6 form a “synthetic” transmission line with a single-ended characteristic impedance Zo equal to:

By maximizing the product (N+l)Tthe single-ended characteristic impedance Zo of the respective circuit branch of the load circuit 3 may be made sufficiently high. The total length of the synthetic transmission line (i.e. of the distributed active load circuit formed by the N+l transistors 4, N inductive elements 6 and N+l nodes 7 of a respective circuit branch of the load circuit 3) may be approximated by the product NT. For this approximation it is considered that the number of inductive elements (i.e. transmission lines in case of Figure 9) is N and the N+l transistors are much smaller than a transmission line segment. The distributed active load circuit may be referred to as distributed current source or distributed current generator. For example the single-ended characteristic impedance Zo of the respective circuit branch of the load circuit 3 may be made as close as possible to 50 Q single-ended. This allows to significantly improve in the amplifier circuits of Figures 6, 7 and 8 both the output return loss and the bandwidth of the respective amplifier circuit topology. The same applies to the case, in which the N+l transistors 4 of each circuit branch of the load circuit 3 are separated by inductors instead of transmission lines (i.e. the N inductive elements are inductors). In such case, the N+l transistors 4 and the inductors 6 form a “synthetic” transmission line with a single-ended characteristic impedance Zo equal to:

wherein Lo is the inductance of each of the N inductors 6 between adjacent transistors of the N+l transistors 4. The use of inductors, instead of transmission lines, as inductive elements 4 contributes to form a synthetic transmission line together with the N+l transistors 4.

Figure 10 shows an example of an equivalent circuit for a load circuit according to an embodiment of the present disclosure. In the following, it assumed that the load circuit 3 is part of an amplifier circuit comprising a transconductance circuit 2, such as the amplifier circuit of e.g. Figure 7. Further, it is assumed that an external load 19 is connected to the amplifier circuit and, thus, to the load circuit 3, wherein the external load 19 has an external load impedance ROUT- AS shown in Figure 10 (a), the more the characteristic impedance Zo of the synthetic transmission line (which may be formed either by the N+l transistors 4 and N transmission lines 6 as shown in Figure 9 or N+l transistors 4 and N inductors 6) is closer to 50 Q, the lesser the impact of CPARI is on the load circuit 3. For example, under the assumption that the external load impedance ROUT of the external load 19 and the internal termination impedance RTERM are matched (e.g. to approximately 50 Q and 100 Q, respectively), the impedance seen by the transconductance circuit 2 (from a viewpoint towards the external load 19) may be the external load impedance ROUT of the external load 19. In such a case, it may be said that the (internal) load circuit 3 would be practically almost ideal. In other words, in such a case it may be said that the load circuit 3 would be practically invisible for the transconductance circuit 2 (from a viewpoint towards the external load 19). That is, for the transconductance circuit 2, the load circuit 3 does not represent an additional external load in addition to the actual external load 19. The above means that the output time constant may be much lower than the time constant of the load circuit 3 of Figure 3 (i.e. ROUT’CPARI) or, in other terms that the bandwidth of the amplifier circuit 1 according to Figures 6, 7 and 8 may be wider compared to the bandwidth of the amplifier circuit 1 of Figure 3.

Under the same assumptions, as shown in Figure 10 (b), the amplifier circuit’s differential output impedance Zour.diff may be equal to the internal differential termination RTERM, without any impact from CPARI, thus resulting in an ideally perfect output return loss. In reality, because of other topological, technological and geometrical constraints, Zo will not be perfectly matched to RTER /2 and ROUT (e.g. close to 50 Q) and, thus, the amplifier circuit’s bandwidth and output return loss will not be infinitely wide and low, respectively. Nevertheless, the bandwidth and output return loss of the amplifier circuit 1 of Figures 6, 7 and 8 significantly enhance those of the amplifier circuits of Figures 2 and 3. This is also shown in Figures 12 and 13

Thus, a main idea of the load circuits 3 and, thus, amplifier circuits 1 according to examples of the present disclosure is to “absorb” the heavy load parasitic capacitance (CPARI = (N+1)*CPAR) due to N+l transistors 4 of a respective circuit branch of the load circuit 3 into the N inductive elements (e.g. transmission liens or inductors), forming a “synthetic” transmission line with characteristic impedance as close as possible to a wanted impedance matching with a load electrically connectable to the load circuit 3 and, thus, the amplifier circuit 1. The desired impedance matching may be for example impedance matching of 50 Q or close to 50 Q. In such way, both the amplifier circuit’s bandwidth and output return loss significantly improves. The load circuits and amplifier circuits according to the present disclosure allow operating under a nominal supply voltage (e.g. 3.3V in 55nm BiCMOS). Therefore, the topologies of the load circuits 3 and, thus, amplifier circuits 1 shown in Figures 4 to 8 do not introduce penalty in terms of power consumption and, moreover, they do not require the use of an additional (higher) supply voltage, which may not even be available within a system in which the load circuit or the amplifier circuit is used. In addition, the load circuits and amplifier circuits according to the present disclosure feature low design complexity.

The above description with regard to differential topologies of the amplifier circuit 1 and, thus, of the transconductance circuits 2 and load circuits 3 is correspondingly valid for a single-ended topology of the amplifier circuit 1 and, thus, of the transconductance circuits 2 and load circuits 3, as exemplarily shown in Figure 4.

To demonstrate the advantage of the amplifier circuits according to the present disclosure with regard to the amplifier circuits of Figures 2 and 3, the performance of the amplifier circuits of Figures 2 and 3 and the amplifier circuit of e.g. Figure 7 is compared. For the sake of comparison, the transistors of the transconductance circuits 2 are identical among the three topologies. Similarly, the resistance of the resistors RL of the amplifier circuit of Figure 2 is equal to half the resistance of the resistor RTERM of the amplifier circuit of Figure 3 and equal to half the resistance of the termination impedance 14 of amplifier circuit of Figure 7 (RL = RTERM/2 = (termination impedance)/2 = e.g. 50Q). As a result, the three topologies (of Figure 2, 3 and 7) being compared are assumed to exhibit the same voltage gain.

Figure 11 shows an example of total harmonic distortion versus peak-to-peak differential output voltage for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and a differential amplifier circuit according the second aspect of the present disclosure. In Figure 11, the line LI (having squares) shows the performance of the amplifier circuit of Figure 2 and the line L2 (having triangles) shows the performance of the amplifier circuit of Figure 3 and the amplifier circuit of Figure 7.

Figure 11 shows the total harmonic distortion (THD) versus the output peak-to-peak differential voltage amplitude for a differential input sinewave at e.g. 1GHz. The amplifier circuit of Figure 3 and the amplifier circuit of Figure 7 perform equally, given that they exhibit the same output voltage range. They appreciably outperform the amplifier circuit of Figure 2. For example, they exhibit about 7% lower THD at 3.5VPPD output (where “VPPD” stands for “Volt peak-to-peak differential”) or, for the same THD of 3.2%, they ensure a 1.3VPPD larger output signal.

Figure 12 shows an example of normalized gain versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure. In Figure 12, the line LI (having squares) shows the performance of the amplifier circuit of Figure 2, the line L2 (having diamonds) shows the performance of the amplifier circuit of Figure 3 and the line L3 (having triangles) shows the performance of the amplifier circuit of Figure 7.

Figure 12 shows the three normalized transfer functions (normalized in terms of their gain at 1GHz, set to OdB for the sake of illustration). The detrimental effect of the big parasitic capacitance CPARI of the transistors T3 of the load circuit 3 of the amplifier circuit 1 of Figure 3 is visible in the form of a very narrow-band transfer function, which presents a -3dB bandwidth of nearly 17GHz (and 30GHz at -6dB). By properly splitting the single transistor T3 of a respective circuit branch of the active load circuit 3 of Figure 3 into smaller units (i.e. the N+l transistors 4) and isolating them using inductive elements (e.g. N transmission lines or N inductors), thus forming the above-mentioned synthetic transmission line, the load circuit 3 of the amplifier circuit 1 of Figure 7 significantly enhances the bandwidth performance of the amplifier circuit of Figure 3, reaching a -3dB bandwidth of about 57GHz (and 98GHz at -6dB). The amplifier circuit of Figure 7 also outperforms the amplifier circuit of Figure 2 with regard to bandwidth. Because of the aforementioned reason, the output return loss of the amplifier circuit of Figure 7 is also significantly better than that of the amplifier circuits of Figures 2 and 3, as shown in Figure 13.

Figure 13 shows an example of output return loss versus frequency for the amplifier circuit of Figure 2, the amplifier circuit of Figure 3 and an amplifier circuit according the second aspect of the present disclosure. In Figure 13, the line LI (having squares) shows the performance of the amplifier circuit of Figure 2, the line L2 (having diamonds) shows the performance of the amplifier circuit of Figure 3 and the line L3 (having triangles) shows the performance of the amplifier circuit of Figure 7.

Therefore, the load circuit proposed by the present disclosure allows increasing the output voltage swing of an amplifier circuit, such as the amplifier circuit of Figure 2 or 3, for a given total harmonic distortion when the load circuit of the present disclosure is used in the amplifier circuit. Moreover, using the load circuit in an amplifier circuit, such as the amplifier circuit of Figure 2 or 3, has no penalties in terms of bandwidth, output impedance matching and power consumption.

Figure 14 shows an example of an electro-optical transmitter according to an embodiment of the present disclosure. The electro-optical transmitter 15 comprises an amplifier circuit 1 and an optical modulator 18, wherein the amplifier circuit 1 is configured to amplify a signal for driving the optical modulator 18. The amplifier circuit 1 is an amplifier circuit according to the second aspect of the present disclosure. Thus, the amplifier circuit 1 may be implemented in line with the description of Figures 6, 7 and 8. Since the amplifier circuit 1 is used in the electro-optical transmitter 15 for amplifying a driver signal for driving the optical modulator 18, the amplifier circuit 1 is a driver amplifier. As shown in Figure 14 the amplifier circuit 1 may be part of an analog integrated circuit 17 (analog IC). The analog IC 17 and, thus, the amplifier circuit 1 may be implemented using different integrated circuit (IC) complementary technologies including (but not limited to) bipolar complementary metal oxide semiconductor (BiCMOS), complementary metal oxide semiconductor (CMOS), and Silicon Carbide (SiC) and III-V semiconductors, such as Gallium Arsenide (GaAs) or Gallium Nitride (GaN). The optical modulator 18 may be a Mach-Zehnder modulator (MZM), such as a silicon photonics (SiPh) MZM, an electroabsorption modulated laser (EML) or any other known optical modulator.

The electro-optical transmitter 15 may comprise an optional digital integrated circuit 16 (digital IC). The digital IC 16 may provide an analog signal to the amplifier circuit 1 for being amplified so that the amplifier circuit 1 may output the amplified analog signal as a signal for driving the optical modulator 18. The digital IC 16 may comprise a digital signal processor 16a (DSP) and a digital-to-analog- con verter 16b (DAC).

The electro-optical transmitter 15 is an example of a radio-frequency integrated circuit. Thus, the amplifier circuit 1 of the present disclosure (e.g. the amplifier circuit 1 of Figures 6 to 8) may be used in radio-frequency integrated circuits (RFIC). The amplifier circuit 1 of the present disclosure may represent a broadband amplifier circuit for optical and wireline communications. The ever increasing demand for high data-rates in wireline, wireless and optical communications requests RFICs with broader signal bandwidths. In addition, the increasing complexity of data modulation schemes further demands high quality signals without penalty in terms of power consumption. In the specific example of broadband radio-frequency transmitters for optical communications, the driver amplifier (i.e. the amplifier circuit) plays a critical role. Namely, the amplifier circuit may represent the interface between the digital domain (e.g. the digital signal processor (DSP) and digital-to-analog-converter (DAC)) and the optical modulator, as exemplarily shown in Figure 14. Due to its beneficial characteristics, outlined above, the amplifier circuit of the present disclosure is suitable to be used radio-frequency integrated circuits (RFIC), e.g. in electro-optical transmitters.

For example, the amplifier circuit of the present disclosure (e.g. the one of Figures 6, 7 and 8) may feature an impedance matched output (e.g. 50 Q or close to 50 Q in case of a single-ended topology of the amplifier circuit or e.g. 100 Q or close to 100 Q in case of a differential topology of the amplifier circuit) so as to offer compatibility to a wide range of optical modulators. Thus, the amplifier topologies proposed by the present disclosure are suitable for broadband fully-integrated optical modulators and wireline driver amplifiers requiring low distortion, large output signal swing and output impedancematching.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed subject-matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A load circuit (3) for use in an amplifier circuit (1), the amplifier circuit (1) comprising a transconductance circuit (2), the load circuit (3) comprising a supply terminal (8) and one circuit branch (3a) or two circuit branches (3a, 3b), wherein each circuit branch comprises: two terminals (5a, 5a’; 5b, 5b’),

N inductive elements (6) and N+l nodes (7), wherein N is one or more than one, wherein the N inductive elements (6) and the N+l nodes (7) are electrically connected in series between the two terminals (5a, 5a’; 5b, 5b’), wherein any two successive nodes of the N+l nodes (7) are electrically connected to each other via a respective inductive element of the N inductive elements (6), and

N+l transistors (4); wherein each of the N+l nodes (7) is electrically connected to the supply terminal (8) via a respective transistor of the N+l transistors (4).

2. The load circuit (3) according to claim 1, wherein each respective transistor of the N+l transistors (4) is dimensioned such that

(N+l) * R1 = R2 wherein R1 is a ratio between channel width and channel length of the respective transistor (4) and R2 is a ratio between channel width and channel length of a virtual single transistor (T3) that is suited for a supply voltage (VDD) of the amplifier circuit (1).

3. The load circuit (3) according to any one of the previous claims, wherein each of the N+l transistors (7) comprises: a first terminal (4a) which is electrically connected with the supply terminal (8), a second terminal (4b) which is electrically connected with the respective node (7), and a third terminal (4c) which is a control terminal.

4. The load circuit (3) according to claim 3, wherein each respective transistor of the N+l transistors (4) is one of the following: a metal -oxide-semiconductor field-effect transistor, MOSFET, having a gate terminal as the third terminal (4c); or a bipolar junction transistor, BJT, having a base terminal as the third terminal (4c).

5. The load circuit (3) according to any one of the previous claims, wherein each of the N inductive elements (6) comprises an inductor or a transmission line.

25 The load circuit (3) according to any one of the previous claims, wherein a characteristic impedance of a synthetic transmission line formed by the N inductive elements (6) and parasitic capacitances of the N+l transistors (4) is impedance-matched to a load electrically connectable to a terminal of the two terminals. The load circuit (3) according to any one of the previous claims, wherein the transconductance circuit (2) has a single-ended topology and the load circuit (3) comprises the one circuit branch (3a). The load circuit (3) according to any one of claims 1 to 6, wherein the transconductance circuit (2) has a differential topology and the load circuit (3) comprises the two circuit branches (3a, 3b). An amplifier circuit (1) comprising a transconductance circuit (2) and the load circuit (3) according to any one of the previous claims, electrically connected with each other. The amplifier circuit (1) according to claim 9, wherein the transconductance circuit (2) comprises one circuit branch (2a) or two circuit branches (2a, 2b), each circuit branch of the transconductance circuit (2) comprising a first transistor (9) and a second transistor (10) electrically connected in series, a first terminal (9a) of the first transistor (9) is electrically connected with a terminal (5a’; 5b’) of the two terminals (5a, 5a’; 5b, 5b’) of a respective circuit branch of the one (3a) or two circuit branches (3a, 3b) of the load circuit (3), a second terminal (9b) of the first transistor (9) is electrically connected with a first terminal (10a) of the second transistor (10), and a control terminal (10c) of the second transistor (10) is electrically connected with an input terminal (I la; 1 lb) of the circuit branch of the transconductance circuit (2). The amplifier circuit (1) according to claim 10, wherein the first transistor (9) of the circuit branch is one of the following: a bipolar junction transistor, BJT, having a base terminal as a third terminal, the base terminal being a control terminal; or a metal -oxide-semiconductor field-effect transistor, MOSFET, having a gate terminal as a third terminal, the gate terminal being a control terminal. The amplifier circuit (1) according to claim 10 or 11, wherein the second transistor (10) of the circuit branch is one of the following: a bipolar junction transistor, BJT, having a base terminal as the control terminal (10c); or a metal -oxide-semiconductor field-effect transistor, MOSFET, having a gate terminal as the control terminal (10c).

13. The amplifier circuit (1) according to any one of claims 10 to 12, wherein the transconductance circuit (2) comprises the one circuit branch (2a) of the transconductance circuit (2) and the load circuit (3) comprises the one circuit branch (3a) of the load circuit (3), wherein a terminal (5a’) of the two terminals (5a, 5a’) of the circuit branch (3a) of the load circuit (3) is electrically connected with the first terminal (9a) of the first transistor (9) of the circuit branch (2a) of the transconductance circuit (2), and a termination impedance (12) is electrically connected with the terminal (5a’) of the two terminals (5a, 5a’) of the circuit branch (3a) of the load circuit (3).

14. The amplifier circuit (1) according to any one of claims 10 to 12, wherein the transconductance circuit (2) comprises the two circuit branches (2a, 2b) of the transconductance circuit (2) and the load circuit (3) comprises the two circuit branches (3a, 3b) of the load circuit (3), wherein a terminal (5a’) of the two terminals (5a, 5a’) of a first circuit branch (3a) of the two circuit branches (3a, 3b) of the load circuit (3) is electrically connected with the first terminal (9a) of the first transistor (9) of a first circuit branch (2a) of the two circuit branches (2a, 2b) of the transconductance circuit (2), a terminal (5b’) of the two terminals (5b, 5b’) of a second circuit branch (3b) of the two circuit branches (3a, 3b) of the load circuit (3) is electrically connected with the first terminal (9a) of the first transistor (9) of a second circuit branch (2b) of the two circuit branches (2a, 2b) of the transconductance circuit (2), and a termination impedance (14) is electrically connected between the terminal (5a’) of the two terminals (5a, 5a’) of the first circuit branch (3a) of the load circuit (3) and the terminal (5b’) of the two terminals (5b, 5b’) of the second circuit branch (3b) of the load circuit (3).

15. An electro-optical transmitter (15) comprising an optical modulator (18), and an amplifier circuit (1) according to claim 13 or 14; wherein the amplifier circuit (1) is configured to amplify a signal for driving the optical modulator (18).