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WO2023184517A1 - Dispositif mems pour lithographie sans masque euv - Google Patents

Dispositif mems pour lithographie sans masque euv Download PDF

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Publication number
WO2023184517A1
WO2023184517A1 PCT/CN2022/084944 CN2022084944W WO2023184517A1 WO 2023184517 A1 WO2023184517 A1 WO 2023184517A1 CN 2022084944 W CN2022084944 W CN 2022084944W WO 2023184517 A1 WO2023184517 A1 WO 2023184517A1
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Prior art keywords
layer
silicon
mems
membrane
drive electrode
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English (en)
Inventor
Philippe Muller
Yijian Chen
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
    • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
    • G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
    • G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
    • G02B26/0841—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD the reflecting element being moved or deformed by electrostatic means
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70283—Mask effects on the imaging process
    • G03F7/70291—Addressable masks, e.g. spatial light modulators [SLMs], digital micro-mirror devices [DMDs] or liquid crystal display [LCD] patterning devices
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B5/00—Optical elements other than lenses
    • G02B5/08—Mirrors
    • G02B5/0891—Ultraviolet [UV] mirrors

Definitions

  • the present disclosure relates to a micro-electro-mechanical-system (MEMS) device and to a method for fabricating the MEMS device.
  • MEMS micro-electro-mechanical-system
  • the MEMS device is configured to implement micromirrors, which can be used for mask-less extreme ultra violet (EUV) lithography.
  • the micromirrors are fabricated above a complementary metal oxide semiconductor (CMOS) substrate of the MEMS device.
  • CMOS complementary metal oxide semiconductor
  • EUV lithography uses fixed mask gratings and a set of mirrors and lenses, in order to focus the EUV light to the target substrate for patterning.
  • micromirrors that are suitable for mask-less EUV lithography are not commercially available.
  • Some conventional MEMS devices are designed to be suitable for 193 nm wavelength deep UV (DUV) light.
  • these MEMS devices implement micromirrors of more than 4 ⁇ m in size. The sizes of the micromirrors would have to be significantly smaller than 4 ⁇ m for mask-less EUV lithography.
  • a possible approach may be to produce MEMS structures on a separate wafer, and then transfer the patterned structure to the CMOS substrate.
  • the alignment accuracy in this case prevents structures below 10 ⁇ m to be manufactured, since no electrical connection can be achieved in this case with the CMOS substrate.
  • an objective of this disclosure is to manufacture micromirrors above a CMOS substrate, which may act as a CMOS control chip, in order to realize mask-less lithography using EUV in the range of 6-16 nm.
  • the disclosure aims to provide a MEMS device and corresponding fabrication method to implement such micromirrors.
  • the size of the mobile structures and the micromirrors of the MEMS device should be equal to or lower than 1 ⁇ m. Further, a high-flatness and a low-roughness of the micromirrors is desired, in order to allow reflecting EUV radiation with a high yield.
  • a first aspect of this disclosure provides a MEMS device for use in EUV, lithography system, the MEMS device comprising: a CMOS substrate; a dielectric layer arranged on the CMOS substrate and comprising four bias pads and a drive electrode, which are formed in the dielectric layer, wherein each bias pad and the drive electrode extends from the CMOS substrate through the dielectric layer; four support structures arranged on the dielectric layer, wherein each support structure extends from one of the bias pads; a silicon-based MEMS layer comprising a suspended membrane and four mounting elements formed integrally with the suspended membrane; wherein one or more mirror structures are provided on a top surface and/or on a bottom surface of the suspended membrane; wherein each mounting element is attached to one of the support structures, wherein a part of the mounting element is sandwiched by the support structure; and wherein the CMOS substrate is configured to actuate the MEMS layer to move the suspended membrane by controlling the drive electrode and by biasing the MEMS layer via the bias pads and the support structures.
  • the CMOS substrate may comprise a CMOS control circuit, which may be configured to actuate the MEMS layer by controlling the drive electrode, and/or may be configured to bias the MEMS layer.
  • the CMOS substrate may, to this end, include back-end-of-line (BEOL) circuitry connected to the MEMS layer.
  • BEOL back-end-of-line
  • the mirror structures may implement the micromirrors, which are suitable for the mask-less EUV lithography system.
  • a lateral dimension of the mirror structures, and respectively of the membrane, may be lower than 1 ⁇ m.
  • the mirror structures may be arranged on the bottom surface of the membrane, for example, if the membrane is transparent for EUV radiation.
  • the mirror structures may have a high-flatness and a low-roughness, and may thus better reflect EUV radiation than deposited materials. The mirror structures are thus suitable for EUV mask-less lithography.
  • the MEMS device of the first aspect provides mirror structures (micromirrors) above a CMOS substrate, which may act to actuate and control the MEMS layer to move the mirror structures. This enables mask-less lithography using EUV, for example, in the range of 6-16 nm.
  • one or more sensors are arranged on at least one of the bottom surface of the suspended membrane, the top surface of the suspended membrane, and one or more of the support structures.
  • the one or more sensors can thus be provided directly at the movable MEMS structure and/or directly at the mirror structures.
  • the one or more sensors include at least one of a thermal sensor, a magnetic sensor, and a piezoelectric sensor.
  • one or more temperature control elements are arranged on the bottom surface of the suspended membrane.
  • the CMOS substrate is configured to control the one or more sensors and/or temperature control elements via the bias pads and the support structures.
  • the CMOS substrate (acting as CMOS control circuit) can control the MEMS layer including the mirror structures based on sensor data and/or temperature control, i.e., which higher accuracy.
  • one or more control lines for biasing the MEMS layer or for controlling the one or more sensors and/or temperature control elements, are routed from the CMOS substrate to the MEMS layer through at least one support structure and the bias pad associated with this support structure.
  • multiple control lines which are insulated from each other, are routed from the CMOS substrate to the MEMS layer through the at least one support structure and the bias pad associated with this support structure.
  • the CMOS substrate may thus have full control over the MEMS layer, sensors, and control elements, while all control lines are integrated with the structure of the MEMS device, and enable a compact device suitable for EUV lithography.
  • the suspended membrane is arranged aligned, with an alignment accuracy of 10 nm or less, with the drive electrode in a top view of the MEMS device, and a gap is formed between the drive electrode and the suspended membrane.
  • the drive electrode may be controlled by the CMOS substrate to actuate (e.g., capacitively) the MEMS layer membrane.
  • a bond dielectric is arranged on the bottom surface of the membrane.
  • the bond dielectric is a fingerprint of the fabrication method of the second aspect, during which a silicon-based layer –which is later patterned into the MEMS layer –is bonded to a sacrificial layer –which is later removed to form the gap between drive electrode and membrane.
  • the one or more mirror structures each have a dimension of less than 1 ⁇ m; and/or the one or more mirror structures comprise Bragg mirrors or phase shifters.
  • the mirror structures thus implement micromirrors, which are suitable for mask-less EUV lithography.
  • a second aspect of this disclosure provides a method for fabricating a MEMS device for an extreme ultraviolet, EUV, lithography system, the method comprising: providing a CMOS substrate; forming a dielectric layer on the CMOS substrate; forming four bias pads and a drive electrode in the dielectric layer, wherein each bias pad and the drive electrode extends from the CMOS substrate through the dielectric layer; forming a sacrificial layer on the dielectric layer; forming four hinge elements in the sacrificial layer, wherein each hinge element extends through the sacrificial layer from one of the bias pads; bonding a silicon-based layer to the sacrificial layer, wherein the silicon-based layer is arranged on a support substrate; removing the support substrate; forming at least four anchor elements on the silicon-based layer, wherein each anchor element extends through the silicon-based layer onto one of the hinge elements to form a support structure with this hinge element, and wherein each anchor element covers a part of the surface of the silicon-based layer; patterning
  • each bias pad and the drive electrode comprises a metal core surrounded by a barrier material and/or a dielectric material; and/or each hinge element comprises a metal core surrounded by a barrier material.
  • the method further comprises forming two or more control line through the metal core of at least one bias pad and the metal core of the hinge element associated with this bias pad, wherein dielectric material is formed in the metal cores to insulate the control lines from each other.
  • the four bias pads and the drive electrode are formed in the dielectric layer by using a damascene process
  • the dielectric layer is coated with a protection layer before forming the sacrificial layer on the dielectric layer coated with the protection layer.
  • one or more sensors and/or mirror structures are formed on the sacrificial layer before bonding the silicon-based layer to the sacrificial layer.
  • a bond dielectric is arranged on at least one of the sacrificial layer and the silicon-based layer before bonding the silicon-based layer to the sacrificial layer.
  • the bonding of the silicon-based layer to the sacrificial layer is performed at room temperature and is followed by an annealing step of at least 250°C.
  • the silicon-based layer arranged on the support substrate is a silicon-on-insulator (SOI) substrate or wafer.
  • SOI silicon-on-insulator
  • more than four bias pads and more than one drive electrode are formed in the dielectric layer, wherein each bias pad and each drive electrode extends from the CMOS substrate through the dielectric layer; more than four hinge elements are formed in the dielectric layer, wherein each hinge element extends through the sacrificial layer from one of the bias pads; more than four anchor elements are formed on the silicon-based layer, wherein each anchor element extends through the silicon-based layer onto one of the hinge elements to form a support structure with this hinge element, and wherein each anchor element covers a part of the surface of the silicon-based layer; and the MEMS layer comprises more than one membrane and more than four mounting elements, wherein each membrane is integral with four mounting elements, wherein each mounting element is attached to one of the support structures, and wherein each membrane is arranged in alignment with one drive electrode.
  • the method of the second aspect can fabricate the MEMS device of the first aspect.
  • the method of the second aspect achieves the same advantages as described above for the MEMS device of the first aspect.
  • this disclosure proposes transferring an unpatterned supporting material for micromirrors to a CMOS substrate, and then realizing the patterning of the MEMS layer.
  • the transfer is performed after all CMOS manufacturing steps are finished.
  • the transfer may comprise dielectric bonding.
  • the transfer of the unpatterned material allows a high quality material to be used (e.g., a single crystal or low Coefficient of Thermal Expansion (CTE) material) , which is compatible with the BEOL thermal budget ( ⁇ 400 °C) .
  • CTE Coefficient of Thermal Expansion
  • Single crystal silicon for instance, is a reliable and smooth material without too much internal stress.
  • silicon dioxide is a very good insulator layer, which allows patterning both sides of the mobile structures (the MEMS layer) with extremely thin electrical wires and gratings.
  • Ceramics like Zerodur, silicon carbide (SiC) , graphene or quartz could also be transferred, in order to achieve a lower CTE, and therefore a better thermal stability of the mirror structures during operation of the MEMS device under EUV irradiation.
  • the backside of the mirror structures may be patterned with a counter electrode.
  • the MEMS layer can be patterned using DUV exposition, which allows ⁇ 1 ⁇ m size of the mirror structures.
  • the patterning can use stepper and scanner lithography with high overlay resolutions.
  • all required metal layers of the MEMS device can be deposited using a damascene process, which allows extremely small feature sizes.
  • FIG. 1 shows a MEMS device according to this disclosure in a side-view.
  • FIG. 2 shows a MEMS device according to this disclosure in a top-view.
  • FIG. 3 shows a method according to this disclosure.
  • FIG. 4 shows a first step of a method for fabricating a MEMS device of this disclosure.
  • FIG. 5 shows a further step of the method.
  • FIG. 6 shows a further step of the method.
  • FIG. 7 shows a further step of the method.
  • FIG. 8 shows further step of the method.
  • FIG. 9 shows further step of the method.
  • FIG. 10 shows further step of the method.
  • FIG. 11 shows a final step of the method, and shows the resulting MEMS device after the final step in a side-view.
  • FIG. 12 shows the resulting MEMS device after the final step in a top-view.
  • FIG. 1 and 2 show a MEMS device 100 according to a solution of this disclosure.
  • the MEMS device 100 is suitable for being used in a EUV lithography system.
  • the MEMS device 100 implements micromirrors that can be used for mask-less EUV lithography.
  • FIG. 1 shows the MEMS device in a side-view
  • FIG. 2 shows the MEMS device in a top-view. Same elements are labelled with the same reference signs in FIG. 1 and FIG. 2.
  • the MEMS device 100 comprises a CMOS substrate 101, which may be or may comprise a CMOS control circuit, which can be configured to control the MEMS device, particularly, movement of the movable structures of the MEMS device 100.
  • the CMOS substrate 101 may comprise a silicon-based substrate layer and a BEOL layer provided on the silicon-based substrate layer.
  • the MEMS device 100 further comprises a dielectric layer 102, which is arranged on the CMOS substrate 102.
  • the dielectric layer 102 may be an oxide layer, for instance, a silicon oxide layer.
  • At least four bias pads 103 and one or more drive electrodes 104 are respectively formed in the dielectric layer 102 (two bias pads 103 and the drive electrode 104 are shown in FIG. 1; the four bias pads 103 may respectively be arranged below the four support structures 105, as shown in FIG. 2) .
  • Each bias pad 103 and the drive electrode 104 respectively, extends from the CMOS substrate 101 and through the dielectric layer 102. That is, each bias pad 103 and the drive electrode 104 may be exposed at a surface of the dielectric layer 102.
  • the surface of the dielectric layer 102 may be covered by a surface layer 109, which may be at least one of an oxide layer or a protection layer.
  • Each bias pad 103 and the drive electrode 104 may comprise a metal core, which is surrounded by a barrier material and/or by a dielectric material (as indicated by the different shadings in FIG. 1) .
  • the metal may, for example, be copper.
  • the MEMS device 100 further comprises four support structures 105 (visible in FIG. 2) , which are arranged on the dielectric layer 102.
  • Each of the support structures 105 extends from one of the bias pads 103 (as shown in FIG. 1) .
  • At least a part of each of the support structures 105 may comprise a metal core, which is surrounded by a barrier material (as indicated by the different shadings in FIG. 1) .
  • the metal may, for example, be copper, tungsten, or other metals compatible with damascene process.
  • the MEMS device 100 further comprises a silicon-based MEMS layer, which comprises a suspended membrane 106 and four mounting elements 107.
  • the four mounting elements 107 are formed integrally with the suspended membrane 106.
  • the membrane 106 is suspended because there is a gap formed between the surface of the dielectric layer 102 and the bottom surface of the membrane 106, as shown. In particular, the gap may be between the drive electrode 104 and the membrane 106.
  • the suspended membrane 106 is thus movable, and can be actuated using the drive electrode 104.
  • the MEMS layer may be patterned from a silicon-based layer, as described later.
  • the MEMS device 100 may further comprise one or more mirror structures 108, which are provided on a top surface and/or on a bottom surface of the suspended membrane 106.
  • the mirror structures 108 may thus be formed on or below the membrane 106.
  • the membrane 106 surface may be treated to provide the mirror structures 108.
  • the whole surface of the membrane 106 can also itself function as a mirror structure 108.
  • the material of the membrane 106 may, for example, be EUV radiation reflective itself.
  • the one or more mirror structures 108 implement one or more micromirrors (since they may have micron or sub-micron dimensions) , which are suitable for mask-less EUV lithography.
  • Each silicon-based mounting element 107 is attached to one of the support structures 105 (as shown in FIG. 2) . Thereby, a part of each mounting element 107 is sandwiched by the support structure 105, to which it is attached (as shown in FIG. 1) .
  • the CMOS substrate 101 is configured to actuate the MEMS layer, in order to move (e.g., a tilting movement) the suspended membrane 106 and thereby the one or more mirror structures 108.
  • the CMOS substrate 101 is configured to control the drive electrode 104, for instance, to actuate a first tilting movement of the MEMS layer.
  • the CMOS substrate 101 may also be configured to control a second drive electrode, for instance, to actuate a second tilting movement in the opposite way of the first tilting movement. This may lead to better contrast when irradiated by EUV radiation.
  • the MEMS device may also comprise one or more mechanical stops to prevent the MEMS layer to touch the dielectric layer 102 when actuated, which could cause stiction due to charge trapping in the dielectric layer 102.
  • the CMOS substrate 101 is configured to bias the MEMS layer via the bias pads 103 and via the support structures 105. In this way, the CMOS substrate 101 may control the movement of the mirror structures 108 precisely, and can thus be used for mask-less EUV lithography.
  • FIG. 3 shows a flow-diagram of a method 300 for fabricating a MEMS device according to this disclosure.
  • the method 300 can, in particular, be used to fabricate the MEMS device 100 shown in FIG. 1 and 2, which is suitable for the EUV lithography system.
  • the method 300 comprises a step 301 of providing the CMOS substrate 101, a step 302 of forming the dielectric layer 102 on the CMOS substrate 101, and a step 303 of forming the four bias pads 103 and the drive electrode 104 in the dielectric layer 102.
  • each bias pad 103 and the drive electrode 104 is formed such that it extends from the CMOS substrate 101 through the dielectric layer 102.
  • the four bias pads 103 and the drive electrode 104 may be formed using a damascene process.
  • the method 300 further comprises as step 304 of forming a sacrificial layer on the dielectric layer 102, and a step 305 of forming 305 four hinge elements in the sacrificial layer.
  • Each of the hinge elements extends through the sacrificial layer from one of the bias pads 103.
  • Each of the hinge elements is a lower part of the support structures 105, which is shown in FIG. 1 and 2.
  • the method 300 further comprises a step 306 of bonding a silicon-based layer (e.g., a silicon top layer of a SOI substrate) to the sacrificial layer, wherein the silicon-based layer is arranged on a support substrate, and then a step 307 of removing the support substrate.
  • a bond dielectric may be arranged on at least one of the sacrificial layer and the silicon-based layer, before bonding the silicon-based layer to the sacrificial layer.
  • the bonding of the silicon-based layer to the sacrificial layer may be performed at room temperature, and may be followed by an annealing step of at least 250°C.
  • the method 300 further comprises a step 308 of forming at least four anchor elements on the silicon-based layer, wherein each anchor element extends through the silicon-based layer onto one of the hinge elements to form a support structure 105 with this hinge element. Accordingly, each anchor elements is an upper part of one of the support structures 105. Each anchor element covers a part of the surface of the silicon-based layer. In this way, the silicon-based layer is partly sandwiched by the support structure 105.
  • the method 300 further comprises a step 309 of patterning the silicon-based layer into a MEMS layer, wherein the MEMS layer comprises –as described with respect to FIG. 1 and 2 –the membrane 106 and the four mounting elements 107, which are integral with the membrane 106.
  • Each mounting element 107 is attached to, and partly sandwiched by, one of the support structures 105.
  • the method 300 further comprises a step 310 of forming one or more mirror structures 108 on the membrane, and a step 311 of removing the sacrificial layer. Removing the sacrificial layer leads to the membrane 106 being suspended and, in particular, to the gap being formed between the drive electrode 104 and the suspended membrane 106.
  • FIG. 4 to FIG. 12 show an exemplary implementation of the method 300 of FIG. 3.
  • the exemplary implementation of the method 300 may lead to the MEMS device 100 shown in FIG. 11 (side-view) and FIG. 12 (top-view) , respectively.
  • This MEMS device 100 builds on the MEMS device 100 shown in FIG. 1. Same elements in all the figures are again labelled with the same reference signs and may be implemented likewise.
  • the manufacturing method 300 starts after the CMOS substrate 101 is finished.
  • the CMOS substrate 101 may comprise a silicon-based substrate 101a and a BEOL layer 101b, and may function as a CMOS control circuit for the MEMS layer of the MEMS device 100.
  • the dielectric layer 102 is provided onto the CMOS substrate 101, and the driving electrode 104 and the bias pads 103 are formed in the dielectric layer 102.
  • a damascene process may help to realize the driving electrode 104 and the bias pads 103.
  • a 200 nm silicon dioxide layer 102 and a 10 nm SiCN layer may be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) , or the like. These layers may then be patterned using, for example, a photosensitive layer exposed by a stepper using DUV. The patterns formed in the photoresist mask may be transferred by dry etching into the dielectric layer 102.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a barrier material and a seed layer for the metal core of each bias pad 13 and the drive electrode 104 may be deposited.
  • the barrier material can be Ti/TiN or TiW, Ta/TaN, and the seed layer is usually Cu.
  • the deposition may be performed by Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD) .
  • the pattern filling may be performed by electrochemical plating. After filling, a sintering step may also be performed at around 420 °C, and then a Chemical and Mechanical Polishing (CMP) may be performed stopping on the dielectric layer 102.
  • ALD Atomic Layer Deposition
  • PVD Physical Vapor Deposition
  • CMP Chemical and Mechanical Polishing
  • a protection layer 401 (e.g., implementing the optional surface layer 109 shown in FIG. 1) , for instance a thick SiCN layer, may be deposited on the dielectric layer 102 and onto he top surfaces of bias pads 103 and drive electrode 104, as shown in FIG. 4.
  • This layer 401 may be configured to protect the drive electrode 104 and the BEOL layer 101b of the CMOS substrate 101 during a MEMS release process performed at a later stage.
  • the protection layer 401 may be deposited either by ALD or PECVD, or CVD, and beneficially has a good density to resist the release process.
  • a sacrificial layer 502 for example, a silicon oxide layer, is deposited on the dielectric layer 102, and may be patterned to later form the mechanical stop of the MEMS layer and mirror structures.
  • the four hinge elements 503 are now formed in the sacrificial layer 502, such that each hinge element 503 extends through the sacrificial layer 502 from one of the bias pads 103.
  • This process may be performed again by a damascene process, similar to that described before.
  • the Cu can be replaced by electroplated Ni or CVD W for more stiffness of the hinge structures 503 (compared to the bias pads 103 and the drive electrode 104) .
  • the hinge structures 503 may be designed to allow electrical bias of the MEMS layer to be performed by the CMOS substrate 101 in the final MEMS device 100. To this end, one or more control lines, potentially isolated by dielectric material, may be formed in the metal cores of the hinge structures 503. Note that the design of the hinge structures 503 may include more complex shapes than illustrated in FIG. 5, for example, in order to allow also sensor signals to be connected through them to the CMOS substrate 101.
  • the metal filling/core of the hinge structures 503 can be Cu damascene or other higher young modulus metals like W or Ni, in order to increase the mechanical stability.
  • an additional dielectric layer may be deposited (not shown) on the sacrificial layer 502 and may be patterned to form one or more sensors, like heaters, thermocouples of piezoelectric layers on the hinge structures 503, to later monitor the mirror structure positions.
  • SiCN may be used as the additional dielectric layer.
  • a CMP step may be performed, before a bonding layer 501 (bond dielectric, e.g., SiCN, shown in FIG. 5) may be deposited on the sacrificial layer 503. That is, the sacrificial layer 502 may be capped with the bonding layer 501.
  • the overall roughness of the bonding surface may be ⁇ 0.5 nm, or may even be ⁇ 0.1 nm, and a slope may be less than 1nm/ ⁇ m to ensure a void free bonding.
  • FIG. 6 shows that then the silicon-based layer 601 on the support substrate 602 (e.g., composed of an oxide layer 602a and silicon layer 602b of a SOI substrate) may be transferred, after a bonding layer deposition on the silicon-based layer 601.
  • the transfer may be performed by fusion bonding of the two SiCN layers (the two bonding layers, respectively, formed on the sacrificial layer 502 and the silicon-based layer 601) .
  • the bonding may be performed by room temperature bonding and then a post bonding annealing of 250 °C minimum. Ideally the highest temperature of any further processing steps is used for annealing.
  • FIG. 7 shows that the support substrate 602 is then removed, for example, by mechanical and/or chemical processes, form the silicon-based layer 601. These steps may be adjusted to the material of choice.
  • a simple solution may be using silicon with a SiGe etch stop layer or a buried oxide layer. In that case grinding and/or CMP may be followed by plasma etching and finally wet etching to remove the SiGe.
  • Anchor elements 801 may then be formed to complete the support structures 105.
  • each anchor element 801 is formed such that it extends through the silicon-based layer 601 onto one of the hinge elements 503, in order to form one of the support structures 105 with this hinge element 503.
  • Each anchor element 801 also covers a part of the surface of the silicon-based layer 601, so that the silicon-based layer 601 is sandwiched by each of the support structures 105.
  • the next step may comprise the patterning of the silicon-based layer 601 into the MEMS layer, i.e., forming the mounting elements 107 and the membrane 106, and then forming the one or more mirror structures 108 on the top and/or bottom surface of the membrane 106.
  • the membrane 106 and mirror structures 108 may have a dimension 901 that is equal to or lower than 1 ⁇ m.
  • the mirror structures 108 may be Bragg mirrors or phase shifters, which are suitable to enhance the patterning capabilities of a EUV lithography system.
  • a SiCN or SiN passivation may be further used to protect these mirror structures 108 during the MEMS release step.
  • the MEMS release step may be performed.
  • the sacrificial layer 502 is thereby removed. This can be performed by vapor HF etching or by Inductively Coupled Plasma (ICP) etching.
  • ICP Inductively Coupled Plasma
  • the MEMS layer, in particular, the suspended membrane 106 is now able to be actuated and moved by the CMOS control circuit/substrate 101.
  • An offset to the actuation bias can cope with initial tilt variations, and it is possible to form and use thermal, piezo-resistive, or magnetic sensors on the support structures 105, or on the mirror structures 108 back-sides or front-sides. It is also possible to form and used meander structures on the back of the mirror structures 108, in order to control the temperature of the mirror structures 108.
  • FIG. 11 and 12 show the MEMS device 100 after the exemplary implementation of the method 300.
  • FIG. 11 and FIG. 12 also show how one or more control lines 1101 may be formed through the metal core of at least one bias pad 103 and the metal core of the at least one support structure 105 associated with this at least one bias pad 103.
  • the control lines 1101 may be used for biasing the MEMS layer or for controlling the one or more sensors and/or temperature control elements, and may be routed from the CMOS substrate 101 to the MEMS layer. Thereby, they may be routed through the at least one support structure 105 and the at least one bias pad 103 associated with this at least one support structure 105.
  • Multiple control lines 1101, which are insulated from each other, may also be routed from the CMOS substrate 101 to the MEMS layer.
  • a dielectric material may be formed in the metal cores of the bias pad 103 and the support structure 105 associated with the bias pad 103, in order to insulate the multiple control lines 1101 from each other.
  • the CMOS wafer can then be diced to separate the various MEMS devices 100.

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Abstract

Un dispositif MEMS (100) configuré pour mettre en œuvre des structures de miroir (108) pour une lithographie EUV sans masque est divulgué. Les structures de miroir (108) sont disposées au-dessus d'un substrat CMOS (101). Une couche diélectrique (102) est disposée sur le substrat CMOS (101) et comprend quatre plots de polarisation (103) et une électrode d'attaque (104) s'étendant à partir du substrat CMOS (101) à travers la couche diélectrique (102). Quatre structures de support (105) sont disposées sur la couche diélectrique (102) et s'étendent à partir des plots de polarisation (103). En outre, une couche MEMS comprenant une membrane suspendue (106) et quatre éléments de montage (107) est fixée aux structures de support (105), une partie de chaque élément de montage (107) étant prise en sandwich par l'une des structures de support (105). Les structures de miroir (108) sont disposées sur une surface supérieure et/ou inférieure de la membrane (106). Le substrat CMOS (101) est configuré pour actionner la couche MEMS pour déplacer la membrane suspendue (106) par commande de l'électrode d'attaque (104) et par polarisation de la couche MEMS par l'intermédiaire des plots de polarisation (103) et des structures de support (105).
PCT/CN2022/084944 2022-04-02 2022-04-02 Dispositif mems pour lithographie sans masque euv Ceased WO2023184517A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020117728A1 (en) * 2000-08-03 2002-08-29 Brosnihhan Timothy J. Bonded wafer optical MEMS process
CN103547955A (zh) * 2011-03-25 2014-01-29 卡尔蔡司Smt有限责任公司 反射镜阵列
CN112946877A (zh) * 2021-02-05 2021-06-11 西安知象光电科技有限公司 一种芯片级密封的电磁驱动振镜及其制备方法
CN113003533A (zh) * 2019-12-20 2021-06-22 意法半导体股份有限公司 利用抗反射表面制造具有可倾斜结构的光学微机电设备的工艺
CN113942973A (zh) * 2020-11-13 2022-01-18 台湾积体电路制造股份有限公司 形成微机电系统结构的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020117728A1 (en) * 2000-08-03 2002-08-29 Brosnihhan Timothy J. Bonded wafer optical MEMS process
CN103547955A (zh) * 2011-03-25 2014-01-29 卡尔蔡司Smt有限责任公司 反射镜阵列
CN113003533A (zh) * 2019-12-20 2021-06-22 意法半导体股份有限公司 利用抗反射表面制造具有可倾斜结构的光学微机电设备的工艺
CN113942973A (zh) * 2020-11-13 2022-01-18 台湾积体电路制造股份有限公司 形成微机电系统结构的方法
CN112946877A (zh) * 2021-02-05 2021-06-11 西安知象光电科技有限公司 一种芯片级密封的电磁驱动振镜及其制备方法

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