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WO2023092478A1 - Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique Download PDF

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Publication number
WO2023092478A1
WO2023092478A1 PCT/CN2021/133598 CN2021133598W WO2023092478A1 WO 2023092478 A1 WO2023092478 A1 WO 2023092478A1 CN 2021133598 W CN2021133598 W CN 2021133598W WO 2023092478 A1 WO2023092478 A1 WO 2023092478A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
channel
drain
work function
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/133598
Other languages
English (en)
Chinese (zh)
Inventor
张强
李伟
侯朝昭
董耀旗
许俊豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to PCT/CN2021/133598 priority Critical patent/WO2023092478A1/fr
Priority to CN202180099648.7A priority patent/CN117529818A/zh
Publication of WO2023092478A1 publication Critical patent/WO2023092478A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and electronic equipment.
  • the first intercalation layer adopts high work function material, and the Fermi energy level of the high work function material is no more than 1/3 of its energy gap from the valence band of the channel semiconductor;
  • the source uses N-type heavily doped semiconductor;
  • the first intercalation layer uses a low work function material, and the Fermi level of the low work function material is no more than 1/3 of its energy gap from the conduction band of the channel semiconductor .
  • the channel layer 2 is formed by light doping on the surface of the substrate 1 through step 11.
  • the undoped part below the channel layer 2 is used as the substrate of the device, and the channel layer 2
  • the subsequent manufacturing process is used to form the channel of the transistor, for details, reference may be made to the subsequent manufacturing process.
  • the thickness of the first intercalation layer 10 can be set at 1 nm to 10 nm, so that the holes can be guaranteed to pass through the thinner first intercalation layer 10. Finally, maintain the "cold" state to ensure the cold source effect.
  • the thickness of the first intercalation layer 10 may be set to be 2 nm ⁇ 5 nm.
  • the fourth embodiment provides a P-type transistor 04 with a symmetrical source-drain structure.
  • the difference between the P-type transistor 04 and the N-type transistor 03 in the third embodiment will be described below.
  • Step 43 exposing the source terminal and the drain terminal by etching the substrate, and forming a first intercalation layer and a second intercalation layer on the sides of the channel layer respectively located at the source terminal and the drain terminal.

Landscapes

  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente demande se rapporte au domaine technique des semi-conducteurs, et concerne un dispositif à semi-conducteur et son procédé de fabrication et un appareil électronique, permettant de réduire l'oscillation de sous-seuil d'un transistor. Le dispositif à semi-conducteur comprend un transistor. Le transistor comprend un canal, une source et un drain ; la source et le drain sont disposés à deux extrémités du canal ; une première couche d'intercalation est disposée entre la source et le canal, et la première couche d'intercalation est en contact avec la source et le canal. Le canal utilise un semi-conducteur légèrement dopé ou un semi-conducteur intrinsèque. Le drain utilise un semi-conducteur fortement dopé. La source utilise un semi-conducteur fortement dopé de type p, la première couche d'intercalation utilise un matériau à fonction de travail élevée, et la distance du niveau de Fermi du matériau à fonction de travail élevée à partir d'une bande de valence de semi-conducteur de canal ne dépasse pas 1/3 d'un espace d'énergie de celle-ci ; ou la source utilise un semi-conducteur fortement dopé de type N, la première couche d'intercalation utilise un matériau à faible fonction de travail, et la distance du niveau de Fermi du matériau à faible fonction de travail à partir d'une bande de conduction de semi-conducteur de canal ne dépasse pas 1/3 d'un espace d'énergie de celle-ci.
PCT/CN2021/133598 2021-11-26 2021-11-26 Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique Ceased WO2023092478A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/133598 WO2023092478A1 (fr) 2021-11-26 2021-11-26 Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique
CN202180099648.7A CN117529818A (zh) 2021-11-26 2021-11-26 半导体器件及其制作方法、电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/133598 WO2023092478A1 (fr) 2021-11-26 2021-11-26 Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique

Publications (1)

Publication Number Publication Date
WO2023092478A1 true WO2023092478A1 (fr) 2023-06-01

Family

ID=86538609

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/133598 Ceased WO2023092478A1 (fr) 2021-11-26 2021-11-26 Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique

Country Status (2)

Country Link
CN (1) CN117529818A (fr)
WO (1) WO2023092478A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116581147A (zh) * 2023-06-06 2023-08-11 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090200605A1 (en) * 2008-02-07 2009-08-13 Bjoerk Mikael T Metal-Oxide-Semiconductor Device Including an Energy Filter
CN103606563A (zh) * 2013-10-22 2014-02-26 清华大学 无结型隧穿场效应晶体管及其形成方法
CN109712892A (zh) * 2018-12-27 2019-05-03 中国科学院微电子研究所 Mos器件的制作方法
CN109920842A (zh) * 2019-02-22 2019-06-21 中国科学院微电子研究所 冷源结构mos晶体管及其制作方法
CN112424917A (zh) * 2018-06-06 2021-02-26 港大科桥有限公司 具有冷源极的金属氧化物半导体场效应晶体管

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090200605A1 (en) * 2008-02-07 2009-08-13 Bjoerk Mikael T Metal-Oxide-Semiconductor Device Including an Energy Filter
CN103606563A (zh) * 2013-10-22 2014-02-26 清华大学 无结型隧穿场效应晶体管及其形成方法
CN112424917A (zh) * 2018-06-06 2021-02-26 港大科桥有限公司 具有冷源极的金属氧化物半导体场效应晶体管
CN109712892A (zh) * 2018-12-27 2019-05-03 中国科学院微电子研究所 Mos器件的制作方法
CN109920842A (zh) * 2019-02-22 2019-06-21 中国科学院微电子研究所 冷源结构mos晶体管及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116581147A (zh) * 2023-06-06 2023-08-11 长鑫存储技术有限公司 半导体结构及其制备方法

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