WO2023071074A1 - Semiconductor structure and preparation method therefor, and test system - Google Patents

Abstract

Embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a preparation method therefor, and a test system. The semiconductor structure comprises: a system board; a package structure, comprising a package layer, a package substrate, and a bare die located in the package layer, the package layer being located on the surface of the package substrate away from the system board; an electric connection structure, part of the electric connection structure being located in the package structure, and the electric connection structure being electrically connected to the bare die and the system board; and a conductive structure, which is located on the surface of the package substrate and comprises a first portion covered by the package layer and electrically connected to the electric connection structure, and a second portion not covered by the package layer and used for connecting a test apparatus, the second portion comprising a connection section connected to the first portion, a contact section for connecting the test apparatus, and a connection device connecting the connection section to the contact section, and the connection device being detachably connected between the connection section and the contact section. The embodiments of the present invention facilitate improvement of the test quality of performing signal test on the semiconductor structure.

Description

Semiconductor structure and its preparation method, testing system

Cross References to Related Applications

This disclosure is based on a Chinese patent application with application number 202111275407.1 and a filing date of October 29, 2021, and claims the priority of this Chinese patent application. The entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

technical field

Embodiments of the present disclosure relate to but are not limited to a semiconductor structure, a manufacturing method thereof, and a testing system.

Background technique

With the development of science and technology, semiconductor chips are more and more widely used in various electronic products, and semiconductor chips are usually arranged on printed circuit boards. In order to improve the yield rate of semiconductor chips, it is generally necessary to perform a high-speed signal test on each semiconductor chip when the semiconductor chip is electrically connected to a printed circuit board. When testing, high-speed signals need to have better signal integrity and power integrity, so as to truly reflect the performance of semiconductor chips.

However, at present, when a high-speed signal is tested on a semiconductor chip, there is a phenomenon that the test signal is distorted, thereby affecting the quality of the test.

Contents of the invention

An embodiment of the present disclosure provides a semiconductor structure, including: a system board; a packaging structure, the packaging structure is arranged on the surface of the system board, the packaging structure includes a die, a packaging layer and a packaging substrate, and the packaging layer is located on the surface of the packaging substrate away from the system board, The packaging layer encapsulates the bare chip; the electrical connection structure, part of the electrical connection structure is located in the packaging structure, and the electrical connection structure is respectively electrically connected to the bare chip and the system board; the conductive structure is located on the surface of the packaging substrate away from the system board, and the packaging layer Covering a part of the conductive structure, the conductive structure includes a first part covered by the encapsulation layer and electrically connected to the electrical connection structure, and a second part not covered by the encapsulation layer and used for connecting the test device, the second part includes a part connected to the first part The connection section, the contact section arranged at a distance from the connection section and used for connecting the test device, and the connection device connecting the connection section to the contact section, the connection device is detachably connected between the connection section and the contact section.

Correspondingly, an embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including: providing a packaging substrate and a system board; forming an electrical connection structure and a conductive structure connected to the electrical connection structure on the packaging substrate, and the electrical connection structure and the die Electrically connected, the conductive structure includes a first part and a second part, the second part is used to connect the test device, the second part includes a connecting segment connected to the first part, is spaced from the connecting segment and is used to connect the contact segment of the testing device, and connects A connection device connecting the segment to the contact segment, the connection device is detachably connected between the connection segment and the contact segment; an encapsulation layer is formed on the surface of the packaging substrate, and the encapsulation layer encapsulates the die, the first part and a part of the electrical connection structure ; electrically connecting the package substrate to the system board based on the electrical connection structure.

Correspondingly, an embodiment of the present disclosure further provides a test system, including a test device, which is used to test any one of the above-mentioned semiconductor structures.

Description of drawings

One or more embodiments are exemplified by corresponding pictures in the drawings, and these exemplifications are not construed as limiting the embodiments, unless otherwise stated, and the pictures in the drawings are not limited in scale.

FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

3 is a schematic structural diagram corresponding to the step of forming an electrical connection structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

4 to 5 are structural schematic diagrams corresponding to the step of forming a conductive structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

6 is a schematic structural diagram corresponding to the step of forming an encapsulation layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

Fig. 7 is a schematic structural diagram of a testing system provided by an embodiment of the present disclosure.

Detailed ways

It can be seen from the background art that currently there is a problem that the test quality is not high when the signal test is performed on the semiconductor chip. The analysis found that one of the reasons for the low test quality when performing signal tests on semiconductor chips is that usually when testing high-speed signals on semiconductor chips, an adapter board is connected between the system board and the adapter board . On the one hand, the adapter board can play the role of electrically connecting the semiconductor chip and the system board; Testing of semiconductor chips. However, the existence of the adapter board introduces an additional electrical connection line between the semiconductor chip and the system board. The existence of the electrical connection line makes the signal transmission path longer, which is not conducive to the rapid transmission of test signals, resulting in The test signal is distorted, resulting in lower test quality.

An embodiment of the present disclosure provides a semiconductor structure, including: a system board and a packaging structure, the packaging structure is arranged on the surface of the system board, the packaging structure includes a die, a packaging layer and a packaging substrate, the packaging layer is located on the surface of the packaging substrate away from the system board, and the packaging The layer encapsulates the bare chip; the electrical connection structure, part of the electrical connection structure is located in the package structure, and the electrical connection structure is respectively electrically connected to the bare chip and the system board; the conductive structure is located on the surface of the package substrate away from the system board, and the conductive structure includes The first part covered by the encapsulation layer and electrically connected to the electrical connection structure, and the second part not covered by the encapsulation layer and used to connect the test device, the second part includes a connection section connected to the first part, and is spaced apart from the connection section and used For connecting the contact section of the test device and the connection device connecting the connection section to the contact section, the connection device is detachably connected between the connection section and the contact section, that is to say, a conductive structure is provided on the package substrate as a connection device. The test point of the test device, in this way, makes the distance between the test point and the die shorter, so that the signal transmission path is shorter, which is conducive to the fast transmission of the signal, and there is no need to additionally set the electrical connection between the die and the system board Therefore, the influence on the signal itself is small, so that the authenticity of the test signal can be improved and the test quality can be improved. In addition, a connecting device is provided in the conductive structure, which can realize the on-off of the current between the conductive structure and the electrical connection structure. In this way, after the test of the bare chip is completed, the connection device can be removed to disconnect the connection between the conductive structure and the electrical connection structure, so that the conductive structure on the packaging substrate will not affect the normal performance of the bare chip, so that the improved performance can be achieved. While testing the quality of the signal, the performance of the bare chip itself is maintained.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in various embodiments of the present disclosure, many technical details are provided for readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be realized.

FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure.

Referring to FIG. 1, the semiconductor structure includes: a system board 100; a packaging structure 110, the packaging structure 110 is arranged on the surface of the system board 100, the packaging structure 110 includes a die 111, a packaging layer 112 and a packaging substrate 113, and the packaging layer 112 is located on the packaging substrate 113 Away from the surface of the system board 100, the packaging layer 112 encapsulates the bare chip 111; the electrical connection structure 120, part of the electrical connection structure 120 is located in the packaging structure 110, and the electrical connection structure 120 is respectively electrically connected to the bare chip 111 and the system board 100; Structure 130, the conductive structure 130 is located on the surface of the packaging substrate 113 away from the system board 100, the packaging layer 112 covers a part of the conductive structure 130, the conductive structure 130 includes a first part 131 covered by the packaging layer 112 and electrically connected to the electrical connection structure 120, and The second part 132 that is not covered by the encapsulation layer 112 and is used to connect the test device, the second part 132 includes a connection segment 133 connected to the first part 131, a contact segment 134 that is spaced apart from the connection segment 133 and is used to connect the test device, and Connecting section 133 is connected to connecting means 135 of contacting section 134 , connecting device 135 is detachably connected between connecting section 133 and contacting section 134 .

The conductive structure 130 is set on the packaging substrate 113 as a test point for connecting the test device, so that the distance between the test point and the bare chip 111 is relatively short, so that the signal transmission path is relatively short, which is conducive to the rapid transmission of the signal, And there is no need to additionally set up an electrical connection line between the bare chip 111 and the system board 100 , so the influence on the signal itself is small. In addition, a connection device 135 is provided in the conductive structure 130 to control the on-off of the current between the conductive structure 130 and the electrical connection structure 120 . In this way, after the test of the bare chip 111 is completed, the connection device 135 can be removed to disconnect the connection between the conductive structure 130 and the electrical connection structure 120, so that the conductive structure 130 on the packaging substrate 113 will not affect the normal operation of the bare chip 111. Performance, so that while improving the quality of the test signal, the performance of the bare chip 111 itself can be kept better.

The semiconductor production process includes wafer manufacturing and packaging testing. In these two links, two testing steps, wafer testing and finished product testing, are to be completed. Among them, finished product testing refers to the functional and electrical parameter testing of the packaged chip. After the bare chip 111 is packaged, it is called a chip. The chip is generally electrically connected to a printed circuit board (PCB, Printed Circuit Board). There are metal wires on the PCB board, which can realize the interconnection and relay transmission between the chips. The current completes functions such as amplification, attenuation, modulation, decoding, and encoding in the bare chip 111 along a preset circuit. After the chip is electrically connected to the PCB board, it is necessary to test the related electrical characteristics of the chip. Specifically, it is necessary to lead the electrical signal of the chip under test to the test point, and the test device inputs the test signal to the chip and collects the output signal of the chip to judge whether the function and performance of the chip meet the design specification requirements. Usually, the test signal of the test device is a high-speed signal. In order to truly reflect the electrical characteristics of the chip, the high-speed signal needs to have better signal integrity and power integrity when testing.

The system board 100 is directly electrically connected to the die 111 in the packaging structure 110 , which is equivalent to the electrical connection between the chip and the system board 100 . In some embodiments, the system board 100 may be a PCB board.

The package structure 110 encapsulates the die 111, which can protect the die 111 from the influence of the surrounding environment. At the same time, the package structure 110 also includes an electrical connection structure 120, which is used to connect the die 111 to the system board 100. electrical connection. Specifically, the packaging substrate 113 in the packaging structure 110 provides functions such as electrical connection, protection, support, and assembly for the bare chip 111 , which can achieve multi-pin, improve electrical performance, and achieve high density. The encapsulation layer 112 is used to cover part of the electrical connection structure 120 and the die 111, so that the die 111 and the electrical connection structure 120 can be protected from damage, and the problem of gas entering to oxidize the internal die 111 can be prevented. In addition, it can also Ensure product safety and stability. In some embodiments, the material of the encapsulation layer 112 may be an encapsulation molding compound, such as any one of epoxy molding compound, silicon rubber or polyimide.

Specifically, in some embodiments, the orthographic projection of the encapsulation layer 112 on the surface of the encapsulation substrate 113 falls into the surface of the encapsulation substrate 113 . That is to say, in the direction parallel to the surface of the packaging substrate 113, the area of the packaging layer 112 is smaller than the area of the packaging substrate 113, that is, the packaging layer 112 covers part of the packaging substrate 113, and the part of the packaging substrate 113 not covered by the packaging layer 112 can be used for The conductive structure 130 is carried so that the conductive structure 130 can be exposed, so as to be used for connecting the testing device. In addition, the connection device 135 is also exposed, so the connection device 135 can be disassembled more conveniently, so as to achieve the purpose of controlling the current connection between the conductive structure 130 and the electrical connection structure 120 .

In some embodiments, the contact section 134 includes: a conductive part 136, the conductive part 136 contacts the end of the connecting device 135 away from the connecting part 133; an electrical contact structure 137, the electrical contact structure 137 is located at the end of the conductive part 136 away from the connecting device 135 department. That is to say, the electrical contact structure 137 is used as a test point for electrically connecting with the test device, and the conductive part 136 is used for electrically connecting the electrical contact structure 137 and the bare chip 111, so that the test signal is transmitted between the test device and the bare chip 111. transmission. It can be understood that the conductive part 136 and the electrical contact structure 137 are used for different functions. For the electrical contact structure 137, since it needs to be in electrical contact with the test device, the electrical contact structure 137 needs to have a relatively large contact area. , thereby facilitating electrical contact with the test device. The conductive part 136 is used to electrically connect the electrical contact structure 137 and the bare chip 111 . The difficulty of forming the conductive part 136 needs to be considered, so that the process of actually preparing the conductive part 136 is relatively simple, which is conducive to large-scale production.

Referring to FIG. 2 , FIG. 2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, the shape of the orthographic projection of the electrical contact structure 137 on the surface of the packaging substrate 113 is a rectangle. The shape of the electrical contact structure 137 is rectangular. In this way, when it is necessary to form multiple electrical contact structures 137 in the semiconductor structure, the aspect ratio of the electrical contact structure 137 is adjusted under the condition that the area of the electrical contact structure 137 is kept constant. In the direction along which the plurality of electrical contact structures 137 are arranged at intervals, the width of the electrical contact structures 137 is smaller, so that denser electrical contact structures 137 can be arranged to meet different product requirements. It can be understood that, in some other embodiments, the shape of the orthographic projection of the electrical contact structure 137 on the surface of the packaging substrate 113 may also be a circle or other geometric shapes.

In some embodiments, the area of the orthographic projection of the electrical contact structure 137 on the surface of the packaging substrate 113 is greater than the area of the orthographic projection of the conductive portion 136 on the surface of the packaging substrate 113 . In this way, the surface area of the electrical contact structure 137 is relatively large, so that when the electrical contact structure 137 is externally connected to the test device, the contact area between the electrical contact structure 137 and the connecting wire of the test device is relatively large, so that the contact between the electrical contact structure 137 and the connecting wire The resistance is small, so that the test signal output by the test device can be transmitted to the bare chip 111 quickly, and the feedback signal of the test signal from the bare chip 111 can also be transmitted to the test device quickly. Therefore, a high degree of authenticity of the test signal can be maintained, thereby improving the problem that the test quality is affected by the delayed transmission of the test signal. It can be understood that, in other embodiments, the area of the orthographic projection of the electrical contact structure 137 on the surface of the packaging substrate 113 may also be equal to the area of the orthographic projection of the conductive portion 136 on the surface of the packaging substrate 113 .

The connection device 135 is detachably connected between the connection section 133 and the contact section 134, so that the current on and off between the connection section 133 and the contact section 134 can be controlled, thereby controlling the connection between the conductive structure 130 and the electrical connection structure 120 The current is turned on and off, that is, it plays the role of a switch. Specifically, when the bare chip 111 needs to be tested, the connection device 135 electrically connects the connection segment 133 and the contact segment 134, that is, conducts the current between the conductive structure 130 and the electrical connection structure 120, so that the electric current generated by the bare chip 111 The signal can be transmitted to a test device. When it is not necessary to test the bare chip 111, the connection device 135 can be disassembled, so as to realize the disconnection between the connection segment 133 and the contact segment 134, so that after the test of the bare chip 111 is completed, due to the conductive structure 130 and The electrical connection structures 120 are in an open circuit state, therefore, the normal performance of the die 111 will not be affected. Therefore, the product used for testing can also be used as an actual product for mass production. Specifically, in some embodiments, the connecting device 135 may be an external resistor. The structure of the external resistor is simple and the cost is low, which is beneficial to the mass production of the semiconductor structure provided by the embodiments of the present disclosure.

Specifically, in some embodiments, the resistance of the external resistor is zero ohms. In this way, when using an external resistor to connect the connection section 133 to the contact section 134 to test the bare chip 111, since the resistance value of the external resistor is zero, it is equivalent to directly connecting the connection section 133 to the contact section 134, which is beneficial to the test signal. The fast transmission between the conductive structure 130 and the electrical connection structure 120 can improve the problem of distortion of the test signal caused by the delayed transmission of the test signal, thereby improving the test quality.

The electrical connection structure 120 is electrically connected to the bare chip 111 and the system board 100 respectively, and is used to realize the electrical connection between the bare chip 111 and the system board 100. In addition, the electrical connection structure 120 is also electrically connected to the conductive part 136, so that the The electrical signal is drawn out for testing. In some embodiments, the electrical connection structure 120 may include: pads 121, the pads 121 are located on the surface of the package substrate 113 away from the system board 100; bonding wires 122, the bonding wires 122 are electrically connected to the die 111 and the pads 121; The wiring 123 and the solder ball 124 electrically connected to the wiring 123 , the wiring 123 penetrates the packaging substrate 113 and is electrically connected to the pad 121 , the solder ball 124 is located between the packaging substrate 113 and the system board 100 and is electrically connected to the system board 100 .

In some embodiments, the connection segment 133 may be connected to an end of the pad 121 adjacent to the conductive structure 130 . Both the connection section 133 and the pad 121 are located on the surface of the package substrate 113 away from the system board 100, therefore, when the conductive structure 130 is actually prepared, the connection section 133 and the pad 121 can be formed in the same process step, so that The preparation process is relatively simple, which is beneficial to large-scale production. In addition, the pad 121 has a relatively large surface area. Therefore, in the actual manufacturing process, the process parameters for preparing the connection section 133 can be controlled to regulate the contact area between the connection section 133 and the pad 121. In this way, the connection section 133 and The contact resistance between the pads 121 is small, which is conducive to the rapid transmission of test signals. It can be understood that, in some other embodiments, the connection segment 133 may also be electrically connected to the surface of the pad 121 away from the packaging substrate 113 .

In the semiconductor structure provided in the above embodiments, the semiconductor structure includes: a system board 100, a packaging structure 110, an electrical connection structure 120, and a conductive structure 130, wherein the packaging structure 110 includes a die 111, a packaging layer 112, and a packaging substrate 113, and the packaging layer 112 encapsulates die 111 therein. Part of the electrical connection structure 120 is located in the package structure 110 , and the electrical connection structure 120 is electrically connected to the die 111 and the system board 100 respectively. The conductive structure 130 is located on the surface of the package substrate 113 away from the system board 100. The package layer 112 covers a part of the conductive structure 130. The conductive structure 130 includes a first part 131 covered by the package layer 112 and electrically connected to the electrical connection structure 120, and a part not packaged. Layer 112 covers and is used to connect the second part 132 of testing device, and second part 132 comprises the connection segment 133 that is connected with first part 131, and the contact segment 134 that is arranged at interval with connection segment 133 and is used for connecting test device, and connects segment 133 is connected to the connection device 135 of the contact segment 134, the connection device 135 is detachably connected between the connection segment 133 and the contact segment 134, the connection device 135 is equivalent to a switch, and can control the flow of current between the conductive structure 130 and the electrical connection structure 120 broken. That is to say, disposing the conductive structure 130 on the packaging substrate 113 as a test point for connecting the test device, compared to introducing an interposer board between the die 111 and the system board 100 for providing a test point, The test point is built into the semiconductor structure, so that the distance between the test point and the bare chip 111 is closer, so that the signal transmission path is shorter, which is conducive to the rapid transmission of the signal, and there is no need to additionally set the distance between the bare chip 111 and the system board 100 Therefore, the influence on the signal itself is small, so as to reflect the quality of the signal itself more truly. The connection device 135 can realize the on-off of the electric current between the conductive structure 130 and the electrical connection structure 120 . In this way, after the test of the bare chip 111 is completed, the connection device can be removed to disconnect the connection between the conductive structure 130 and the electrical connection structure 120, so that the conductive structure 130 on the packaging substrate 113 will not affect the normal performance of the bare chip 111 , so that while improving the quality of the test signal, the performance of the bare chip 111 itself can be kept better.

Correspondingly, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can form the semiconductor structure provided in the previous embodiment. The semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings The preparation method is described in detail.

Fig. 3 to Fig. 6 are structural schematic diagrams corresponding to each step in the method for preparing a semiconductor structure provided by another embodiment of the present disclosure.

Referring to FIG. 3 , FIG. 3 is a schematic structural diagram corresponding to the step of forming an electrical connection structure 120 in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure, providing a packaging substrate 113 and a system board; forming an electrical connection structure 120 on the packaging substrate 113 , the electrical connection structure 120 is electrically connected to the die 111 .

In some embodiments, the packaging substrate 113 may be a rigid packaging substrate, such as any one of a polymer substrate, a metal substrate, a composite substrate, or a ceramic substrate. In some other embodiments, the packaging substrate 113 may also be a flexible packaging substrate, and the material of the flexible packaging substrate 113 may be any one of PI (polyimide) resin or PE (polyester) resin.

The system board is used to form an electrical connection with the bare chip 111 , specifically, the system board and the bare chip 111 may be electrically connected through the electrical connection structure 120 , thereby forming an electrical connection between the system board and the bare chip 111 . Therefore, in some embodiments, the system board may be located on a side of the package substrate 113 away from the die 111 .

Specifically, in some embodiments, the step of forming the electrical connection structure 120 on the packaging substrate 113 may include:

Wiring 123 is formed in the packaging substrate 113, part of the wiring 123 runs through the packaging substrate 113, and part of the wiring 123 is also located on the surface of the packaging substrate 113 away from the system board;

A pad 121 is formed on the surface of the packaging substrate 113 away from the system board, and the pad 121 is electrically connected to the wiring 123. Specifically, in some embodiments, the pad 121 may be formed by electroplating;

Forming the bonding wire 122, the bonding wire 122 is used to electrically connect the pad 121 and the die 111, specifically, in some embodiments, the bonding wire 122 can be formed by pressure bonding, that is, using thermal pressure or ultrasonic energy , the bonding wires 122 are soldered to the pads 121 and the die 111 respectively, so as to form an electrical connection between the pads 121 and the die 111 .

Specifically, in some embodiments, the material of the electrical connection structure 120 may be at least one of copper, tin or gold.

Referring to FIG. 4 and FIG. 5 , FIG. 4 to FIG. 5 are structural schematic diagrams corresponding to the step of forming the conductive structure 130 in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. The conductive structure 130, the conductive structure 130 includes a first part 131 and a second part 132, the second part 132 is used to connect the test device, the second part 132 includes a connection section 133 connected to the first part 131, and is spaced apart from the connection section 133 and used for The test device contact section 134 is connected, and the connection device 135 connecting the connection section 133 to the contact section 134 is detachably connected between the connection section 133 and the contact section 134 . That is to say, the conductive structure 130 can be directly formed on the packaging substrate 113 , thus making the manufacturing process simpler. In addition, the connection section 133 can be formed to connect with the electrical connection structure 120 in the same process step, which further simplifies the process flow and facilitates large-scale production.

Specifically, in some embodiments, the process steps of forming the conductive structure 130 include:

Referring to FIG. 4, a conductive portion 136, an electrical contact structure 137, and an initial connection segment 133 electrically connected to the electrical connection structure 120 are formed on the packaging substrate 113. The electrical contact structure 137 is located at the end of the conductive portion 136 away from the electrical connection structure 120. Initially A part of the connection section 133 is used as the connection section 133 , the rest of the initial connection section 133 is used as the first part 131 , and the conductive part 136 is spaced apart from the connection section 133 .

That is to say, the conductive portion 136 and the electrical contact structure 137 can be formed separately. In this way, in the step of forming the electrical contact structure 137, the surface area of the electrical contact structure 137 can be adjusted to be relatively large, so that the electrical contact structure 137 is in contact with the test device. When the connecting wires are connected, the contact area between the electrical contact structure 137 and the connecting wires is larger, which is beneficial to the rapid transmission of test signals.

The conductive part 136 is spaced apart from the connecting section 133 , that is, a space is reserved between the conductive part 136 and the connecting section 133 for the connecting device 135 , so that the connecting device 135 is detachably connected between the connecting section 133 and the contacting section 134 .

The initial connection section 133 is divided into a connection section 133 and a first part 131 , and the first part 131 is a part covered by the encapsulation layer 112 subsequently. That is to say, a part of the initial connection section 133 is reserved for being covered by the encapsulation layer 112, so that when the encapsulation layer 112 is subsequently formed on the encapsulation substrate 113, it is possible to prevent the formation of too much encapsulation layer 112 from causing The entire connection segment 133 is covered, thereby increasing the process window for forming the encapsulation layer 112 .

Referring to Fig. 5, connecting device 135 is set between conductive part 136 and electrical connecting structure 120, and connecting device 135 connects connecting segment 133 to conductive part 136, electrical contact structure 137, conductive part 136, connecting device 135, connecting segment 133 and The first portion 131 forms the conductive structure 130 . A space for forming the connection device 135 is reserved between the conductive portion 136 and the electrical connection structure 120 , so that the manufacturing process is relatively simple.

Specifically, in some embodiments, the conductive structure 130 may be formed by an electroplating process. Specifically, the conductive structure 130 can be formed by a dry electroplating process, such as vacuum electroplating, vapor phase electroplating, and molten electroplating using molten metal. In this way, only the part that needs to form the conductive structure 130 can be electroplated without Other parts in the encapsulation layer 112 are affected.

In some embodiments, the material of the conductive structure 130 includes any one of copper, tin or gold. Specifically, in some embodiments, the material of the conductive structure 130 may be copper. On the one hand, copper has better conductivity, so that the electrical signal of the bare chip 111 can be output faster through the conductive part 136; on the other hand, the price of copper is low, so the manufacturing cost of the semiconductor structure can be lowered. Facilitate large-scale production.

Referring to FIG. 6 , FIG. 6 is a schematic structural diagram corresponding to the step of forming the encapsulation layer 112 in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure. The encapsulation layer 112 is formed on the surface of the encapsulation substrate 113 , and the encapsulation layer 112 encapsulates the die 111 , the first part 131 and part of the electrical connection structure 120 are packaged inside. Specifically, in some embodiments, the encapsulation layer 112 can be formed on the surface of the encapsulation substrate 113 using a plastic encapsulation process, and the material of the encapsulation layer 112 can be an encapsulation molding compound, such as epoxy molding compound, silicone rubber or polyimide. either of.

Referring to FIG. 1 , the package substrate 113 is electrically connected to the system board 100 based on the electrical connection structure 120 . Specifically, in some embodiments, a plurality of solder balls 124 arranged at intervals may be formed between the packaging substrate 113 and the system board 100, and the solder balls 124 are electrically connected to the wiring 123 and the system board 100, thereby realizing the electrical connection structure 120 and the system board 100. Electrical connection of the system board 100 . Specifically, in some embodiments, a soldering method may be used to form a plurality of solder balls 124 arranged at intervals.

In the manufacturing method of the semiconductor structure provided in the above embodiments, the electrical connection structure 120 and the conductive structure 130 connected to the electrical connection structure 120 are formed on the packaging substrate 113, the electrical connection structure 120 is electrically connected to the die 111, and the conductive structure 130 includes a first A part 131 and a second part 132, the second part 132 is used to connect the test device, the second part 132 includes a connection section 133 connected with the first part 131, is arranged at intervals with the connection section 133 and is used to connect the test device contact section 134, and the The connection section 133 is connected to the connection device 135 of the contact section 134, and the connection device 135 is detachably connected between the connection section 133 and the contact section 134; an encapsulation layer 112 is formed on the surface of the package substrate 113, and the encapsulation layer 112 encapsulates the die 111 , the first part 131 and part of the electrical connection structure 120 are packaged; the packaging substrate 113 is electrically connected to the system board 100 based on the electrical connection structure 120 . A conductive structure 130 for connecting the testing device is formed on the packaging substrate 113, and is electrically connected to the electrical connection structure 120 in the packaging structure 110 to realize signal transmission between the bare chip 111 and the testing device. Not only the preparation process is relatively simple, And the connection distance between the test point and the bare chip 111 is shortened, so that the signal transmission path is short, which is beneficial to the transmission of the test signal. In addition, a detachable connection device 135 is set in the conductive structure 130 to control the on-off of the current between the bare chip 111 and the conductive structure 130, so that when the test on the bare chip 111 is completed, the connection device 135 can be removed to disconnect the current. Opening the connection between the bare chip 111 and the conductive structure 130, so that the conductive structure 130 will not affect the normal performance of the bare chip 111, so that the performance of the bare chip 111 itself can be kept better while improving the quality of the test signal the goal of.

Correspondingly, referring to FIG. 7, FIG. 7 is a schematic structural diagram of a test system provided by an embodiment of the present disclosure. The embodiment of the present disclosure also provides a test system, including a test device 1, which is used to test any of the above-mentioned semiconductors. structure to test. Referring to FIG. 1 and FIG. 7, in the embodiment of the present disclosure, a conductive structure 130 is provided on the packaging substrate 113 as a test point for connecting the test device 1, which is equivalent to building the test point into the semiconductor structure, compared with the bare chip 111 and the system board 100 additionally introduce an adapter board for providing test points, so that the distance between the test points and the bare chip 111 is closer, so that the signal transmission path is shorter, which is conducive to the rapid transmission of signals, Moreover, there is no need to additionally set up an electrical connection line between the bare chip 111 and the system board 100 , therefore, the influence on the signal itself is small, so as to reflect the quality of the signal itself more truly. The connection device 135 is detachably connected between the connection section 133 and the contact section 134 , so as to realize the on-off of the electric current between the conductive structure 130 and the electrical connection structure 120 . In this way, after the test of the bare chip 111 is completed, the connection device 135 can be removed to disconnect the connection between the conductive structure 130 and the electrical connection structure 120, so that the conductive structure 130 on the packaging substrate 113 will not affect the normal operation of the bare chip 111. Performance, in this way, when using the test system to test the semiconductor structure, not only the quality of the test signal can be improved, but also the performance of the die 111 itself can be kept good.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and spirit of the present disclosure. scope. Any person skilled in the art can make respective alterations and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined in the claims.

Claims (14)

A semiconductor structure comprising: system board; A packaging structure, the packaging structure is arranged on the surface of the system board, the packaging structure includes a bare chip, a packaging layer and a packaging substrate, the packaging layer is located on the surface of the packaging substrate away from the system board, the packaging layer encapsulating the die; an electrical connection structure, part of the electrical connection structure is located in the package structure, and the electrical connection structure is electrically connected to the bare chip and the system board; a conductive structure, the conductive structure is located on the surface of the packaging substrate away from the system board, the packaging layer covers a part of the conductive structure, and the conductive structure includes a structure covered by the packaging layer and connected to the electrical connection structure The first part that is electrically connected, and the second part that is not covered by the encapsulation layer and is used to connect the test device, the second part includes a connection section connected to the first part, is spaced from the connection section and is used for A contact section of a connection test device, and a connection device connecting the connection section to the contact section, the connection device being detachably connected between the connection section and the contact section. The semiconductor structure of claim 1, wherein the contact segment comprises: a conductive part, the conductive part is in contact with the end of the connecting device away from the connecting segment; An electrical contact structure, the electrical contact structure is located at the end of the conductive portion away from the connecting device. The semiconductor structure according to claim 2, wherein the shape of the orthographic projection of the electrical contact structure on the surface of the packaging substrate is a rectangle. The semiconductor structure according to claim 2, wherein an orthographic area of the electrical contact structure on the surface of the packaging substrate is larger than an orthographic area of the conductive part on the surface of the packaging substrate. The semiconductor structure of claim 1, wherein an orthographic projection of the encapsulation layer on the surface of the encapsulation substrate falls into the surface of the encapsulation substrate. The semiconductor structure according to claim 1, wherein the connecting device is an external resistor. The semiconductor structure according to claim 6, wherein the resistance value of the external resistor is zero ohms. The semiconductor structure according to claim 1, wherein said electrical connection structure comprises: a pad, the pad is located on the surface of the packaging substrate away from the system board; a bonding wire electrically connecting the die and the pad; Wiring and solder balls electrically connected to the wiring, the wiring runs through the packaging substrate and is electrically connected to the pad, the solder ball is located between the packaging substrate and the system board and is electrically connected to the system board. The semiconductor structure of claim 8, wherein the connection segment is connected to an end of the pad adjacent to the conductive structure. A method for preparing a semiconductor structure, comprising: Provide packaging substrates and system boards; An electrical connection structure and a conductive structure connected to the electrical connection structure are formed on the packaging substrate, the electrical connection structure is electrically connected to the die, the conductive structure includes a first part and a second part, and the second part For connecting a test device, the second part includes a connection section connected to the first part, a connecting section spaced apart from the connection section and used for connecting a test device contact section, and a connecting section connected to the contact section connection means detachably connected between the connection segment and the contact segment; forming an encapsulation layer on the surface of the encapsulation substrate, the encapsulation layer encapsulating the die, the first part and part of the electrical connection structure; The package substrate is electrically connected to the system board based on the electrical connection structure. The preparation method of semiconductor structure according to claim 10, wherein, the processing step of forming described conductive structure comprises: A conductive portion, an electrical contact structure, and an initial connection segment electrically connected to the electrical connection structure are formed on the packaging substrate, the electrical contact structure is located at an end of the conductive portion away from the electrical connection structure, and the initial A part of the connection section is used as the connection section, the remaining part of the initial connection section is used as the first part, and the conductive part is spaced apart from the connection section; A connection device is provided between the conductive part and the electrical connection structure, the connection device connects the connection segment to the conductive part, the electrical contact structure, the conductive part, the connection device, the The connecting segment and the first part form the conductive structure. The method for manufacturing a semiconductor structure according to claim 11, wherein the conductive structure is formed by an electroplating process. The method for fabricating a semiconductor structure according to claim 10, wherein the material of the conductive structure comprises any one of copper, tin or gold. A test system, comprising a test device, which is used to electrically connect the semiconductor structure described in any one of claims 1 to 9 for testing.

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