[go: up one dir, main page]

WO2023065750A1 - Procédé et appareil de synchronisation d'état, et dispositif - Google Patents

Procédé et appareil de synchronisation d'état, et dispositif Download PDF

Info

Publication number
WO2023065750A1
WO2023065750A1 PCT/CN2022/107583 CN2022107583W WO2023065750A1 WO 2023065750 A1 WO2023065750 A1 WO 2023065750A1 CN 2022107583 W CN2022107583 W CN 2022107583W WO 2023065750 A1 WO2023065750 A1 WO 2023065750A1
Authority
WO
WIPO (PCT)
Prior art keywords
lag
lag port
processor
state
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/107583
Other languages
English (en)
Chinese (zh)
Inventor
殷拔群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of WO2023065750A1 publication Critical patent/WO2023065750A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/111—Switch interfaces, e.g. port details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/24—Negotiation of communication capabilities
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • the present application relates to the field of communication technologies, and in particular to a state synchronization method, device and equipment.
  • Inter-device link aggregation group (multichassis link aggregation group, M-LAG) is a mechanism to achieve inter-device link aggregation.
  • a device is used to perform cross-device link aggregation with two other devices through active-active mode, which not only increases bandwidth, improve link reliability, load sharing, and improve link reliability from the board level to the device level.
  • device 1 is dual-homed to device 2 and device 3, device 2 and device 3 can communicate through a peer-to-peer link (peer-link), and device 2 and device 3 can also communicate through a tunnel .
  • peer-link peer-to-peer link
  • M-LAG ports also called M-LAG member ports.
  • the port connecting device 2 to device 1 is M-LAG member port 1
  • the port connecting device 3 to device 1 is M-LAG member port 2.
  • the multicast, broadcast and unknown unicast (broadcast, unknown unicast and multicast, BUM) traffic sent from device 1 to the network side is flooded between devices (as shown by the dotted line in Figure 1).
  • the unidirectional isolation mechanism to avoid sending traffic to M-LAG member interfaces through peer-link links.
  • the one-way isolation mechanism can also be used to avoid sending traffic from the peer-link link to the M-LAG member interface.
  • the unidirectional isolation mechanism refers to setting unidirectional traffic isolation between the peer-link link and the M-LAG member interface.
  • the network side When an M-LAG member interface fails, the network side does not perceive the failure, and may still send traffic to the M-LAG device where the failed M-LAG member interface is located. In this case, to ensure that traffic is not lost, the isolation of the M-LAG member ports of device 2 or device 3 needs to be released.
  • two M-LAG devices need to negotiate the state of the M-LAG member interface. The negotiation process consumes a long time, which affects the failure convergence speed.
  • the present application provides a state synchronization method, device and equipment, so as to shorten the negotiation process and improve the failure convergence speed and message forwarding efficiency in the case of an M-LAG port failure.
  • a state synchronization method is provided, the method is applied to the first device, wherein the first device and the second device form an inter-device link aggregation group M-LAG, the first device and the second
  • the devices each include a main processor and subordinate processors.
  • the lower-level processor of the first device will sense the state change and generate a first synchronization message, which includes the M-LAG port of the state change.
  • - Status information of the LAG port The lower-level processor of the first device sends the first synchronization message to the lower-level processor of the second device.
  • the lower-level processor of the second device After receiving the first synchronization message, the lower-level processor of the second device parses the first synchronization message to update the The isolation state of the M-LAG port of the second device determines the forwarding process of the service message and improves the forwarding efficiency of the service message. That is, in this implementation, when the status of the M-LAG port of the first device changes, the lower-level processors of the first device and the lower-level processors of the second device perform status synchronization negotiation without the need for each main processor to negotiate Then notify the corresponding lower-level processors, shorten the negotiation path, and improve the forwarding efficiency of service packets. Wherein, the lower-level processor is used to assist the main processor to complete the processing work that it cannot perform or perform with low efficiency and effect.
  • the lower-level processor of the first device senses that the state of the local M-LAG port changes, it will also update the isolation state of its own M-LAG port, so that according to the updated isolation state Determine whether to forward packets received by a specific interface to improve packet forwarding efficiency.
  • the form of lower-level processing of the first device depends on the form of the first device.
  • the first device includes only one printed circuit board, such as a box-type device
  • both the main processor and the lower-level processor of the first device are deployed on the printed circuit board.
  • the first device includes a main control board and an interface board
  • the main processor of the first device is deployed on the main control board
  • the lower-level processor of the first device is deployed on the interface.
  • the second device includes only one printed circuit board, such as a box-type device
  • both the main processor and the lower-level processor of the second device are deployed on the printed circuit board.
  • the second device includes a main control board and an interface board
  • the main processor of the second device is deployed on the main control board
  • the lower-level processor of the second device is deployed on the interface.
  • the lower-level processor of the first device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on the interface board.
  • the state change of the M-LAG port of the first device may include two situations, one is changing from a normal state to a fault state; the other is returning from a fault state to a normal state.
  • the first synchronization message includes the fault information of the M-LAG port of the first device, so that the second device receives the first synchronization message
  • the isolation state of the local M-LAG port is updated.
  • the first synchronization message includes the normal information of the M-LAG port of the first device, so that the second device receives the first synchronization After receiving the message, it can be known that the M-LAG port of the first device is back to normal, and then the isolation status of the local M-LAG port is updated.
  • the lower-level processor of the second device may also generate a state synchronization message when it senses that the state of the local M-LAG port changes, that is, the second synchronization message, and send a second synchronization message to the lower-level processor of the first device.
  • the lower-level processor of the first device updates the isolation state of the local M-LAG port according to the second synchronization message, and then when the first device receives the service message forwarded by the second device, Whether to forward the service message is determined according to the isolation state of the M-LAG port.
  • the lower-level processors of the two devices directly negotiate and update the M-LAG port without the main processor of the second device and the main processor of the first device participating in the negotiation.
  • the isolation state of the LAG port improves the negotiation speed and packet forwarding efficiency.
  • the lower-level processor of the second device senses that the status of the local M-LAG port changes, it will also update the isolation status of the local M-LAG port.
  • the lower-level processor of the first device updates the isolation state of the M-LAG port of the first device according to the second synchronization message, which may specifically be implemented in the following manner.
  • the lower-level processor of the first device deletes the isolation rule of the M-LAG port of the first device. That is, when the local M-LAG port is in a normal state and the peer M-LAG port is faulty, delete the isolation rule of the M-LAG port of the first device, so that the first device forwards to the local M-LAG port Packets received by the first path.
  • the lower-level processor of the first device issues the The isolation rule of the M-LAG port of the first device.
  • the isolation rule of the M-LAG port of the first device includes not forwarding the message received through the first path to the M-LAG port of the first device, and the first path is used for communication between the first device and the second device.
  • a state synchronization device is provided, the device is applied to a first device, and the first device and the second device belong to the same inter-device link aggregation group M-LAG, and the first device includes The main processor and the device, the second device includes a main processor and a lower-level processor, and the device includes: a generating unit, configured to generate a A first synchronization message, where the first synchronization message includes status information of the M-LAG port of the first device; a sending unit, configured to send the first synchronization message to a second device, so that the The lower-level processor of the second device updates the isolation state of the M-LAG port of the second device according to the first synchronization packet.
  • the apparatus further includes: an update unit, configured to update the isolation status of the M-LAG port of the first device when the state of the M-LAG port of the first device changes. state.
  • the first device includes only one printed circuit board, and the main processor of the first device and the device are both deployed on the printed circuit board.
  • the first device includes a main control board and an interface board, the main processor of the first device is deployed on the main control board, and the device of the first device is deployed on the interface board.
  • the device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on the interface board.
  • the state of the M-LAG port of the first device changes from a normal state to a fault state
  • the first synchronization message includes the M-LAG port of the first device or
  • the state of the M-LAG port of the first device changes from a fault state to a normal state
  • the first synchronization message includes the normal information of the M-LAG port of the first device .
  • the apparatus further includes: a receiving unit, configured to receive a second synchronization message sent by a lower-level processor of the second device, where the second synchronization message includes the second The state information of the M-LAG port of the device, the second synchronization message is generated by the lower-level processor in the second device when the state of the M-LAG port of the second device changes; the update unit , configured to update the isolation state of the M-LAG port of the first device according to the second synchronization packet.
  • the first device communicates with the second device through a first path
  • the updating unit is configured to: when the M-LAG port of the first device is in a normal state and the When the M-LAG port of the second device is in a fault state, delete the isolation rule of the M-LAG port of the first device; or, between the M-LAG port of the first device and the M-LAG port of the second device When the LAG ports are all in the normal state, or the M-LAG port of the first device is in the fault state, issue the isolation rule of the M-LAG port of the first device; the M-LAG port of the first device
  • the isolation rule includes not forwarding packets received through the first path to the M-LAG port of the first device.
  • a state synchronization system in the third aspect of the present application, includes a first device and a second device, the first device and the second device belong to the same inter-device link aggregation group M-LAG, Both the first device and the second device include a main processor and a lower-level processor; the lower-level processor of the first device is configured to, when the state of the M-LAG port of the first device changes, generating a first synchronization message, and sending the first synchronization message to the second device, the first synchronization message including the state information of the M-LAG port of the first device; the subordinate of the second device A processor, configured to update the isolation state of the M-LAG port of the second device according to the first synchronization message.
  • the first device includes only one printed circuit board, and both the main processor and the lower-level processor of the first device are deployed on the printed circuit board; and/or, the The second device includes only one printed circuit board, and both the main processor and the lower-level processors of the second device are disposed on the printed circuit board.
  • the first device includes a main control board and an interface board, the main processor of the first device is deployed on the main control board of the first device, and the The lower-level processor is deployed on the interface board of the first device; and/or, the second device includes a main control board and an interface board, and the main processor of the second device is deployed on the main On the control board, the lower-level processor of the second device is deployed on the interface board of the second device.
  • the lower-level processor of the first device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on an interface board of the first device; and/or , the lower-level processor of the second device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on an interface board of the second device.
  • a communication device in the fourth aspect of the present application, includes: a main processor, a lower-level processor, and a memory; the main processor is used to manage the communication device; the memory is used to store Instructions or computer programs; the lower-level processor is configured to execute the instructions or computer programs in the memory, so that the communication device executes the state synchronization method described in the first aspect.
  • the first device and the second device both include a main processor and a lower-level processor .
  • the lower-level processor of the first device When the state of the M-LAG port of the first device changes, the lower-level processor of the first device generates a first synchronization message when sensing the state change, and the first synchronization message includes the M-LAG port of the first device status information.
  • the first device sends the first synchronization message to the lower-level processor of the second device, and then the lower-level processor of the second device updates the isolation status of the local M-LAG port according to the first synchronization message.
  • the lower-level processor of the M-LAG device can generate a synchronization message, and directly send the synchronization message to the other party through the forwarding plane.
  • the forwarding plane of the end does not require the participation of the main processor, thereby shortening the negotiation process, so that the peer device can sense the status change of the M-LAG port in time, so as to quickly update the isolation status of its own M-LAG port, and improve the packet forwarding efficiency.
  • FIG. 1 is a schematic diagram of a cross-device link aggregation group M-LAG scenario
  • FIG. 2 is a schematic diagram of a multi-level M-LAG scenario provided by an embodiment of the present application
  • FIG. 3 is a flow chart of a state synchronization method provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an M-LAG port isolation table provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an interface board provided in an embodiment of the present application.
  • FIG. 6 is a structural diagram of a state synchronization device provided by an embodiment of the present application.
  • FIG. 7 is a structural diagram of a network device provided in an embodiment of the present application.
  • FIG. 8 is a structural diagram of another network device provided by the embodiment of the present application.
  • the M-LAG feature is mainly used in scenarios where servers or switches are dual-homed to the network. On the one hand, it can be used for load sharing and traffic, and on the other hand, it can be used for backup protection.
  • device 1, device 2 and device 3 in Figure 1 are switch A1, switch A2 and switch A3 respectively, in order to achieve redundant backup and improve link utilization rate, deploy M-LAG between switch A2 and switch A3 to implement dual-homing access to switch A1.
  • switch A2 and switch A3 can jointly forward traffic through load sharing.
  • the traffic can be quickly switched to another switch to ensure the normal operation of the business.
  • device 1 in Figure 1 is the server
  • device 2 and device 3 are switches B1 and B2 respectively
  • M-LAG is deployed between switch B1 and switch B2 to implement Dual-homing access to the server.
  • Switch B1 and switch B2 jointly forward traffic through load sharing. When one of the switches fails, it can be quickly switched to another switch to ensure the normal operation of the business.
  • M-LAG networking can be divided into single-level M-LAG and multi-level M-LAG.
  • single-level M-LAG is shown in Figure 1
  • multi-level M-LAG is shown in Figure 2.
  • Servers are dual-homed to switch D1 and switch D2, and M-LAG1 is deployed between switch D1 and switch D2.
  • -LAG1 includes M-LAG member port 1 and M-LAG member port 2; switch D1 is dual-homed to switch D3 and switch D4 to form M-ALG2, which includes M-LAG member port 3 and M-LAG member port 5; switch D2 is dual-homed to switch D3 and switch D4 to form M-LAG3, which includes M-LAG member port 4 and M-LAG member port 6.
  • M-LAG deployed between the switch D3 and the switch D4 can be cascaded with the lower-layer M-LAG.
  • multi-level M-LAGs you can use M-LAG identifiers to distinguish M-LAGs deployed on different switches.
  • the known unicast traffic sent from the user side to the network side is forwarded by the M-LAG device in load balancing on a flow-by-flow basis.
  • the known unicast traffic sent from the network side to the user side is also load-balanced and forwarded by the M-LAG device on a flow-by-flow basis.
  • the BUM traffic sent from the user side to the network side is flooded between devices.
  • the one-way isolation mechanism of M-LAG is used to isolate the traffic sent from the peer-link link to the Traffic on M-LAG member ports.
  • the one-way isolation mechanism is also used to isolate the traffic sent from the peer-link link to the M-LAG member interface.
  • the peer M-LAG device sets up unidirectional traffic isolation between the peer-link link and the M-LAG member interface, that is, from The incoming traffic of the peer-link interface will not be forwarded out through the M-LAG interface, so no loop will be formed. This is the M-LAG unidirectional isolation mechanism.
  • the interfaces directly connected to both ends of the peer-link link are peer-link interfaces.
  • the BUM traffic sent from the network side to the user side is still sent to the M-LAG device where the M-LAG member interface fails because the network does not detect the failure.
  • the peer M-LAG device needs to release the isolation mechanism between the peer-link interface and the M-LAG member ports of the peer M-LAG device, so that BUM traffic can pass through the peer-link link Bypass and forward to the user side.
  • the main control board of the first device learns of the failure of the M-LAG member port by subscribing to port fault events, and then communicates with the main control board of the second device.
  • M-LAG member port status negotiation so that the second device can synchronize the fault status of the M-LAG member port of the first device, and then the interface board of the second device releases the connection between the peer-link interface and its own M-LAG member port. isolation mechanism.
  • the M-LAG state negotiation process of the main control board is processed in the M-LAG module of the central processing unit (central processing unit, CPU), depending on whether the CPU can be scheduled in time.
  • CPU central processing unit
  • the embodiment of the present application provides a state synchronization method, which is used to solve the problem of long fault convergence time in an M-LAG fault scenario.
  • the lower-level processor of the first device and the lower-level processor of the second device can synchronize the status of the M-LAG port between devices without the need for a main processor Participation, improve the speed of negotiation, and then improve the speed of fault convergence.
  • FIG. 3 is a flow chart of a state synchronization method provided in the embodiment of the present application. As shown in FIG. 3, the method may include:
  • the first device and the second device construct an inter-device link aggregation group M-LAG, wherein both the first device and the second device include a main processor and a lower-level processor.
  • the lower-level processor is used to assist the main processor to complete the work that needs to be processed quickly.
  • the specific form of the main processor and the lower-level processor is related to the form of the first device.
  • the first device only includes one printed circuit board, such as a box-type device
  • the main processor and the lower-level processor of the first device are both deployed on the printed circuit board.
  • the first device includes a main control board and an interface board
  • the main processor of the first device is deployed on the main control board
  • the lower-level processor is deployed on the interface board.
  • the lower-level processor may be a central processing unit CPU, a network processor (network processor, NP), or a field programmable logic gate array (field programmable gate array, FPGA) on the interface board.
  • the lower-level processor is NP or FGPA.
  • the lower-level processor of the first device When the M-LAG port of the first device changes, the lower-level processor of the first device directly generates the first synchronization message when sensing the change of the M-LAG port, without the participation of the main processor.
  • the first synchronization packet includes status information of the M-LAG port of the first device.
  • the change of the M-LAG port of the first device may be that the M-LAG port of the first device fails, that is, the state of the M-LAG port of the first device changes from a normal state to a fault state.
  • the first synchronization report The document includes the fault information of the M-LAG port of the first device; or the M-LAG port of the first device recovers from a fault, that is, the state of the M-LAG port of the first device changes from a fault state to a normal state.
  • the A synchronization packet includes normal information of the M-LAG port of the first device.
  • the first synchronization packet may also include an M-LAG identifier, so that the second device - the LAG identifier determines that the M-LAG port itself and the M-LAG port of the first device belong to the same M-LAG identifier.
  • the first device is the switch D3 in Figure 2.
  • the M-LAG member port 3 in the switch D3 fails, the M-LAG member port 3 belongs to M-LAG2, and the first synchronization message includes the M-LAG member Fault information of port 3 and M-LAG2.
  • the first device sends a first synchronization packet to the second device.
  • the lower-level processor of the second device updates the isolation state of the M-LAG port of the second device according to the first synchronization message
  • the first device sends the first synchronization message to the second device. That is, the lower-level processor of the first device sends the first synchronization packet to the lower-level processor of the second device, and then the lower-level processor of the second device determines the M-LAG of the first device through the first synchronization packet
  • the status of the port is used to update the isolation status of the local M-LAG port according to the status of the M-LAG port of the first device. That is, the lower-level processor of the second device determines to delete the isolation rule of the M-LAG port on the second device according to the state of the M-LAG port of the first device, or issues the isolation rule of the local M-LAG port.
  • the first device is device 2 in FIG. 1, and the second device is device 3 in FIG. 1.
  • the lower-level processor in device 2 senses that the status of M-LAG member port 1 of device 2 changes, Generate the first synchronization message, and send the first synchronization message to the lower-level processor of the device 3 through the peer-link link.
  • the first device is device 3 in Figure 1
  • the second device is device 2 in Figure 1
  • the lower-level processor in device 3 senses that the status of M-LAG member port 2 of device 3 changes , generate a first synchronization message, and send the first synchronization message to the lower-level processor of device 2 through the peer-link link.
  • the lower-level processor of the second device can maintain an M-LAG port state table, and the M-LAG port state table includes both the local (second device) M-LAG port state and the peer device (first device) M-LAG port status.
  • the lower-level processor of the second device After receiving the first synchronization packet sent by the first device, the lower-level processor of the second device updates the M-LAG port state table maintained by itself according to the first synchronization packet, and then according to the updated M-LAG port state table
  • the state table updates the isolation state table of the M-LAG port of the second device maintained by the switch chip (hereinafter referred to as LSW).
  • the M-LAG port state table can be maintained in the NP, and the NP of the second device receives the first synchronization message sent by the first device. After the message, refresh the maintained M-LAG port state table, and update the isolation state of the M-LAG port of the second device in the LSW according to the refreshed M-LAG port state table.
  • the lower-level processor of the second device deletes the M-LAG port of the second device Port isolation rules, so that the M-LAG port of the second device can forward packets received through the first path.
  • the first path is a communication path between the first device and the second device, such as the peer-link in FIG. 1 .
  • the isolation rule of the M-LAG port of the second device includes not forwarding the message received through the first path to the M-LAG port of the second device.
  • the isolation rule for M-LAG member port 2 of device 3 may be that device 3 does not forward packets received through the peer-link link to M-LAG member port 2,
  • M-LAG member port 1 of the first device device 2
  • M-LAG member port 2 is in a normal state
  • device 3 will delete the isolation rule on M-LAG member port 2, so that device 3 can Forward the packet received through the peer-link link to M-LAG member port 2, so as to forward the packet to device 1.
  • the lower-level processor of the second device delivers the isolation rule of the M-LAG port of the second device. That is, when both the M-LAG ports of the peer device (the first device) and the local device (the second device) are in the normal state, or the M-LAG port of the local device is in the fault state, the lower-level processor of the local device will Send the isolation rule of the M-LAG port of the local device, so that the M-LAG port of the local device does not forward the packets received through the first path.
  • the first device is device 2 in Figure 1
  • the second device is device 3 in Figure 1.
  • M-ALG member port 1 recovers from a fault and M-LAG member port 2 is in a normal working state
  • device 3 The lower-level processing of the M-LAG member port 2 will issue the isolation rule so that device 3 will not forward the packets received through the peer-link link to the M-LAG member port 2, that is, the It will be forwarded from M-LAG member port 2 to avoid loops.
  • M-ALG member port 2 of device 3 (the second device) fails, regardless of whether M-LAG member port 1 is faulty or normal, the lower-level processor of device 3 will issue the isolation status of M-LAG member port 2. rule.
  • LLinkSate indicates the status of the local M-LAG port
  • PlinkState indicates the status of the M-LAG port of the peer device
  • UP indicates normal
  • Down indicates failure.
  • the isolation action of the local device is: Isolation; when the M-LAG port status of the local device is UP and the M-LAG port status of the peer device is Down, the isolation action of the local device is: delete the isolation between the Peer-link interface and the M-LAG port; When the M-LAG port status of the local device is Down, regardless of whether the M-LAG port status of the peer device is UP or Down, the isolation action of the local device is: send the isolation between the peer-link interface and the M-LAG port .
  • the lower-level processor of the first device When the state of the M-LAG port of the first device changes, the lower-level processor of the first device will also update the isolation state of its own M-LAG port. That is, when the state of the M-LAG port of the first device changes, the lower-level processor of the first device can detect the state change in time, and update the isolation state of the local M-LAG port according to the state change. Specifically, when the state of the M-LAG port of the first device changes from a normal state to a fault state, the lower-level processor of the first device issues an isolation rule of the M-LAG of the first device. That is, issue the isolation between the peer-link interface and the local M-LAG interface.
  • the state of the M-LAG port of the second device may also change.
  • the lower-level processor of the second device senses that the state of the local M-LAG port Generate a second synchronization packet, where the second synchronization packet includes status information of the M-LAG port of the second device.
  • the second synchronization packet may also include an M-LAG identifier.
  • both the main processor and the lower-level processor of the second device are deployed on the printed circuit board.
  • the main processor is deployed on the main control board
  • the lower-level processor is deployed on the interface board.
  • the lower-level processor may be a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on the interface board.
  • the lower-level processor is NP or FGPA, it can realize the synchronization of the M-LAG port status between two M-LAG devices through hardware; when the lower-level processor is CPU, it can realize the synchronization of two M-LAG ports through software. Synchronization of M-LAG port status between LAG devices.
  • a change in the state of the M-LAG port of the second device may be a failure of the M-LAG port of the second device, that is, the M-LAG port of the second device changes from a normal state to a fault state.
  • the second synchronization message Including fault information of the M-LAG port of the second device.
  • the change of the status of the M-LAG port of the second device can restore the failure of the M-LAG port of the second device, that is, the M-LAG port of the second device changes from the fault state to the normal state.
  • the second synchronization The packet includes normal information of the M-LAG port of the second device.
  • S305 The second device sends a second synchronization packet to the first device.
  • the lower-level processor of the first device updates the isolation state of the M-LAG port of the first device according to the second synchronization packet.
  • the lower-level processor of the second device after the lower-level processor of the second device generates the second synchronization message, it directly sends the second synchronization message to the lower-level processor of the first device, so that the lower-level processor of the first device according to the second
  • the second synchronization message updates the isolation state of the M-LAG port of the first device, without requiring the main processors of the first device and the second device to participate in state negotiation, thereby increasing the convergence speed.
  • the NP is connected to the CPU and the LSW respectively.
  • the CPU is the control unit of the interface board.
  • the running program and statically configured parameters are stored in the flash memory.
  • the code and data executed when the program is running are stored in the random access memory (RAM) connected to the CPU.
  • RAM random access memory
  • the CPU controls the LSW to initialize, deliver service table items, send and receive protocol packets, and perform various interruptions (failure or recovery of ports).
  • the LSW can choose an external RAM to store the packets to be forwarded, so as to solve the problem of insufficient internal cache of the LSW.
  • the PHY connected under the LSW completes the interconnection of optical ports or electrical ports between devices.
  • the NP and the LSW cooperate with each other to implement rapid traffic convergence when the M-LAG port fails or recovers from the failure.
  • the NP on the interface board of the first device is called NP1
  • the NP on the interface board of the second device is called NP2.
  • NP1 the NP on the interface board of the first device
  • NP2 the NP on the interface board of the second device
  • the first device reports the status change of the M-LAG port to NP1.
  • NP1 constructs the first synchronization message according to the state change of the local M-LAG port, and sends it to the second device.
  • NP1 When NP1 perceives the state change of the local M-LAG port, it updates the M-LAG port state table maintained by itself, generates a first synchronization message, and sends the first synchronization message to the second device.
  • the first synchronization message may include not only the M-LAG port state information of the first device, but also the M-LAG identifier. Two M-LAG ports belonging to the same M-LAG correspond to the same M-LAG ID.
  • NP2 updates the locally stored M-LAG port state table according to the first synchronization message, and updates the isolation state of the local M-LAG port according to the M-LAG port state table.
  • the LSW of the second device after receiving the first synchronization message, sends the first synchronization message to NP2, and the NP2 obtains the M-LAG identifier and the first device ID by parsing the first synchronization message.
  • the state of the M-LAG port and determine the corresponding M-LAG port state table according to the M-LAG identifier, and then update the M-LAG port state table.
  • the M-LAG state table includes not only the state of the local M-LAG port, but also the state of the M-LAG port of the peer device (the first device).
  • NP2 updates the isolation state of the local M-LAG port according to the updated M-LAG port state table. Specifically, NP2 will update the isolation table in the LSW according to the updated M-LAG port status table.
  • NP1 can directly construct a synchronization message to synchronize the status of M-LAG ports between devices without relying on the negotiation between the main control board and the interface board, which improves the speed of status synchronization.
  • NP2 can control the M-LAG port isolation status in the LSW according to the updated M-LAG port status, without relying on the main control board to issue forwarding entries, which improves traffic convergence performance.
  • the original M-LAG port state negotiation process can still be retained for the first device and the second device including the main control board and the interface board.
  • the board sends the negotiation result (for example, updating the isolation table in the LSW) to the lower-level processor of the interface board, so that the synchronization result of the above state synchronization method can be verified.
  • an embodiment of the present application provides a state synchronization device, which will be described below with reference to the accompanying drawings.
  • this figure is a structural diagram of a state synchronization device provided by the embodiment of the present application.
  • the device can be applied to the first device, and can realize the function of the lower-level processor of the first device in the above method embodiment , the first device and the second device belong to the same inter-device link aggregation group M-LAG, the first device includes a main processor and the apparatus, the second device includes a main processor and a lower-level processor, and the apparatus 600 may include : generating unit 601 and sending unit 602.
  • a generating unit 601 configured to generate a first synchronization message when the state of the M-LAG port of the first device changes, where the first synchronization message includes the state of the M-LAG port of the first device information.
  • the generating unit 601 reference may be made to the relevant description of S301 in the foregoing method embodiments.
  • a sending unit 602 configured to send the first synchronization message to the second device, so that the lower-level processor in the second device updates the M-LAG port of the second device according to the first synchronization message state of isolation.
  • the sending unit 602 reference may be made to the relevant description of S302 in the foregoing method embodiments.
  • the device further includes: an update unit (not shown in the figure);
  • An updating unit configured to update the isolation status of the M-LAG port of the first device when the status of the M-LAG port of the first device changes.
  • the update unit refer to the related description of S303.
  • the first device includes only one printed circuit board, and the main processor of the first device and the device are both deployed on the printed circuit board.
  • the first device includes a main control board and an interface board
  • the main processor is deployed on the main control board
  • the device is deployed on the interface board.
  • the device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on the interface board.
  • the state of the M-LAG port of the first device changes from a normal state to a fault state
  • the first synchronization message includes the M-LAG port of the first device or
  • the state of the M-LAG port of the first device changes from a fault state to a normal state
  • the first synchronization message includes the normal information of the M-LAG port of the first device .
  • the device further includes: a receiving unit and an updating unit (not shown in the figure);
  • a receiving unit configured to receive a second synchronization packet sent by a lower-level processor of the second device, where the second synchronization packet includes status information of an M-LAG port of the second device, and the second synchronization
  • the message is generated by the lower-level processor in the second device when the state of the M-LAG port of the second device changes.
  • An updating unit configured to update the isolation state of the M-LAG port of the first device according to the second synchronization message.
  • the updating unit refer to the related description of S306 in the above method embodiment.
  • the first device communicates with the second device through a first path
  • the updating unit is configured to: when the M-LAG port of the first device is in a normal state and the When the M-LAG port of the second device is in a fault state, delete the isolation rule of the M-LAG port of the first device; or, between the M-LAG port of the first device and the M-LAG port of the second device When the LAG ports are all in the normal state, or the M-LAG port of the first device is in the fault state, issue the isolation rule of the M-LAG port of the first device; the M-LAG port of the first device
  • the isolation rule includes not forwarding packets received through the first path to the M-LAG port of the first device.
  • FIG. 7 is a schematic structural diagram of a network device provided by an embodiment of the present application.
  • the network device may be, for example, the first device or the second device in the embodiment shown in FIG. 3 .
  • the network device 700 includes: a processor 710 , a communication interface 720 , a memory 730 and a processor 740 .
  • the number of processors in the packet forwarding device 700 may be one or more, and two processors are taken as an example in FIG. 7 .
  • the processor 710 is the main processor, and the processor 740 is the lower-level processor.
  • the processor 710, the communication interface 720, the memory 730, and the processor 740 may be connected through a bus system or other methods. In FIG. 7, the connection through the bus system 750 is taken as an example.
  • Processor 740 may be a CPU, NP, or a combination of CPU and NP.
  • the processor 740 may further include a hardware chip.
  • the aforementioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof.
  • the aforementioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof.
  • the communication interface 720 is used to receive and send packets, specifically, the communication interface 720 may include a receiving interface and a sending interface.
  • the receiving interface can be used to receive messages, and the sending interface can be used to send messages.
  • the memory 730 may include a volatile memory (volatile memory), such as a random access memory (random access memory, RAM); the memory 730 may also include a non-volatile memory (English: non-volatile memory), such as a flash memory ( flash memory), a hard disk (hard disk drive, HDD) or a solid-state drive (solid-state drive, SSD); the memory 730 may also include a combination of the above types of memory.
  • the memory 730 may, for example, store the aforementioned status information of the M-LAG port.
  • the memory 730 stores operating systems and programs, executable modules or data structures, or their subsets, or their extended sets, and the programs may include various operating instructions for implementing various operations.
  • the operating system may include various system programs for implementing various basic services and processing hardware-based tasks.
  • the processor 740 can read the program in the memory 730 to implement the state synchronization method provided in the embodiment of the present application.
  • the memory 730 may be a storage device in the network device 700 , or a storage device independent of the network device 700 .
  • the bus system 750 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus system 750 can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 7 , but it does not mean that there is only one bus or one type of bus.
  • FIG. 8 is a schematic structural diagram of another network device 800 provided by an embodiment of the present application.
  • the network device 800 may be configured as the first device or the second device in the foregoing embodiments.
  • the network device 800 includes: a main control board 810 and an interface board 830 .
  • the main control board 810 is also referred to as a main processing unit (main processing unit, MPU) or a route processing card (route processor card).
  • the main control board 810 is used to control and manage various components in the network device 800. Device management, device maintenance, protocol processing functions.
  • the main control board 810 includes a CPU 811 and a memory 812 .
  • the interface board 830 is also called a line interface unit card (line processing unit, LPU), a line card (line card), or a service board.
  • the interface board 830 is used to provide various service interfaces and implement forwarding of data packets.
  • the service interface includes but not limited to Ethernet interface, POS (Packet over SONET/SDH) interface, etc., and the Ethernet interface is, for example, a Flexible Ethernet client (Flexible Ethernet client, FlexE Client) interface.
  • the interface board 830 includes: a central processing unit 831 , a network processor 832 , a forwarding entry storage 834 and a physical interface card (physical interface card, PIC) 833 .
  • the CPU 831 on the interface board 830 is used to control and manage the interface board 830 and communicate with the CPU 811 on the main control board 810 .
  • the network processor 832 is configured to implement message forwarding processing.
  • the form of the network processor 832 may be a forwarding chip.
  • the processing of the uplink message includes: processing of the inbound interface of the message, lookup of the forwarding table; processing of the downlink message: lookup of the forwarding table, and so on.
  • the physical interface card 833 is used to implement the interconnection function of the physical layer. The original traffic enters the interface board 830 through this, and the processed packets are sent out from the physical interface card 833 .
  • the physical interface card 833 includes at least one physical interface.
  • the physical interface card 833 is also called a daughter card, which can be installed on the interface board 830, and is responsible for converting the photoelectric signal into a message, checking the validity of the message and forwarding it to the network processor 832 for processing.
  • the central processor 831 of the interface board 803 can also execute the functions of the network processor 832 , such as implementing software forwarding based on a general-purpose CPU, so that the physical interface card 833 does not need the network processor 832 .
  • the network device 800 includes multiple interface boards.
  • the network device 800 further includes an interface board 840
  • the interface board 840 includes: a central processing unit 841 , a network processor 842 , a forwarding entry storage 844 and a physical interface card 843 .
  • the network device 800 further includes a switching fabric unit 820 .
  • the SFU 820 may also be called a switch fabric unit (SFU).
  • SFU switch fabric unit
  • the switching fabric board 820 is used to complete data exchange between the interface boards.
  • the interface board 830 and the interface board 840 may communicate through the switching fabric board 820 .
  • the main control board 810 is coupled to the interface board 830 .
  • the main control board 810, the interface board 830, the interface board 840, and the switching fabric board 820 are connected to the system backplane through the system bus to realize intercommunication.
  • an inter-process communication protocol IPC
  • IPC inter-process communication
  • the network device 800 includes a control plane and a forwarding plane.
  • the control plane includes a main control board 810 and a central processing unit 831.
  • the forwarding plane includes various components for performing forwarding, such as a forwarding entry storage 834, a physical interface card 833, and a network processing device 832.
  • the control plane executes router functions, generates forwarding tables, processes signaling and protocol packets, configures and maintains device status, and sends the generated forwarding tables to the forwarding plane.
  • the network processor 832 based on the control plane
  • the issued forwarding table looks up and forwards the packets received by the physical interface card 833 .
  • the forwarding table issued by the control plane may be stored in the forwarding table item storage 834 . In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.
  • the network processor 832 may generate a first synchronization packet, and trigger the physical interface card 833 to send the first synchronization packet to the second device.
  • the sending unit 602 in the state synchronization device 600 may be equivalent to the physical interface card 833 or the physical interface card 843 in the network device 800; the generation unit 601 in the state synchronization device 600 may be equivalent to the network device 800 processor 832 or network processor 842.
  • the operations on the interface board 840 in the embodiment of the present application are consistent with the operations on the interface board 830 , and are not repeated for brevity.
  • the network device 800 in this embodiment may correspond to the first device or the second device in the foregoing method embodiments, and the interface board 830 and/or interface board 840 in the network device 800 may implement the foregoing method embodiments
  • the functions and/or various steps implemented by the first device or the second device will not be repeated here.
  • main control boards there may be one or more main control boards, and when there are multiple main control boards, it may include an active main control board and a standby main control board.
  • the network device can have at least one SFU, through which the data exchange between multiple interface boards can be realized, and large-capacity data exchange and processing capabilities can be provided. Therefore, the data access and processing capabilities of network devices with a distributed architecture are greater than those with a centralized architecture.
  • the form of the network device can also be that there is only one board, that is, there is no switching fabric board, and the functions of the interface board and the main control board are integrated on this board.
  • the central processing unit and the main control board on the interface board The central processing unit on the board can be combined into one central processing unit on the board to perform the superimposed functions of the two.
  • the data exchange and processing capabilities of this form of equipment are low (for example, low-end switches or routers and other network equipment). Which architecture to use depends on the specific networking deployment scenario.
  • the embodiment of the present application also provides a chip system, including a processor and an interface circuit, the interface circuit is used to receive instructions and transmit them to the processor; the processor, for example, can be one of the state synchronization devices 600 shown in FIG. 6
  • the specific implementation form can be used to execute the above method for state synchronization.
  • the processor is coupled with a memory, and the memory is used to store a program or an instruction.
  • the chip system implements the method in any one of the above method embodiments.
  • processors in the chip system there may be one or more processors in the chip system.
  • the processor can be realized by hardware or by software.
  • the processor may be a logic circuit, an integrated circuit, or the like.
  • the processor may be a general-purpose processor implemented by reading software codes stored in a memory.
  • the memory can be integrated with the processor, or can be set separately from the processor, which is not limited in this application.
  • the memory can be a non-transitory processor, such as a read-only memory ROM, which can be integrated with the processor on the same chip, or can be respectively arranged on different chips.
  • the setting method of the processor is not specifically limited.
  • an embodiment of the present application further provides a state synchronization system, and the system may include: a first device and a second device.
  • the first device and the second device belong to the same cross-device link aggregation group M-LAG, and both the first device and the second device include a main processor and a lower-level processor.
  • the lower-level processor of the first device is configured to generate a first synchronization message when the state of the M-LAG port of the first device changes, and send the first synchronization message to the second device
  • the first synchronization message includes status information of the M-LAG port of the first device
  • the lower-level processor of the second device is configured to update the isolation state of the M-LAG port of the second device according to the first synchronization packet.
  • the first device includes only one printed circuit board, and both the main processor and the lower-level processor of the first device are deployed on the printed circuit board; and/or, the The second device includes only one printed circuit board, and both the main processor and the lower-level processors of the second device are disposed on the printed circuit board.
  • the first device includes a main control board and an interface board, the main processor of the first device is deployed on the main control board of the first device, and the The lower-level processor is deployed on the interface board of the first device; and/or, the second device includes a main control board and an interface board, and the main processor of the second device is deployed on the main On the control board, the lower-level processor of the second device is deployed on the interface board of the second device.
  • the lower-level processor of the first device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on an interface board of the first device; and/or , the lower-level processor of the second device is a central processing unit CPU, a network processor NP or a field programmable logic gate array FPGA on an interface board of the second device.
  • the disclosed system, device and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical business division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each business unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software business units.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Hardware Redundancy (AREA)

Abstract

Est divulgué dans la présente demande un procédé de synchronisation d'état. Pour deux dispositifs qui constituent un groupe d'agrégation de liaisons multichâssis (M-LAG), chaque dispositif d'un premier dispositif et d'un second dispositif comprend un processeur principal et un processeur secondaire. Lorsque l'état d'un port M-LAG du premier dispositif change, le processeur secondaire du premier dispositif génère un premier message de synchronisation, le premier message de synchronisation comprenant des informations d'état du port M-LAG du premier dispositif. Le premier dispositif envoie le premier message de synchronisation au second dispositif, et le processeur secondaire du second dispositif met à jour un état d'isolation d'un port M-LAG local selon le premier message de synchronisation. Ainsi, lorsque l'un des dispositifs M-LAG détecte qu'un port M-LAG local a changé, un processeur secondaire du dispositif M-LAG peut générer un message de synchronisation, et peut envoyer directement le message de synchronisation à un plan de transfert d'un terminal homologue au moyen d'un plan de transfert, sans la participation de processeurs principaux, de sorte qu'un processus de négociation est raccourci, et l'efficacité de transfert de message est améliorée.
PCT/CN2022/107583 2021-10-21 2022-07-25 Procédé et appareil de synchronisation d'état, et dispositif Ceased WO2023065750A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111231100.1A CN116016385A (zh) 2021-10-21 2021-10-21 一种状态同步方法、装置及设备
CN202111231100.1 2021-10-21

Publications (1)

Publication Number Publication Date
WO2023065750A1 true WO2023065750A1 (fr) 2023-04-27

Family

ID=86023949

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/107583 Ceased WO2023065750A1 (fr) 2021-10-21 2022-07-25 Procédé et appareil de synchronisation d'état, et dispositif

Country Status (2)

Country Link
CN (1) CN116016385A (fr)
WO (1) WO2023065750A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118827523A (zh) * 2024-06-28 2024-10-22 新华三技术有限公司 一种设备接口配置管理方法、装置、设备及可读存储介质

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8730963B1 (en) * 2010-11-19 2014-05-20 Extreme Networks, Inc. Methods, systems, and computer readable media for improved multi-switch link aggregation group (MLAG) convergence
US20140140219A1 (en) * 2012-11-22 2014-05-22 Fujitsu Limited Transmission device and transmission method
US20180019938A1 (en) * 2016-07-12 2018-01-18 Dell Products, L.P. System and method for virtual link trunking
CN108512751A (zh) * 2017-02-28 2018-09-07 华为技术有限公司 一种端口状态处理方法以及网络设备
CN108632099A (zh) * 2018-05-18 2018-10-09 新华三技术有限公司 一种链路聚合的故障检测方法及装置
CN109151620A (zh) * 2017-06-28 2019-01-04 中兴通讯股份有限公司 聚合组端口切换方法、装置及光线路终端olt设备
CN110166356A (zh) * 2018-02-11 2019-08-23 华为技术有限公司 发送报文的方法和网络设备
CN110351127A (zh) * 2019-06-28 2019-10-18 迈普通信技术股份有限公司 一种优雅重启的方法、设备及系统
CN111786805A (zh) * 2019-04-04 2020-10-16 华为技术有限公司 一种专线业务的配置方法、设备及存储介质
CN112134796A (zh) * 2019-06-25 2020-12-25 中兴通讯股份有限公司 一种实现流量切换的方法、装置及系统
CN112217658A (zh) * 2019-07-11 2021-01-12 华为技术有限公司 一种堆叠分裂处理方法及装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8730963B1 (en) * 2010-11-19 2014-05-20 Extreme Networks, Inc. Methods, systems, and computer readable media for improved multi-switch link aggregation group (MLAG) convergence
US20140140219A1 (en) * 2012-11-22 2014-05-22 Fujitsu Limited Transmission device and transmission method
US20180019938A1 (en) * 2016-07-12 2018-01-18 Dell Products, L.P. System and method for virtual link trunking
CN108512751A (zh) * 2017-02-28 2018-09-07 华为技术有限公司 一种端口状态处理方法以及网络设备
CN109151620A (zh) * 2017-06-28 2019-01-04 中兴通讯股份有限公司 聚合组端口切换方法、装置及光线路终端olt设备
CN110166356A (zh) * 2018-02-11 2019-08-23 华为技术有限公司 发送报文的方法和网络设备
CN108632099A (zh) * 2018-05-18 2018-10-09 新华三技术有限公司 一种链路聚合的故障检测方法及装置
CN111786805A (zh) * 2019-04-04 2020-10-16 华为技术有限公司 一种专线业务的配置方法、设备及存储介质
CN112134796A (zh) * 2019-06-25 2020-12-25 中兴通讯股份有限公司 一种实现流量切换的方法、装置及系统
CN110351127A (zh) * 2019-06-28 2019-10-18 迈普通信技术股份有限公司 一种优雅重启的方法、设备及系统
CN112217658A (zh) * 2019-07-11 2021-01-12 华为技术有限公司 一种堆叠分裂处理方法及装置

Also Published As

Publication number Publication date
CN116016385A (zh) 2023-04-25

Similar Documents

Publication Publication Date Title
US10686749B2 (en) Packet sending method and network device
US9628375B2 (en) N-node link aggregation group (LAG) systems that can support various topologies
US9660939B2 (en) Protection switching over a virtual link aggregation
US7639605B2 (en) System and method for detecting and recovering from virtual switch link failures
US8654630B2 (en) Techniques for link redundancy in layer 2 networks
CN112565046B (zh) 同步多播路由器能力
US9385944B2 (en) Communication system, path switching method and communication device
US20140301401A1 (en) Providing aggregation link groups in logical network device
US20060029056A1 (en) Virtual machine task management system
US9065678B2 (en) System and method for pinning virtual machine adapters to physical adapters in a network environment
US20240267324A1 (en) Packet forwarding method and apparatus
CN112995041B (zh) 网络通信方法、装置、电子设备及存储介质
CN115152192A (zh) Pce受控网络可靠性
CN111901133A (zh) 一种组播切换方法、装置、网络设备和存储介质
CN104040973B (zh) 聚合组链路协商方法、装置和系统
WO2023065750A1 (fr) Procédé et appareil de synchronisation d'état, et dispositif
CN114531319B (zh) 报文发送方法、设备及系统
CN118740727A (zh) 基于云平台的高可用组播流量转发方法及系统
CN106533771A (zh) 一种网络设备以及控制信息传输方法
JP2013192022A (ja) ネットワーク装置、リンクアグリゲーションシステム及びそれらに用いる冗長化方法
CN116980952A (zh) 跨分段网络的故障检测方法、通信系统及相关装置
KR101442567B1 (ko) 링 네트워크 토폴로지에서 프레임기반 라우팅을 이용한 프레임 무손실 통신 방법
WO2020156355A1 (fr) Système, dispositif et procédé de partage de charge, carte unique et support de stockage
JPWO2007018164A1 (ja) 通信システム、ノード、端末、プログラム及び通信方法
CN103840952B (zh) 用于mac黑洞预防的方法以及相应的分布式双宿节点

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22882372

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22882372

Country of ref document: EP

Kind code of ref document: A1