WO2023047329A1

WO2023047329A1 - Inverted conductive paths on a substrate

Info

Publication number: WO2023047329A1
Application number: PCT/IB2022/058967
Authority: WO
Inventors: Mehdi NOSRATI
Original assignee: National Research Council of Canada
Current assignee: National Research Council of Canada
Priority date: 2021-09-21
Filing date: 2022-09-22
Publication date: 2023-03-30
Anticipated expiration: 2024-03-21

Abstract

A structure for laying out electrically conductive paths over a substrate provides both AC and DC structures that can be used to improve the performance of existing structures. In an AC structure, a microstrip transmission can be reduced to half of a conventional length by having part of the signal path on the top of a substrate, and then the remaining part on the bottom of the substrate. This can be accomplished using vias, but should also be matched by moving the ground path, which is a second electrically conductive path, from the bottom of the substrate to the top so that the signal path is always opposed to a ground path. A similar structure of alternating electrical paths can be used in both solar cells and batteries, where segments of the anode of cathode can be inverted so that they maintain their opposed configuration while inverted.

Description

INVERTED CONDUCTIVE PATHS ON A SUBSTRATE

Cross Reference to Related Applications

[001] This application claims the benefit of priority to US Provisional Patent Application Serial No. 63/246,412 entitled “Inverted Conductive paths on a substrate” filed September 21, 2021 the contents of which are incorporated herein by reference.

Technical Field

[002] This application relates generally to a conductor configuration that can be used for a microstrip transmission line or a capacitor for connection to a battery or solar cell. More particularly this application relates to configuration of electrical conductors that alternate from a top to a bottom of a substrate that allows for a compact microstrip transmission line that can be implemented in a smaller footprint than a conventional stripline and a capacitor that provides improved efficiency for battery and solar cell energy implementations.

Background

[003] As telecommunications networks progress towards new generations, there is increased demand for higher throughput communication networks, with lower latency and more ubiquitous coverage. To enable these networks, new designs in antenna design and signal transmission and control are required. Reducing the size and footprint of these designs is essential to both manage power consumption and to allow the designs to be implemented in devices sufficiently small to allow for portability.

[004] One of the underlying technologies in this field is a so-called microstrip transmission line which can be built using a thin flat conductor on one side of an insulator, parallel to a ground plane. These micro strip transmission lines are designed to carry short wavelength signals so that despite the small length of the microstrip transmission line, it behaves like a classical transmission line having a much longer length.

[005] Figure 1 illustrates a pair of conventional microstrip transmission lines on a printed circuit board (PCB) 50. PCB 50 is shown as transparent to better provide the viewer with an understanding of its structure. It should be apparent to those skilled in the art that PCB 50 has length 152, depth d 54 and height h 56. Sitting atop PCB 50 are a pair of transmission lines 58 and 60, while the base of PCB 50 form a ground plane 62. Ground plane 62 may be provided by an uninterrupted electrically conductive layer that be connected to an electrical ground. In some embodiments, transmission lines 58 and 60 would be shown as having height, but for the purposes of this discussion, the height of these lines will be omitted. [006] In many implementations, this pairing of transmission lines allows for a balanced signal pair that may be used to carry high speed signals. Similarly, these transmission lines may be curved, with the radius of curvature being determined in accordance with the width Wo of the line. Determining the radius of curvature of the stripline as a function of the width Wo allows for designs that avoid reflection of the signal back towards the source.

[007] It should be understood that the electromagnetic wave carried by the stripline is at least partially transmitted within the dielectric material that forms the PCB substrate.

[008] Transmission lines can be used for any number of functions on a PCB including their use in power amplifiers and other components of interest to wireless communication systems. In many of these uses, the length of the transmission line has to be matched to the wavelength of the signal being transmitted. This provides a lower limit on the size of a conventional microstrip transmission line. As a result of this lower limit, and required spacing requirements between components, there is a limitation on the miniaturization processes employed in designing communication systems. For 5G transmissions taking advantage of mm-wave technology, the wavelength of many signals may be up to 1 cm (10mm), and using microstrip transmission lines for the design of components like a band pass filter requires the use of 1 quarter wavelength lines coupled with a half wavelength transmission line. This can result in a large PCB size for various applications.

[009] It should also be understood that in its most basic form, a conventional microstrip transmission line is simply the placement of a ground line and a signal line in a geometric configuration where the signal line is used to carry a signal. Effectively, a microstrip transmission line can be seen as the equivalent to the placement of an anode and cathode in a structure such as a solar cell or a battery.

[0010] Figure 2 illustrates a simplified rendition of the anode and cathode structure of a conventional solar cell 64. Cell 64 has a P-type doped semiconductor layer 66 connected to an electrode 68, which effectively acts as a cathode. An N-type doped layer 70 is connected to an electrode 72 which effectively acts as the anode, and is analogous to the ground plane shown in Figure 1. Between the P-type layer 66 and the N-type layer 70 is a depletion layer 74 that spaces apart the two doped layers. This depletion layer 74 provides a source for the electrons that will move as a result of the exposure of the solar cell to light.

[0011] Figure 3 illustrates a simplified structure for a battery 76. Within battery 76 is a cathode 78 and an anode 82 with these layers separated by a separator 86. Conventionally, the separator layer 86 is configured to allow the controlled movement of charge in a defined direction during a discharge cycle, and can be reloaded with power / charge by the application of a voltage during a charging cycle. The anode 84 is connected to an electrode 84 that allows for connection to external loads, while the cathode 78 is connected to an electrode 80 which provides a positive power terminal to the battery. Those skilled in the art will appreciate that the power stored by the battery is often a function of the size and chemistry of the separator layer 86.

[0012] It would therefore be beneficial to have a mechanism to allow for a more compact design of components using microstrip transmission lines and other such electrode structures.

Summary

[0013] It is an object of the aspects of the present invention to obviate or mitigate the problems of the above-discussed prior art. Conventional designs for transmission lines, batteries and solar cells make use of a static substrate and conductive path topology. In embodiments of the present invention, conductive paths that would otherwise exist on a two- dimensional plane, make use of both top and bottom surfaces of the substrate.

[0014] In a first aspect of the present invention, there is provided an electronic device. This device comprises a substrate and first and second electrical paths. The substrate has a top and bottom side. These top and bottom sides are opposing sides. The first electrical path has a first segment on the top side of the substrate, and a second segment, electrically connected to the first segment on the bottom side of the substrate. The second electrical path, is paired with the first electrical path, and has a first segment on the bottom side of the substrate, and a second segment, electrically connected to the first segment, on the top side of the substrate, the first and second segments of the second electrical path aligned with the first and second segments of the first electrical path respectively.

[0015] In an embodiment of the first aspect, the substrate comprises a printed circuit board. In a further embodiment, at least one of the first segments of the first electrical path is a trace printed on the top surface of the printed circuit board. In another embodiment, the second electrical path is a ground plane. In a further embodiment, the first segment of the first electrical path is electrically connected to the second segment of the first electrical path through a via. In another embodiment, the length of the first and second electrical paths are matched. In another embodiment, the first and second segments of the second electrical path are substantially vertically aligned with the first and second segments of the first electrical path respectively. In another embodiment, the device further comprises third and fourth electrical paths. The third path is parallel to the first electrical path, and has a first segment on the top side of the substrate and a second segment, electrically connected to the first segment, on the bottom side of the substrate. The fourth electrical path is paired with the third electrical path, and has a first segment on the bottom side of the substrate, and a second segment, electrically connected to the first segment, on the top side of the substrate, the first and second segments of the fourth electrical path aligned with the first and second segments of the third electrical path respectively.

[0016] In another embodiment of the first aspect, the substrate comprises an anode, cathode and separation layer of a battery cell. In a further embodiment, the first electrical path is connected to the cathode. In another embodiment, a portion of the cathode is located adjacent the bottom side of the substrate and is connected to the second segment of the first electrical path. In a further embodiment, the second electrical path is connected to the anode. In another embodiment, a portion of the anode is located adjacent to the top side of the substrate and is connected to the second segment of the first electrical path. In another embodiment, the first electrical path further comprises a third segment on the top of the substrate, connected to the cathode, electrically connected to the second segment of the first electrical path and the second electrical path further comprises a third segment on the bottom of the substrate, connected to the anode, electrically connected to the second segment of the second electrical path.

[0017] In another embodiment, the electronic device comprises a solar cell and wherein the substrate comprises a depletion layer situated between a P-type doped semiconductor layer and an N-type doped semiconductor layer. In a further embodiment, the first electrical path is connected to the P-type doped semiconductor layer. In another embodiment, a portion of the P-type doped semiconductor layer is located adjacent to the bottom of the substrate, and is connected to the second segment of the first electrical path. In another embodiment, the second electrical path is connected to the N-type doped semiconductor layer. In a further embodiment, a portion of the N-type doped semiconductor layer is located adjacent to the top of the substrate, and is connected to the second segment of the second electrical path. In another embodiment, the first electrical path comprises a third segment on the top of the substrate, connected to the P-type doped semiconductor layer, electrically connected to the second segment of the first electrical path and the second electrical path comprises a third segment on the bottom of the substrate, connected to the N-type doped semiconductor layer, electrically connected to the second segment of the second electrical path. Brief Description of the Drawings

[0018] Embodiments of the present invention will now be described in further detail by way of example only with reference to the accompanying figure in which:

Figure 1 illustrates a conventional pair of microstrip transmission lines;

Figure 2 illustrates a conventional solar panel making use of an anode and cathode on opposing sides of the substrate;

Figure 3 illustrates a conventional battery making use of an anode and cathode on opposing sides of a substrate;

Figure 4illustrates a pair of microstrip transmission lines according to an embodiment of the present invention;

Figure 5 illustrates an alternate embodiment of a pair of microstrip transmission lines; Figure 6 illustrates the microstrip transmission lines of Figures 4 or 5 schematically as resistances with a load;

Figure 7 illustrates a solar cell according to an embodiment; and Figure 8 illustrates a battery according to an embodiment.

[0019] In the above described figures like elements have been described with like numbers where possible.

Detailed Description

[0020] In the instant description, and in the accompanying figures, reference to dimensions may be made. These dimensions are provided for the enablement of a single embodiment and should not be considered to be limiting or essential. Disclosure of numerical range should be understood to not be a reference to an absolute value unless otherwise indicated. Use of the terms about or substantively with regard to a number should be understood to be indicative of an acceptable variation of up to ±10% unless otherwise noted.

[0021] The use of microstrip transmission lines is driven by a number of different factors including the ease of implementation. PCB driven implementations allow for complex patterns to be laid out consecutively to provide functions such as antennae, couplers, power dividers and filters. As demands for higher frequency transmissions, including mm-wave transmissions, increase, microstrip transmission lines become more and more important to implementations in both mobile devices and mobile network infrastructure. This increases the requirements for miniaturization of these components. As noted above, this has traditionally been a demand that is limited by the nature of microstrip transmission lines, and the requirement that they be matched to the wavelength of the signal being transmitted. [0022] To address requirements for decreased size, embodiments of the present invention provide for a microstrip transmission line that can provide similar or improved characteristics to a conventional microstrip transmission line with a reduction in length of approximately 50%.

[0023] Figure 4 illustrates a coupled microstrip transmission line (MTL) 100 according to an embodiment of the present invention. A substrate 102 has first 104 and second 106 surfaces. While in the prior art, a MTL would exist solely on a single surface with the ground plane occupying the other surface, in the illustrated embodiment, each of the coupled MTLs 100 makes use of both first surface 104 and second surface 106.

[0024] Treating the second surface 106 as a ground plane, conductive element 108 situated on surface 104, is part of the ground plane through its connection to the ground plane on surface 106 through a vertical connection 110. This vertical connection may take any number of forms including through the use of a via. Below conductive element 108, and separated from the ground plane in surface 106 is a conductive element 112 that can be used to carry the transmitted signal. The transmitted signal is also carried by conductive element 114 which is connected to conductive element 112 through vertical connection 116. Similarly, the second microstrip transmission line is composed of conductive element 118 on surface 104, and conductive element 122 on the second surface 106, connected by a vertical connection 120. The associated ground is provided through conductive element 124 which is connected to the ground plane on the second surface through vertical connection 126.

[0025] It should be understood that the illustrated embodiment makes use of a microstrip transmission line that proceeds along the length of the substrate by alternating the surface on which the ground plane and the transmission line are situated. This may be referred to as an inverse couple MTL. In testing it has been found that for a conventional MTL, such as that illustrated in Figure 1, with a length of 15mm, the overall length of the coupled MTL 100 can be reduced to 7.5 mm, for an overall reduction of 50%. When holding transmitted frequency constant, the performance is found to be maintained despite the reduction in length. This configuration can be used to reduce the length of other conventional MTLs, so that what would normally be */s wavelength, * wavelength or Vi wavelength MTLs could be replaced by Vie wavelength, */s wavelength and % wavelength MTLs respectively.

[0026] Figure 5 illustrates an alternate embodiment for the pair MTLs 100. As before paired MTLs are implemented within substrate 102 having a first surface 104 and a second surface 106 having a grounding plane. Ground element 108 sits on surface 104, but is connected to the ground plane through the use of vertical element 110. It should be understood that the strip 108 used as a ground connection on the top surface 104 need not be situated at the edge of the substrate 102. Similarly, although vertical element 110 is shown as a simple vertical element, it may be angled in any direction, or it may make use of a traditional via to connect the ground plane 106 to a small strip that is connected to ground element 108.

[0027] Conductive elements 122 are located on the second surface 106, but are separated from the ground plane so that they can connect to conductive elements 118 and 114 through vertical connections 116 and 120 respectively. In this configuration, the signal is still transmitted as before by a conductive element that is partially located on the first surface 104, and partially located on a second surface 106, but is substantially located on a different surface than the ground plane.

[0028] In communications systems, a variety of components such as filters and amplifiers are required to allow for the selection of a received signal component based on the frequency of the received component, and for the amplification of a signal or more commonly a signal component. In many implementations, microstrip lines (and in many cases pairs of microstrip lines) are employed. Because the length of the MTL is conventionally tied to the wavelength (and thus the frequency) of the signal of interest, there has been a barrier to the reduction of the communication systems based on the lower limit of the size of the various components. When a filter and amplifier are implemented in series, and they are both limited to a length of the wavelength in question, the size of the overall components becomes cumbersome. Through a configuration in which the signal path alternates the side of the substrate that it is mounted to (with a corresponding alternation of the side of the substrate that the ground plane is mounted to), the overall length of a microstripline structure can be reduced by up to 50%.

[0029] This structural modification can also provide a performance advantage over a conventional MTL structure, even while reducing the overall length. It should be understood that in addition to the degrees of freedom allowed in a conventional MTL implementation, the embodiments discussed above allow for an additional degree of freedom through the presence of a new parameter in the design. Through the use of this parameter, the amplitude of the coupled signal can be controlled. Because these effects are frequency sensitive, signals outside the desired wavelength range (or the desired frequency range) are suppressed because they cannot be efficiently coupled.

[0030] These effects may be explained with reference to Figure 6 which schematically shows an MTL 150 according to the above illustrated embodiments. A first section 152 of the MTL 150 in which the signal and ground lines appear as they would be in a conventional implementation, and a second section 154 in which the signal and ground lines have been inverted as shown in the previous figures. In this section (from z=-l_m to z=0). In the second section 154 the polarization of the coupled EM wave propagated through the signal path 156 is inverted as a result of the inverted orientation of the signal path 156 and ground plane 158. A signal propagated along the full path would thus experience both polarization orientations. The voltage and current on the a conventional transmission line are shown in equations (1) and (2) below, and the voltage reflection coefficient is shown in equation (3). At the location -I, the input impedance can be calculated using (4) above.

[0031] Because of the change in the polarization of the wave carried in MTL 150, the above equations do not properly model the system, unless they account for a phase shift

.

Similarly, the voltage and current on the transmission line can be described with the understanding that

[0032] It should be understood that represents a ratio of the inverted and non-inverted sections of the MTL 150. This yields equation (5) showing the voltage on the TL, equation

(6) showing the current on the TL, and equation (7) showing the reflection current, while the input impedance is shown in equation (8)

[0033] A comparison of equations (4) and (8) shows that the specific phase can be used to allow for a reduction in the length of MTL 150 in comparison to a conventional MTL. [0034] It should be noted that the open circuit and short circuit versions of the MTL 150 can be modelled and compared to the corresponding conventional implementation. This confirms that there can be an effective reduction in the length of the transmission line by 50% (a factor of 2).

[0035] As noted earlier, the structure of the MTL described above bear similarities to both solar cells and batteries. Figure 7 illustrates a simplified view of an embodiment of a solar cell 200. Solar cell 200 has a P-typed doped layer 202, that is largely aligned with the top of the cell 200 and an N-type doped layer 204 that is largely aligned with the bottom of the cell 200. It will be noted that a segment of the P-type layer 202, and a segment of the N-type layer 204 are effectively switched in orientation so that there is a P-type layer 202 in line with N-type layers 204, and an N-type layer 204 in line with P-Type layers 202. Between the P- type layers and the N-Type layers, is a depletion layer 206. Electrically connected to the P- type layer is the conductive surface 210 which functions as a cathode. Conductive surface 210 is also connected to conductive surface 214 through vertical connection 212. One skilled in the art will appreciate that in different embodiments, conductive surface 214 may be present on the opposite side of the P-type layer that it is connected to. Electrically connected to the N-type layer 204, is conductive surface 216 which serves as the anode for cell 200 and is connected to conductive surface 220 through vertical connection 218.

[0036] In conventional solar panels, there has been an observed phenomenon that as a panel generates power, a heating of the solar cells occurs. This heating can have a negative impact on the performance of a solar cell, and of the panel in which the cell is situated. Typically, the heating is believed to be associated with a single layer within the solar cell. Using the architecture of solar cell 200 allows for the heat generating layer to be interrupted as portions of the P-type doped layer are interspersed within the N-type doped layer. This spreads out the heat generating and may allow for a lower operating temperature.

[0037] Furthermore, simulations of this configuration indicate that while keeping the output voltage constant, in comparison to a prior art design, a higher output current can be maintained. Although typically a higher output voltage is associated with an increased operating temperature, this was not observed in simulations, possibly for the reasons stated above.

[0038] Figure 8 illustrates the novel structure of a battery 250 using the designed discussed above. Battery 250 has a cathode 252 and an anode 254, but a portion of the anode 254 is inverted so that it appears in line with parts of the cathode 252, while a corresponding piece of the cathode 252 appears in line with parts of the anode 254. Between the anode 254 and cathode 252 is a separation layer 270. This separation layer may include the chemistry used to accept charge during a charging cycle, store the received charge and discharge it when a load is connected to the anode 254 and cathode 252. As noted above, an electrical contact 256 is connected to cathode 252 at the top layer of battery 250. The electrical contact 256 is connected to contact 260 affixed to cathode 252 at the bottom of battery 250 by way of vertical connection 258. Similarly, electrical contact 262 is connected to the anode 254 at the bottom of battery 250, and is connected to contact 266, which is affixed to cathode 254 at the top of battery 250, through vertical connection 264.

[0039] By allowing portions of the anode and cathode to be inverted, this design of a battery allows for a different configuration of the electrodes 256 and 262. In some embodiments this may allow the battery to receive larger quantities of charge in a time interval (increased rate of charging) and may similarly allow for a greater rate of discharge (higher output current). The design of the battery, using cell 250 can constrain the output current as needed. It should also be understood that the input charging current that can be handled by cell 250 is similarly increased. Those skilled in the art will further appreciate that by interspersing the anode 254 and cathode 252 segments the increased heating caused by charging and discharging that are typically associated with one of the anode and cathode, can be moderated by having the layer segment that is being heated being surrounded by segments that are not being heated. This allows for better dissipation of the heating, and may aid in increasing the increased current discussed above. £

[0040] In the above described embodiments, a pair of electrical paths are substantially vertically aligned with each other on opposing sides of a substrate. In the MTL embodiment, the sbustrate is a PCB, while in the other embodiments the substrate is more involved, being either a portion of a battery cell or a solar cell. These electrical paths would conventionally start and conclude on a single surface of the substrate. However, as shown above, the electrical paths in the illustrated embodiments are segmented, so that different segments of the path are located on different surfaces of the substrate, while remaining electrically connected. With the MTL embodiment, one of the paths is used for carrying a high frequency signal while the second path is used as a ground plane. With the other embodiments, instead of an alternating current signal, the conductive paths are used as the anode and cathode of a battery, or the positive and negative terminals of a solar cell. In these embodiments, portions of the substrate materials themselves maybe inverted along with a corresponding conductive path. It should be well understood that when conductive paths are inverted, they are isolated from the other paths on that sufrace. Thus, in the battery example, the segment of the anode and corresponding electrical path that are inverted are isolated from the cathode and its corresponding electrical path, and similarly for the cathode, the portion that is inverted is isolated from the neighboring segments of the anode.

[0041] As noted above, the sizes provided in the drawings are provided for exemplary purposes and should not be considered limiting of the scope of the invention, which is defined solely in the claims.

[0042] In the instant description, and in the accompanying figures, reference to dimensions may be made. These dimensions are provided for the enablement of a single embodiment and should not be considered to be limiting or essential. The sizes and dimensions provided in the drawings are provided for exemplary purposes and should not be considered limiting of the scope of the invention, which is defined solely in the claims.

Claims

1. An electronic device comprising: a substrate having top and bottom sides opposing each other; a first electrical path, having a first segment on the top side of the substrate, and a second segment, electrically connected to the first segment on the bottom side of the substrate; a second electrical path, paired with the first electrical path, having a first segment on the bottom side of the substrate, and a second segment, electrically connected to the first segment, on the top side of the substrate, the first and second segments of the second electrical path aligned with the first and second segments of the first electrical path respectively.

2. The electronic device of claim 1 wherein the substrate comprises a printed circuit board.

3. The electronic device of claim 2 wherein at least one of the first segments of the first electrical path is a trace printed on the top surface of the printed circuit board.

4. The electronic device of any one of claims 2 and 3 wherein the second electrical path is a ground plane.

5. The electronic device of any one of claims 2 to 4 wherein the first segment of the first electrical path is electrically connected to the second segment of the first electrical path through a via.

6. The electronic device of any one of claims 2 to 5 wherein the length of the first and second electrical paths are matched.

7. The electronic device of any one of claims 2 to 6 wherein the first and second segments of the second electrical path are substantially vertically aligned with the first and second segments of the first electrical path respectively

8. The electronic device of any one of claims 2 to 7 further comprising: a third electrical path parallel to the first electrical path, having a first segment on the top side of the substrate and a second segment, electrically connected to the first segment, on the bottom side of the substrate; and a fourth electrical path, paired with the third electrical path, having a first segment on the bottom side of the substrate, and a second segment, electrically connected to the first segment, on the top side of the substrate, the first and second segments of the fourth electrical path aligned with the first and second segments of the third electrical path respectively.

9. The electronic device of claim 1 wherein the substrate comprises an anode, cathode and separation layer of a battery cell.

10. The electronic device of claim 9 wherein the first electrical path is connected to the cathode.

11. The electronic device of claim 10 wherein a portion of the cathode is located adjacent the bottom side of the substrate and is connected to the second segment of the first electrical path.

12. The electronic device of any one of claims 9 to 11 wherein the second electrical path is connected to the anode.

13. The electronic device of claim 12 wherein a portion of the anode is located adjacent to the top side of the substrate and is connected to the second segment of the first electrical path.

14. The electronic device of any one of claims 9 to 13 wherein: the first electrical path further comprises a third segment on the top of the substrate, connected to the cathode, electrically connected to the second segment of the first electrical path; and the second electrical path further comprises a third segment on the bottom of the substrate, connected to the anode, electrically connected to the second segment of the second electrical path.

15. The electronic device of claim 1 wherein the electronic device comprises a solar cell and wherein the substrate comprises a depletion layer situated between a P-type doped semiconductor layer and an N-type doped semiconductor layer.

16. The electronic device of claim 15 wherein the first electrical path is connected to the P-type doped semiconductor layer.

17. The electronic device of claim 16 wherein a portion of the P-type doped semiconductor layer is located adjacent to the bottom of the substrate, and is connected to the second segment of the first electrical path.

18. The electronic device of any one of claims 15 to 17 wherein the second electrical path is connected to the N-type doped semiconductor layer.

19. The electronic device of claim 18 wherein a portion of the N-type doped semiconductor layer is located adjacent to the top of the substrate, and is connected to the second segment of the second electrical path.

20. The electronic device of any one of claims 15 to 19 wherein: 14 the first electrical path comprises a third segment on the top of the substrate, connected to the P-type doped semiconductor layer, electrically connected to the second segment of the first electrical path; and the second electrical path comprises a third segment on the bottom of the substrate, connected to the N-type doped semiconductor layer, electrically connected to the second segment of the second electrical path.