WO2022256994A1

WO2022256994A1 - Driving and encoding of a digitial liquid crystal on silicon (lcos) display

Info

Publication number: WO2022256994A1
Application number: PCT/CN2021/098745
Authority: WO
Inventors: Denise LEE; Guang Yang; Tengjie SUI
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-07
Filing date: 2021-06-07
Publication date: 2022-12-15
Anticipated expiration: 2023-12-07
Also published as: CN117377995A; EP4338149A1; EP4338149A4

Abstract

Described is a driver (300) for driving a pixel of a digital liquid crystal on silicon display, the driver comprising: a control circuit (301) comprising one or more transistors, the control circuit (301) configured to: clock an input binary signal for latching the state of the pixel for each frame; and form a logical control signal for the pixel in dependence on the input binary signal; a voltage scaling circuit (302) comprising one or more transistors, the voltage scaling circuit (302) configured to: receive the logical control signal from the control circuit (301); and form a pixel drive signal for driving the pixel in dependence on the logical control signal; wherein the size of the transistors in the voltage scaling circuit (302) is greater than the size of the transistors in the control circuit (301). By providing the transistors in the voltage scaling circuit (302) of greater size than the transistors in the control circuit (301) this may enable to overall size of the driver (300) to be reduced which may reduce the pixel pitch size.

Description

DRIVING AND ENCODING OF A DIGITIAL LIQUID CRYSTAL ON SILICON (LCOS) DISPLAY

FIELD OF THE INVENTION

This invention relates to apparatus and methods for driving a digital Liquid Crystal on Silicon (LCoS) display, for example for buffered digital pixel architecture.

BACKGROUND

Some examples of LCoS displays have been disclosed in the following prior art:

Introduction to Microdisplays: (2006) David Armitage, Ian Underwood and Shin-Tson Wu (ISBN-13 978-0-470-85281-1) . Chapter 2 (Electronic Addressing) and Chapter 3 (CMOS Backplane Technology) discuss pixel drive scheme circuit design and fabrication.

VAN LCOS Microdisplays: A Decade of Technological Evolution: (2011) Dieter Cuypers, Herbert De Smet, André Van Calster. Vertically Aligned Nematic (VAN) liquid crystal (LC) for LCoS is a widely adopted LC technology for high contrast ratio and fast response time operation of LCoS.

Beyond the display: phase-only liquid crystal on Silicon devices and their applications in photonics: (2019) Grigory Lazarev, Po-Ju Chen, Johannes Strauss, Nicolas Fontaine, and Andrew Forbes. This publication builds on the Introduction to Microdisplays and highlights a more recent application of LCoS in optical data communications (for Wavelength Selective Switch, WSS) as Spatial Light Modulators (SLM) , limitation of shrinking pixel pitch (fringe effect, pixel cross-talk, phase flicker) associated with method of drive scheme and the application of SLM for laser beam shaping.

SXRD (Silicon X-tal Reflective Display) ; A New Display Device for Projection Displays: (2005) S. Hashimoto, O. Akimoto, H. Ishikawa, T. Kiyomiya, T. Togawa, T. Isozaki, H. Abe, M. Nakai, H. Terakawa, H. Horikiri, T. Ishii, M. Kogure. This publication demonstrates mass-produced 4K (4096x2160, 8.5um pixel) Analog LCoS for high quality projection display utilising VAN LC.

High-Performance Displays for Wearable and HUD Applications: (2018) Akheelesh K. Abeeluck, Andrew Iverson, Howard Goetz, Edmund Passon. This publication demonstrates a state of the art digital drive scheme, with a pixel pitch of 3.015um for 4K LCoS Microdisplay for Augmented Reality (AR) and Head-Up Display (HUD) . The publication illustrates a digital drive ASIC with low latency (<1ms) , high video frame rate (>120Hz) and a color field sequential operation of color sub-frame rate (>720Hz) . The adopted digital interface is a MIPI-D-Phy.

Digital Driving Method for Low Frame Frequency and 256 Gray Scales in Liquid Crystal on Silicon Panels: (2012) Jin-Seong Kang, Oh-Kyong Kwon. This publication demonstrates a LCoS microdisplay (854x480 pixel) for projection with digital drive scheme with PWM for 8bit greyscale. A binary weighted sub-frame is summed together as a single frame in which an 8bit resolution greyscale constitutes a 34 sub-frame. The adopted interface is a LVDS.

Digital Modulation on Micro Display and Spatial Light Modulator: (2017) Chen Wang, Ron Hsu. This publication demonstrates a method of digital driving scheme (or digital modulation) with PWM and ‘Terminated Write Pointer’ which is a said built-in scheme to turn off a pixel without changing the written data. The paper presents a method of encoding pulse width, where it integrates (or averages) to a resulting greyscale.

Active matrix field sequential color electrically suppressed helix ferroelectric liquid crystal for high resolution displays: (2018) Liangyu Shi, Abhishek Kumar Srivastava, Alex Cheung, Chia-Ting Hsieh, Ching-Lang Hung Ching-Hsiang Lin, Ching-Huan Lin, Norio Sugiura, Chia-Wei Kuo, Vladimir G. Chigrinov, Hoi Sing Kwok. This publication demonstrates a method of analogue drive scheme for ferroelectric LC, which translates an analogue voltage of an in pixel storage element to a digital PWM with the application of a global (i.e. with respect to all pixels) voltage ramp waveform.

An analogue pixel, such as a DRAM-style analogue pixel, is described in Introduction to Microdisplays. A device structure of SXRD is described in SXRD (Silicon X-tal Reflective Display) ; A New Display Device for Projection Displays. It is common to provide a pass switch to a capacitor as the analogue voltage storage element, with the exception of Active matrix field sequential color electrically suppressed helix ferroelectric liquid crystal for high resolution displays which demonstrates an alternative structure where there is an in-pixel conversion of analogue voltage to digital PWM. In all of the prior art there is provided a DAC component to translate the digital data representation to an analogue voltage. The associated electro-optic response of LC with the application of analogue drive scheme is illustrated in Introduction to Microdisplays.

Figures 1A and 1B herein show schematic illustrations of a driver 100 for driving a pixel of a digital liquid crystal on silicon display 109 of the prior art (Introduction to Microdisplays) . Figure 1A shows a block level schematic illustration of the driver 100 for driving a pixel of a digital liquid crystal on silicon display 109 of the prior art. Figure 1B shows a schematic cross-sectional view of a single pixel 109 being driven by the driver 100 of the prior art. The driver 100 may employ off-chip voltages V0 106 and V1 105 routed to the pixel pad and a fixed voltage Vc on the ITO electrode 113.

Figure 2 schematically illustrates an analogue liquid crystal driving voltage for a digital LCoS pixel of the prior art. (Introduction to Microdisplays) . Vc is the common electrode 109 voltage and V0 and V1 are the pixel voltages.

Frame buffering on LCoS may be utilised as a way of synchronising to a common electrode. The common electrode may comprise a transparent conductive Indium Tin Oxide (ITO) , front plane. In this way, the LCoS may maintain a DC balance, in other words the DC component or voltage offset is zero. The DC balance may be beneficial for the synchronisation of illumination technique such as field sequential colour. The synchronisation operation may retain displayed data whilst the next frame is being updated in the background, a global signal may be initiated to transfer the stored frame as the displayed data. In this way, the synchronisation operation may allow for concurrent writing and displaying of an image frame.

A first drawback of frame buffering for an analogue pixel is the need for additional of storage elements, such as a capacitor. The complementary metal-oxide-semiconductor (CMOS) fabrication process of the capacitor may be defined by the device area (A) of the conductors, the separation distance (d) of the conductors and the effective dielectric constant (ε) of separation (C=εA/d) . By increasing the size of the capacitor, the driver size may be increased which may increase the pixel pitch, or separation distance.

A second drawback of frame buffering for an analogue pixel is the manner of transferring written information. The transfer may be a charge transfer, i.e. between storage elements, which may require a charge division. The charge transfer may require a high voltage which may require large electrical components. By increasing the size of the electrical components, the driver size may be increased which may increase the pixel pitch, or separation distance. The voltage may be reduced by using an amplifier device, in basic form of a source follower configuration, but this may limit the signal range of voltages and may result in a non-linearity of operation. Thus, without a specialised CMOS process or a process tolerant to high voltages, neither is conducive to shrinking the pixel pitch.

It is desirable to develop a driver and method that overcomes the above problems.

SUMMARY

According to a first aspect there is provided a driver for driving a pixel of a digital liquid crystal on silicon display, the driver comprising: a control circuit comprising one or more transistors, the control circuit configured to: clock an input binary signal to latch a state of the pixel for each sub-frame of a frame; and form a logical control signal for the pixel in dependence on the input binary signal; a voltage scaling circuit comprising one or more transistors, the voltage scaling circuit configured to: receive the logical control signal from the control circuit; and form a pixel drive signal for driving the pixel in dependence on the logical control signal; wherein the size of the transistors in the voltage scaling circuit is greater than the size of the transistors in the control circuit.

The size of the transistors, or other suitable electrical components, may determine the size of the driver. As each pixel is driven by a driver, the size of the driver may in turn determine how close the pixels can be positioned relative to one another. This is known as pixel pitch size. It is preferable for the pixel pitch size to be reduced so that the pixel density, and therefore quality of the display, can be increased.

By providing the transistors in the voltage scaling circuit of greater size than the transistors in the control circuit, this may enable the overall size of the driver to be reduced which may reduce the pixel pitch size.

In some implementations, the driver may be configured wherein the transistors of the control circuit and the transistors of the voltage scaling circuit are formed by a dual gate oxide process. In some implementations, the dual gate oxide process may be a dual gate oxide CMOS process.

A dual gate oxide CMOS process may enable the gate oxide thickness to be varied on different types of transistors, for example MOSFET transistors. The different gate oxide thicknesses may be used to provide various operational characteristics of the transistor.

By forming the transistors using a dual gate oxide CMOS process, this may provide a variability in the operational characteristics of the MOSFET transistors.

In some implementations, the driver may be configured wherein the gate oxide thickness of the transistors in voltage scaling circuit is greater than the gate oxide thickness of the transistors in the control circuit.

By providing a thicker gate oxide layer on the voltage scaling circuit than the control circuit, this may enable the transistors of the control circuit to be smaller than the transistors of the voltage scaling circuit. Additionally, the thicker gate oxide layer on the voltage scaling circuit may enable the voltage scaling circuit to withstand higher operating voltages.

In other words, in the voltage scaling circuit, its minimum sized transistor (that of thick gate oxide) is dimensionally larger than thin gate oxide transistor. Whereas the control circuit comprises thin gate oxide transistors, where its minimum sized transistor (that of thin gate oxide) is smaller than thick gate oxide transistor and operates with a lower voltages than thick gate oxide transistor.

In some implementations, the driver may be configured wherein the operating voltage of the voltage scaling circuit is greater than operating voltage of the control circuit.

In some implementations, the driver may be configured wherein the operating voltage of the voltage scaling circuit is greater than 3V and the operating voltage of the control circuit is less than 0.9V.

By configuring the driver to operate the voltage scaling circuit at a higher voltage domain than the control circuit, this may increase the driving voltage to the pixels where high voltage may be required while separating the voltage domain from the pixels where high voltage may not be required. In this way, this may reduce the number of high voltage devices (i.e. thick gate oxide transistors) which may enable pixel pitch shrink.

In some implementations, the driver may be configured wherein the voltage scaling circuit comprises an overcurrent protective device for limiting current in the voltage scaling circuit.

By providing an overcurrent protective device in the voltage scaling circuit this may enable the current to be limited. This may reduce switching shoot-through current due to concurrency of switching edges. This may allow the driver to maintain a lower average power dissipation and robust power distribution network on the LCoS chip.

In some implementations, the driver may be configured wherein the driver comprises a pitch size of less than 3.7um.

By providing a pitch size of less than 3.7um this may enable a higher display quality (i.e. higher resolution) for a given active area in a projection system. Likewise in minimising the active area for a given resolution, cost attributable to chip die, packaging assemblies and optics can be lowered, as is the miniaturisation of a packaged module for portability

In some implementations, the driver may be configured wherein the control circuit comprises a static random-access (SRAM) memory configured to store the input binary signal and the logical control signal.

By providing an SRAM memory, this may enable the input binary signal to be clocked and stored until it is required to form the logical control signal. Additionally, the SRAM memory may enable the logical control to be formed and stored until the it is required by the voltage scaling circuit.

In some implementations, the driver may be configured such that the SRAM memory comprises a master memory bit and a slave memory bit, wherein: the control circuit is configured to clock the input binary signal in dependence on the master memory bit; and the control circuit is configured to form and hold the logical control signal in dependence on the slave memory bit.

By clocking the input binary signal in dependence on the master memory bit, this may enable the input binary signal to be stored until it is required by the slave memory bit. By forming and holding the logical control signal in dependence on the slave memory bit, this may enable the logical control signal to be stored until it is required by the voltage scaling circuit.

In some implementations, the driver may be configured wherein the voltage scaling circuit comprises a digital to analogue converter (DAC) to form the pixel drive signal for driving the pixel.

In some implementations, the driver may be configured wherein the logical control signal is digital, and the pixel drive signal is analogue.

By providing a DAC in the voltage scaling circuit, this may enable the binary digital input to be converted into an analogue signal that can be used by the pixel.

According to a second aspect there is provided a driver for driving a pixel of a digital liquid crystal on silicon display, the driver comprising a circuit with one or more transistors configured to: receive a grey level for each pixel of a set of pixels of the display; determine a PWM duty cycle for each pixel of the set of pixels in dependence on the grey level; generate a PWM waveform for each pixel of the set of pixels in dependence on the PWM duty cycle, the PWM waveform defining an output illumination intensity control; control each pixel of the set of pixels to illuminate for an illumination period, the illumination period being dependent on the PWM waveform; wherein the illumination periods of any two of the set of pixels do not start simultaneously.

If more information needs to be sent to control the pixel, this may result in a greater data interfacing requirement between the host controller and the LCoS backplane. An increasing data interfacing rate may result in an increasing number of signalling pins or an increasing data signalling frequency. Both of which may incur a cost in resources on both the host controller and LCoS backplane. A high bandwidth (frequency) data signalling may also be incompatible or limited by the CMOS process. It is therefore preferable to reduce the data interfacing requirement to enable an increase pixel density or higher frame refresh rate.

By controlling each pixel of a set of pixels to illuminate for an illumination period in which the illumination period of any two of the set of pixels do not start simultaneously, this may reduce the data interface requirement during any given global update of the pixels. By reducing the data interface requirement, this may result in an increased pixel density or higher frame refresh rate.

In some implementations, the circuit is configured to receive the grey level for each pixel of the display.

By receiving the grey level for each pixel of the display, this may enable the entire display to receive a global update during which the illumination periods of any two of the set of pixels do not start simultaneously.

In some implementations, the circuit is configured to control each pixel of the set of pixels to illuminate for an illumination period comprising a frame period, the frame period comprising a plurality of sub-frame periods.

By dividing the frame period into a plurality of sub-frame periods, this may provide a resolution to the frame period resulting in the ability to vary the length of the illumination period. As the illumination period is dependent on the PWM waveform, the ability to vary the length of the illumination period may enable the illumination intensity control to be varied.

In some implementations, the circuit is configured to control each pixel of the set of pixels to illuminate for an illumination period wherein the illumination periods of any two of the set of pixels do not start in the same sub-frame period.

By controlling each pixel of a set of pixels to illuminate for an illumination period in which the illumination period of any two of the set of pixels do not start in the same sub-frame, this may reduce the data interface requirement during any given global update of the pixels. By reducing the data interface requirement this may result in an increased pixel density or higher frame refresh rate. Additionally, as the pixels are not updated in the same sub-frame period, this may enable the data interface requirement to be further reduced through the use of a prescribed scheduled update.

In some implementations, the circuit is configured wherein the frame period comprises a blanking period between each sub-frame period.

In some implementations, the circuit is configured to receive the grey level for each pixel of a set of pixels of the display during the blanking period. A blanking period may be a period where the pixel outputs no luminance.

In some implementations, the circuit is configured to control each pixel of the set of pixels to illuminate during the sub-frame period after the blanking period.

In a driver comprising a single SRAM memory, without a separate master memory bit and slave memory bit (i.e. a frame buffering feature) , providing a frame period comprising a blanking period may enable to pixels to be updated during the blanking period.

In some implementations, the circuit is configured wherein the duration of the blanking period is less than the duration of the sub-frame period.

By providing a blanking period with a shorter duration than the sub-frame period, this may minimise the period during which the pixel is not being controlled to illuminate, so as to improve the maximum luminance output of a display.

In some implementations, the circuit is configured to receive the grey level for each pixel of the set of pixels of the display during the sub-frame period and hold the grey level for each pixel of the set of pixels of the display until the pixel is updated in a subsequent sub-frame period. In some implementations, the grey level may be held constant over time for more than one sub-frame period.

In some implementations, the circuit is configured to control each pixel of the set of pixels to illuminate during the subsequent sub-frame period.

In a driver comprising a separate master memory bit and slave memory bit the grey level information may be held until the subsequent sub-frame period without the need for a blanking period during which the pixel is not being controlled to illuminate.

In some implementations, the circuit is configured wherein the sub-frame period comprises a plurality of binary weights.

By providing a sub-frame period with a plurality of binary weights, this may enable the data interface requirement to be reduced through the use of Bitplane scheduling.

In some implementations, the grey level for each pixel of the set of pixels of the display comprises a grey level of at least 8bit.

By providing a grey level of at least 8bit, this may provide a sufficient resolution to the illumination intensity control to produce a standard quality output of the display.

According to a third aspect there is provided a method for driving a pixel of a digital liquid crystal on silicon display, the method comprising: receiving a grey level for each pixel of a set of pixels of the display; determining a PWM duty cycle for each pixel of the set of pixels in dependence on the grey level; generating a PWM waveform for each pixel of the set of pixels in dependence on the PWM duty cycle, the PWM waveform defining an output illumination intensity control; controlling each pixel of the set of pixels to illuminate for an illumination period, the illumination period being dependent on the PWM waveform; wherein the illumination periods of any two of the set of pixels do not start simultaneously.

If more information needs to be sent to control the pixel, this may result in a greater data interfacing requirement between the host controller and the LCoS backplane. An increasing data interfacing rate may result in an increasing number of signalling pins or an increasing data signalling frequency, both of which may incur a cost in resources on both the host controller and LCoS backplane. A high bandwidth (frequency) data signalling may also be incompatible or limited by the CMOS process. It is therefore preferable to reduce the data interfacing requirement to enable an increase pixel density or higher frame refresh rate.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

Figures 1A and 1B schematically illustrate a driver for driving a pixel of a digital liquid crystal on silicon display of the prior art. Figure 1A shows a block level schematic illustration of the driver for driving a pixel of a digital liquid crystal on silicon display of the prior art. Figure 1B shows a schematic cross-sectional view of a single pixel being driven by the driver of the prior art.

Figure 2 schematically illustrates an analogue liquid crystal driving voltage for a digital LCoS pixel of the prior art.

Figure 3 schematically illustrates an exemplary embodiment of a driver for driving a pixel of a digital liquid crystal on silicon display.

Figure 4 schematically illustrates an exemplary embodiment of a global signal generator of the driver to automatically switch the driving signals for a pixel of a digital liquid crystal on silicon display.

Figure 5 schematically illustrates examples of signals used to actuate the electro-optic response of the display in the driver.

Figure 6 schematically illustrates an image frame of a digital liquid crystal on silicon display.

Figure 7 schematically illustrates an exemplary embodiment of sequencing the bitplanes for driving a pixel of a digital liquid crystal on silicon display.

Figure 8 schematically illustrates exemplary programmable PWM waveforms of a pixel of a digital liquid crystal on silicon display.

Figure 9 shows an example method of driving a pixel of a digital liquid crystal on silicon display.

Figure 10 schematically illustrates a first exemplary embodiment of a PWM encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display.

Figure 11 schematically illustrates a second exemplary embodiment of a PWM encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display, as represented by the pixel data bitstream.

Figure 12 schematically illustrates a third exemplary embodiment of a PWM encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display, as represented by the pixel data bitstream.

Figures 13A and 13B schematically illustrate a fourth exemplary embodiment of a PWM encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display. Figure 13A schematically illustrates the encoding scheme of the fourth exemplary embodiment. Figure 13B schematically illustrates the bitstream of the fourth exemplary embodiment.

Figures 14A and 14B schematically illustrate a fifth exemplary embodiment of a PWM encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display. Figure 14A schematically illustrates the encoding scheme of the fifth exemplary embodiment. Figure 14B schematically illustrates the bitstream of the fifth exemplary embodiment.

Figure 15 schematically illustrates a driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit of the prior art.

Figure 16 schematically illustrates a first exemplary embodiment of a sequencing of PWM waveform for the driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit.

Figures 17A and 17B schematically illustrate a second exemplary embodiment of a sequencing of PWM waveform for the driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit. Figure 17A schematically illustrates the second exemplary embodiment of a sequencing of PWM waveform with a blanking period. Figure 17B schematically illustrates the second exemplary embodiment of a PWM waveform sequence with blanking periods swapped.

Figure 18 schematically illustrates a third exemplary embodiment of a PWM encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit.

DETAILED DESCRIPTION

The drivers and methods described herein concern driving a pixel of a digital liquid crystal on silicon (LCoS) display.

Embodiments of the present invention tackle one or more of the problems mentioned herein by providing transistors in the voltage scaling circuit having a greater size than the transistors in the control circuit. In this way, this may enable the overall size of the driver to be reduced, which may reduce the pixel pitch size. Additionally, the driver may control each pixel of a set of pixels to illuminate for an illumination period in which the illumination period of any two of the set of pixels do not start simultaneously. In this way, the driver may have a reduced data interfacing requirement between the host controller and the LCoS backplane.

A first exemplary embodiment of the driver and its global signal generator are schematically illustrated in Figures 3 and 4 respectively and signals actuated by the driver are shown in Figure 5.

Figure 3 shows a driver 300 for driving a pixel of a digital liquid crystal on silicon display. Each pixel in the display may have a corresponding driver 300 as shown in Figure 3.

The driver 300 comprises a control circuit 301 comprising one or more transistors and a voltage scaling circuit 302 comprising one or more transistors. The size of the transistors in the voltage scaling circuit 302 may be greater than the size of the transistors in the control circuit 301.

The size of the transistors, or other suitable electrical components, may determine the size of the driver 300. As each pixel is driven by a driver 300, the size of the driver 300 may in turn determine how close the pixels can be positioned relative to one another. This is known as pixel pitch size. It is preferable for the pixel pitch size to be reduced so that the pixel density, and therefore quality of the display, can be increased.

By providing the transistors in the voltage scaling circuit 302 of greater size than the transistors in the control circuit 301, this may enable the overall size of the driver 300 to be reduced, which may reduce the pixel pitch size.

The transistors of the control circuit 301 and the transistors of the voltage scaling circuit 302 may be formed on a dual gate oxide process, such as a dual gate oxide CMOS process. The transistors of the control circuit 301 may comprise core logic devices (i.e. thin gate oxide transistors) . In particular, the transistors may have a high threshold voltage to provide the benefit of low leakage operation, in-line with the operating temperature Liquid crystal in intended phase transition state (Smectic or Nematic) and their positive temperature coefficient to improved response time.

The transistors of the voltage scaling circuit 302 forms a voltage domain level shifter to translate from digital logic domain (of 301) to analogue (pixel) voltage domain 313 (of 302) . This may reduce the number of high voltage devices (i.e. thick gate oxide transistor) which may enable pixel pitch shrink. Within the level shifting block (302) , the driver 300 may employ current limiting control 314 to reduce the likelihood of switching shoot-through current due to concurrency of switching edges. This may allow the driver 300 to maintain a power dissipation celling and a robust power distribution network.

As shown in Figure 3, the driver 300 may be configured so that the operating voltage of the voltage scaling circuit 302 is greater than operating voltage of the control circuit 301. In particular, the driver 300 may be configured so that the operating voltage of the voltage scaling circuit 302 is greater than 3V and the operating voltage of the control circuit 301 is less than 0.9V.

The driver 300 may be configured so that the driver 300 comprises a pitch size of less than 3.7um. By providing a pitch size of less than 3.7um, this may enable a higher display quality.

The control circuit 301 may be configured to clock an input binary signal for latching the state of the pixel for each frame. The input binary signal may comprise PIXEL DATA 307 and ROW SELECT 308 signals. The input binary signal may provide a desired state for the pixel in terms of binary data.

The control circuit 301 may also be configured to form a logical control signal for the pixel in dependence on the input binary signal. The control circuit 301 may take the desired state for the pixel in the input binary signal and convert it into a logical control signal to select a signal, either the VCOM0 311 or VCOM1 312 using a multiplexer 305.

The control circuit 301 may comprise a static random-access (SRAM)

memory

303, 304 configured to store the input binary signal (in 303) and the logical control signal (in 304) . By providing an

SRAM memory

303, 304 this may enable the input binary signal to be clocked and stored until it is required to form the logical control signal. Additionally, the

SRAM memory

303, 304 may enable the input binary signal to be formed and the prior logical control signal to be retained until it is to be transferred using a Global Update signal 310 (i.e. a transfer of master bit data, latching to slave bit) and displayed.

The SRAM memory may comprise a master memory bit 303 and a slave memory bit 304.

The control circuit 301 may be configured to clock the input binary signal in dependence on the master memory bit 303. By clocking the input binary signal in dependence on the master memory bit 303, this may enable the input binary signal to be stored until it is transferred to the slave memory bit 304.

The control circuit 301 may also be configured to form and hold the logical control signal in dependence on the slave memory bit 304. By forming and holding the logical control signal in dependence on the slave memory bit 304, this may enable the logical control signal to be stored. The logical control signal may be retained until a Global Update signal 310 is asserted.

The voltage scaling circuit 302 may be configured to receive the selected signal, either VCOM0 311 or VCOM1 312 via the multiplexer 305, as asserted by the logical control signal stored in 304.

The voltage scaling circuit 302 may also be configured to form a pixel drive signal for driving the pixel in dependence on the logical control signal (as stored in slave SRAM 304) . The voltage scaling circuit 302 may translate the digital signal, VCOM1 312 or VCOM0 311, to the analogue pixel driving signal.

The voltage scaling circuit 302 may comprise a digital to analogue converter (DAC) to form the pixel drive signal for driving the pixel. The DAC may convert the digital signals, VCOM1 312 or VCOM0 311, as selected by the logical control signal into the analogue pixel drive signal.

The embodiment of the driver 300 for driving a pixel of a digital liquid crystal on silicon display will now be described in more detail.

The LCoS display pixel array may comprise a common electrode, VITO (shown as Vc in prior art) . The common electrode may be modulated in a fixed period to a sub-frame duration (which is also known as a Bitplane) . In this exemplary embodiment, the common electrode may be modulated at 50%duty between two binary voltage levels. The two binary levels may comprise a high level, VH and a low level, VL. The VITO may be generated external to the LCoS chip and its on-chip digital domain equivalent is VCOM 402.

The VCOM1 408 (VCOM1 312 in figure 3) and VCOM0 407 (VCOMO 311 in figure 3) signals may be generated on-chip. The VCOM1 408 and VCOM0 407 signals may synchronised to the VCOM 402 signal and delivered as global signals to all pixels (for a given partition) . It is preferable that the global signal levels are compatible with the digital logic domain. In other words, the global signals are Binary Unipolar Non-Return-To-Zero signals, where the DC bias is equivalent to the digital logic supply voltage.

The VCOM1 408 and VCOM0 407 signals may be limited and programmable waveforms of different duties with instructions from the Host controller. The VCOM1 and VCOM0 signals may change as and when required by the required grey level. The VCOM1 and VCOM0 signals may be generated with an on-chip PWM generator where its output is fed into figure 4 as TW_PWM 403. On figure 4 a default logic state ‘0’ 401 is shown as input signal for VCOM0. A plurality of VCOM1 and VCOM0 signals may be employed to partition a display frame, where they are global to each partition.

Additionally, a voltage domain level shifter 302, or voltage scaling circuit 302, may be provided to translate the signal from a digital logic domain to analogue (pixel) voltage domain. This may enable a reduction in the number of high voltage devices in the voltage domain level shifter 302, or voltage scaling circuit 302.

The voltage domain level shifter 302, or voltage scaling circuit 302, may employ a current limiting control 314 to reduce switching current shoot-through caused by a concurrency of switching edges. This may provide the benefit of maintaining a power dissipation celling and a robust power distribution network.

The driver 300 may also comprise core (digital) logic CMOS devices to provide a master SRAM bit memory 303 and a slave SRAM bit memory 304. The master SRAM bit memory 303 and a slave SRAM bit memory 304 may enable a VCOM1 and VCOM0 signal via a selection mux.

It is preferable that the core logic CMOS MOSFET provide a high threshold voltage to enable a low leakage operation in-line with the operating temperature LC in intended phase transition state (Smectic or Nematic) and their positive temperature coefficient to improved LC response time.

The frame buffering may use a master SRAM bit memory 303 and a slave SRAM bit memory 304 for each pixel, together with the partitioning of a display frame where each partition operates synchronously, to encode the PWM resolution to each pixel.

The encoding scheme may have one or more of the following features:

A scheduling scheme to update and transfer written pixel data 307 (i.e. per bit basis within each pixel, between its two memory bits, namely Master 303 and Slave 304) , in-line with a prescribed PWM pattern.

The scheduling scheme may operate at full data rate (no partitioning of updates to display frame) , at half data rate (halve partition to display frame) , at a third data rate (three partition of display frame) or a quarter data rate (four partition of display frame) , with the aim of reducing data rate (bits per second) whilst maintaining a similar capability of PWM resolution control. The separated partitions may be interlaced in terms of group of pixel rows, for example for half data rate, it is divided to two groups of odd and even number rows.

The method of encoding PWM may follow a lossless data compression method, where following its first write, a consecutive run length of 1s or 0s does not necessitate an update, thereafter until the next run length. This is the basis for Golomb coding (or run length encoding) , a lossless compression technique where the nature of data representation of symbols follows geometric distributions.

The PWM pattern may comprise a plurality of unary weights and binary weights. Each unary weight may be equal to a Bitplane period. A binary weight may be a subdivision of a unary weight. The summation, or integration, of the binary and unary weights may allow for an arbitrary selection of a greyscale value (luminance level) for a particular pixel, with respect to a programmable bit stream up to the limits of resolution.

The driver 300 may comprise a control circuit 301 operating in the CORE VDD voltage domain (for example at 0.9V in the illustrated exemplarity embodiment) . The control circuit 301, may comprise a master SRAM bit memory 303 and a slave SRAM bit memory 304. Writing to the master SRAM bit memory 303 may be provided by asserting a ROW SELECT 308 signal and switching and transferring the PIXEL DATA 307. The PIXEL DATA 307 may comprise a bit stream representation of a pixel luminance. The transfer of the buffered data from the master SRAM bit memory 303 to the slave SRAM bit memory 304 may be in dependence of a LOAD 310 signal for a global update of the pixels.

The VCOM1 311 and VCOM0 312 are global signals which are mux selectable in dependence on the state of the slave SRAM bit memory 304.

A IOVDD 313 analogue voltage pixel supply voltage may be provided to the level shifter 302, or voltage scaling circuit 302. A VPE 315 output electrode of a pixel may be provided by the level shifter 302, or voltage scaling circuit 302.

Figure 4 shows a global signal generator 400 of the driver 300. The global signal generator 400 may provide the

VCOM1

311, 407 and

VCOM0

312, 408 signals.

VCOM 402 is a digital logic signal, a synchronised in-phase equivalent to the external VITO common front electrode signal of equal duty. In this embodiment, for correct field inversion, that is to say, to achieve a zero DC component in an AC signal, the voltage across the liquid crystal, VLC, which is sandwiched between the common electrode and the pixelate electrode, auto inversion may be performed with a pair of

XOR logic gates

404, 406. The

logic gates

404, 406 may utilise an XOR logic operation 405 which is preferably placed external to pixel circuitry.

If VCOM0 407 is derived with Logic 0 then the global signal generator 400 may obtain a signal in-phase with VCOM 402. If VCOM1 is derived with Logic 1 then the global signal generator 400 may obtain a signal out-of-phase with VCOM 402.

TW_PWM 403 is a Host programmable PWM waveform generator. The PWM generator may allow for a premature terminated write of a pixel data (i.e. pixel state change or turning off of a pixel, prior to it being turned on and vice versa) . This may enable the sub-division of unary weight PWM to binary weight as described herein.

Figure 5 schematically illustrates examples of signals used to actuate the electro-optic response of the display in the

driver

300, 400. Figure 5 shows six exemplary encoding signals.

VITO 501, the common front plane signal, has signal levels VH and VL of 50%duty cycle. A period of VITO is equal a Bitplane, or sub-frame, period.

VBP 502, the backplane signal, on a per pixel basis comprises the signal levels V1 and V0.

VLC 503, the voltage across the LC, with respect to VITO 501 and VBP 503, is defined by Equation 1. Equation 1 may be true if the LC is assumed to behave like a dielectric.

VLC = VITO –VBP (1)

VLC^2 504, squaring of VLC, is a component of the RMS calculation. The effective RMS of VLC may facilitate alignment modification of the LC (director twist) . The alignment modification of the LC is a property that may affect the incident polarisation of light.

1T is equal to a unary weight.

0.5T is an exemplary sub-division of a unary weight to carry a binary weight. For example, 1/2 ¹ x T.

0.25T is an exemplary sub-division of a unary weight to carry a binary weight. For example, 1/2 ² x T.

Further sub-division of a unary weight may be included if required to form a smaller binary weight. For example 1/2 ^NT, where N is a positive integer, may be used. (i.e. 1/2 ^N, for N equal positive integer) , to form additional smaller binary weight

The frame 601 may illustrate an output image 602, for example the stick-man shown in Figure 6. The frame 601 may be configured into a two-dimensional pixel array frame. The frame 601 may comprise a plurality of sub-frames 603, or Bitplanes 603 over time 604. The sub-frames 603, or Bitplanes 603, may be integrated, or summed, over time 604 to form an image 602. The number of sub-frames 603, or bitplanes 603, may be determined by the encoding scheme.

Data may be provided by an IO Phy 701, a physical layer of an Open Systems Interconnection (OSI) model, comprising individually numbered Bitplanes. In other words, each a two-dimensional pixel array sub-frame of one bit depth. The

Bitplane period

702, 703, 704 may be interleaved with a blanking period 705. The blanking period 705 may be shorter that the

Bitplane period

702, 703, 704. The blanking period 705 may be a period where no update to the pixel array is performed.

During the blanking period 705, a Host control instruction may be issued to LCoS state machine, indicating how a preceding data bit of a Bitplane is commonly handled. A retrieval of preloaded register of values for the TW_PWM generator 403 may be directed.

An exemplary Host control instruction is shown in Table 1. The Host control instruction shown in Table 1 comprises a 32bit bus width.

Table 1

A TW_PWM 403 signal may be generated using a host instruction as described in Table 2. The TW_PWM 403 signal as prescribed by a Host instruction 705 may be generated with a set of two stored values TWP_REG0 (12bit) and TW_REG1 (12bit) .

TW_PWM 403 may default to logic 1 if the Host instructs TW? = 0, this operation results in the generation of a unary weight (1T) . TW_PWM signal duty may be arbitrarily programmable and does not necessarily conform to binary sub-division, as shown in Table 2 for TWP<3: 0> = {10, 11, 12, 13} . Number of clocks per Bitplane is derivative of a system clock, for simplicity, shown here as 2000 clock cycle per Bitplane period. TWP_REG0 and TWP_REG1 stores the duty of TW_PWM as the number of clock cycles.

Table 2

Figure 8 schematically illustrates exemplary PWM waveforms 800 for a pixel of a digital liquid crystal on silicon display before automatic field inversion (as shown in Figure 4) . Figure 8 illustrates some of the TW_PWM waveforms of Table 2 (TWP<3: 0>= 0, 1, 2, 3, 6 and 11, shown at 801, 804, 802, 805, 803 and 806 respectively) . These waveforms will be described in more detail herein.

The initial condition (i.e. the start of a Bitplane period) may assign TW_PWM 403 = TSR bit, for if TW? = 1. Thereafter, the duration of duty, set by the TW_REG0 and TW_REG1 values in terms of a number of clock cycles, is circular. The duty follows TW_REG0 first, then TW_REG1, and thereafter repeats. At the end of each of the cycle counts, TW_PWM inverts its state, until the end of a Bitplane period. For the purpose of correct field inversion, each of these waveforms f (t) of period T preferably satisfies the rule shown in Equation 2 below. In other words, the integration of the first half of the period T is preferably equal to the integration of the second half of T.

Table 3 shows an exemplary PWM encoding scheme of the prior art with 7 unary weights (7T) and 5 binary weights (5B) . The binary weight is a sub-division of a unary weight. The unary weight may correspond to, or be interchangeable with the term, a sub-frame period. The number of unary weights and binary weights sum to form the number of Bitplane periods.

The encoded PWM resolution is given by Equation 3. In Equation 3, M is the number of unary weight and N the number of binary weights. In the example shown in Table 3, 7T, M = 7, 5B, N = 5. Thus, the effective resolution of programmability is (7 + 1) x 25 = 256

(M + 1) × 2N (3)

The programming of each individual pixel is demonstrated in Table 3. In the example in Table 3 there are three pixels in a one-dimensional pixel array (Pixel 1 to 3) . Thus, a Bitplane in this example is one dimension of length 3 bit.

The number of Bitplanes used in the example in Table 3 for the encoding scheme is 12, as indicated by the Bitplane numbering order. A PWM resolution level (grey level) is encoded with respect to normalised value of the least signal bit (the smallest sub-division) . In the example shown in Table 3, pixel 1 comprises a grey level = 56, pixel 2 comprises a grey level = 193 and pixel 3 comprises a grey level = 83.

The ordering of the Bitplanes, i.e. the order of 1 to 12, is interchangeable as it does not affect the resolution of programmability. However, the ordering is preferable to achieve electro-optical benefit of modulating LC to prepare an order that relates to higher signalling frequency.

The digital encoding shown in the example in Table 3 provides a 12bit bitstream (12 Bitplane of 1 bit depth per pixel) . This results in an effective grey level resolution equivalent to 8Bit (2 ⁸ = 256) . This produces an encoding efficiency of 8/12 = 66.7%.

Table 3

A function v (t) may be used to represent a PWM signal. The RMS of the PWM signal, with a periodic waveform v (t) of period T, is given by Equation 4.

The PWM signal may include a duty ratio, D. If the PWM includes a duty ratio, then the RMS of the PWM signal is given by Equation 5.

The maximum duty, D, for an encoding scheme is the ratio of the sum of all defined weight divided by the number of Bitplane, as given by Equation 6.

For M = 7, N = 5, as shown in the example in Table 3, the maximum duty is 66.4%.

If the encoding scheme shown in Table 3 was to be extended to produce a higher PWM resolution of 10bit, this would require M=31 and N=5. This would result in the number of Bitplanes increasing to 36 (36bit bitstream) which would reduce the encoding efficiency to 10/36 = 27.8%.

It is desirable to develop an encoding scheme for a driver for driving a pixel of a digital liquid crystal on silicon display that is more efficient for higher PWM resolution, for example a resolution of 10 bit.

Figure 9 summarises an example of a method for driving a pixel of a digital liquid crystal on silicon display. At step 901, the method comprises receiving a grey level for each pixel of a set of pixels of the display. At step 902, the method comprises determining a PWM duty cycle for each pixel of the set of pixels in dependence on the grey level. At step 903, the method comprises generating a PWM waveform for each pixel of the set of pixels in dependence on the PWM duty cycle, the PWM waveform defining an output illumination intensity control. At step 904, the method comprises controlling each pixel of the set of pixels to illuminate for an illumination period, the illumination period being dependent on the PWM waveform; wherein the illumination periods of any two of the set of pixels do not start simultaneously.

The driver used to implement the method may comprise a circuit comprising one or more transistors, as shown in Figure 3. The circuit of the driver 300 may be configured to carry out the encoding scheme.

The driver 300 may be configured to receive a grey level for each pixel of a set of pixels of the display. The set of pixels may comprise two or more pixels. The two or more pixels may be located anywhere on the display.

It is preferable for the grey level for each pixel of the set of pixels of the display to comprise a grey level of at least 8bit. By providing a grey level of at least 8bit, this may provide a sufficient resolution to the illumination intensity control to produce a standard output of the display.

The driver 300 may also be configured to determine a PWM duty cycle for each pixel of the set of pixels in dependence on the grey level. The grey level may be in the form of a numerical level for a particular frame period. For example, for an 8bit grey level resolution of 256, the grey level may be between 0 and 255. In dependence on this grey level, a PWM duty cycle is determined. The PWM duty cycle may determine the proportion of the frame period that the pixel should be illuminated.

The driver 300 may also be configured to receive a sequenced number of programmable PWM waveforms 800 (see Figure 8) for each pixel of the set of pixels in dependence on the PWM duty cycle. The PWM waveform 800 may define an output illumination intensity control for a single sub-frame period. As described herein, the PWM duty cycle may determine the proportion of the frame period that the pixel should be illuminate. The PWM waveform 800 determines when the pixel should illuminate during the sub-frame period, as shown in Figure 8. For example, the PWM waveform 800 may turn on and off during the sub-frame period, as shown in 801, 802 and 806, the PWM waveform 800 may turn on at each end of the sub-frame period and on in the middle, as shown in 803, or the PWM waveform may turn on and off multiple times during the sub-frame period, as shown in 804 and 805.

The driver 300 may also be configured to control each pixel of the set of pixels to illuminate for an illumination period. The illumination period may be dependent on the PWM waveform. The driver 300 may use the PWM waveform 800 to control the driving of the pixel to illuminate a particular rate, such that the pixel produces the desired output illumination.

Examples of the encoding scheme for the driver 300 will now be described in more detail with further reference to Figures 10 to 18.

Figure 10 schematically illustrates a first exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display. The encoding, or scheduling, scheme uses a buffered pixel (303 and 304) as described herein. Figure 10 shows a half data rate implementation of the scheduling encoding format, with a pixel array of column 1007 = 1 and row 1008 = 2. A single bitstream updates two pixels, shown by the 2 rows 1008. Both of the pixels have the same PWM encoding scheme but with different ordering.

The number of times by which the master SRAM bit memory 303 of the pixel is updated may depend on the run length of the period T. For example, a 1T period, as shown by 1001, is updated once during the 1 Bitplane period. Similarly, a 2T period, as shown by 1002, is updated once during the 2 Bitplane period and a 4T period is updated once during the 4 Bitplane period. Thus, a sequence of 1T + 2T + 4T, as shown in the first pixel, sums to form a 7 Bitplane period, is encoded with just 3 update bits. Similarly, a 2T + 2T + 1T + 2T, as shown by the second pixel, sums to form a 7 Bitplane period, but is encoded with 4 update bits. In other words, the number of bits used in encoding the pixel is determined based on the number of updates during the Bitplane period.

The two pixels can consequently be encoded with 7bit (3 bits for the first pixel and 4 bits for the second pixel) . This may result in a lossless compression of data. It is preferable for the binary encoding PWM sequence to use an increasing power of 2 (i.e. 2 ⁰T, 2 ¹T, 2 ²T …2 ^NT etc. ) . This is known as a half-rate PWM encoding block as half the data may be required.

To improve the flexibility of sequencing the bitstream, an algorithmic rule would allow for any integer weight less than or equal the next increasing power of 2, within a complete sequence. For example, a sequence can be 2 ⁰T, 2 ⁰T, 2 ¹T, 3T, 2 ²T, 5T. The ordering of sequence is made to service the data bitstream.

As shown Figure 10, the encoding scheme may comprise a first and second encoding block. For a combination of the two encoding blocks, both pixels are encoded with 13T + 1B. The 1B 1005 is a sub-frame processed as a PMW waveform 800, as per host instruction (table 1, TW? = 1) 705. T is a sub-frame processed as host instruction TW? = 0, where in figure 4 TW_PWM is held as logic 1 resulting in a sub-frame duty = 1.

Alternatively, the encoding scheme may comprise more PWM encoding blocks, for example four additional blocks with the same encoding pattern as the second encoding block. This may result in the encoding (7T) + (B + 6T) + 4 x (B + 6T) = 37T + 5B. This may provide 1216 levels (>10Bit resolution) .

Utilising the six PWM encoding blocks may result in 6 x 7bit, a 42bit bitstream. Using a half data rate, the two pixels may be encoded with the 42bit bitstream, each pixel requiring 21 bits data representation to encode a PWM resolution of >10Bit. This may result in an encoding efficiency of 10/21 = 47.6%. This is an improvement over what is described in Table 3.

What is described for a one dimensional pixel array, of 1 column and 2 rows, may equally apply in practice to two equal partitions of a two dimensional pixel array. The separated partitions may be interlaced in terms of group of pixel rows, for example, the pixel array may be divided into two groups of odd and even number rows.

It is preferable that the illumination periods of any two of the set of pixels do not start simultaneously. In other words, as shown in Figure 10, the illumination period of a first pixel 1001 does not start at the same time as the illumination period of a second pixel 1002.

If more information needs to be sent to control the pixel, this may result in a greater data interfacing requirement between the host controller and the LCoS backplane. By increasing the data interface requirement this may increase the voltage level. The increased interface requirement may therefore require larger electrical components to withstand the increase voltage level. It is therefore preferable to reduce the data interfacing requirement to enable an increase pixel density.

By controlling each pixel of a set of pixels to illuminate for an illumination period in which the illumination period of any two of the set of pixels do not start simultaneously this may reduce the data interface requirement during any given global update of the pixels. By reducing the data interface requirement this may result in an increased pixel density.

The driver 300 may be configured to receive the grey level for each pixel of the display. In other words, the set of pixels may comprise all of the pixels of the display. Alternatively, there may be a plurality of sets of pixels which make up all of the pixels of the display. By receiving the grey level for each pixel of the display this may enable the entire display to receive a global update during which the illumination periods of any two of the set of pixels do not start simultaneously. As described herein, each pixel may be driven by a single driver 300, in which case each driver 300 would receive the grey level for the respective pixel. Alternatively, a single driver 300 may drive a plurality of pixels, in which case the single driver 300 would receive the grey level of all of the pixels the single driver 300 is driving.

The illumination period of the pixel may comprise a frame period. In other words, the illumination period may occur within a frame period. There may be more than one illumination period within the frame period. The frame period may comprise a plurality of sub-frame periods. By using the sub-frame periods to divide the frame period the illumination period may be defined in terms of the sub-frame periods.

By dividing the frame period into a plurality of sub-frame periods this may provide a resolution to the frame period resulting in the ability to vary the length of the illumination period. As the illumination period is dependent on the PWM waveform, the ability to vary the length of the illumination period may enable the illumination intensity control to be varied.

The driver 300 may be configured to control each pixel of the set of pixels to illuminate for an illumination period in which the illumination periods of any two of the set of pixels do not start in the same sub-frame period. In other words, as shown in Figure 10, the illumination period of a first pixel 1001 does not start in the same division of the frame period as the illumination period of a second pixel 1002.

By controlling each pixel of a set of pixels to illuminate for an illumination period in which the illumination period of any two of the set of pixels do not start in the same sub-frame this may reduce the data interface requirement during any given global update of the pixels. By reducing the data interface requirement this may result in an increased pixel density. Additionally, as the pixels are not updated in the same sub-frame period, this may enable the data interface requirement to be further reduced through the use of Bitplane encoding, as described herein.

The driver 300 may be configured such that the sub-frame period comprises a plurality of binary weights. By providing a sub-frame period with a plurality of binary weights this may provide further resolution to the frame period and enable the data interface requirement to be reduced through the use of Bitplane encoding, as described herein.

Figure 11 schematically illustrates a second exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display. This exemplary encoding scheme services two pixels (Pixel 0 and 1) . The encoding scheme shows the contents of the pattern 1101, 1104, master bit 1102, 1105 and the slave bit 1103, 1106 for each of the two pixels. The pattern 1101, 1104 illustrates what is being driven during the respective period.

In Figure 11, the previous (N-1) data frame (of 7 bits) is denoted as Dx’ and the subsequent (N+1) data frame is denoted as Dx”, for x equal to the order of data bits.

The sequencing of data bits of a PWM encoding block is demonstrated as follows: Pixel 0 displayed data bits = D5’, D0, D2 (i.e. the contents of Slave SRAM) and Pixel 1 displayed data bits = D6’, D1, D3, D4. Thus, there are a total of 7 data bits for each PWM encoding block.

Whilst bitstream data bits are selectively buffered in respective Master SRAM for each of the two pixels, data bits from previous and subsequent data frames are expected to overlap. A transfer (or loading) of buffered data bits from respective Master to Slave SRAM is denoted by a Global Select (or update) signal,

GSx

1107, 1108, as shown in Figure 3 (310) . The x denotes the respective pixel. Although the GSx signals 1107, 1108 are shown in Figure 11 to be separate, it is also possible for one common GS signal to be applied. A GS signal may be applied upon completion of pixel update (i.e. at the end of a Bitplane period) . Prior written data to a Master SRAM bit would be repeating a transfer if there is no change (viz. a 2T or 4T sequence show no new updates over the duration of the extended period) .

The

GSx signal

1107, 1108 may be applied upon completion of pixel data update to the master bit (with 307, 308 and 309) . This may be at the end of the Bitplane period such that the master bit is transferred to the slave bit. The

GSx signal

1107, 1108 may be applied at the beginning of any new sequence, be it 1T, 2T or 4T, where the slave bit 304 acts as the logical control signal which switches the pixel driving signal.

Figure 12 schematically illustrates a third exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display.

This encoding scheme services three pixels (

Pixel

0, 1 and 2) . The encoding scheme shows the contents of the pattern, master bit and the slave bit for each of the three

pixels

1201, 1202, 1203. The pattern illustrates what is being driven during the respective period.

As shown in Figure 12, the three

pixels

1201, 1202, 1203 may be encoded with a PWM encoding block of 15T + B. This results in a 16 bits bitstream. Alternatively, by extension of a Host instruction, as shown in Table 1, some of the pixels may be encoded as 14T + 2B (i.e. a T weight is repurposed as a B weight, for TW? = 1) such that the PWM block still results in a 16 bits bitstream.

A preferable embodiment may comprise the following encoding (15T + B) + (14T +2B) + (14T + 2B) = 43T + 5B. In this embodiment M = 43, N = 5 which, using Equation 3, results in 1408 Levels and a >10Bit resolution.

At 1/3 data rate, the three pixels may be encoded with a 48bit bitstream, each pixel requiring 16 bits data representation to encode a PWM resolution of >10Bit. This results in an encoding efficiency of 10/16 = 62.5%. This is an improvement on exemplary embodiments shown in Table 3 and Figure 10.

Figures 13A and 13B schematically illustrate a fourth exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display. Figure 13A schematically illustrates the encoding scheme of the fourth exemplary embodiment. Figure 13B schematically illustrates the bitstream of the fourth exemplary embodiment, with the lighter coloured block indicative of a written pixel data bit of a consecutive bitstream (i.e. prior to a GS update at the beginning of any new sequence) .

These examples show alternative 48 bits (48 Bitplane) encoding schemes to the encoding scheme shown in Figure 12. Here the number of T and B are varied.

Figures 14A and 14B schematically illustrate a fifth exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display. Figure 14A schematically illustrates the encoding scheme of the fifth exemplary embodiment. Figure 14B schematically illustrates the bitstream of the fifth exemplary embodiment.

These examples show an encoding scheme which service four pixels (

Pixel

0, 1, 2 and 3) . This encoding scheme uses a quarter data rate with a data frame with 44 bits (44 Bitplane) . The encoding block comprises 39T + 5B. Here M = 39, N = 5 which, using Equation 3, results in 1280 Levels and a >10Bit resolution.

At 1/4 data rate, the four pixels may be encoded with a 44bit bitstream, each pixel requiring 11 bits data representation to encode a PWM resolution of >10Bit. This results in an encoding efficiency of 10/11 = 90.9%. This is an improvement on exemplary embodiments shown in Table 3, Figure 10 and Figure 13.

This exemplary embodiment of the digitally encoded PWM drive scheme requires only a 11bit data representation to encode a >=10Bit PWM control resolution. A 10bit data representation to encode a DAC voltage resolution of 10Bit for an analogue pixel provides nearly equal representation. However, this does not have the limitations of analogue pixel, i.e. charge leakage, charge injection or a high Signal-to-Noise Ratio (SNR) required for fidelity to absolute voltage. This is significantly improved over a prior art digital drive scheme, which comprises 34 sub-frame (an equivalent to a sequence of 34bit data representation) for 8Bit greyscale.

This encoding scheme may provide improved efficiency to reduce the data interfacing requirement between a Host controller and a LCoS backplane chip.

Implementing the encoding scheme shown in Figure 14 into a digital LCoS pixel design may provide an IO data rate of 4096 x 2160 x 120Hz x 11bit = 11.68Gbps to a 4K display.

Figure 15 schematically illustrates a driver 1500 for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit of the prior art. Driver 1500 has a single memory bit 1507 (asingle SRAM memory) , instead of a master SRAM bit memory 303 and a slave SRAM bit memory 304 (a separate master memory bit and slave memory bit) , as in driver 300. The encoding scheme may be adapted to function on a single memory bit 1507 driver 1500.

In the embodiment of Figure 3 of the present invention, driver 300 comprises a separate master memory bit 303 and slave memory bit 304. In this configuration, the driver 300 is configured to receive the grey level for each pixel of the set of pixels of the display during the

sub-frame period

1001, 1002 and hold the grey level for each pixel of the set of pixels of the display until the subsequent sub-frame period 1001. The driver 300 may be configured to control each pixel of the set of pixels to illuminate during the

subsequent sub-frame period

1001, 1002.

In a driver 300 comprising a separate master memory bit 303 and slave memory bit 304, the grey level information may be held until the

subsequent sub-frame period

1001, 1002 without the need for a blanking period during which the pixel is not being controlled to illuminate.

Figure 16 schematically illustrates a first exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit.

Without a separate master SRAM bit memory 303 and a slave SRAM bit memory 304 the update of pixels may be formed using a blanking period 1605. The blanking period 1605 may be where the pixel is effectively in an off state (or black) . The blanking period 1605 is positioned between subsequent PWM sequence blocks 1604, 1605.

Further to using a blanking period to update pixel data, as shown in Figure 16, an off state duty cycle of a Binary Weighted (B) bitplane period may be used to update the pixel. Figures 17A and 17B schematically illustrate a second exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit. Figure 17A schematically illustrates the second exemplary embodiment of an encoding scheme with a blanking period that is less than one bitplane period. Figure 17B schematically illustrates the second exemplary embodiment of an encoding scheme with blanking periods swapped to increase the duration of a blanking period associated with B weight.

In addition to using the blanking periods 1704 to update the pixel data, the driver may also use an off-duty cycle of a Binary Weighted Bitplane period 1705 to update the pixel, as shown in Figure 17A. In this embodiment, the blanking periods 1704 are broken up by the Binary Weighted Bitplane periods 1705.

Further optimisation of a sequence of the Binary Weighted Bitplane periods 1705, as shown in Figure 17B, may increase the duration of the blanking period. This may increase the time allowed to update the pixel and hence reduce the IO data rate.

As shown in Figures 16, 17A and 17B, the driver 300 may be configured so that a sequence of

sub-frame period

1600, 1700 comprises a

blanking period

1605, 1704 between each

sub-frame period

1604, 1606, 1705. During the

blanking period

1605, 1704 the driver may be configured to receive the pixel data 307 for each pixel of a set of pixels of the display. The driver may also be configured to control each pixel of the set of pixels to illuminate during the

sub-frame period

1606, 1705 after the

blanking period

1605, 1704.

In a driver comprising a single SRAM memory 1507, without a separate master memory bit and slave memory bit, providing a sequence of

sub-frame period

1600, 1700 comprising a

blanking period

1605, 1704 may enable to pixels to be updated during the

blanking period

1605, 1704, interleaving the

subsequent sub-frame period

1606, 1705.

As shown in Figures 16, 17A and 17B, the duration of the

blanking period

1605, 1704 may be less than the duration of the

sub-frame period

1604, 1606, 1705. By providing a

blanking period

1605, 1704 with a shorter duration than the

sub-frame period

1604, 1606, 1705 this may minimise the period during which the pixel is not being controlled to illuminate.

Figure 18 schematically illustrates a third exemplary embodiment of an encoding scheme for the driver for driving a pixel of a digital liquid crystal on silicon display comprising a single memory bit. This exemplary encoding scheme services four pixels (

Pixel

0, 1, 2 and 3) with blanking periods indicated in black. The encoding scheme has 48 Bitplane encoded to 36T + 6B PWM levels.

Other alternative encoding schemes may be implemented accordingly.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

A driver (300) for driving a pixel of a digital liquid crystal on silicon display, the driver (300) comprising:

a control circuit (301) comprising one or more transistors, the control circuit (301) configured to:

clock an input binary signal to latch a state of the pixel for each sub-frame of a frame; and

form a logical control signal for the pixel in dependence on the input binary signal;

a voltage scaling circuit (302) comprising one or more transistors, the voltage scaling circuit (302) configured to:

receive the logical control signal from the control circuit (301) ; and

form a pixel drive signal for driving the pixel in dependence on the logical control signal;

wherein a size of the transistors in the voltage scaling circuit (302) is greater than a size of the transistors in the control circuit (301) .
The driver (300) according to claim 1, wherein the transistors of the control circuit (301) and the transistors of the voltage scaling circuit (302) are formed by a dual gate oxide process.
The driver (300) according to claim 2, wherein a gate oxide thickness of the transistors in the voltage scaling circuit (302) is greater than a gate oxide thickness of the transistors in the control circuit (301) .
The driver (300) according to any preceding claim, wherein an operating voltage of the voltage scaling circuit (302) is greater than an operating voltage of the control circuit (301) .
The driver (300) according to any preceding claim, wherein the operating voltage of the voltage scaling circuit (302) is greater than 3 V and the operating voltage of the control circuit (301) is less than 0.9 V.
The driver (300) according to any preceding claim, wherein the voltage scaling circuit comprises an overcurrent protective device for limiting current in the voltage scaling circuit
The driver (300) according to any preceding claim, wherein the driver (300) comprises a pitch size of less than 3.7 um.
The driver (300) according to any preceding claim, wherein the control circuit (301) comprises a static random-access (SRAM) memory (303, 304) configured to store the input binary signal and the logical control signal.
The driver (300) according to claim 8, wherein:

the SRAM memory comprises a master memory bit (303) and a slave memory bit (304) , wherein:

the control circuit (301) is configured to clock the input binary signal in dependence on the master memory bit (303) ; and

the control circuit (301) is configured to form and hold the logical control signal in dependence on the slave memory bit (304) .
The driver (300) according to any preceding claim, wherein the voltage scaling circuit (302) comprises a digital to analogue converter to form the pixel drive signal for driving the pixel.
The driver (300) according to claim 10, wherein the logical control signal is digital, and the pixel drive signal is analogue.
A driver (300) for driving a pixel of a digital liquid crystal on silicon display, the driver (300) comprising a circuit with one or more transistors configured to:

receive a grey level for each pixel of a set of pixels of the display;

determine a PWM duty cycle for each pixel of the set of pixels in dependence on the grey level;

generate a PWM waveform (800) for each pixel of the set of pixels in dependence on the PWM duty cycle, the PWM waveform (800) defining an output illumination intensity control;

control each pixel of the set of pixels to illuminate for an illumination period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) , the illumination period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) being dependent on the PWM waveform (800) ;

wherein the illumination periods (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) of any two of the set of pixels do not start simultaneously.
The driver (300) according to claim 11, wherein the circuit is configured to receive the grey level for each pixel of the display.
The driver (300) according to claim 12 or 13, wherein the circuit is configured to control each pixel of the set of pixels to illuminate for an illumination period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) comprising a frame period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) , the frame period comprising a plurality of sub-frame periods (1001, 1002) .
The driver (300) according to claim 14, wherein the circuit is configured to control each pixel of the set of pixels to illuminate for an illumination period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) wherein the illumination periods (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) of any two of the set of pixels do not start in the same sub-frame period (1001, 1002, 1604, 1606, 1706) .
The driver (300) according to claim 14 or 15, wherein the frame period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) comprises a blanking period (1605, 1704) between each sub-frame period (1604, 1606, 1706) .
The driver (300) according to claim 16, wherein the circuit is configured to receive the grey level for each pixel of a set of pixels of the display during the blanking period (1605, 1704) .
The driver (300) according to claim 17, wherein the circuit is configured to control each pixel of the set of pixels to illuminate during the sub-frame period (1606, 1705) after the blanking period (1605, 1704) .
The driver (300) according to any of claims 16 to 18, wherein the duration of the blanking period (1605, 1704) is less than the duration of the sub-frame period (1604, 1606, 1706) .
The driver (300) according to any of claim 14 or 15, wherein the circuit is configured to receive the grey level for each pixel of the set of pixels of the display during the sub-frame period (1001, 1002) and hold the grey level for each pixel of the set of pixels of the display until the subsequent sub-frame period (1001, 1002) .
The driver (300) according to claim 20, wherein the circuit is configured to control each pixel of the set of pixels to illuminate during the subsequent sub-frame period (1001, 1002) .
The driver (300) according to any of claims 14 to 21, wherein the sub-frame period (1001, 1002) comprises a plurality of binary weights (1005, 1705) .
The driver (300) according to any of claims 12 to 22, wherein the grey level for each pixel of the set of pixels of the display comprises a grey level of at least 8bit.
A method (900) for driving a pixel of a digital liquid crystal on silicon display, the method comprising:

receiving (901) a grey level for each pixel of a set of pixels of the display;

determining (902) a PWM duty cycle for each pixel of the set of pixels in dependence on the grey level;

generating (903) a PWM waveform (800) for each pixel of the set of pixels in dependence on the PWM duty cycle, the PWM waveform defining an output illumination intensity control;

controlling (904) each pixel of the set of pixels to illuminate for an illumination period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) , the illumination period (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) being dependent on the PWM waveform (800) ;

wherein the illumination periods (1000, 1100, 1200, 1300, 1400, 1600, 1700, 1800) of any two of the set of pixels do not start simultaneously.