[go: up one dir, main page]

WO2022115985A1 - Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint - Google Patents

Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint Download PDF

Info

Publication number
WO2022115985A1
WO2022115985A1 PCT/CN2020/133051 CN2020133051W WO2022115985A1 WO 2022115985 A1 WO2022115985 A1 WO 2022115985A1 CN 2020133051 W CN2020133051 W CN 2020133051W WO 2022115985 A1 WO2022115985 A1 WO 2022115985A1
Authority
WO
WIPO (PCT)
Prior art keywords
cell
selector
memory
liner
lcpcm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/133051
Other languages
English (en)
Inventor
Jun Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Original Assignee
Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze River Advanced Storage Industry Innovation Center Co Ltd filed Critical Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority to PCT/CN2020/133051 priority Critical patent/WO2022115985A1/fr
Priority to CN202080004158.XA priority patent/CN112655093B/zh
Publication of WO2022115985A1 publication Critical patent/WO2022115985A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions

Definitions

  • the present disclosure generally relates to three-dimensional electronic memories, and more particularly, to reducing programming current and thermal cross talk in adjacent memory cells.
  • Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process.
  • feature sizes of the memory cells approach a lower limit
  • planar process and fabrication techniques become challenging and costly.
  • memory density for planar memory cells approaches an upper limit.
  • a three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
  • Phase-change memory is a non-volatile solid-state memory technology that exploits reversible, thermally-assisted switching of phase-change materials like chalcogenide compounds such as GST (Germanium-Antimony-Tellurium) , between states with different electrical resistance.
  • the fundamental storage unit (the “cell” ) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. Programmable cell-states can be used to represent different data values, permitting storage of information.
  • PCM cells are programmed or erased by thermal self-heating to induce an amorphous or crystalline state to denote 1 and 0.
  • Programming current is directly proportional to the size and cross-sectional area of the PCM cell.
  • each cell can be set to one of two states, a “SET” state and a “RESET” state, permitting storage of one bit per cell.
  • RESET state which corresponds to a wholly amorphous state of the phase-change material
  • the electrical resistance of the cell is very high.
  • the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state on rapid cooling.
  • Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase-change material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell, this current being dependent on resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state.
  • Cell state detection can then be performed by comparing the resistance metric with predefined reference levels.
  • Programming current (I) is typically in the order of 100-200 ⁇ A. The voltage drop may be significant if the write line (WL) and bit line (BL) in the cell encounters large resistance.
  • a new liner confined cell structure for 3D X-Point Memory is presented allowing a reduced programming current and reduced thermal cross talk as compared to current state of the art 3D X-Point Memory cell structures.
  • each stack is composed of a perpendicular word line and bit line with a phase change memory (PCM) in series with an ovonic threshold switch (OTS) in between the word line and the bit line.
  • PCM phase change memory
  • OTS ovonic threshold switch
  • the PCM memory cell and the OTS selection device are self-aligned to the word line and bit line.
  • the PCM memory cell is composed of a liner confined cell in bit line direction in electrical contact with the OTS selection device.
  • a method for forming a new recessed liner confined cell structure for 3D X-Point Memory allowing a reduced programming current and reduced thermal cross talk as compared to current state of the art 3D X-Point Memory cell structures.
  • the method includes forming a cross point memory array with parallel bit lines (BL) and perpendicular word lines (WL) .
  • a PCM memory cell in series with an ovonic threshold switch (OTS) is formed at the cross point of the WL and the BL and is self-aligned.
  • a liner confined cell is formed by deposition of sacrificial material on the sidewall of dielectric mesa, removal of the sacrificial material and backfilling with PCM material and planarizing by chemical mechanical polishing (CMP) .
  • CMP chemical mechanical polishing
  • a 3D X-Point Memory Die architecture includes quantities of memory arrays (tiles) separated by a small space.
  • the memory array is composed of multiple memory cells (PCM) with liner confined memory cell and ovonic threshold switch (OTS) .
  • a three-dimensional memory with a liner confined cell structure includes a word line and a bit line perpendicular to each other and coupled to at least one memory cell stack; a selector, a modified liner confined phase change memory (lcPCM) cell, a first electrode, a second electrode, and a third electrode contained within the memory cell stack; the lcPCM cell disposed between the first and the second electrodes, and the selector disposed between the second and the third electrodes; the lcPCM cell and the selector confined between the word line and the bit line, and the lcPCM is in series with the selector; a word line direction running parallel to the word line, and a bit line direction running parallel to the bit line; wherein, the lcPCM cell and the selector are self-aligned with respect to the word line and the bit line; and wherein, the lcPCM is formed in the bit line direction and in electrical contact with the selector.
  • lcPCM modified liner confined phase change memory
  • the lcPCM cell is disposed within a nitride liner.
  • the lcPCM cell, the selector, and the first, the second and the third electrodes each have size dimensions relative to the word line and the bit line directions; and the lcPCM is smaller in dimensions relative to the selector for providing reduced required current to the lcPCM.
  • the selector is an ovonic threshold switch
  • the cell stack further includes an encapsulation layer to protect the lcPCM cell and the ovonic threshold switch.
  • the three-dimensional memory includes additional memory cells in a region above or below a two-dimensional region defined by the word line.
  • the cell stack further includes a nitride layer, a tungsten layer, an oxide layer, a gap fill layer and the first and the second electrodes are carbon electrodes.
  • the gap fill layer contains material selected from a group consisting of cobalt based material, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) , and lead selenide (PbSe) , and any combination thereof.
  • cobalt based material gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmi
  • a three-dimensional X-Point Memory Die architecture with a liner confined cell structure includes a plurality of top arrays or tiles of phase change memory cells; a plurality of bottom arrays or tiles of phase change memory cells; a plurality of bit lines coupled to the top array and coupled to the bottom array; a plurality of word lines, comprising a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array; and wherein, the top array of memory cells are each separated by a first space defined by adjacent phase change memory cell with a liner confined cell and a selector in the top array, and the bottom array of phase change memory cells are each separated by a second space defined by adjacent phase change memory cell with a liner confined cell and a selector in the bottom array.
  • the top and the bottom word lines are coupled thereto.
  • the top and the bottom arrays of recess liner confined cells have a reduced size as compared to a selector disposed within each respective array.
  • the selector is an ovonic threshold switch.
  • a method of forming a three-dimensional memory with a recess liner confined cell structure includes forming a cross point memory array with a plurality of parallel bit lines and a plurality of perpendicular word lines; self-aligned forming a recess liner confined phase change memory (lcPCM) cell in series with an ovonic threshold switch (OTS) selection device at a cross point of the word line and the bit line; and wherein the lcPCM cell is formed by recessing a sacrificial material to form a recess and deposition of phase change memory cell material in the recess and planarization by chemical mechanical planarization (CMP) .
  • CMP chemical mechanical planarization
  • Figs. 1A and 1B are isometric views of a prior multi-section and a single section of three-dimensional cross point memory, respectively.
  • Fig. 2A is an isometric view of a section of a three-dimensional cross point memory
  • Fig. 2B is a diagram showing abbreviations for layers in the cell stack.
  • Figs. 3A and 3B are plan views of a section of a three-dimensional cross point memory showing deposition of a nitride layer
  • Fig. 3C is a top view of Fig. 3B.
  • Fig. 4A is a plan view of a section of a three-dimensional cross point memory showing sacrificial material deposition followed by etching to form liner electrodes.
  • Fig. 4B is a top view of Fig. 4A.
  • Fig. 4C is a plan view of a section of the three-dimensional cross point memory of Fig. 4A showing recess of the sacrificial material and backfilling with PCM material.
  • Fig. 4D is a top view of Fig. 4C.
  • Figs. 5A and 5B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 4A and 4B showing bottom cell double patterning with a first partial etch to etch through the top electrode and memory cell, stopping on the middle electrode to form parallel lines.
  • Figs. 6A and 6B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 5A and 5B showing bottom cell etch with a second partial etch to etch to form parallel bottom cell bit lines followed by encapsulation, gap filling and polishing.
  • Figs. 7A and 7B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 6A and 6B showing word line metal deposition.
  • Figs. 8A and 8B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 7A and 7B showing bottom cell word line double patterning to form parallel lines.
  • Figs. 9A and 9B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 8A and 8B showing encapsulation, gap filling and polishing the cell stack.
  • Figs. 10 is a plan view of the three-dimensional cross point memory in accordance with the embodiment of Figs. 9A and 9B showing a second stack of memory cell deposition on top of the stack shown in Fig. 9A.
  • Fig. 11 is a plan view of a section of an alternative embodiment of a three-dimensional cross point memory.
  • references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” and the like, merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
  • terminology may be understood at least in part from usage in context.
  • the term “one or more” as used herein, depending at least in part upon context may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense.
  • terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
  • spatially relative terms such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • substrate may refer to any workpiece on which formation or treatment of material layers is desired.
  • Non-limiting examples include silicon, germanium, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glasses, combinations or alloys thereof, and other solid materials.
  • the substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate can include a wide array of semiconductor materials, including but not limited to silicon, germanium, gallium arsenide, indium phosphide, and the like.
  • the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
  • a layer refers to a material portion including a region with a thickness.
  • a layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface.
  • a substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow.
  • a layer can include multiple layers.
  • an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
  • horizontal as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate.
  • vertical will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above” , “below” , “bottom” , “top” , “side” (e.g. sidewall) , “higher” , “lower” , “upper” , “over” , and “under” , are defined with respect to the horizontal plane.
  • on means there is direct contact between the elements. The term “above” will allow for intervening elements.
  • a material e.g. a dielectric material or an electrode material
  • crystalline if it exhibits greater than or equal to 30%crystallinity as measured by a technique such as x-ray diffraction (XRD) .
  • XRD x-ray diffraction
  • first, ” “second, ” and other ordinals will be understood to provide differentiation only, rather than imposing any specific spatial or temporal order.
  • oxide of an element
  • nitride of an element
  • FIG. 1A is an isometric view of a section of three-dimensional crosspoint memory.
  • the memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in the X direction. Above the first layer of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction.
  • bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration.
  • an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.
  • FIG. 1B shown is a single section 100 of the cell structure in FIG. 1A. Shown is a top cell bit line 110 connected to a top cell stack 150. Stack 150 is composed of several layers that will be described herein in the improvement of this standard stack 150. Perpendicular to the top cell bit line 110 is top cell write line 130 and bottom cell write line 140. Connected to bottom cell write line 140 is a bottom cell stack 160. Parallel to top cell bit line 110 is bottom cell bit line 120. Bottom cell bit line 120 is coupled to the bottom cell stack 160. Like cell stack 150, cell stack 160 is also made of several layers. FIGS. 1A and 1B illustrate the general structure of a 3D X-Point Memory cell that terminology is used herein to describe the improvement. The FIG.
  • the section includes a number of word lines, e.g. word lines 130, 140, extending in the X (horizontal) direction, a number of top cell bit lines, e.g., bit lines 110, 120, extending along the Y (vertical) direction and corresponding to a top cell array of memory cells 150, and a number of bottom cell bit lines extending along the vertical direction and corresponding to a bottom cell array of memory cells 160.
  • the word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate.
  • the memory may employ complementary metal-oxide semiconductor (CMOS) technology.
  • CMOS complementary metal-oxide semiconductor
  • FIG. 2A Adverting to FIG. 2A is a plan view of an exemplary three-dimensional cross point bottom cell stack. Each stack is made of several layers. The cell stacks are similar in function and composition. For the description of materials disclosed herein, similar reference numerals to common elements in various figures denote similar material and functions of the elements shown and described.
  • FIG. 2A shown is a single section 200 of the cell structure of an embodiment. Shown is a bottom cell write line 210 connected to a bottom cell stack 230. Perpendicular to the bottom cell write line 210 is a bottom cell bit line 220.
  • Layer 201 is a nitride layer. Examples of such materials include metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x ⁇ 2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials.
  • deposition may be accomplished by chemical vapor deposition (CVD) .
  • CVD chemical vapor deposition
  • a vacuum deposition method is used to produce high quality, high performance, and solid materials.
  • the water (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit.
  • Layers 202a, 202b, and 206c are a-C or electrode layers.
  • the electrodes can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon.
  • the electrode may be a carbon electrode or any other electrode known to one skilled in the art.
  • Layer 203 is a modified phase change memory (PCM) cell or liner confined PCM 203.
  • FIG. 2A shows the liner confined PCM 203 in an amorphous 203a and crystalline 203b state, respectively.
  • Liner confined PCM 203 is confined in nitride layer 201 as shown in FIG. 2A.
  • the PCM 203 is disposed between electrodes 202a and 202b in the cell stack as shown in FIG. 2A.
  • Memory cell 203 is disposed into or thereon nitride layer 201.
  • a selector or ovonic threshold switch (OTS) 205 is also disposed between two electrodes, 202b, 202c.
  • FIG. 2B is a diagram showing abbreviations for the various layers described herein.
  • the features described are particularly advantageous for multi-level cells, these features can also be applied to advantage in single-level cells in some embodiments.
  • the prior configuration as exemplified in FIGS. 1A, and 1B is inefficient in its use of memory area (or “memory real estate” ) .
  • the configuration is susceptible to cross talk from adjacent cells causing interference with the memory cells.
  • power requirements are dramatically increased as the number of the cells is increased due to increased need for additional memory.
  • the disclosed new configurations provide improved memory cell density and bit line density as well as reduced cross talk and power required for the memory cell.
  • the new configuration includes a reduced sized PCM 203, 503 in relation to the selector and/or electrodes in its respective stack. This reduced size and cross sectional area may be seen for example starting at a process shown from FIGS. 3A and 3B through to FIG. 10.
  • FIG. 3A illustrates a bottom cell stack deposition.
  • Layer 301 may be a tungsten based compound, or a cobalt based compound, and functions as a conductor among other things. Depending on the embodiment, the conductor may be made of other materials that have conductive properties.
  • Layers 202b and 202c are a-C or electrode layers.
  • a selector or ovonic threshold switch (OTC) 205 is disposed between electrode layers 202b and 202c.
  • Layer 302 may be a substrate depending on the embodiment or represent the bottom bit line. In FIG. 3B, shown is a nitride layer 201 deposition covering electrode 202b.
  • a first etching occurs to etch through the nitride layer 201 and stops on electrode 202b to form parallel lines of nitride layer 201a and 201b.
  • Etching depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide. Other methods known by those skilled in the art may also be utilized.
  • FIG. 3C shown is a top view of the parallel lines of nitride layer 201 formed.
  • FIG. 4A illustrates a liner sacrificial material deposition step.
  • Liner sacrificial material 404 is disposed between the parallel lines of nitride layer 201a, 201b.
  • a second etching occurs to etch the liner sacrificial material 404 to form liner sacrificial layers 404a, 404b, 404c.
  • Nitride material is disposed between the liner sacrificial layers 404a, 404b, 404c to form parallel lines of nitride layer 401a, 401b, and chemical mechanical polishing (CMP) treatment occurs, planarizing the nitride-liner sacrificial layer surface 410.
  • CMP chemical mechanical polishing
  • 4B is a top view of the embodiment of FIG 4A, showing resultant alternating parallel lines of nitride layer 401a, 201a, 401b, 201b and liner sacrificial layer 404a, 404b, 404c.
  • FIG. 4C illustrates liner sacrificial layer recess and PCM deposition steps.
  • Liner sacrificial layers 404a, 404b, 404c are recessed and backfilled with PCM material to form liner confined PCM layer 403a, 403b, 403c.
  • the liner confined PCM layers 403a, 403b, 403c are disposed between nitride layers 401a, 201a, 401b, 201b, respectively.
  • Chemical mechanical polishing (CMP) treatment occurs, planarizing the nitride-recess liner confined PCM layer 420.
  • FIG. 4D is a top view of the embodiment of FIG. 4C.
  • FIG. 5A illustrates an electrode deposition step.
  • an electrode layer 202a and a nitride layer 501 hard mask are produced.
  • the electrode can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon.
  • the electrode layer 202a may be a carbon electrode or any other electrode known to one skilled in the art.
  • the nitride layer 501 may be TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x ⁇ 2 indicates reduction) , or metals such as W, Ni, Co, or carbon based materials.
  • FIG. 5B illustrates bottom cell double patterning.
  • a first partial etch occurs to etch through the top electrode 202a and nitride-liner confined PCM 203 and stops on electrode 202b to form parallel lines.
  • Bottom cell double patterning with first etching or partial etching, depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide or other methods known by those skilled in the art.
  • FIG. 5B illustrates deposition of nitride and oxide encapsulation 510, 512 to cover stacks 1, 2, and 3 to protect the exposed electrode and nitride-recess liner confined phase change memory cell in each stack.
  • Encapsulation layer 510 may be composed of silicon nitride or other suitable materials.
  • Stacks 1, 2, and 3 may be further encapsulated with oxide layer 512 including a substrate.
  • FIG. 6A illustrates the second etching to etch through the remaining electrodes 202b, 202c, ovonic thermal switch 205 and conductor 301 to form parallel bottom cell bit lines.
  • Encapsulation layer 610 deposition covering stacks 1, 2, and 3 to protect the now exposed ovonic thermal switch 205 in each stack.
  • gap fill 601 cover the stacks 1, 2, and 3.
  • Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) or flowable chemical vapor deposition (CVD) oxide.
  • SOD Spin on Dielectric
  • CVD flowable chemical vapor deposition
  • gap fill materials include, but are not limited to, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) and lead selenide (PbSe) and Cobalt based compounds and any combination thereof.
  • FIG. 6B illustrates oxide/nitride chemical mechanical polishing (CMP) treatment to the stacks 1, 2, and 3. The CMP treatment stops on the carbon electrode 202a as shown in FIG. 6B.
  • CMP oxide/nitride chemical mechanical polishing
  • FIG. 7A illustrates a word line metal and nitride metal deposition step. Shown in the X direction, a metal layer 701 and a nitride layer 702 are produced.
  • the metal layer 701 may be tungsten or any other conductor metal.
  • the nitride layer 702 may be TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x ⁇ 2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials.
  • deposition may be accomplished by chemical vapor deposition (CVD) .
  • FIG. 5B is a cross section taken from stack 1 of FIG. 7A along line 7B-7B showing the various layers described in FIG. 7A in the Y direction.
  • FIGS. 8A and 8B illustrate bottom cell word line double patterning to form parallel bottom cell write lines perpendicular to bit lines that are in contact with the bottom cell top carbon electrode 202a.
  • FIG. 8B which is a cross-section of FIG. 8A in a direction 8B-8B, a first partial etch occurs to etch through the top electrode 202a, liner confined PCM 203, and stops on electrode 202b to form parallel lines.
  • Etching depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide, or by other methods known by those skilled in the art.
  • FIGS. 9A and 9B illustrate deposition of nitride and oxide encapsulation 910, 912 to cover stacks 1, 2, and 3 to protect the exposed electrode and nitride-recess liner confined phase change memory cell in each stack.
  • Encapsulation layer 910 may be composed of silicon nitride or other suitable materials.
  • Stacks 1, 2, and 3 may be further encapsulated with oxide layer 912 including a substrate.
  • Bottom cell write line etching then occurs with a second etching to etch through the remaining electrodes 202b, 202c, ovonic thermal switch 205, and conductor 301 to form parallel bottom cell word lines.
  • gap fill 9 cover the stacks 801, 802, and 803.
  • Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) or flowable chemical vapor deposition (CVD) oxide.
  • Oxide chemical mechanical polishing (CMP) is done and stopped in conductor 701, as shown in FIG. 9B.
  • conductor 701 may be tungsten (W) or another conductive material
  • FIG. 10 illustrates a second stack of memory cell deposition and patterning with the new cell structure described herein with a recess and reduced dimension. Shown is top section 1010 and bottom section 1030 both having reduced phase change memory cells 203 relative to electrodes 202a, 202b, 202c and selector 205. Top cell and bottom cell write lines 1020 separate the two stacks. Oxide/nitride chemical mechanical polishing (CMP) treatment to the stacks 1001, 1002, and 1003. The CMP treatment stops on conductor 701 as shown in FIG. 9B.
  • CMP chemical mechanical polishing
  • FIG. 11 illustrates a single section 1100 of the cell structure of another embodiment. Shown is liner confined PCM 203 disposed within nitride liner 201. The nitride liner 201 and liner confined PCM 201 are disposed between metal electrodes 1101a and 1101b. Metal electrodes 1101a and 1101b may be tungsten or any other conductor metal. This embodiment could utilize all other elements of the embodiment described in FIGS. 2A-10.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

Architecture de mémoire tridimensionnelle comprenant un réseau de cellules supérieures de cellules de mémoire et un réseau de cellules inférieures des cellules de mémoire; une pluralité de lignes de mots et de lignes de bits sont couplées aux réseaux. Les cellules de mémoire sont des cellules de mémoire à changement de phase (MCP) qui sont modifiées pour former un matériau MCP confiné dans un revêtement formé dans l'évidement d'un matériau sacrificiel. Une zone de contact réduite entre l'électrode et la cellule MCP et le volume de matériau cellulaire réduit conduit à un besoin moindre de courant pour la programmation de la cellule. La distance plus grande entre les cellules de mémoire adjacentes permet de réduire la diaphonie thermique. Une taille de cellule MCP plus petite que la taille de sélecteur permet de réduire une exigence de densité de courant dans le sélecteur de courant (également appelé limiteur de courant ou élément de direction courant) dans un élément de mémoire à commutation résistive.
PCT/CN2020/133051 2020-12-01 2020-12-01 Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint Ceased WO2022115985A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/133051 WO2022115985A1 (fr) 2020-12-01 2020-12-01 Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint
CN202080004158.XA CN112655093B (zh) 2020-12-01 2020-12-01 具有衬垫限制单元结构的三维存储器及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/133051 WO2022115985A1 (fr) 2020-12-01 2020-12-01 Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint

Publications (1)

Publication Number Publication Date
WO2022115985A1 true WO2022115985A1 (fr) 2022-06-09

Family

ID=75368542

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/133051 Ceased WO2022115985A1 (fr) 2020-12-01 2020-12-01 Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint

Country Status (2)

Country Link
CN (1) CN112655093B (fr)
WO (1) WO2022115985A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114270520B (zh) * 2021-11-16 2025-01-21 长江先进存储产业创新中心有限责任公司 相变存储器设备及其形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100078619A1 (en) * 2008-09-30 2010-04-01 Stmicroelectronics S.R.L. Resistive memory cell and method for manufacturing a resistive memory cell
US10050194B1 (en) * 2017-04-04 2018-08-14 Sandisk Technologies Llc Resistive memory device including a lateral air gap around a memory element and method of making thereof
US10199434B1 (en) * 2018-02-05 2019-02-05 Sandisk Technologies Llc Three-dimensional cross rail phase change memory device and method of manufacturing the same
US20200287133A1 (en) * 2019-03-07 2020-09-10 Intel Corporation Memory device with boron nitride liner
US20200287129A1 (en) * 2019-03-07 2020-09-10 Intel Corporation Memory device with multi-layer liner structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8625322B2 (en) * 2010-12-14 2014-01-07 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof
CN108807667B (zh) * 2018-05-30 2020-08-04 华中科技大学 一种三维堆叠存储器及其制备方法
JP7394881B2 (ja) * 2019-10-14 2023-12-08 長江存儲科技有限責任公司 ３次元相変化メモリデバイスを形成するための方法
KR102659033B1 (ko) * 2019-10-14 2024-04-22 양쯔 메모리 테크놀로지스 씨오., 엘티디. 3차원 상변화 메모리 디바이스들
CN112041997B (zh) * 2020-07-27 2024-01-12 长江先进存储产业创新中心有限责任公司 用于3D X-Point存储器的具有减小的编程电流和热串扰的新单元结构
CN111969110B (zh) * 2020-09-04 2022-02-01 长江先进存储产业创新中心有限责任公司 一种存储器及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100078619A1 (en) * 2008-09-30 2010-04-01 Stmicroelectronics S.R.L. Resistive memory cell and method for manufacturing a resistive memory cell
US10050194B1 (en) * 2017-04-04 2018-08-14 Sandisk Technologies Llc Resistive memory device including a lateral air gap around a memory element and method of making thereof
US10199434B1 (en) * 2018-02-05 2019-02-05 Sandisk Technologies Llc Three-dimensional cross rail phase change memory device and method of manufacturing the same
US20200287133A1 (en) * 2019-03-07 2020-09-10 Intel Corporation Memory device with boron nitride liner
US20200287129A1 (en) * 2019-03-07 2020-09-10 Intel Corporation Memory device with multi-layer liner structure

Also Published As

Publication number Publication date
CN112655093B (zh) 2023-04-18
CN112655093A (zh) 2021-04-13

Similar Documents

Publication Publication Date Title
WO2022021014A1 (fr) Nouvelle structure cellulaire à courant de programmation réduit et diaphonie thermique pour mémoire à points x 3d
US8168469B2 (en) Nonvolatile memory device made of resistance material and method of fabricating the same
US6969866B1 (en) Electrically programmable memory element with improved contacts
TWI497706B (zh) 具有自動對準底電極和二極體存取裝置之蕈狀記憶胞
WO2016140715A1 (fr) Mémoire vive résistive tridimensionnelle à lignes de bits parallèles
WO2022104591A1 (fr) Cellule de mémoire à changement de phase 3d verticale et schéma de lecture de programme
US20250344406A1 (en) Switching cell
US12464961B2 (en) Semiconductor device and method for fabricating the same
WO2022077167A1 (fr) Nouveau schéma de contact de semi-damasquinage auto-aligné pour réduire le coût pour pcm 3d
US20230131200A1 (en) Semiconductor device and method for fabricating the same
US20230171967A1 (en) Semiconductor device and method for fabricating the same
WO2022115985A1 (fr) Nouvelle structure cellulaire confinée dans un revêtement et procédé de fabrication à courant de programmation réduit et diaphonie thermique pour mémoire 3d xpoint
WO2022115984A1 (fr) Nouvelle structure cellulaire confinée à revêtement d'évidement et procédé de fabrication à courant de programmation et diaphonie thermique réduits pour mémoire à points x en 3d
WO2022115986A1 (fr) Nouvelle structure cellulaire d'électrode de revêtement et procédé de fabrication à courant de programmation et diaphonie thermique réduits destinés à une mémoire 3d xpoint
WO2022109773A1 (fr) Nouvelle structure cellulaire de super-réseau et procédé de fabrication à courant de programmation et diaphonie thermique réduits pour mémoire à points x en 3d
WO2022073222A1 (fr) Procédé de réduction de la diaphonie thermique dans un réseau de mémoire à points x en 3d
WO2022077176A1 (fr) Nouvelle structure cellulaire de constriction et procédé de fabrication à courant de programmation et diaphonie thermique réduits pour mémoire à points x en 3d
WO2022104505A1 (fr) Nouveau remplissage d'espace et structure cellulaire pour une fiabilité thermique de sélecteur améliorée pour pcm 3d
WO2022032490A1 (fr) Nouvel empilement de cellules à résistance wl et bl réduite pour mémoire à points x 3d pour amélioration de programme et augmentation de taille de réseau
WO2022032489A1 (fr) Nouveau schéma de ligne de bits et de ligne de mots de remplacement pour mémoire à changement de phase 3d afin d'améliorer le programme et d'augmenter la taille de matrice
CN118234250A (zh) 半导体装置
US12396178B2 (en) Semiconductor device and method for fabricating the same
US20230380192A1 (en) Semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20963834

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20963834

Country of ref document: EP

Kind code of ref document: A1