WO2022185581A1 - Control device and data transfer method - Google Patents

Abstract

A data transfer circuit of this control device comprises a first request issuing unit that issues a first read request to a memory in response to execution of a first task by a processor, a second request issuing unit that issues a second read request to the memory in response to execution of a second task by the processor, and a management unit that manages the number of read requests that can be issued continuously. The priority of the first task is higher than that of the second task. The management unit limits the number of second read requests that can be issued continuously by the second request issuing unit so as to be smaller in a first period in which the first task is planned to be executed than in a second period other than the first period.

Description

Control device and data transfer method

The present disclosure relates to a control device and a data transfer method.

FA (Factory Automation) technology using control devices such as PLCs (Programmable Logic Controllers) is widely used in various production sites. In FA technology, improvement in data transfer throughput is desired in order to meet the demand for real-time performance. By increasing the data size that can be transferred at one time, the transfer throughput is improved. However, if the transfer of high-priority data becomes necessary immediately after the transfer of low-priority data is requested, the transfer of high-priority data is delayed. Therefore, it is desirable to suppress delays in transferring data with high priority.

Japanese Patent Application Laid-Open No. 2019-54350 (Patent Document 1) discloses a transfer device that dynamically controls the maximum data request size by referring to scheduling information that indicates a schedule of timings at which data transfers occur. The transfer device sets the maximum data request size of the second data at the timing at which the transfer interrupt of the first data may occur during the transfer of the second data whose priority is lower than that of the first data. Control to a value below the threshold. As a result, the delay in transferring the first data with high priority is suppressed.

JP 2019-54350 A

A technology is known that can issue multiple data transfer requests in succession. Patent Literature 1 does not assume such a technique. Therefore, when this technology is applied to Patent Document 1, a request for transferring data with low priority may be issued a plurality of times in succession. This can cause a delay in transferring high priority data.

The present disclosure has been made in view of the above problems, and an object thereof is to provide a control device and a data transfer method capable of suppressing delays in transferring high-priority data.

According to one example of the present disclosure, a control device includes a processor, a memory, and a data transfer circuit. The data transfer circuit includes a first request issuing unit that issues a first read request to the memory in accordance with the execution of the first task by the processor, and a second request to the memory in response to the execution of the second task by the processor. It includes a second request issuing unit that issues read requests, and a management unit that manages the number of read requests that can be continuously issued. The first task has a higher priority than the second task. The management unit sets the number of second read requests that can be continuously issued by the second request issuing unit to be smaller in a first period during which execution of the first task is scheduled than in a second period other than the first period. limit to

According to the above disclosure, the number of read requests issued by the second request issuing unit in response to the execution of the second low-priority task by the processor during the first period in which the execution of the first high-priority task is scheduled limited in number. Thereby, the first request issuing unit can issue a read request in accordance with the execution of the high-priority first task by the processor in the first period. As a result, a delay in transferring read data corresponding to a high-priority task is suppressed.

In the above disclosure, the management unit limits the number of second read requests that can be continuously issued by the second request issuing unit to 1 in the first period.

According to the above disclosure, even if the processor first executes the low-priority second task in the first period, the second request issuing unit can issue only one read request in succession. Therefore, during the remaining period, the first request issuing unit can issue a read request according to the execution of the high-priority first task by the processor.

In the above disclosure, the processor executes a user program for controlling the controlled object. The first period is predetermined based on the user program.

The user program can estimate the processing sequence of the processor. Therefore, according to the above disclosure, it is possible to accurately determine the first period during which the execution of the first task is scheduled.

In the above disclosure, the processor executes a user program for controlling the controlled object. The first period is included in the period during which the processor executes the user program to control the controlled object, and is not included in the activation period and termination period of the user program.

　In the user program startup period and termination period, the order of data to be transferred does not matter. Therefore, according to the above disclosure, the first period is not included in the activation period and the termination period of the user program, so the number of second read requests that can be issued in succession is not limited. As a result, the frequency of waiting for the issuance of read requests is reduced, and the data transfer throughput is improved.

In the above disclosure, the management unit does not limit the number of first read requests that can be issued continuously by the first request issuing unit in the first period and the second period.

According to the above disclosure, the number of read requests corresponding to the execution of the high-priority first task is not limited, and the delay in transferring data corresponding to the read requests is suppressed.

In the above disclosure, the data transfer circuit further includes a third request issuing unit that issues a third read request to the memory in response to execution of the third task by the processor. The third task has a lower priority than the first task. The management unit limits the number of second read requests that can be continuously issued by the second request issuing unit to a first value in the first period, and limits the number of second read requests that can be continuously issued by the third request issuing unit to a first value. The number of requests is limited to a second value during the first time period.

According to the above disclosure, the limit on the number of read requests that can be issued consecutively can be changed according to the task.

In the above disclosure, the third task has higher priority than the second task. The first value is less than the second value.

According to the above disclosure, it is possible to suppress delays in transferring data corresponding to read requests in response to execution of tasks with high priority.

In the above disclosure, the data transfer circuit further includes a third request issuing unit that issues a third read request to the memory in response to execution of the third task by the processor. The third task has a lower priority than the first task and a higher priority than the second task. The management unit sets the number of second read requests that can be continuously issued by the second request issuing unit to a first value in the first period, and sets the number to the second value in the third period when execution of the third task is scheduled. value, and set to the third value in periods other than the first period and the third period. The first value and the second value are less than the third value.

According to the above disclosure, it is possible to suppress delays in transferring data corresponding to read requests in response to the execution of the first task and the third task, which have higher priority than the second task.

In the above disclosure, the first value is smaller than the second value. According to the above disclosure, the delay in transferring data corresponding to the read request according to the execution of the first task can be suppressed more than the third task.

In the above disclosure, the data transfer circuit further includes an arbitration circuit that arbitrates access to the memory. The manager may be included in the arbitration circuit.

According to an example of the present disclosure, a data transfer method in a control device comprising a processor and a memory includes the steps of issuing a first read request to the memory in response to execution of a first task by the processor; The method includes the steps of: issuing a second read request to the memory according to execution of the task; and managing the number of read requests that can be continuously issued. The first task has a higher priority than the second task. The managing step includes setting the number of first read requests that can be issued in succession to be smaller in a first period during which execution of the first task is scheduled than in a second period other than the first period. include. Also in this disclosure, delay in transferring data with high priority is suppressed.

According to the present disclosure, it is possible to suppress delays in transferring high-priority data.

It is a figure which shows typically an example of a structure of the control apparatus which concerns on this Embodiment. It is a figure which shows an example of data transfer in a reference form which does not have a change signal output part and a management part. FIG. 4 is a diagram showing an example of data transfer in the embodiment; FIG. 1 is a schematic diagram showing a configuration example of a control system including a control device according to an embodiment; FIG. It is a figure which shows the structure of a support apparatus roughly. It is a figure which shows an example of the processing sequence of a control apparatus. FIG. 10 is a diagram showing an example of a period during which a change signal is activated; FIG. 10 is a diagram showing another example of data transfer in the embodiment; FIG. It is a figure which shows the structure of the control apparatus which concerns on a modification.

Embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated.

§1 Application Example First, an example of a scene to which the present invention is applied will be described. FIG. 1 is a diagram schematically showing an example of the configuration of a control device 1 according to this embodiment. The control device 1 is, for example, an industrial controller such as a PLC (Programmable Logic Controller). In the following description, a PLC will be described as a specific example as a typical example of the "control device", but the technical idea disclosed in this specification is not limited to the PLC, and can be applied to any control device. Applicable.

As shown in FIG. 1, the control device 1 includes a processor 10, a main memory 20, a root complex 30, a clock section 40, a data transfer circuit 50, ports 61 and 62, and a memory 63. .

The processor 10 is composed of, for example, a CPU (Central Processing Unit), an MPU (microprocessor unit), and the like. The processor 10 reads various programs stored in a storage (not shown), develops them in the main memory 20, and executes them, thereby performing control according to the control target. The storage is composed of, for example, non-volatile storage devices such as HDDs (Hard Disk Drives) and SSDs (Solid State Drives). The main memory 20 is composed of a volatile storage device such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

The clock unit 40 is composed of, for example, a free-running counter. Based on the count value of the clock unit 40, the processor 10 executes various processes for controlling the control target.

The root complex 30 executes communication with the data transfer circuit 50. The root complex 30 communicates with the data transfer circuit 50 according to a communication standard such as PCIe (Peripheral Component Interconnect Express). Note that the root complex 30 may communicate with the data transfer circuit 50 according to other communication standards than PCIe.

Further, the root complex 30 is connected to the processor 10 via a system bus and connected to the main memory 20 via a memory bus. Furthermore, the root complex 30 is connected to the clock section 40 .

The data transfer circuit 50 is a circuit that transfers data between the main memory 20 and the device or memory 63 . The data transfer circuit 50 is configured by, for example, an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). The data transfer circuit 50 includes DMACs (Direct Memory Access Controllers) 51 to 53, an arbitration circuit 54, an endpoint 55, a clock section 56, a change signal output section 57, Phy chips 58 and 59, memory I/ F (interface) 60 and .

The endpoint 55 is connected to the root complex 30 and communicates with the root complex 30.

Phy chips 58 and 59 are connected to ports 61 and 62, respectively. Ports 61 and 62 are connected to units such as I/O devices. This allows the data transfer circuit 50 to communicate with an external unit.

The memory I/F 60 is connected with the memory 63 . This allows the data transfer circuit 50 to access the memory 63 .

The DMAC 51 is connected to the Phy chip 58 and transfers data directly between the main memory 20 and units connected to the port 61 . DMAC 52 is connected to Phy chip 59 and transfers data directly between main memory 20 and units connected to port 62 . DMAC 53 is connected to memory I/F 60 and directly transfers data between main memory 20 and memory 63 .

The DMACs 51 to 53 issue read requests to the main memory 20 according to instructions from the processor 10 . The root complex 30 reads data from the main memory 20 and transfers the read data (hereinafter referred to as read data) to the data transfer circuit 50 in response to the read request.

The root complex 30 can continuously accept read requests until the transfer of read data is completed. The upper limit value Nmax of the number of read requests that the root complex 30 can continuously accept is determined according to the communication standard, buffer capacity, and the like. The upper limit value Nmax is set in the endpoint 55 in advance. The endpoint 55 only requests read requests up to the upper limit Nmax. That is, the endpoint 55 outputs read requests issued from the DMCs 51 to 53 to the root complex 30 only when the number of read requests for which corresponding read data has not yet been transferred is less than the upper limit value Nmax.

Management units 51a to 53a are added to the DMACs 51 to 53, respectively. The management units 51a-53a respectively manage the number of read requests issued by the DAMCs 51-53.

Specifically, the management units 51a to 53a limit the number of read requests that can be continuously issued from the DMACs 51 to 53 to the limit value N in response to the change signal output from the change signal output unit 57 being active. , respectively (hereinafter referred to as "restriction function"). The limit value N is smaller than the upper limit value Nmax of the number of read requests that the root complex 30 can continuously accept.

For example, when the change signal is active, the management unit 53a limits the number of read requests that the DMAC 53 can issue continuously to "1". In this case, even if the number of read requests for which the corresponding read data has not been transferred is less than the upper limit value Nmax, the DMAC 53 issues the read request and completes the transfer of the read data corresponding to the read request. Until this time, the next read request cannot be issued.

The management units 51a to 53a can switch between enabling/disabling the restriction function. For example, when the limiting functions of the management units 51a and 52a are set to be disabled and the limiting function of the management unit 53a is set to be enabled, the number of read requests that can be issued continuously in response to the change signal only for the DMAC 53 is the limit value. is limited to N. In the DMACs 51 and 52, even if the change signal is active, the number of read requests that can be continuously issued is not limited to the limit value N (<Nmax). Note that the management units 51a to 53a may disable the limiting function by setting the limiting value N to the upper limit value Nmax.

The arbitration circuit 54 arbitrates access requests to the main memory 20 . For example, the arbitration circuit 54 performs arbitration to avoid conflicts due to simultaneous accesses from the DMACs 51-53.

The clock unit 56 is composed of, for example, a free-running counter. The count value of clock section 56 is synchronized in advance with the count value of clock section 40 .

The change signal output unit 57 generates a change signal based on the predetermined schedule information and the count value of the clock unit 56, and outputs the generated change signal to the DMACs 51-53. The schedule information indicates the start timing and end timing of the period during which the change signal is active. The change signal output unit 57 switches the change signal from inactive to active when the count value of the clock unit 56 reaches the start timing indicated by the schedule information. The change signal output unit 57 switches the change signal from active to inactive when the count value of the clock unit 56 reaches the end timing indicated by the schedule information.

FIG. 2 is a diagram showing an example of data transfer in a reference form that does not have the change signal output section 57 and management sections 51a to 53a. FIG. 2 shows an example in which the upper limit value Nmax of the number of read requests that the root complex 30 can continuously accept is four. In FIG. 2, the horizontal axis indicates time. Level 1 shows a read request sent from the DMAC 51 to the endpoint 55 . The second row shows a read request sent from the DMAC 53 to the endpoint 55 . The third row shows a read request transmitted from endpoint 55 to root complex 30 . The fourth row shows read data to be transferred.

In the example shown in FIG. 2, the DMAC 53 continuously issues four read requests R1 to R4 in response to receiving a read instruction from the processor 10 at time t1.

At time t2 when the read request R4 is transmitted to the root complex 30, the endpoint 55 determines that the number of read requests whose read data transfer has not been completed is the upper limit value Nmax. Therefore, the endpoint 55 does not issue the next read request to the root complex 30 until the transfer of the read data D1 corresponding to the read request R1 is completed. As a result, even if DMAC 51 receives a read instruction from processor 10 at time t 2 , read requests R 5 and R 6 from DMAC 51 are not output from endpoint 55 to root complex 30 .

At the time t3 when the transfer of the read data D1 corresponding to the read request R1 is completed, the endpoint 55 determines that the number of read requests for which the transfer of the read data has not been completed (3) is less than the upper limit value Nmax (=4). We judge that it is. As a result, the endpoint 55 outputs the read request R5 issued from the DMAC 51 to the root complex 30 .

When the endpoint 55 outputs the read request R5 to the root complex 30, the endpoint 55 determines that the number of read requests for which the transfer of read data has not been completed is the upper limit value Nmax. Therefore, the endpoint 55 does not request the next read request R6 from the root complex 30 until the transfer of the read data D2 corresponding to the read request R2 is completed.

At the time t4 when the transfer of the read data D2 corresponding to the read request R2 is completed, the root complex 30 endpoint 55 determines that the number of read requests (three) for which the transfer of the read data has not been completed reaches the upper limit value Nmax (=4). pieces). As a result, the endpoint 55 outputs the read request R6 issued from the DMAC 51 to the root complex 30 .

The transfer of read data D5 corresponding to read request R5 is started at time t5 after the transfer of read data D1 to D4 respectively corresponding to read requests R1 to R4 is completed. Transfer of read data D6 corresponding to read request R6 is started following transfer of read data D5.

When the DMAC 51 issues a read request according to execution of a task with high priority and the DMAC 53 issues a read request according to execution of a task with low priority, as shown in FIG. A problem arises in that the transfer of the read data D5 and D6 corresponding to .

The control device 1 according to the present embodiment has a change signal output section 57 and management sections 51a to 53a in order to solve such problems. Based on the execution schedule of each task, the change signal output unit 57 generates an active change signal during a first period during which the high-priority task is scheduled to be executed, and generates an inactive change signal during a second period other than the first period. Generate a change signal. Further, the validity/invalidity of the limiting function of each of the management units 51a to 53a is set according to the priority of the task. Specifically, the limiting function of the management unit 51a of the DMAC 51 that issues read requests according to the execution of high-priority tasks is disabled, and the DMAC 53 that issues read requests according to the execution of low-priority tasks is managed. The limiting function of the section 53a is set to valid.

FIG. 3 is a diagram showing an example of data transfer in this embodiment. FIG. 3 shows an example in which the upper limit value Nmax is 4 and the limit value N is 1. In FIG. However, the limiting function of the management section 51a is disabled, and the limiting function of the management section 53a is enabled.

In Figure 3, the horizontal axis indicates time. The first row shows the change signal. The second row shows a read request sent from the DMAC 51 to the endpoint 55 . The third row shows a read request sent from the DMAC 53 to the endpoint 55 . The fourth row shows a read request transmitted from endpoint 55 to root complex 30 . Level 5 shows read data to be transferred.

As shown in FIG. 3, the change signal is active during the period T1 during which the high priority task is scheduled to be executed. FIG. 3 shows an example in which the DMAC 53 receives a read instruction corresponding to execution of a low-priority task by the processor 10 at time t1 within the period T1. In the example shown in FIG. 3, it is necessary to issue four read requests R1 to R4 in response to the read instruction.

The DMAC 53 issues a read request R1 at time t1. The change signal is active during the period T1. Therefore, the management unit 53a of the DMAC 53 limits the number of read requests that can be issued continuously to the limit value N (=1). As a result, the DMAC 53 cannot issue the next read request R2 until the read data transfer corresponding to the read request accepted by the root complex 30 is completed.

At time t6, which is later than time t1 and within period T1, the DMAC 51 receives a read instruction according to the execution of the high-priority task by the processor 10. Assume that two read requests R5 and R6 need to be issued in response to the read instruction. The restriction function of the management unit 51a of the DMAC 51 is disabled. Therefore, the DMAC 51 continuously issues read requests R5 and R6.

At time t7 at the end of period T1, the change signal switches to inactive. At time t7, the number of read requests for which the transfer of read data has not been completed is three, which is less than the upper limit value Nmax. As a result, at time t6, the DMAC 53 issues the next read request R2. Read request R6 is output from endpoint 55 to root complex 30 .

When the endpoint 55 outputs the read request R2, it determines that the number of read requests for which the transfer of read data has not been completed is the upper limit value Nmax. As a result, the endpoint 55 does not request the remaining read requests R3 and R4 issued from the DMAC 53 to the root complex 30 .

After that, at time t3 when the transfer of the read data D1 corresponding to the read request R1 is completed, the endpoint 55 determines that the number of read requests whose read data transfer has not been completed is less than the upper limit value Nmax. As a result, the endpoint 55 outputs the read request R3 issued by the DMAC 53 to the root complex 30 .

When the endpoint 55 outputs the read request R3, it determines that the number of read requests for which the transfer of read data has not been completed is the upper limit value Nmax. Therefore, the endpoint 55 does not request the remaining read request R4 issued from the DMAC 53 to the root complex 30 .

After that, at time t8 when the transfer of read data D5 corresponding to read request R5 is completed, the endpoint 55 determines that the number of read requests whose read data transfer has not been completed is less than the upper limit value Nmax. As a result, the endpoint 55 outputs the read request R4 issued from the DMAC 53 to the root complex 30. FIG.

As shown in FIG. 3, the change signal becomes active during the period T1 during which the high-priority task is scheduled to be executed. Therefore, even if the DMAC 53 receives a read instruction corresponding to the execution of a low-priority task in the period T1, the DMAC 53 can issue only the number of read requests equal to or less than the limit value N in succession. As a result, the DMAC 51 can issue a read request when receiving a read instruction corresponding to the execution of a high-priority task during the period T1. As a result, a delay in transferring read data corresponding to a high-priority task is suppressed.

§2 Concrete example <A. System configuration example>
FIG. 4 is a schematic diagram showing a configuration example of a control system including the control device 1 according to this embodiment. As shown in FIG. 4, the control system comprises a control device 1, one or more units 2, and a support device 3.

The unit 2 is equipment and devices to be controlled, and various devices (sensors, actuators, etc.) placed there.

The support device 3 creates a user program to be executed in the control device 1 and installs the user program in the control device 1 . A user program is a sequence program for controlling a controlled object, and includes an IO refresh program, a control operation program, a peripheral processing program, a communication program, and the like.

Further, the support device 3 analyzes the user program and generates schedule information for determining the period during which the change signal is active according to the priority of each task executed by the control device 1. The schedule information is set in the change signal output section 57 of the control device 1 . The schedule information indicates the start timing and end timing of the period during which the change signal is active.

<B. Configuration of support device>
FIG. 5 is a diagram schematically showing the configuration of the support device 3. As shown in FIG. As shown in FIG. 5 , the support device 3 includes a CPU 302 , a ROM 303 , a RAM 304 , an HDD 305 , a communication controller 307 and an I/O (Input/Output) interface 308 . Support device 3 further includes keyboard 309 and display 310 . Keyboard 309 accepts input including instructions to support device 3 from the user. Support device 3 may include other devices, such as a mouse, to accept the input. The display 310 includes an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) and displays a video or image according to a video signal or image signal output from the support device 3 . The support device 3 is provided with an R/W (reader/writer) device 306 for detachably mounting an external storage medium 301 and reading/writing programs and/or data from/to the mounted storage medium 301 .

The communication controller 307 controls communication between the support device 3 and external devices (including the control device 1) via the network. The communication controller 307 includes, for example, a NIC (Network Interface Card). I/O interface 308 controls the exchange of data between CPU 302 and keyboard 309 and display 310 .

The HDD 305 includes a system program 70 including an OS, a UPG generation program 71 for generating user programs 69, a UPG library 172 storing one or more generated user programs 69, and a scheduler 72.

The UPG generation program 71 operates according to user operations received from the keyboard 309, such as an editor that edits (generates) the user program 69, a compiler that compiles the edited user program 69, a builder that converts the user program 69 into an executable format, and the like. include. Note that the builder may also include a compilation function.

The scheduler 72 is a program that estimates a processing sequence when the user program 69 is executed by the control device 1 and generates schedule information. The scheduler 72 is a program that analyzes the user program 69 and estimates resource allocation such as usage time of the processor 10 and execution timing according to priorities set for a plurality of tasks defined by the user program 69 .

<C. Method of generating schedule information>
A method of generating schedule information will be described with reference to FIG. The user program 69 is created based on the information shown in (a) to (e) below.
(a) Control cycle (b) Model and number of units 2 connected to control device 1 (c) Contents of data transmitted to each unit 2 (d) Contents of data received from each unit 2 (e) Operation processing content.

The scheduler 72 determines the sequence of each process in the control cycle by analyzing the user program 69.

FIG. 6 is a diagram showing an example of a processing sequence of the control device 1. FIG. In the example shown in FIG. 6, in the control cycle TC, data transmission processing to each unit 2, arithmetic processing for controlling the controlled object, data reception processing from each unit 2, and other processing are performed in this order. executed. Other processing includes, for example, communication processing with a host device.

Based on (b) the model and number of units 2 connected to the control device 1 and (c) the content of data to be transmitted to each unit 2, the scheduler 72 schedules each unit 2 in the control cycle TC. A period T2 during which the data transmission process is scheduled to be executed is estimated.

The scheduler 72 estimates the period during which the execution of the arithmetic processing for controlling the controlled object is scheduled in the control cycle TC based on the above (e) information on the content of the arithmetic processing.

Based on (b) the model and number of units 2 connected to the control device 1 and (d) the amount of data to be transmitted to each unit 2, the scheduler 72 sends data to each unit 2 in the control cycle TC. Estimates a period T3 during which the reception process of is scheduled to be executed.

Furthermore, the scheduler 72 uses the priority set for each of the multiple tasks defined by the user program 69 and the processing sequence obtained by analyzing the user program 69 to generate schedule information. For example, the CPU 302 identifies from the processing sequence a period during which the task with the highest priority or a predetermined number of tasks with the highest priority are executed, and generates schedule information indicating the start timing and end timing of the identified period. . In the example shown in FIG. 6, schedule information indicating the start timing and end timing of a period T1 during which the data transmission process is scheduled to be executed, and the start timing and end timing of a period T2 during which the data reception process is scheduled to be executed. is generated.

The scheduler 72 sets the generated schedule information in the change signal output unit 57 of the control device 1 . Thereby, the change signal output unit 57 switches the change signal to active between the periods T2 and T3. Thus, the periods T2 and T3 in which the number of read requests that can be continuously issued by the DMAC are limited are predetermined based on the user program 69. FIG.

Further, the scheduler 72 enables the limiting function of the DMAC management unit used in executing the task with the lowest priority or the predetermined number of lower-priority tasks among the plurality of DMACs possessed by the control device 1. and disable the limiting function of the remaining DMAC management units.

When the power is turned on, the control device 1 activates the installed user program and executes the user program 69 . Furthermore, the control device 1 terminates the user program 69 when an abnormality occurs or for reasons such as maintenance of the controlled object.

FIG. 7 is a diagram showing an example of a period during which the change signal is activated. It is desirable that the read data corresponding to the execution of the task with high priority be transferred before other data. Therefore, as shown in FIG. 7, the scheduler 72 includes the period during which the change signal is activated within the period during which the user program 69 is executed to control the controlled object.

On the other hand, during the start-up period of the user program 69, the multiple pieces of read data required for start-up can be transferred in any order. Similarly, during the termination period of the user program 69, the plurality of read data required for termination may be transferred in any order. Therefore, as shown in FIG. 7, the scheduler 72 does not include the period during which the change signal is activated within the activation period and the termination period of the user program 69 .

<D. Examples of restrictions on read requests that can be issued in succession>
(D-1. Restriction example 1)
When a plurality of DMAC limit functions are enabled, the limit values of the plurality of DMACs may be the same or different from each other.

For example, when the DMAC 51 issues a read request according to the execution of the first task, the DMAC 53 issues the read request according to the execution of the second task, and the DMAC 52 issues the read request according to the execution of the third task. will be described as an example of setting the limit value. Note that the second task has a lower priority than the first task. The third task has a lower priority than the first task and a higher priority than the second task.

In this case, the limiting function of the DMACs 52 and 53 is enabled, and an active change signal is output during the period T1 during which the execution of the first task is scheduled. When the change signal is active, the management unit 53a limits the number of DMACs 53 that can continuously issue read requests to a first limit value. The management unit 52a limits the number of DMACs 52 that can issue read requests in succession to a second limit value when the change signal is active. The first limit value may be the same as the second limit value. Alternatively, the first limit value may be set smaller than the second limit value according to the priority of the second task and the third task. For example, the first limit value is set to "1" and the second limit value is set to "2".

(D-2. Restriction example 2)
The change signal output section 57 may output a plurality of change signals. In this case, the limit value may be different for each change signal for the DMAC with the limit function enabled.

FIG. 8 is a diagram showing another example of data transfer in this embodiment. FIG. 8 shows an example in which the upper limit value Nmax is 4 and the limit values for the first and second change signals are 1 and 2, respectively. However, the limiting functions of the management units 51a and 52a are disabled, and the limiting function of the DMAC 53 is enabled.

In FIG. 8, the horizontal axis indicates time. The first row shows the first modification signal. The second row shows the second modified signal. The third row shows a read request sent from the DMAC 51 to the endpoint 55 . The fourth row shows a read request sent from DMAC 52 to endpoint 55 . Level 5 shows a read request sent from the DMAC 53 to the endpoint 55 . Row 6 shows a read request transmitted from endpoint 55 to root complex 30 . Level 7 shows read data to be transferred.

The first change signal is generated so as to be active during the period T4 during which the high-priority task is scheduled to be executed. The second change signal is generated to be active during the period T5 during which the medium priority task is scheduled to be executed. Note that the period T4 and the period T5 may overlap each other. When both the period T4 and the period T5 are active, the number of read requests that can be issued consecutively in the DMAC with the limit function enabled corresponds to the first change signal and the second change signal, respectively. Limited to the lesser of the two limits.

FIG. 8 shows an example in which the DMAC 53 receives a read instruction corresponding to execution of a low-priority task by the processor 10 at time t11 in period T4. In the example shown in FIG. 8, it is necessary to issue three read requests R11 to R13 in response to the read instruction. However, during time period T1, the first modification signal is active. Therefore, the management unit 53a limits the number of read requests that can be continuously issued by the DMAC 53 to "1". Therefore, the DMAC 53 issues only the read request R11 and cannot issue the read requests R12 and R13 consecutively.

Assume that the DMAC 51 receives a read instruction corresponding to the execution of the high-priority task by the processor 10 at time t12 after time t11 within period T4. It is necessary to issue two read requests R21 and R22 according to the read instruction. Since the limiting function of the management unit 51a is invalid and the number of read requests for which the transfer of read data has not been completed is 1, which is less than the upper limit value Nmax (=4), the DMAC 51 continuously outputs the read requests R21 and R22. to be issued.

After that, at time t13 at the end of period T4, the first change signal switches to inactive. As a result, the DMAC 53 issues the remaining read request R12. Since the transfer of the read data D11 corresponding to the read request R11 is completed before time t13, the DMAC 53 can also issue the read request R13 following the read request R12.

Thus, the first change signal becomes active during the period T4 during which the high-priority task is scheduled to be executed. Therefore, even if the DMAC 53 receives a read instruction corresponding to execution of a low-priority task during the period T4, the DMAC 53 can issue only one read request R11. As a result, the DMAC 51 can issue the read requests R21 and R22 when receiving a read instruction corresponding to the execution of the high-priority task during the period T4. As a result, the transfer delay of the read data D21 and D22 corresponding to the high-priority task is suppressed.

Furthermore, FIG. 8 shows an example in which the DMAC 53 receives a read instruction corresponding to the execution of a low-priority task by the processor 10 at time t14 within the period T3. In the example shown in FIG. 8, it is necessary to issue three read requests R14 to R16 in response to the read instruction. However, in time period T5, the second modification signal is active. Therefore, the management unit 53a limits the number of read requests that can be continuously issued by the DMAC 53 to "2". Therefore, the DMAC 53 continuously issues the read requests R14 and R15 and cannot issue the read request R16.

At time t15 after time t14 in period T5, it is assumed that the DMAC 52 receives a read instruction according to the execution of the medium-priority task by the processor 10 . It is necessary to issue two read requests R31 and R32 according to the read instruction. Since the limiting function of the management unit 52a is invalid and the number of read requests for which the transfer of read data has not been completed is 2, which is less than the upper limit value Nmax (=4), the DMAC 52 continuously issues the read requests R31 and R32. to be issued.

After that, at time t16 at the end of period T5, the second change signal switches to inactive. As a result, the DMAC 53 issues the remaining read request R16. Since transfer of read data D14 corresponding to read request R14 is completed before time t16, DMAC 53 can issue read request R16 after time t16.

In this way, the second change signal becomes active during the period T3 during which the medium-priority task is scheduled to be executed. Therefore, even if the DMAC 53 receives a read instruction corresponding to execution of a low-priority task during the period T5, the DMAC 53 can issue only two read requests R14 and R15. As a result, the DMAC 52 can issue a read request when receiving a read instruction corresponding to the execution of a medium-priority task during the period T5. As a result, a delay in transferring read data corresponding to a medium-priority task is suppressed.

The limit value should be set according to the priority of the task. By reducing the limit value, the number of read requests associated with the execution of low-priority tasks is reduced, and the delay in read data transfer associated with the execution of the target task is suppressed. However, there is a possibility that the number of read requests waiting to be issued due to the execution of low-priority tasks will increase, so the transfer of read data that accompanies the execution of low-priority tasks will be delayed.

For example, as shown in FIG. 8, even if time T6 from time t11 to time t12 and time T7 from time t15 to time t16 are the same, read requests R11 to R13, R21, and R22 are handled. The time T8 required to transfer the read data D11-D13, D21 and D22 is longer than the time T9 required to transfer the read data D14-D16, D31 and D32 corresponding to the read requests R14-R16, R31 and R32.

In this way, the limit value also affects transfer efficiency. Therefore, the limit value of each DMAC is set in consideration of both transfer efficiency and task priority.

<E. Variation>
In the above description, the DMAC is provided with a management unit that limits the number of read requests issued in succession by the DMAC. However, the management unit may be provided in the arbitration circuit.

FIG. 9 is a diagram showing the configuration of a control device according to a modification. As shown in FIG. 9, the control device 1A differs from the control device 1 in that the data transfer circuit 50 is replaced with a data transfer circuit 50A. The data transfer circuit 50A is different from the data transfer circuit 50 in that it includes an arbitration circuit 64 instead of the arbitration circuit 54, and the DMACs 51-53 do not have management units 51a-53a, respectively. The change signal output unit 57 outputs a change signal to the arbitration circuit 64 .

The arbitration circuit 64 has the same function as the arbitration circuit 54. Further, the arbitration circuit 64 has a management section 64a. The management unit 64a manages the number of consecutively issued read requests for each of the DMACs 51-53. Specifically, the management unit 64a limits the number of consecutively issued read requests to the limit value for each of the DMACs 51 to 53 in response to the active change signal. Note that the management unit 64a can switch between enabling/disabling the function of limiting the number of consecutively issued read requests for each of the DMACs 51-53. The management unit 64a switches enable/disable of the restriction function for each of the DMACs 51 to 53 according to the setting by the support device 3. FIG.

§3 Supplementary Note As described above, the present embodiment includes the following disclosures.

(Configuration 1)
A control device (1, 1A),
a processor (10);
a memory (20);
a data transfer circuit (50, 50A),
The data transfer circuit (50, 50A)
a first request issuing unit (51) that issues a first read request to the memory (20) in accordance with execution of the first task by the processor (10);
a second request issuing unit (53) for issuing a second read request to the memory (10) in accordance with execution of the second task by the processor (10);
a management unit (53a to 53c, 64a) that manages the number of read requests that can be issued in succession,
the first task has a higher priority than the second task;
The management units (53a to 53c, 64a) control the number of second read requests that can be continuously issued by the second request issuing unit (53) during the first period during which the execution of the first task is scheduled. a control device (1, 1A) that limits the second period other than the first period in the second period.

(Configuration 2)
According to the configuration 1, the management unit (53a to 53c, 64a) limits the number of the second read requests that can be continuously issued by the second request issuing unit (53) to 1 in the first period. A control device (1, 1A) as described.

(Composition 3)
The processor (20) executes a user program (69) for controlling a controlled object,
The control device (1, 1A) according to configuration 1 or 2, wherein said first time period is predetermined based on said user program (69).

(Composition 4)
The processor (10) executes a user program (69) for controlling a controlled object,
The first period is included within the period during which the processor (10) executes the user program (69) to control the controlled object, and within the startup period and the termination period of the user program (69) A controller (1, 1A) according to configuration 1 or 2, not included.

(Composition 5)
The management units (53a to 53c, 64a) do not limit the number of the first read requests that can be issued continuously by the first request issuing unit (51) during the first period and the second period. 5. The control device according to any one of configurations 1 to 4.

(Composition 6)
The data transfer circuit (50, 50A) further includes a third request issuing unit (52) that issues a third read request to the memory in response to execution of a third task by the processor (10),
the third task has a lower priority than the first task;
The management units (53a to 53c, 64a) limit the number of the second read requests that can be continuously issued by the second request issuing unit (53) to a first value in the first period, and The control device (1, 1A) according to configuration 1, wherein the number of said third read requests that can be continuously issued by said third request issuing section (52) is limited to a second value in said first period.

(Composition 7)
the third task has a higher priority than the second task;
7. Control device (1, 1A) according to configuration 6, wherein said first value is less than said second value.

(Composition 8)
The data transfer circuit (50, 50A) further includes a third request issuing unit (52) that issues a third read request to the memory (20) in response to execution of a third task by the processor (10). including
the third task has a lower priority than the first task and a higher priority than the second task;
The management units (53a to 53c, 64a) set the number of the second read requests that can be continuously issued by the second request issuing unit (53) to a first value in the first period, and set to a second value in a third period during which execution of the third task is scheduled, and set to a third value in periods other than the first period and the third period;
Control device (1, lA) according to configuration 1, wherein said first value and said second value are less than said third value.

(Composition 9)
9. The controller (1, lA) of arrangement 8, wherein said first value is less than said second value.

(Configuration 10)
The data transfer circuit (50A) further includes an arbitration circuit (64) that arbitrates access to the memory (20),
The control device (1A) according to any one of Configurations 1 to 8, wherein the management section (64a) is included in the arbitration circuit (64).

(Composition 11)
A data transfer method in a control device (1, 1A) comprising a processor (10) and a memory (20),
issuing a first read request to the memory in response to execution of a first task by the processor (10);
issuing a second read request to the memory in response to execution of a second task by the processor (10);
managing the number of read requests that can be issued in succession;
the first task has a higher priority than the second task;
In the managing step, the number of the first read requests that can be continuously issued is set to be smaller in a first period during which execution of the first task is scheduled than in a second period other than the first period. A data transfer method, including steps to configure.

Although the embodiment of the present invention has been described, it should be considered that the embodiment disclosed this time is illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims, and is intended to include all changes within the meaning and range of equivalents to the claims.

1, 1A control device, 2 unit, 3 support device, 10 processor, 20 main memory, 30 root complex, 40, 56 clock section, 50, 50A data transfer circuit, 51a, 52a, 53a, 64a management section, 54, 64 Arbitration circuit, 55 endpoint, 57 change signal output unit, 58, 59 Phy chip, 60 memory I/F, 61, 62 port, 63 memory, 69 user program, 70 system program, 71 UPG generation program, 72 scheduler, 172 Library, 301 storage medium, 302 CPU, 303 ROM, 304 RAM, 306 R/W device, 307 communication controller, 308 I/O interface, 309 keyboard, 310 display.

Claims (11)

a controller,
a processor;
memory;
a data transfer circuit;
The data transfer circuit is
a first request issuing unit that issues a first read request to the memory in response to execution of the first task by the processor;
a second request issuing unit that issues a second read request to the memory in response to execution of the second task by the processor;
a management unit that manages the number of read requests that can be issued in succession,
the first task has a higher priority than the second task;
The managing unit determines the number of second read requests that can be continuously issued by the second request issuing unit during a first period during which the execution of the first task is scheduled, in a second period other than the first period. A controller that restricts to less than The control device according to claim 1, wherein the management unit limits the number of second read requests that can be issued continuously by the second request issuing unit to one during the first period. The processor executes a user program for controlling a controlled object,
3. The control device according to claim 1, wherein said first period is predetermined based on said user program. The processor executes a user program for controlling a controlled object,
3. The first period is included in a period during which the processor executes the user program to control the controlled object, and is not included in a startup period and a termination period of the user program. The control device according to . 5. The management unit according to any one of claims 1 to 4, wherein the management unit does not limit the number of the first read requests that can be issued continuously by the first request issuing unit during the first period and the second period. The control device according to . the data transfer circuit further includes a third request issuing unit that issues a third read request to the memory in response to execution of a third task by the processor;
the third task has a lower priority than the first task;
The management unit limits the number of second read requests that can be continuously issued by the second request issuing unit to a first value in the first period, and the third request issuing unit continuously issues the second read requests. 2. The controller of claim 1, wherein the number of possible third read requests is limited to a second value during the first time period. the third task has a higher priority than the second task;
7. The controller of claim 6, wherein said first value is less than said second value. the data transfer circuit further includes a third request issuing unit that issues a third read request to the memory in response to execution of a third task by the processor;
the third task has a lower priority than the first task and a higher priority than the second task;
The management unit sets the number of second read requests that can be continuously issued by the second request issuing unit to a first value in the first period, set to a second value in three periods, and set to a third value in periods other than the first period and the third period;
2. The controller of claim 1, wherein said first value and said second value are less than said third value. The control device according to claim 8, wherein said first value is smaller than said second value. the data transfer circuit further includes an arbitration circuit that arbitrates access to the memory;
The control device according to any one of claims 1 to 8, wherein said management unit is included in said arbitration circuit. A data transfer method in a control device comprising a processor and a memory,
issuing a first read request to the memory in response to execution of a first task by the processor;
issuing a second read request to the memory in response to execution of a second task by the processor;
managing the number of read requests that can be issued in succession;
the first task has a higher priority than the second task;
In the managing step, the number of the first read requests that can be continuously issued is set to be smaller in a first period during which execution of the first task is scheduled than in a second period other than the first period. A data transfer method, including steps to configure.

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