WO2022184131A1 - Circuit board assembly and manufacturing method therefor, and electronic device - Google Patents

Abstract

The present application provides a circuit board assembly and a manufacturing method therefor, and an electronic device. The circuit board assembly comprises a circuit board, an adapter layer, and a package chip; the adapter layer comprises M conductive paths each having a first end and a second end, the M conductive paths are arranged at intervals, the first ends of all the conductive paths are in a same direction, and the second ends of all the conductive paths are in a same direction; each of the first ends is electrically connected to the circuit board, and each of the second ends is electrically connected to the package chip; and the area of an arrangement area of the M second ends is less than that of an arrangement area of the M first ends, wherein M is an integer greater than or equal to 2. The circuit board assembly provided in the present application is not easy to warp during manufacturing.

Description

Circuit board assembly, method of making the same, and electronic device

This application claims the priority of the Chinese patent application with the application number of 202110233877.5 and the application title of "circuit board assembly and its manufacturing method and electronic equipment", which was filed with the China Patent Office on March 3, 2021, the entire contents of which are incorporated by reference in in this application.

technical field

The present application relates to the field of chip board level interconnection, and in particular, to a circuit board assembly, a manufacturing method thereof, and an electronic device.

Background technique

Electronic equipment such as communication equipment includes circuit board assemblies. The package substrate carrying the chip in the circuit board assembly is usually fixed to the circuit board by a surface mount process. However, the size of the package substrate in the prior art is relatively large, and the larger size of the package substrate is prone to warping in the surface mount process engineering, which has a large arc surface impact on the surface mount process and reduces the surface mount quality of workmanship.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a circuit board assembly, an electronic device including the circuit board assembly, and a manufacturing method of the circuit board assembly, aiming to reduce the risk of warpage of the circuit board assembly.

In a first aspect, the present application provides a circuit board assembly. The circuit board assembly includes a circuit board, a transfer layer and a packaged chip, the transfer layer includes M conductive paths with first ends and second ends, the M conductive paths are arranged at intervals, and the first conductive paths of all the conductive paths are arranged at intervals. The ends are in the same direction, the second ends of all the conductive paths are in the same direction, each of the first ends is electrically connected to the circuit board, and each of the second ends is electrically connected to the packaged chip; M number of the second ends The area of the arrangement regions of the ends is smaller than the area of the arrangement regions of the M first ends, where M is an integer greater than or equal to 2.

It can be understood that, the M first ends can be arranged in various forms, for example, the M first ends can be arranged in an array form or a non-array form. The arrangement forms of the M second ends are various, for example, the M second ends may be arranged in an array form or a non-array form.

It can be understood that the circuit board assembly includes a first reference plane and a second reference plane, the end surfaces of the M first ends are all located on the first reference plane, and the end surfaces of the M second ends are all located on the second reference plane. The arrangement area of the M first ends is, on the first reference plane, an area surrounded by several first ends located at the outermost periphery among the M first ends. The arrangement area of the M second ends is, on the second reference plane, an area surrounded by several second ends located at the outermost periphery among the M second ends. The explanation of the "arrangement area" that appears below is the same as the above description, and will not be repeated. The packaged chip of the circuit board assembly in the related art is directly arranged on the circuit board. During the process of packaging, welding, etc., it will be affected by materials, processing technology, etc., and thermal and mechanical stress will remain, resulting in warpage or solder joint cracking. question. The circuit board assembly in this embodiment realizes the transfer between the package chip and the circuit board through the transfer layer. The first end of the transfer layer is electrically connected to the circuit board, the second end is electrically connected to the package chip, and M second ends are electrically connected to the circuit board. The area of the arrangement area of the ends is smaller than the area of the arrangement area of the M first ends. It can be understood that the transition layer is a fan-in type transition layer, that is, the fan-in type transition layer realizes the fan-in from the circuit board to the packaged chip. Compared with the packaged chip that is directly fixed to the circuit board, fixed through the transition layer. The size of the packaged chip on the circuit board can be made smaller, for example, the size of the packaged chip is reduced from 100*100mm to 80*80mm, so that the circuit board components will warp and crack the solder joints during packaging, welding and other processing. Less risk and improved reliability of circuit board assemblies. At the same time, the reduced size of the packaged chip can increase the layout area of other components on the circuit board, or can reduce the size of the circuit board, which is beneficial to the miniaturization of circuit board components.

In a possible implementation manner, the area of the arrangement area of the second end is less than or equal to 80% of the area of the arrangement area of the first end, that is, the size of the packaged chip can be reduced to 80% or Smaller, when the size of the packaged chip is reduced to 80% or less, the risk of warpage and solder joint cracking of the circuit board assembly can be effectively reduced, and the reliability of the circuit board assembly can be improved. Of course, in other embodiments, the area of the arrangement regions of the M second ends may also be smaller than the area of the arrangement regions of the M first ends by other values.

In a possible implementation manner, the thermal expansion coefficient of the transition layer is smaller than the thermal expansion coefficient of the circuit board and greater than the thermal expansion coefficient of the packaged chip. The transition layer buffers the thermal expansion coefficient difference between the circuit board and the packaged chip, which can effectively reduce the risk of mismatch between the two, reduce the risk of warping and cracking of the circuit board components, and improve the reliability of the circuit board components.

In a possible implementation manner, the transition layer further includes a buffer function layer, the conductive path runs through the buffer function layer, and the first end and the second end respectively expose two of the buffer function layer. opposite surfaces. On the one hand, the buffer function layer is used to fix the conductive path, and on the other hand, the buffer function layer can buffer heat and mechanical stress when the packaged chip is fixed on the transfer layer, thereby reducing the risk of warpage and cracking of the solder joints of the circuit board assembly.

In a possible implementation manner, the buffer functional layer adopts an insulating material. Among them, the insulating material can be various, such as polypropylene, polyimide and other dielectric materials.

In a possible implementation manner, the elastic modulus of the buffer functional layer is greater than or equal to 200 MPa, which can effectively buffer thermal and mechanical stress, and reduce the risk of warping and cracking of solder joints in the circuit board assembly.

In a possible implementation manner, the packaged chip further includes a plurality of solder balls, and each of the solder balls is electrically connected to the second terminal in a one-to-one correspondence.

In a possible implementation manner, the circuit board assembly further includes a conductive layer, the conductive layer is located between the transfer layer and the packaged chip, the conductive layer includes a buffer layer and a The conductive medium of the buffer layer is electrically connected between the second end and the package chip. In this embodiment, the packaged chip is connected with the transition layer through the conductive layer, and multiple components in the circuit board assembly are fixed into a package. Reduce the risk of warping and cracked solder joints in circuit board assemblies.

In a possible implementation manner, the circuit board assembly further includes a plurality of first pads placed on the circuit board and a plurality of second pads placed on the packaged chip, and the The first end is connected to the corresponding first pad, and the second end of the conductive path is connected to the corresponding second pad.

In a possible implementation manner, the packaged chip includes a chip and a package substrate, the chip is mounted on the package substrate, and the package substrate includes a conductive surface facing away from the chip, the conductive surface is connected to the package substrate. The second end is electrically connected.

In a second aspect, the present application also provides a method for manufacturing a circuit board assembly. The manufacturing method includes:

A transfer layer is formed on the mounting surface of the circuit board, wherein the transfer layer includes M conductive paths with a first end and a second end, the M is an integer greater than or equal to 2, and the M conductive paths of the second ends The area of the arrangement area is smaller than the area of the arrangement area of the M first ends, and the first ends are electrically connected to the circuit board;

The packaged chip is fixed to the side of the transfer layer facing away from the circuit board and electrically connected to the second end.

In the manufacturing method provided in this embodiment, a transfer layer is formed between the circuit board and the package chip, and the area of the M second ends that are electrically connected between the transfer layer and the circuit board is smaller than the area where the transfer layer is electrically connected to the package chip. The area of the arrangement area of the M first ends, it can be understood that the transition layer is a fan-in type transition layer, that is, the fan-in type transition layer realizes the fan-in from the circuit board to the packaged chip. The chip is directly fixed on the circuit board, and the size of the packaged chip fixed on the circuit board through the transfer layer can be made smaller, so that the risk of warpage and solder joint cracking of the circuit board assembly during packaging, welding and other processing is smaller. , improve the reliability of circuit board components. At the same time, the reduced size of the packaged chip can increase the layout area of other components on the circuit board, or can reduce the size of the circuit board, which is beneficial to the miniaturization of circuit board components.

In a possible implementation manner, the method for forming the transition layer includes: forming a first buffer base layer on the mounting surface of the circuit board; forming a first opening exposing the circuit board on the first buffer base layer; A conductive path having a first end and a second end is formed in the first opening. On the one hand, the buffer function layer is used to fix the conductive path, and on the other hand, the buffer function layer can buffer heat and mechanical stress when the packaged chip is fixed on the transfer layer, thereby reducing the risk of warpage and cracking of the solder joints of the circuit board assembly.

In a possible implementation manner, the elastic modulus of the first buffer base layer is greater than or equal to 200 MPa, which can effectively buffer thermal and mechanical stress, and reduce the risk of warping and cracking of solder joints of the circuit board assembly.

In a possible implementation manner, before the package chip is electrically connected to the second end, the manufacturing method further includes: forming a connection with the second end on the side of the transition layer facing away from the circuit board. A conductive layer connected to the terminal; the package chip is electrically connected to the second end including the package chip and the conductive layer being bonded and fixed. In this embodiment, the packaged chip is connected with the transition layer through the conductive layer, and multiple components in the circuit board assembly are fixed into a package. Reduce the risk of warping and cracked solder joints in circuit board assemblies.

In a possible implementation manner, the method for forming the conductive layer includes: forming a second buffer base layer on the side of the transition layer facing away from the circuit board; A second opening at two ends; a conductive medium conductively connected to the second end is formed in the second opening; the bonding and fixing of the packaged chip and the conductive layer includes the packaged chip and the conductive layer The conductive medium is fixed by bonding.

In a possible implementation manner, the area of the arrangement area of the second end is less than or equal to 80% of the area of the arrangement area of the first end, that is, the size of the packaged chip can be reduced to 80% or Smaller, when the size of the packaged chip is reduced to 80% or less, the risk of warpage and solder joint cracking of the circuit board assembly can be effectively reduced, and the reliability of the circuit board assembly can be improved. Of course, in other embodiments, the area of the arrangement regions of the M second ends may also be smaller than the area of the arrangement regions of the M first ends by other values.

In a possible implementation manner, the thermal expansion coefficient of the transition layer is smaller than the thermal expansion coefficient of the circuit board and greater than the thermal expansion coefficient of the packaged chip. The transition layer buffers the thermal expansion coefficient difference between the circuit board and the packaged chip, which can effectively reduce the risk of mismatch between the two, reduce the risk of warping and cracking of the circuit board components, and improve the reliability of the circuit board components.

In a third aspect, the present application also provides a method for manufacturing a circuit board assembly. The manufacturing method includes:

A transfer layer is formed on the packaged chip, wherein the transfer layer includes M conductive paths with a first end and a second end, the M is an integer greater than or equal to 2, and the arrangement of the M second ends The area of the area is smaller than the area of the arrangement area of the M first ends, and the second ends are electrically connected to the package chip;

The side of the transition layer facing away from the packaged chip is fixed to the circuit board, and the first end is electrically connected to the circuit board.

In the manufacturing method provided in this embodiment, a transfer layer is formed between the circuit board and the package chip, and the area of the M second ends that are electrically connected between the transfer layer and the circuit board is smaller than the area where the transfer layer is electrically connected to the package chip. The area of the arrangement area of the M first ends, it can be understood that the transition layer is a fan-in type transition layer, that is, the fan-in type transition layer realizes the fan-in from the circuit board to the packaged chip. The chip is directly fixed on the circuit board, and the size of the packaged chip fixed on the circuit board through the transfer layer can be made smaller, so that the risk of warpage and solder joint cracking of the circuit board assembly during packaging, welding and other processing is smaller. , improve the reliability of circuit board components. At the same time, the reduced size of the packaged chip can increase the layout area of other components on the circuit board, or can reduce the size of the circuit board, which is beneficial to the miniaturization of circuit board components.

In a fourth aspect, the present application further provides an electronic device. The electronic device includes the above-mentioned circuit board assembly. The electronic device is, for example, a communication device or an electronic device with a circuit board assembly related to information and communication technology.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the accompanying drawings that need to be used in the embodiments of the present application or the background technology will be described below.

1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

2 is a schematic structural diagram of a circuit board assembly of the electronic device shown in FIG. 1;

FIG. 3 is a schematic diagram of the comparison between the circuit board assembly shown in FIG. 2 and the circuit board assembly of the related art;

FIG. 4 is a schematic diagram of the warpage risk of the two circuit board assemblies shown in FIG. 3;

5 is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2;

FIG. 6 is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2;

FIG. 7 is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2;

FIG. 8 is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 7;

FIG. 9 is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2;

10 is a schematic flowchart of a method for manufacturing a circuit board assembly provided by an embodiment of the present application;

Fig. 11 is a specific process schematic diagram of the manufacturing method shown in Fig. 10;

12 is a schematic flowchart of another method for manufacturing a circuit board assembly provided by an embodiment of the present application;

Fig. 13 is the concrete process schematic diagram of the manufacturing method shown in Fig. 12;

14 is a schematic flowchart of another method for manufacturing a circuit board assembly provided by an embodiment of the present application;

Fig. 15 is a specific process schematic diagram of the manufacturing method shown in Fig. 14;

16 is a schematic flowchart of another method for manufacturing a circuit board assembly provided by an embodiment of the present application;

Fig. 17 is the specific process schematic diagram of the manufacturing method shown in Fig. 16;

FIG. 18 is a specific process schematic diagram of another embodiment of the circuit board assembly shown in FIG. 17;

FIG. 19 is a specific process schematic diagram of another embodiment of the circuit board assembly shown in FIG. 17 .

Detailed ways

The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

In the description of the embodiments of the present application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" may be detachable connection, or It is a non-removable connection; it can be a direct connection or an indirect connection through an intermediate medium. Wherein, "fixed connection" refers to connection with each other and the relative positional relationship after connection remains unchanged. Orientation terms mentioned in the embodiments of this application, such as "upper", "bottom", "inside", "outside", etc., only refer to the directions of the drawings. Therefore, the orientation terms used are for better, To clearly describe and understand the embodiments of the present application, rather than indicating or implying that the indicated devices or elements must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as a limitation on the embodiments of the present application. "Plurality" means at least two.

For the convenience of understanding, the technical terms involved in this application are explained and described below.

Coefficient of thermal expansion (CTE), the relative change in length or volume of an object when the temperature increases, is the phenomenon of expansion and contraction of an object due to temperature changes.

Fan-in, wafer-level packaging is mainly divided into two types: fan-in and fan-out. Fan-in can combine multiple logic devices, analog devices and memory. The chip is integrated into the circuit board, which can reduce the overall package area.

It should be understood that the specific embodiments described herein are only used to explain the related invention, but not to limit the invention. In addition, it should be noted that, for the convenience of description, only the parts related to the invention are shown in the drawings.

The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

Please refer to FIG. 1 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

The embodiment of the present application provides an electronic device 100. The electronic device 100 includes a casing 10 and a circuit board assembly 20. The circuit board assembly 20 is arranged inside the casing 10. The circuit board assembly 20 can be understood as having electronic components such as chips and circuit boards. Stacked circuit board assemblies. The circuit board assembly 20 is used to implement functions such as processing, storage, control, and operation of the electronic device 100 . The electronic device 100 may be various types of electronic devices having circuit board assemblies 20 , such as communication devices, electronic devices related to information and communication technology, mobile phones, tablets, computers, and other types of network devices.

Please refer to FIG. 2 , which is a schematic structural diagram of the circuit board assembly 20 of the electronic device 100 shown in FIG. 1 .

The circuit board assembly 20 includes a circuit board 21 , a transfer layer 22 and a packaged chip 23 . The transfer layer 22 is arranged on the mounting surface 211 of the circuit board 21 , and the package chip 23 is arranged on the side of the transfer layer 22 that faces away from the circuit board 21 , that is, the transfer layer 22 is connected between the circuit board 21 and the package chip 23 . between. The transition layer 22 includes M conductive paths 221, and the conductive paths 221 include a first end 221a, a middle section 221b and a second end 221c which are connected in sequence. The M conductive paths 221 are arranged at intervals, and the first ends 221a of all the conductive paths 221 face the same direction, and the second ends 221c of all the conductive paths 221 face the same direction. Each first end 221a is electrically connected to the circuit board 21, and each The two terminals 221c are electrically connected to the packaged chip 23 . The area of the arrangement area of the M second ends 221c is smaller than the area of the arrangement area of the M first ends 221a, where M is an integer greater than or equal to 2.

It can be understood that, the M first ends 221a can be arranged in various forms, for example, the M first ends 221a can be arranged in an array form or a non-array form. The arrangement forms of the M second ends 221c are various, for example, the M second ends 221c may be arranged in an array form or a non-array form.

It can be understood that the circuit board assembly 20 includes a first reference plane and a second reference plane, the end faces of the M first ends 221a are all located on the first reference plane, and the end faces of the M second ends 221c are all located on the second reference plane. The arrangement area of the M first ends 221a is, on the first reference plane, an area surrounded by several first ends 221a located at the outermost periphery among the M first ends 221a. The arrangement area of the M second ends 221c is, on the second reference plane, an area surrounded by several second ends 221c located at the outermost periphery among the M second ends 221c. The "arrangement area" that appears below is the same as the above explanation, and will not be repeated.

Please refer to FIG. 3 and FIG. 4 in conjunction. FIG. 3 is a schematic diagram of a comparison between the circuit board assembly shown in FIG. 2 and the circuit board assembly of the related art. FIG. 4 is a schematic diagram of the warpage risk of the two circuit board assemblies shown in FIG. 3 . FIG. 4 only represents a schematic diagram of the warping effect of the two circuit board assemblies, not the actual structure of the two circuit board assemblies.

The packaged chip 33 of the circuit board assembly 30 in the related art is directly disposed on the circuit board 31. During the process of packaging and welding, it will be affected by materials, processing technology, etc., and thermal and mechanical stress will remain, resulting in the occurrence of warpage or welding. point cracking problem. The circuit board assembly 20 in this embodiment realizes the transfer between the package chip 23 and the circuit board 21 through the transfer layer 22. The first end 221a of the transfer layer 22 is electrically connected to the circuit board 21, and the second end 221c is connected to the package. The chips 23 are electrically connected, and the area of the arrangement area of the M second ends 221c is smaller than the area of the arrangement area of the M first ends 221a. It can be understood that the transition layer 22 is a fan-in type transition layer, that is, the fan-in type transition layer 22 realizes the fan-in from the circuit board 21 to the package chip 23 , compared to the package chip 33 that is directly fixed to the circuit board 31 . , the size of the packaged chip 23 fixed on the circuit board 21 through the transition layer 22 can be made smaller, for example, the size of the packaged chip 23 is reduced from 100*100mm to 80*80mm, so that the circuit board assembly 20 is packaged, welded, etc. There is less risk of warping and cracking of solder joints during processing, and the reliability of the circuit board assembly 20 is improved. At the same time, the reduced size of the packaged chip 23 can increase the layout area of other components on the circuit board 21 , or can reduce the size of the circuit board 21 , which is beneficial to the miniaturization of the circuit board assembly 20 .

It can be understood that, as shown in FIG. 2 , the circuit board 21 includes a plurality of first pads 212 , and the plurality of first pads 212 are arranged on the mounting surface 211 of the circuit board 21 . The surface of the surface 211 may also be embedded in the mounting surface 211 . The plurality of first pads 212 are used for electrical connection with the corresponding first ends 221 a to realize the electrical connection between the circuit board 21 and the transition layer 22 . The packaged chip 23 also includes a plurality of second bonding pads 235 , and the plurality of second bonding pads 235 are used to connect with the corresponding second ends 221 c to realize the electrical connection between the packaged chip 23 and the transfer layer 22 .

Although the spacing between the plurality of second pads 235 of the packaged chip 23 can be made smaller, so that the packaged chip 23 can be made smaller, the spacing between the plurality of first bonding pads 212 on the circuit board 21 cannot be made smaller. As small as the spacing between the plurality of second pads 235 of the packaged chip 23 . Therefore, in the present application, by arranging the transfer layer 22 between the circuit board 21 and the packaged chip 23 to be transferred between the two, it is possible to realize the stacking of the packaged chip 23 and the circuit board 21 with a smaller size, for example, a plurality of second The spacing between the pads 235 is reduced from 1.0 mm to 0.8 mm, which reduces the risk of warping and cracking of the solder joints of the circuit board assembly 20 and improves the reliability of the circuit board assembly 20 .

In this embodiment, the thermal expansion coefficient of the transition layer 22 is smaller than the thermal expansion coefficient of the circuit board 21 and greater than the thermal expansion coefficient of the package chip 23 . It can be understood that the difference between the thermal expansion coefficient of the circuit board 21 and the thermal expansion coefficient of the packaged chip 23 is relatively large. For example, the thermal expansion coefficient of the circuit board 21 is about 20 ppm, and the thermal expansion coefficient of the packaged chip 23 is between 10 ppm and 15 ppm.

In this case, a transfer layer 22 with a thermal expansion coefficient located therebetween is disposed between the circuit board 21 and the package chip 23, and the thermal expansion coefficient of the transfer layer 22 is between 15 ppm and 20 ppm. Since the thermal expansion coefficient of the transfer layer 22 is not much different from the thermal expansion coefficient of the circuit board 21 , the thermal expansion coefficient of the transfer layer 22 and the thermal expansion coefficient of the packaged chip 23 are not much different. The transfer layer 22 buffers the circuit board 21 and the packaged chip. The difference in thermal expansion coefficient between 23 can effectively reduce the risk of mismatch between the transition layer 22 and the circuit board 21 and the packaged chip 23, that is, reduce the risk of mismatch between the circuit board 21 and the packaged chip 23, and reduce the circuit board assembly. The risk of warping and cracking of the solder joints 20 occurs, and the reliability of the circuit board assembly 20 is improved.

As shown in FIG. 2 , the transition layer 22 further includes a buffer function layer 222 , the conductive path 221 runs through the buffer function layer 222 , the middle section 221 b is located in the buffer function layer 222 , and the first end 221 a and the second end 221 c expose the buffer function layer 222 respectively. opposite surfaces. Both the first reference plane and the second reference plane are parallel to two opposite surfaces of the buffer function layer 222 .

In this embodiment, the buffer function layer 222 is used to fix the conductive path 221 on the one hand, and on the other hand, the buffer function layer 222 can also buffer heat and mechanical stress when the package chip 23 is fixed on the transition layer 22 , thereby reducing the occurrence of the circuit board assembly 20 . Risk of warping and cracking of solder joints.

Specifically, the buffer function layer 222 includes a first surface and a second surface that are opposite to each other. The plurality of first ends 221a are arranged on the first surface, and the plurality of second ends 221c are arranged on the second surface. The plurality of first ends 221a may be embedded in the first surface, or may be disposed on the first surface. The plurality of second ends 221c can be embedded in the second surface, or can be disposed on the second surface.

In this embodiment, the buffer function layer 222 is made of insulating materials, such as polypropylene (Polypropylene, PP), polyimide (Polyimide, PI) and other dielectric materials. The buffer function layer 222 has low thermal expansion coefficient and high elasticity, its thermal expansion coefficient is less than or equal to 15ppm, and its elastic modulus is greater than or equal to 200MPa. In some processes of the manufacturing stacking process, the buffer function layer 222 can effectively buffer thermal and mechanical stress, reduce circuit The board assembly 20 is at risk of warping and solder joint cracking.

Of course, in other embodiments, the thermal expansion coefficient and elasticity of the buffer function layer 222 are not limited to the above description, as long as the buffer function layer 222 can reduce the risk of warpage and solder joint cracking of the circuit board assembly 20 .

The conductive path 221 is formed of a conductive material, and the conductive material may be one or more of copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide and tungsten carbide. The materials of the first end 221a, the middle section 221b and the second end 221c in the conductive path 221 may be the same or different.

In this embodiment, the area of the arrangement area of the M second ends 221c is less than or equal to 80% of the area of the arrangement area of the M first ends 221a, that is, the size of the packaged chip 23 can be reduced to 80% or smaller, when the size of the packaged chip 23 is reduced to 80% or smaller, the risk of warpage and solder joint cracking of the circuit board assembly 20 can be effectively reduced, and the reliability of the circuit board assembly 20 can be improved. Of course, in other embodiments, the area of the arrangement area of the M second ends 221c may also be smaller than the area of the arrangement area of the M first ends 221a by other values.

In some embodiments, the packaged chip may be a single chip, or may be a chip structure formed by integrating multiple chips on a package substrate. When the packaged chip is a single chip, the single chip is electrically connected to the second terminal. When the packaged chip is a chip structure formed by integrating multiple chips and a package substrate, the package substrate is electrically connected to the second end to realize electrical connection between the multiple chips and the fan-in via layer 22 .

In this embodiment, as shown in FIG. 2 , the packaged chip 23 is a chip structure formed by integrating a plurality of chips on a package substrate. The packaged chip 23 includes a chip 231, a chip transfer layer 232, a package substrate 233 and solder balls 234. The chip 231 is mounted on the package substrate 233 through the chip transfer layer 232 , that is, the package substrate 233 , the chip transfer layer 232 and the chip 231 are stacked in sequence. The number of chips 231 may be one or more. Other electronic components may also be arranged on the package substrate 233 . The package substrate 233 includes a conductive surface 2331 facing away from the chip 231 , the second pad 235 is provided on the conductive surface 2331 , and the solder balls 234 are provided on the conductive surface 2331 of the package substrate 233 and are conductively connected to the second pad 235 . In order to be electrically connected to the second end 221c, that is, specifically, the number of solder balls 34 is multiple, and the plurality of solder balls 234 are electrically connected to the second end 221c in one-to-one correspondence, so that the package substrate 233 and the transition layer are realized. 22 electrical connections between.

Of course, in other embodiments, the packaged chip may further include a chip, a package substrate and a solder ball. That is to say, a chip transfer layer may not be provided between the chip and the package substrate. Alternatively, in other embodiments, the packaged chip may also be connected to the second end through other connection structures other than solder balls.

In this embodiment, since the size of the packaged chip 23 becomes smaller, the size of the solder balls 234 of the packaged chip 23 is also reduced accordingly. distance between circuit boards 21 . In this embodiment, the distance between the packaged chip 23 and the circuit board 21 is less than or equal to 300 mm, which effectively reduces the transmission path between the chip 231 and the circuit board 21 , reduces link loss, and improves signal quality.

Please refer to FIG. 5 , which is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2 .

In this embodiment, the circuit board assembly 20 includes a circuit board 21 , a transfer layer 22 and a package chip 23 . The packaged chip 23 includes a chip 231 , a package substrate 233 and a chip transfer layer 232 , and the chip 231 is fixed on the package substrate 233 through the chip transfer layer 232 . The first end 221 a of the fan-in transition layer 22 is electrically connected to the corresponding first pad 212 of the circuit board 21 through solder balls, and the second end 221 c of the fan-in transition layer 22 is connected to the second pad 235 of the package substrate 233 . electrical connection.

Please refer to FIG. 6 , which is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2 .

In this embodiment, the circuit board assembly 20 includes a circuit board 21 , a transfer layer 22 and a package chip 23 . The packaged chip 23 includes a chip 231 , a package substrate 233 and a chip transfer layer 232 , and the chip 231 is fixed on the package substrate 233 through the chip transfer layer 232 . The first end 221 a of the fan-in transition layer 22 is electrically connected to the corresponding first pad 212 of the circuit board 21 , and the second end 221 c of the fan-in transition layer 22 is electrically connected to the second pad 235 of the package substrate 233 . The first end 221a may be connected and fixed to the first pad 212 by bonding, eutectic, etc., and the second end 211c may be connected and fixed to the second pad 235 by bonding, eutectic, or the like.

In other embodiments, the circuit board assembly may further include two transfer layers, for example, one transfer layer is formed on the circuit board, one transfer layer is formed on the packaged chip, and the two transfer layers are formed by solder balls or conductors. The connection layer realizes the electrical connection. Alternatively, the circuit board assembly may also include multiple interposer layers.

Please refer to FIG. 7 , which is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2 .

This embodiment is substantially the same as the embodiment shown in FIG. 2 , except that the circuit board assembly 20 in this embodiment includes a conductive layer 24 , and the conductive layer 24 replaces the solder balls to realize the connection between the package substrate 233 and the second end 221 c electrical connection. Specifically, the conductive layer 24 is located between the transfer layer 22 and the package chip 23 , and the conductive layer 24 includes a buffer layer 241 and a conductive medium 242 embedded in the buffer layer 241 , and the conductive medium 242 is electrically connected to the second end 221c and between the second pads 235 of the packaged chip 23 . In this embodiment, the package chip 23 is connected with the transition layer 22 through the conductive layer 24, and the multiple components in the circuit board assembly 20 are fixed into a package. Both are enhanced, effectively reducing the risk of warpage and solder joint cracking of the circuit board assembly 20 .

Specifically, the buffer layer 241 adopts an insulating material, such as a dielectric material such as polypropylene (Polypropylene, PP), polyimide (Polyimide, PI). The buffer layer 241 can be cured at room temperature or high temperature or UV after liquid coating, or it can be laminated with a film material. The buffer layer 241 has low thermal expansion coefficient and high elasticity, its thermal expansion coefficient is less than or equal to 15ppm, and the elastic modulus is greater than or equal to 200MPa. In some processes of manufacturing the circuit board assembly 20, the buffer layer 241 can effectively buffer thermal and mechanical stress, reduce The circuit board assembly 20 is at risk of warping and solder joint cracking. In this embodiment, the material of the buffer layer 241 may be the same as or different from that of the buffer function layer 222 .

The conductive medium 242 is made of pure metal or metal mixture materials including but limited to copper, silver, tin, or a mixture of metals and non-metals. The shape of the conductive medium 242 may be spherical, columnar, needle-like, cone-like, or the like. The size of the conductive medium 242 in this embodiment is smaller than the size of the solder balls 234 shown in FIG. 2 , which can shorten the link length between the package chip 23 and the circuit board 21 to a certain extent, improve the signal quality, and also This reduces the risk of warpage and solder joint cracking of the circuit board assembly 20 .

Please refer to FIG. 8 , which is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 7 .

This embodiment is substantially the same as the embodiment shown in FIG. 7 , except that the conductive layer 24 in this embodiment is connected between the transition layer 22 and the circuit board 21 , and the conductive medium 242 of the conductive layer 24 is electrically connected to the circuit board 21 . between the first pad 212 and the first end 221a. The packaged chip 23 is disposed on the side of the transfer layer 22 facing away from the conductor layer 24 , and the second pad 235 of the packaged chip 23 is electrically connected to the second end 221 c of the transfer layer 22 .

Please refer to FIG. 9 , which is a schematic structural diagram of another embodiment of the circuit board assembly shown in FIG. 2 .

This embodiment is substantially the same as the embodiment shown in FIG. 8 , the difference is that the electrical connection between the circuit board 21 and the package chip 23 is achieved through the conductive layer 24 in this embodiment, that is, the circuit in this embodiment The board assembly 20 does not include a transfer layer, and the conductive layer 24 replaces the traditional solder balls to realize the electrical connection between the circuit board 21 and the packaged chip 23 . In this embodiment, the size of the conductive medium 242 in the conductive layer 24 is smaller than that of the solder ball, which can shorten the link between the package chip 23 and the circuit board 21 and improve the signal quality. And the buffer layer 241 of the conductive layer 24 has a low thermal expansion coefficient and high elasticity, its thermal expansion coefficient is less than or equal to 15ppm, and its elastic modulus is greater than or equal to 200MPa. In some processes of manufacturing the circuit board assembly 20 The buffer layer 241 can effectively buffer Thermal, mechanical stress, reliability and stress are all enhanced, effectively reducing the risk of warpage and solder joint cracking of the circuit board assembly 20 .

Please refer to FIG. 10 . FIG. 10 is a schematic flowchart of a method for manufacturing a circuit board assembly provided by an embodiment of the present application. The manufacturing method is used to manufacture the circuit board assembly shown in FIG. 2 . As shown in FIG. 10 , the manufacturing method of the circuit board assembly includes the following S110 to S120 .

S110 : forming a transition layer 22 on the mounting surface 211 of the circuit board 21 .

Specifically, please refer to FIG. 11 . First, a circuit board 21 is fabricated. Specifically, the circuit board 21 may be formed by processes such as pressing, drilling, electroplating, patterning, solder resist, and surface treatment. The circuit board 21 includes a mounting surface 211 , and the plurality of first pads 212 of the circuit board 21 are exposed from the mounting surface 211 . Then, a transition layer 22 is formed on the mounting surface 211 of the circuit board 21 . Specifically, forming the transition layer 22 on the mounting surface 211 of the circuit board 21 can be implemented in two ways.

In one embodiment, the transition layer 22 is directly formed on the mounting surface 211 of the circuit board 21 .

Specifically, firstly, a press-fitted first buffer base layer is formed on the mounting surface 211 of the circuit board 21 , wherein the first buffer base layer can be formed by pressing or coating. Next, a first sub-opening (not shown) exposing the circuit board 21 is formed on the first buffer base layer by laser or mechanical drilling. The first sub-opening has M, where M is an integer greater than or equal to 2, and a plurality of first The sub-openings expose a plurality of first pads 212 of the circuit board 21 in a one-to-one correspondence, and M first ends 221a are formed in the first sub-openings by methods such as chemical copper/electroplating copper, and the plurality of first ends 221a correspond to the corresponding The first pads 212 of the circuit board 21 are electrically connected.

Next, the above process is repeated to form another first buffer base layer on the side of the first end 221a facing away from the circuit board 21, and M first sub-openings are formed in the first buffer base layer, and the first sub-openings expose a plurality of first sub-openings. end 221a, and then a middle section 221b electrically connected to the first end 221a is formed in the first sub-opening.

Next, the above process is repeated again to form another first buffer base layer on the side of the middle section 221b facing away from the circuit board 21, and then M first sub-openings are formed in the first buffer base layer, and the first sub-openings expose a plurality of middle Then, a second end 221c electrically connected to the middle segment 221b is formed in the first sub-opening, and finally a transfer layer 22 is formed by solder resist and surface treatment.

It can be understood that the first end 221a, the middle section 221b and the second end 221c connected in sequence form the conductive path 221, and the multi-layer first buffer base layer is processed to form the buffer function layer 222. The plurality of first sub-openings form a first opening (not shown). In this embodiment, the conductive path 221 is formed of a conductive material, and the conductive material may be one or more of copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide and tungsten carbide. The materials of the first end 221a, the middle section 221b and the second end 221c in the conductive path 221 may be the same or different.

The first buffer base layer adopts insulating material, such as polypropylene (Polypropylene, PP), polyimide (Polyimide, PI) and other dielectric materials. The first buffer base layer has low thermal expansion coefficient and high elasticity, its thermal expansion coefficient is less than or equal to 15ppm, and its elastic modulus is greater than or equal to 200MPa. In the subsequent process, the buffer function layer 222 can effectively buffer thermal and mechanical stress, and reduce the occurrence of circuit board assembly 20. Risk of warping and cracking of solder joints.

Of course, in other embodiments, the thermal expansion coefficient and elasticity of the buffer function layer 222 are not limited to the above description, as long as the buffer function layer 222 can reduce the risk of warpage and solder joint cracking of the circuit board assembly 20 .

In this embodiment, the area of the arrangement area of the M second ends 221c is smaller than the area of the arrangement area of the M first ends 221a, so that the size of the package chip 23 electrically connected to the second ends 221c in the subsequent process can be Therefore, the risk of warping and cracking of the solder joints of the circuit board assembly 20 during processing such as packaging and soldering is smaller, and the reliability of the circuit board assembly 20 is improved. At the same time, the reduced size of the packaged chip 23 can increase the layout area of other components on the circuit board 21 , or can reduce the size of the circuit board 21 , which is beneficial to the miniaturization of the circuit board assembly 20 .

Exemplarily, the area of the arrangement area of the M second ends 221c is less than or equal to 80% of the area of the arrangement area of the M first ends 221a, that is, the size of the packaged chip 23 can be reduced to 80% or more When the size of the packaged chip 23 is reduced to 80% or smaller, the risk of warping and cracking of the solder joints of the circuit board assembly 20 can be effectively reduced, and the reliability of the circuit board assembly 20 can be improved. Of course, in other embodiments, the area of the arrangement area of the M second ends 221c may also be smaller than the area of the arrangement area of the M first ends 221a by other values.

In another embodiment, the transfer layer may be formed first, and then the transfer layer may be formed on the mounting surface of the circuit board through processes such as bonding and hot pressing.

S120 : Fix the packaged chip 23 to the side of the interposer layer 22 facing away from the circuit board 21 and electrically connect with the second end 221c.

Specifically, as shown in FIG. 11 , in this embodiment, the packaged chip 23 is a chip 231 structure formed by integrating a plurality of chips 231 on a package substrate 233 . The packaged chip 23 includes a chip 231 , a chip transfer layer 232 , a package substrate 233 and solder balls 234 . The chip 231 is mounted on the package substrate 233 through the chip transfer layer 232 , that is, the package substrate 233 , the chip transfer layer 232 and the chip 231 are stacked in sequence. The number of chips 231 may be one or more. Other electronic components may also be arranged on the package substrate 233 . The package substrate 233 includes a conductive surface 2331 facing away from the chip 231 , the second pads 235 are provided on the conductive surface 2331 , and the solder balls 234 are provided on the conductive surface 2331 of the package substrate 233 and are conductively connected to the second pads 235 .

Fixing the packaged chip 23 to the side of the transfer layer 22 facing away from the circuit board 21 is specifically, to set the packaged chip 23 on the surface of the transfer layer 22 facing away from the circuit board 21 , and the solder balls 234 and the second end of the packaged chip 23 The solder balls 234 and the second end 221c of the packaged chip 23 are soldered and fixed through a reflow soldering process, so that the solder balls 234 and the second end 221c are electrically connected to realize the connection between the package substrate 233 and the transfer layer 22. Electrical connections between the two to form the circuit board assembly 20 .

In this embodiment, the thermal expansion coefficient of the transition layer 22 is smaller than the thermal expansion coefficient of the circuit board 21 and greater than the thermal expansion coefficient of the package chip 23 . It can be understood that the difference between the thermal expansion coefficient of the circuit board 21 and the thermal expansion coefficient of the packaged chip 23 is relatively large. For example, the thermal expansion coefficient of the circuit board 21 is about 20 ppm, and the thermal expansion coefficient of the packaged chip 23 is between 10 ppm and 15 ppm.

In this case, a transfer layer 22 with a thermal expansion coefficient located between the circuit board 21 and the package chip 23 is arranged between the two, and the thermal expansion coefficient of the transfer layer 22 is between 15 ppm and 20 ppm. Since the thermal expansion coefficient of the transfer layer 22 is not much different from that of the circuit board 21 , and the thermal expansion coefficient of the transfer layer 22 and the thermal expansion coefficient of the packaged chip 23 are not much different, the transfer layer 22 buffers the circuit board 21 and the packaged chip. The difference in thermal expansion coefficient between 23 can effectively reduce the risk of mismatch between the transition layer 22 and the circuit board 21 and the packaged chip 23, that is, reduce the risk of mismatch between the circuit board 21 and the packaged chip 23, and reduce the circuit board assembly. The risk of warping and cracking of the solder joints 20 occurs, and the reliability of the circuit board assembly 20 is improved.

Of course, in other embodiments, the packaged chip may also be a single chip, and when the packaged chip is a single chip, the single chip is electrically connected to the second end. Alternatively, the packaged chip may further include a chip, a package substrate and solder balls. That is to say, a chip transfer layer may not be provided between the chip and the package substrate. Alternatively, the packaged chip may also be electrically connected to the via layer through other conductive structures other than solder balls. Alternatively, a buffer layer is also filled between the package substrate and the transfer layer. Alternatively, the bonding pads of the package substrate and the second end of the transfer layer are fixedly connected by means of bonding, eutectic or the like.

In the manufacturing method provided in this embodiment, the transfer layer 22 is formed between the circuit board 21 and the package chip 23 , and the area of the arrangement area of the M second ends 221 c electrically connected between the transfer layer 22 and the circuit board 21 is smaller than that of the transfer layer 22 . The area of the arrangement area of the M first ends 221a where the layer 22 is electrically connected to the package chip 23, it can be understood that the transition layer 22 is a fan-in type transition layer, that is, the fan-in type transition layer 22 realizes the circuit The fan-in from the board 21 to the packaged chip 23 can be made smaller than the packaged chip 23 is directly fixed on the circuit board 21. The size of the packaged chip 23 fixed on the circuit board 21 through the transition layer 22 can be made smaller, so that the circuit board assembly The risk of warpage and solder joint cracking during packaging, soldering and other processes is smaller, and the reliability of the circuit board assembly 20 is improved. At the same time, the reduced size of the packaged chip 23 can increase the layout area of other components on the circuit board 21 , or can reduce the size of the circuit board 21 , which is beneficial to the miniaturization of the circuit board assembly 20 .

Please refer to FIG. 12 . FIG. 12 is a schematic flowchart of another method for manufacturing a circuit board assembly provided by an embodiment of the present application. The manufacturing method is used to manufacture the circuit board assembly shown in FIG. 7 . As shown in FIG. 12 , the manufacturing method of the circuit board assembly includes the following S210 to S220 .

S210 : forming a transition layer 22 on the mounting surface 211 of the circuit board 21 .

Specifically, this step is the same as step S110, please refer to S110, and details are not repeated here.

S220: Fix the packaged chip 23 to the side of the interposer layer 22 facing away from the circuit board 21 and electrically connect it to the second end 221c.

Specifically, as shown in FIG. 13 , in this embodiment, the packaged chip 23 is a chip 231 structure formed by integrating a plurality of chips 231 on a package substrate 233 . The packaged chip 23 includes a chip 231 , a chip transfer layer 232 and a package substrate 233 . The chip 231 is mounted on the package substrate 233 through the chip transfer layer 232 , that is, the package substrate 233 , the chip transfer layer 232 and the chip 231 are stacked in sequence. The number of chips 231 may be one or more. Other electronic components may also be arranged on the package substrate 233 . The package substrate 233 includes a conductive surface 2331 facing away from the chip 231 , and the second pad 235 is disposed on the conductive surface 2331 .

Fixing the packaged chip 23 to the side of the transition layer 22 facing away from the circuit board 21 is specifically: first, forming a conductive layer 24 on the side of the transition layer 22 facing away from the circuit board 21 that is conductively connected to the second end 221c; The method for forming the conductive layer 24 is as follows: forming a second buffer base layer on the side of the transition layer 22 facing away from the circuit board 21, and forming a second opening (not shown) on the second buffer base layer exposing the second end 221c. , forming a buffer layer 241; forming a conductive medium 242 connected to the second end 221c in the second opening, and the conductive medium 242 exposing the buffer layer 241; then, bonding and fixing the package chip 23 and the conductive layer 24, that is, The second pad 235 of the package chip 23 is bonded and fixed to the corresponding conductive medium 242 of the conductive layer 24 to realize electrical connection between the package chip 23 and the conductive layer 24 to form the circuit board assembly 20 .

In this embodiment, the package chip 23 and the transition layer 22 are connected to form an integrated structure through the conductive layer 24 . Compared with the connection through solder balls, the reliability and stress are enhanced, and the warpage and solder joints of the circuit board assembly 20 are effectively reduced. risk of cracking.

Specifically, the buffer layer 241 adopts an insulating material, such as a dielectric material such as polypropylene (Polypropylene, PP), polyimide (Polyimide, PI). The buffer layer 241 can be cured at room temperature or high temperature or UV after liquid coating, or it can be laminated with a film material. The buffer layer 241 has low thermal expansion coefficient and high elasticity, its thermal expansion coefficient is less than or equal to 15ppm, and the elastic modulus is greater than or equal to 200MPa. In some processes of manufacturing the circuit board assembly 20, the buffer layer 241 can effectively buffer thermal and mechanical stress, reduce The circuit board assembly 20 is at risk of warping and solder joint cracking.

The conductive medium 242 is made of pure metal or metal mixture materials including but limited to copper, silver, tin, or a mixture of metals and non-metals. The shape of the conductive medium 242 may be spherical, columnar, needle-like, cone-like, or the like. The size of the conductive medium 242 in this embodiment is smaller than the size of the solder balls 234 shown in FIG. 2 , which can shorten the link length between the package chip 23 and the circuit board 21 to a certain extent, improve the signal quality, and also This reduces the risk of warpage and solder joint cracking of the circuit board assembly 20 .

Of course, in other embodiments, a conductive layer may also be formed on the packaged chip, and then the conductive layer and the transfer layer are bonded and fixed, that is, the conductive medium of the conductive layer and the corresponding second terminal key to realize the electrical connection between the packaged chip and the transfer layer.

In this embodiment, the thermal expansion coefficient of the transition layer 22 is smaller than the thermal expansion coefficient of the circuit board 21 and greater than the thermal expansion coefficient of the package chip 23 . It can be understood that the difference between the thermal expansion coefficient of the circuit board 21 and the thermal expansion coefficient of the packaged chip 23 is relatively large. For example, the thermal expansion coefficient of the circuit board 21 is about 20 ppm, and the thermal expansion coefficient of the packaged chip 23 is between 10 ppm and 15 ppm.

In this case, a transfer layer 22 with a thermal expansion coefficient located therebetween is disposed between the circuit board 21 and the package chip 23, and the thermal expansion coefficient of the transfer layer 22 is between 15 ppm and 20 ppm. Since the thermal expansion coefficient of the transfer layer 22 is not much different from the thermal expansion coefficient of the circuit board 21 , the thermal expansion coefficient of the transfer layer 22 and the thermal expansion coefficient of the packaged chip 23 are not much different. The transfer layer 22 buffers the circuit board 21 and the packaged chip. The difference in thermal expansion coefficient between 23 can effectively reduce the risk of mismatch between the transition layer 22 and the circuit board 21 and the packaged chip 23, that is, reduce the risk of mismatch between the circuit board 21 and the packaged chip 23, and reduce the circuit board assembly. The risk of warping and cracking of the solder joints 20 occurs, and the reliability of the circuit board assembly 20 is improved.

Of course, in other embodiments, the packaged chip may also be a single chip, and when the packaged chip is a single chip, the single chip is electrically connected to the second end. Alternatively, the packaged chip may further include a chip and a package substrate. That is to say, a chip transfer layer may not be provided between the chip and the package substrate. Alternatively, the packaged chip may also be electrically connected to the second end through other conductive structures such as solder balls. Alternatively, a buffer layer is also filled between the package substrate and the fan-in adhesive layer.

In the manufacturing method provided by this embodiment, the transfer layer 22 is formed between the circuit board 21 and the package chip 23, and the size of the package chip 23 fixed on the circuit board 21 through the transfer layer 22 can be made smaller, so that the circuit board The risk of warpage and cracking of solder joints in the assembly 20 during packaging, soldering and other processes is smaller, and the reliability of the circuit board assembly 20 is improved. At the same time, the reduced size of the packaged chip 23 can increase the layout area of other components on the circuit board 21 , or can reduce the size of the circuit board 21 , which is beneficial to the miniaturization of the circuit board assembly 20 . And through the contact layer to realize the connection between the package chip 23 and the transition layer 22, the multiple components in the circuit board assembly 20 are fixed into a package as a whole, compared with the solution of realizing the connection through solder balls, reliability and stress Both are enhanced, effectively reducing the risk of warpage and solder joint cracking of the circuit board assembly 20 .

Please refer to FIG. 14. FIG. 14 is a schematic flowchart of another method for manufacturing a circuit board assembly provided by an embodiment of the present application. This manufacturing method is used to manufacture a circuit board assembly as shown in FIG. 8 . The manufacturing method of the circuit board shown in FIG. 14 includes the following S310 to S320.

S310 : forming the transfer layer 22 on the packaged chip 23 .

Specifically, as shown in FIG. 15 , in this embodiment, the packaged chip 23 is a chip 231 structure formed by integrating a plurality of chips 231 on a package substrate 233 . The packaged chip 23 includes a chip 231 , a chip transfer layer 232 and a package substrate 233 . The chip 231 is mounted on the package substrate 233 through the chip transfer layer 232 , that is, the package substrate 233 , the chip transfer layer 232 and the chip 231 are stacked in sequence. The number of chips 231 may be one or more. Other electronic components may also be arranged on the package substrate 233 . The package substrate 233 includes a conductive surface 2331 facing away from the chip 231 , and the second pad 235 is disposed on the conductive surface 2331 .

The transfer layer 22 is formed on the conductive surface 2331 of the package chip 23 , and the second end 221 c of the transfer layer 22 is electrically connected to the second pad 235 of the package chip 23 . Specifically, forming the transfer layer 22 on the conductive surface 2331 of the packaged chip 23 includes two implementations.

In one embodiment, the transfer layer 22 is directly formed on the conductive surface 2331 of the packaged chip 23 . Specifically, the operation steps of forming the transition layer 22 on the conductive surface 2331 of the package chip 23 are similar to the operation steps of forming the transition layer 22 on the circuit board 21 , and will not be repeated.

In another embodiment, the transfer layer 22 may be formed first, and then the transfer layer 22 may be formed on the conductive surface 2331 of the packaged chip 23 through processes such as bonding, hot pressing, etc., so that the second end of the transfer layer 22 is formed. 221c is electrically connected to the corresponding second pad 235 .

In this embodiment, the structure of the transition layer 22 is the same as that of the transition layer 22 in S210. The second end 221c of the transition layer 22 is electrically connected to the second pad 235 of the package chip 23, and the area of the arrangement area of the M second ends 221c is smaller than the area of the arrangement area of the M first ends 221a. The terminal 221a is used for electrical connection with the first pad 212 of the circuit board 21 in the subsequent process, and is connected between the circuit board 21 and the packaged chip 23 through the transition layer 22, so that the size of the packaged chip 23 can be made smaller, thereby The risk of warping and cracking of the solder joints of the circuit board assembly 20 during processing such as packaging and soldering is reduced, and the reliability of the circuit board assembly 20 is improved. At the same time, the reduced size of the packaged chip 23 can increase the layout area of other components on the circuit board 21 , or can reduce the size of the circuit board 21 , which is beneficial to the miniaturization of the circuit board assembly 20 .

Exemplarily, the area of the arrangement area of the second end 221c is less than or equal to 80% of the area of the arrangement area of the first end 221a, that is, the size of the packaged chip 23 can be reduced to 80% or less. The size of the chip 23 is reduced to 80% or smaller, which can effectively reduce the risk of warping and cracking of the solder joints of the circuit board assembly 20 and improve the reliability of the circuit board assembly 20 . Of course, in other embodiments, the arrangement area of the second end 221c may also be smaller than the area of the arrangement area of the first end 221a by other values.

Finally, a conductive layer 24 is formed on the first end 221 a of the transfer layer 22 , so as to realize the electrical connection between the transfer layer 22 and the circuit board 21 through the conductive layer 24 in the subsequent process. Of course, solder balls may also be formed on the first end 221 a of the transition layer 22 .

Of course, in other embodiments, the packaged chip may also be a single chip, and when the packaged chip is a single chip, the single chip is electrically connected to the second end. Alternatively, the packaged chip may further include a chip and a package substrate. That is to say, a chip transfer layer may not be provided between the chip and the package substrate. Alternatively, the packaged chip may also be electrically connected to the second end through other conductive structures other than the conductive layer, such as solder balls.

S320 : Fix the side of the transition layer 22 facing away from the packaged chip 23 to the circuit board 21 , and the first end 221 a is electrically connected to the circuit board 21 .

Specifically, as shown in FIG. 15 , the side of the conductive layer 24 facing away from the packaged chip 23 is disposed on the surface of the circuit board 21 , and the conductive medium 242 of the conductive layer 24 is in one-to-one contact with the first pads 212 of the circuit board 21 . Then, the conductive medium 242 and the first pad 212 of the circuit board 21 are fixed by bonding, eutectic and other processes, so that the conductive medium 242 can realize the electrical connection between the transition layer 22 and the circuit board 21 .

In other embodiments, the connection between the fan-in transfer layer and the circuit board may also be achieved by solder balls, and a buffer layer may also be filled between the transfer layer and the circuit board. Alternatively, the transfer layer can also be fixed to the circuit board by bonding, thermal pressing or other processes.

In the manufacturing method provided in this embodiment, a transition layer 22 is formed between the circuit board 21 and the package chip 23 . It can be understood that the transition layer 22 is a fan-in type transition layer, that is, the fan-in type transition layer 22 realizes The fan-in from the circuit board 21 to the packaged chip 23 is improved. Compared with the packaged chip 23 that is directly fixed on the circuit board 21, the size of the packaged chip 23 fixed on the circuit board 21 through the transition layer 22 can be made smaller, so that the circuit The risk of warping and cracking of solder joints of the board assembly 20 during processing such as packaging and soldering is less, and the reliability of the circuit board assembly 20 is improved. At the same time, the reduced size of the packaged chip 23 can increase the layout area of other components on the circuit board 21 , or can reduce the size of the circuit board 21 , which is beneficial to the miniaturization of the circuit board assembly 20 .

Please refer to FIG. 16. FIG. 16 is a schematic flowchart of another method for manufacturing a circuit board assembly provided by an embodiment of the present application. This manufacturing method is used to manufacture a circuit board assembly as shown in FIG. 9 . The manufacturing method of the circuit board assembly shown in FIG. 16 includes the following S410 to S420.

S410 : forming the conductive layer 24 on the mounting surface 211 of the circuit board 21 .

Specifically, please refer to FIG. 17 . First, a circuit board 21 is fabricated. Specifically, the circuit board 21 may be formed by processes such as pressing, drilling, electroplating, patterning, solder resist, and surface treatment. The circuit board 21 includes a mounting surface 211 , and the plurality of first pads 212 of the circuit board 21 are exposed from the mounting surface 211 . Then, a conductive layer 24 is formed on the mounting surface 211 of the circuit board 21 .

The method of forming the conductive layer 24 is as follows: after cleaning the circuit board 21 , a second buffer base layer is formed on the mounting surface 211 of the circuit board 21 , and the second buffer base layer can be formed by film pressing, slurry coating and other different methods. formed on the mounting surface 211 . The specific steps of laminating the film layers may be as follows: laminating the film material on the mounting surface 211 of the circuit board 21 , and then laminating the film layers to form the second buffer base layer. The specific steps of slurry coating may be as follows: coating the slurry on the mounting surface 211 of the circuit board 21 , and drying or curing the slurry to form the second buffer base layer. Next, laser opening is performed on the second buffer base layer, a second opening exposing the first pad 212 is formed, a buffer layer 241 is formed, and then a conductive medium 242 connected to the first pad 212 is formed in the second opening, and the conductive medium 242 The conductive paste may be formed in the second opening by printing or printing, and then cured to form the conductive medium 242 to expose the buffer layer 241 .

Specifically, the buffer layer 241 adopts an insulating material, such as a dielectric material such as polypropylene (Polypropylene, PP), polyimide (Polyimide, PI). The buffer layer 241 can be cured at room temperature or high temperature or UV after liquid coating, or it can be laminated with a film material. The buffer layer 241 has low thermal expansion coefficient and high elasticity, its thermal expansion coefficient is less than or equal to 15ppm, and its elastic modulus is greater than or equal to 200MPa. The circuit board assembly 20 is at risk of warping and solder joint cracking.

The conductive medium 242 is made of pure metal or metal mixture materials including but limited to copper, silver, tin, or a mixture of metals and non-metals. The shape of the conductive medium 242 may be spherical, columnar, needle-like, cone-like, or the like.

S420 : Fix the packaged chip 23 to the side of the conductive layer 24 facing away from the circuit board 21 and electrically connect with the conductive medium 242 .

Specifically, as shown in FIG. 17 , in this embodiment, the packaged chip 23 is a chip 231 structure formed by integrating a plurality of chips 231 on a package substrate 233 . The packaged chip 23 includes a chip 231 , a chip transfer layer 232 and a package substrate 233 . The chip 231 is mounted on the package substrate 233 through the chip transfer layer 232 , that is, the package substrate 233 , the chip transfer layer 232 and the chip 231 are stacked in sequence. The number of chips 231 may be one or more. Other electronic components may also be arranged on the package substrate 233 . The package substrate 233 includes a conductive surface 2331 facing away from the chip 231 , and the second pad 235 is disposed on the conductive surface 2331 .

Fixing the packaged chip 23 to the side of the conductive layer 24 facing away from the circuit board 21 is specifically, to set the packaged chip 23 on the side of the conductive layer 24 facing away from the circuit board 21 , and the second pad 235 of the packaged chip 23 is connected to the side of the conductive layer 24 facing away from the circuit board 21 . The corresponding conductive medium 242 is in contact, and then the packaged chip 23 and the conductive layer 24 are bonded and fixed by pressing or bonding, that is, the second pad 235 of the packaged chip 23 and the conductive layer 24 The medium 242 is bonded and fixed to realize the electrical connection between the packaged chip 23 and the conductive layer 24 .

In this embodiment, the package chip 23 and the transition layer 22 are connected to form an integrated structure through the conductive layer 24 . Compared with the connection through solder balls, the reliability and stress are enhanced, and the warpage and solder joints of the circuit board assembly 20 are effectively reduced. risk of cracking.

In this embodiment, the thermal expansion coefficient of the conductive layer 24 is smaller than the thermal expansion coefficient of the circuit board 21 and greater than the thermal expansion coefficient of the package chip 23 . It can be understood that the difference between the thermal expansion coefficient of the circuit board 21 and the thermal expansion coefficient of the packaged chip 23 is relatively large. For example, the thermal expansion coefficient of the circuit board 21 is about 20 ppm, and the thermal expansion coefficient of the packaged chip 23 is between 10 ppm and 15 ppm.

In this case, a conductive layer 24 with a thermal expansion coefficient located therebetween is provided between the circuit board 21 and the package chip 23 , and the thermal expansion coefficient of the conductive layer 24 is between 15 ppm and 20 ppm. Since the thermal expansion coefficient of the conductive layer 24 is not much different from the thermal expansion coefficient of the circuit board 21 , the thermal expansion coefficient of the conductive layer 24 and the thermal expansion coefficient of the packaged chip 23 are not significantly different, and the conductive layer 24 buffers the circuit board 21 and the packaged chip. The difference in thermal expansion coefficient between 23 can effectively reduce the risk of mismatch between the conductive layer 24 and the circuit board 21 and the packaged chip 23, that is, reduce the risk of mismatch between the circuit board 21 and the packaged chip 23, and reduce the circuit board assembly. The risk of warping and cracking of the solder joints 20 occurs, and the reliability of the circuit board assembly 20 is improved.

Of course, in other embodiments, the packaged chip may also be a single chip, and when the packaged chip is a single chip, the single chip is electrically connected to the conductive medium. Alternatively, the packaged chip may further include a chip and a package substrate. That is to say, a chip transfer layer may not be provided between the chip and the package substrate.

Please refer to FIG. 18 , FIG. 18 is a specific process schematic diagram of another implementation manner of the circuit board assembly shown in FIG. 17 .

In this embodiment, the circuit board 21 can be fabricated by inner layer patterning, lamination, drilling, chemical copper, electroplating copper, and the conductive medium 242 can be formed by dry film 1, exposure 1, development 1, etching, film removal, Dry film 2, exposure 2, development 2, bump plating, film removal, solder mask printing and surface treatment are formed. Alternatively, the conductive medium 242 may be formed by processes such as dry film 1, exposure 1, development 1, etching, solder mask, surface treatment, photoresist/dry film, exposure, development, bump metal evaporation, or sputtering and stripping. Then, through alignment, the buffer layer 241 is pre-attached, the packaged chip 23 is placed on the side of the buffer layer 241 that faces away from the circuit board 21, the second pad 235 of the packaged chip 23 is in contact with the corresponding conductive medium 242, and then the packaged chip 23 is thermally pressed. The package chip 23 and the conductive layer 24 are bonded and fixed by processes such as eutectic, that is, the second pad 235 of the package chip 23 is bonded and fixed with the corresponding conductive medium 242 of the conductive layer 24, so as to realize the bonding between the package chip 23 and the corresponding conductive medium 242 of the conductive layer 24. Electrical connection between the conductive layers 24 .

Please refer to FIG. 19 . FIG. 19 is a specific process schematic diagram of another implementation manner of the circuit board assembly shown in FIG. 17 .

This embodiment is substantially the same as the embodiment shown in FIG. 18 , the difference is that the conductive medium 242 can be formed on the packaging substrate 233 of the packaging chip 23 in this embodiment, and the packaging substrate 233 is first fabricated (the same steps as those of fabricating the circuit board 21 ). ); then, a conductive medium 242 electrically connected to the second pad 235 on the packaging substrate 233 is formed on the packaging substrate 233; Devices such as the chip 231 are stacked on one side of the second pad 235; then the circuit board 21 is fabricated and a buffer layer 241 with a second opening is formed on the circuit board 21, and the second opening exposes the first pad 212; finally, the chip is packaged The conductive medium 242 on 23 is in contact with the first pad 212 in the corresponding second opening, and the conductive medium 242 is bonded and fixed with the corresponding first pad 212 through a process such as thermocompression eutectic.

The protection scope of the present application is not limited to all the above-mentioned embodiments, and any combination of all the above-mentioned embodiments is also within the protection scope of the present application, that is, the above-described multiple embodiments can also be arbitrarily combined according to actual needs.

The above are only some examples and implementations of the present application, and the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, and should cover within the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (16)

A circuit board assembly, characterized in that, the circuit board assembly includes a circuit board, a transfer layer and a package chip, the transfer layer includes M conductive paths having a first end and a second end, each of the first and second ends. one end is electrically connected to the circuit board, and each of the second ends is electrically connected to the packaged chip; The area of the arrangement regions of the M second ends is smaller than the area of the arrangement regions of the M first ends, where M is an integer greater than or equal to 2. The circuit board assembly according to claim 1, wherein the area of the arrangement area of the second end is less than or equal to 80% of the area of the arrangement area of the first end. The circuit board assembly according to claim 1 or 2, wherein the thermal expansion coefficient of the transition layer is smaller than the thermal expansion coefficient of the circuit board and greater than the thermal expansion coefficient of the packaged chip. The circuit board assembly according to any one of claims 1 to 3, wherein the transition layer further comprises a buffer function layer, the conductive path penetrates the buffer function layer, the first end and the buffer function layer The second ends respectively expose two opposite surfaces of the buffer function layer. The circuit board assembly according to claim 4, wherein the elastic modulus of the buffer function layer is greater than or equal to 200 MPa. The circuit board assembly according to any one of claims 1 to 5, wherein the packaged chip further comprises a plurality of solder balls, and each of the solder balls is electrically connected to the second terminal in a one-to-one correspondence . The circuit board assembly according to any one of claims 1 to 5, wherein the circuit board assembly further comprises a conductive layer, and the conductive layer is located between the transfer layer and the packaged chip , the conductive layer includes a buffer layer and a conductive medium embedded in the buffer layer, and the conductive medium is electrically connected between the second end and the package chip. The circuit board assembly according to any one of claims 1 to 7, wherein the circuit board assembly further comprises a plurality of first pads placed on the circuit board and a plurality of first pads placed on the packaged chip a second pad, the first end of the conductive path is connected to the corresponding first pad, and the second end of the conductive path is connected to the corresponding second pad. The circuit board assembly according to any one of claims 1 to 8, wherein the packaged chip comprises a chip and a package substrate, the chip is mounted on the package substrate, and the package substrate includes a backing to the package substrate. A conductive contact surface of the chip, the conductive contact surface is electrically connected to the second end. A manufacturing method of a circuit board assembly, characterized in that the manufacturing method comprises: A transfer layer is formed on the mounting surface of the circuit board, wherein the transfer layer includes M conductive paths with a first end and a second end, the M is an integer greater than or equal to 2, and the M conductive paths of the second ends The area of the arrangement area is smaller than the area of the arrangement area of the M first ends, and the first ends are electrically connected to the circuit board; The packaged chip is fixed to the side of the transfer layer facing away from the circuit board and electrically connected to the second end. The manufacturing method according to claim 10, wherein the method of forming the fan-in type transition layer comprises: A first buffer base layer is formed on the mounting surface of the circuit board, and the elastic modulus of the first buffer base layer is greater than or equal to 200MPa; forming a first opening exposing the circuit board on the first buffer base layer; A conductive path having a first end and a second end is formed in the first opening. The manufacturing method according to claim 10 or 11, wherein before the packaged chip is electrically connected to the second end, the manufacturing method further comprises: A conductive layer is formed on the side of the transition layer facing away from the circuit board, which is conductively connected to the second end; The electrical connection of the package chip to the second end includes the bonding and fixing of the package chip and the conductive layer. The manufacturing method according to any one of claims 10 to 12, wherein the area of the arrangement area of the second end is less than or equal to 80% of the area of the arrangement area of the first end. The manufacturing method according to any one of claims 10 to 13, wherein the thermal expansion coefficient of the transition layer is smaller than the thermal expansion coefficient of the circuit board and greater than the thermal expansion coefficient of the packaged chip. A manufacturing method of a circuit board assembly, characterized in that the manufacturing method comprises: A transfer layer is formed on the packaged chip, wherein the transfer layer includes M conductive paths with a first end and a second end, the M is an integer greater than or equal to 2, and the arrangement of the M second ends The area of the area is smaller than the area of the arrangement area of the M first ends, and the second ends are electrically connected to the package chip; The side of the transition layer facing away from the packaged chip is fixed to the circuit board, and the first end is electrically connected to the circuit board. An electronic device, characterized in that, the electronic device comprises the circuit board assembly according to any one of claims 1 to 9.

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