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WO2022032470A1 - Puce à changement de température en phase liquide in situ à haute résolution pour microscope électronique à transmission, et son procédé de fabrication - Google Patents

Puce à changement de température en phase liquide in situ à haute résolution pour microscope électronique à transmission, et son procédé de fabrication Download PDF

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WO2022032470A1
WO2022032470A1 PCT/CN2020/108368 CN2020108368W WO2022032470A1 WO 2022032470 A1 WO2022032470 A1 WO 2022032470A1 CN 2020108368 W CN2020108368 W CN 2020108368W WO 2022032470 A1 WO2022032470 A1 WO 2022032470A1
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wafer
layer
type
metal
film
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Chinese (zh)
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廖洪钢
江友红
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Xiamen Chip-Nova Technology Co Ltd
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Xiamen Chip-Nova Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00—Sampling; Preparing specimens for investigation
    • G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
    • G01N1/42—Low-temperature sample treatment, e.g. cryofixation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00—Sampling; Preparing specimens for investigation
    • G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
    • G01N1/44—Sample treatment involving radiation, e.g. heat
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/02—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
    • G01N23/2202—Preparing specimens therefor

Definitions

  • the invention relates to the field of liquid phase chips, in particular to a transmission electron microscope high-resolution in-situ liquid phase temperature change chip and a preparation method thereof.
  • In situ chip transmission electron microscopy a new technology developed in the field of transmission electron microscopy in recent years, has been able to observe the morphology evolution and molecular structure changes of substances in solution environment at the atomic scale under in situ conditions.
  • the chemical reaction process in the liquid environment is of great significance for studying the reaction principle and controlling the reaction process.
  • the existing TEM freezing technology is characterized by rapidly cooling the sample, the solvent molecules become glassy, and the sample is also frozen instantaneously, so as to obtain a more realistic sample morphology. Due to the limitation of the freezing state of the sample, we can often only observe a single static state when the sample is frozen, and cannot observe the entire three-dimensional dynamic change process of the sample in the real solution environment, which makes our research on the real reaction system limited. great limitation.
  • the single state of matter after freezing and the inability to achieve alternate transformation is the biggest obstacle to its application.
  • the present invention provides a liquid phase freezing environment through semiconductor refrigeration, and uses the Joule heat of the heating wire to thaw, and the cooling and heating effects can be used with accurate currents. Free and flexible alternation of freeze-thaw of solution-phase samples can be realized.
  • the present invention provides a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy.
  • the material of the sheet is a silicon substrate with silicon nitride or silicon oxide on both sides, and the upper sheet has two sample injection ports and a central window 1. It is characterized in that the lower sheet is provided with a support layer, a freezing layer, an insulating layer 1, The heating layer, the insulating layer 2, the tunnel and the central window 2; the freezing layer is provided with four contact electrodes, a semiconductor refrigeration film of not less than one level and a conductive metal film, of which the four contact electrodes are placed on the edge of the chip; in the central window 2.
  • the silicon is etched away, leaving a channel, and the support layer covers the channel; the semiconductor refrigeration film and the conductive metal film are placed on the support layer on the channel, and do not directly contact the silicon substrate;
  • the center window 2 is the center, and a circle of metal films is deposited on the support layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the back end is connected to the four contact electrodes on the freezing layer; if it is at least two-stage semiconductor refrigeration film , then the rear end is connected to the semiconductor refrigeration films of all levels with metal films in turn, until the last level of semiconductor refrigeration films is connected to the four contact electrodes on the freezing layer; the freezing layer and the heating layer are separated by the insulating layer 1, and the heating layer is connected to the outside Separated by the insulating layer 2; the heating layer has two contact electrodes and a spiral annular heating wire, and the heating wire is located above the semiconductor refrigeration film;
  • the area of the upper sheet is slightly smaller than that of the lower sheet, the central window 1 of the upper sheet and the central window 2 of the lower sheet are aligned, and both the central window 1 and the central window 2 have a plurality of small holes.
  • the outer dimension of the lower piece is 2*2-10*10mm; preferably, the outer dimension of the lower piece is 4*8mm;
  • the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;
  • the thickness of the silicon nitride or silicon oxide is 5-200nm;
  • the thickness of the silicon substrate is 50-500 ⁇ m.
  • a circle-shaped metal film is deposited on the support layer
  • the support layer is silicon nitride or silicon oxide with a thickness of 0.5-5 ⁇ m.
  • the freezing layer is set to two groups of equivalent circuits, and the two groups of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; one group of loops in the two groups of equivalent circuits is responsible for power supply and cooling, Another set of loops is responsible for real-time monitoring of the current value of semiconductor refrigeration;
  • the shape of the semiconductor refrigeration film of the freezing layer is a regular rectangle; the length is 0.2-0.8mm, the width is 0.1-0.4mm, and the thickness is 50nm-500nm; preferably, the semiconductor in the semiconductor refrigeration film is n-type semiconductors and p-type semiconductors, where n-type semiconductors are n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; is polysilicon, p-type bismuth telluride, p-type silicon germanium, or p-type antimony telluride;
  • the conductive metal in the conductive metal film is gold, silver or copper, with a thickness of 50nm-300nm;
  • the size of the outer square of the conductive metal film is 100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m, and the size of the inner square is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m.
  • both the insulating layer 1 and the insulating layer 2 are one layer, and the thickness is 30-150 nm; preferably, the insulating layer 1 and the insulating layer 2 are made of silicon nitride, silicon oxide or aluminum oxide.
  • the outer diameter of the spiral annular heating wire of the heating layer is 0.15-0.5mm, and the thickness is 50nm-500nm;
  • the spiral annular heating wire adopts metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide;
  • the shape of the helical annular heating wire on the heating layer is relatively symmetrical, and the heating wires are left with gaps and are not connected to each other; the heating wire in the center of the heating layer is placed on the intermediate insulating layer, and is not directly connected to the freezing layer contact.
  • the channel is square; preferably, the length of the channel is 4-7mm; the width is 0.25-0.9mm;
  • the central window 1 and the central window 2 are square central windows; preferably, the size of the square central window is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m; more preferably, the size of the square central window is 20 ⁇ m *50 ⁇ m;
  • the size of the pores is 0.5 ⁇ m-5 ⁇ m.
  • the preparation method of the top sheet is,
  • the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;
  • the exposure time is 15s
  • the development time is 50s;
  • the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
  • the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
  • the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;
  • the time of etching is 2h;
  • the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;
  • the exposure time is 15s
  • the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;
  • the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;
  • the metal is In, Sn or Al;
  • the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;
  • the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
  • the exposure time is 20s;
  • the length of the frozen layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50-500 nm;
  • Wafer B-3 Put the backside of wafer B-2 into a potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out wafer 2, rinse it with a large amount of deionized water, and dry it to obtain Wafer B-3;
  • the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;
  • the etching temperature is 80°C; the etching time is 2h;
  • silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;
  • the thickness of silicon oxide or silicon nitride is 0.5-5 ⁇ m;
  • the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;
  • the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
  • the p-type semiconductor adopts bismuth telluride or antimony telluride
  • S12. utilize the PECVD process to grow a layer of silicon nitride or silicon oxide or aluminum oxide on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;
  • the thickness of the insulating layer is 30-150 nm;
  • the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;
  • the thickness of the insulating layer is 30-150 nm;
  • the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;
  • the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
  • the wafer B-15 is laser diced and divided into independent chips, which are the next wafers.
  • the present invention provides a method for preparing the transmission electron microscope high-resolution in-situ liquid phase cryochip, which is characterized in that:
  • the preparation method of the top sheet is,
  • the photolithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;
  • the exposure time is 15s
  • the development time is 50s;
  • the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
  • the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
  • the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;
  • the time of etching is 2h;
  • the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;
  • the exposure time is 15s
  • the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;
  • the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;
  • the metal is In, Sn or Al;
  • the preparation method of the lower tablet is,
  • the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;
  • the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
  • the exposure time is 20s;
  • the length of the frozen layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50-500 nm;
  • Wafer B-3 Put the backside of wafer B-2 into a potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out wafer 2, rinse it with a large amount of deionized water, and dry it to obtain Wafer B-3;
  • the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;
  • the etching temperature is 80°C; the etching time is 2h;
  • silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;
  • the thickness of silicon oxide or silicon nitride is 0.5-5 ⁇ m;
  • the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;
  • the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
  • the p-type semiconductor adopts bismuth telluride or antimony telluride
  • S12. utilize the PECVD process to grow a layer of silicon nitride or silicon oxide or aluminum oxide on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;
  • the thickness of the insulating layer is 30-150 nm;
  • the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;
  • the thickness of the insulating layer is 30-150 nm;
  • the pinhole pattern of the central window is transferred from the lithography mask to the front side of the wafer B-13, then developed in a positive-gel developer, and then rinsed with deionized water. surface to obtain wafer B-14;
  • the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;
  • the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
  • Assembly Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.
  • the small holes are formed by etching the insulating layer 1, the insulating layer 2 and the support layer. Multiple layers of silicon nitride (support layer, insulating layer 1 and insulating layer 2) are deposited on the central window 2. The thickness of the silicon nitride is too large and requires etching to thin the window silicon nitride for electron microscope observation.
  • the chip has the advantages of a large temperature control range (the temperature range can reach -120°C to +100°C, and the highest can reach +1000°C), the temperature changing rate is fast, and in-situ dynamic observation can be realized.
  • the conventional products only have a single function of heating and cooling or freezing and cooling.
  • the temperature control area of the chip of the invention is small (100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m area), and the heat insulation treatment is designed, so that the heat transfer is small, so the micro-area rapid temperature control can be realized.
  • FIG. 1 is a schematic diagram of the back surface channel of the lower part of the chip of the present invention.
  • FIG. 2 is a schematic view of the front structure of the lower part of the chip of the present invention.
  • FIG. 3 is a schematic diagram of the structure of each layer of the chip of the present invention.
  • FIG. 4 is a schematic structural diagram of the assembled chip of the present invention.
  • FIG. 5 is an enlarged view of the upper-chip center window of the chip of the present invention.
  • FIG. 6 is an enlarged view of the bottom center window of the chip of the present invention.
  • FIG. 7 is an electron microscope image of a sample observed using the chip of the present invention.
  • Fig. 8 is a temperature standard curve diagram obtained by using the chip of the present invention.
  • a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy the structure of which is that an upper sheet and a lower sheet are combined by a metal bonding layer to form an ultra-thin chamber by self-sealing; the upper sheet and the lower sheet are made of nitrogen on both sides
  • the freezing layer is provided with four contact electrodes, no less than one level of semiconductor refrigeration film and conductive metal film, wherein the four contact electrodes are placed on the edge of the chip; in the central window 2 and the area where the semiconductor refrigeration film is located, After the silicon is etched away, a channel is left, and the support layer covers the channel; the semiconductor refrigeration film and the conductive metal film are placed on the support layer on the channel, and are not in direct contact with the silicon substrate; the center window 2 is centered on the support layer.
  • a circle of metal film is deposited on the layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the rear end is connected to the four contact electrodes on the freezing layer; if it is at least two-stage semiconductor refrigeration film, the rear end is sequentially made of metal
  • the film connects all levels of semiconductor refrigeration films until the last level of semiconductor refrigeration films is connected to the four contact electrodes on the freezing layer; the freezing layer and the heating layer are separated by the insulating layer 1, and the heating layer is separated from the outside by the insulating layer 2; heating The layer has two contact electrodes and a spiral annular heating wire, and the heating wire is located above the semiconductor refrigeration film;
  • the area of the upper sheet is slightly smaller than that of the lower sheet, the central window 1 of the upper sheet and the central window 2 of the lower sheet are aligned, and both the central window 1 and the central window 2 have a plurality of small holes.
  • the outer dimension of the lower piece is 2*2-10*10mm; preferably, the outer dimension of the lower piece is 4*8mm;
  • the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;
  • the thickness of the silicon nitride or silicon oxide is 5-200nm;
  • the thickness of the silicon substrate is 50-500 ⁇ m.
  • a circle-shaped metal film is deposited on the support layer
  • the support layer is silicon nitride or silicon oxide with a thickness of 0.5-5 ⁇ m.
  • the freezing layer is set as two sets of equivalent circuits, and the two sets of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; a set of loops in the two sets of equivalent circuits is responsible for power supply and cooling, Another set of loops is responsible for real-time monitoring of the current value of semiconductor refrigeration;
  • the shape of the semiconductor refrigeration film of the freezing layer is a regular rectangle; the length is 0.2-0.8mm, the width is 0.1-0.4mm, and the thickness is 50nm-500nm; preferably, the semiconductor in the semiconductor refrigeration film is n-type semiconductors and p-type semiconductors, where n-type semiconductors are n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; is polysilicon, p-type bismuth telluride, p-type silicon germanium, or p-type antimony telluride;
  • the conductive metal in the conductive metal film is gold, silver or copper, with a thickness of 50nm-300nm;
  • the size of the outer square of the conductive metal film is 100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m, and the size of the inner square is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m.
  • both the insulating layer 1 and the insulating layer 2 are one layer, and the thickness is 30-150 nm; preferably, the insulating layer 1 and the insulating layer 2 are made of silicon nitride, silicon oxide or aluminum oxide.
  • the outer diameter of the spiral annular heating wire of the heating layer is 0.15-0.5mm, and the thickness is 50nm-500nm;
  • the spiral annular heating wire adopts metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide;
  • the shape of the helical annular heating wire on the heating layer is relatively symmetrical, and the heating wires are left with gaps and are not connected to each other; the heating wire in the center of the heating layer is placed on the intermediate insulating layer, and is not directly connected to the freezing layer contact.
  • the channel is square; preferably, the length of the channel is 4-7mm; the width is 0.25-0.9mm;
  • the central window 1 and the central window 2 are square central windows; preferably, the size of the square central window is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m; more preferably, the size of the square central window is 20 ⁇ m *50 ⁇ m;
  • the size of the pores is 0.5 ⁇ m-5 ⁇ m.
  • the preparation method of the top sheet is,
  • the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;
  • the exposure time is 15s
  • the development time is 50s;
  • the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
  • the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
  • the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;
  • the time of etching is 2h;
  • the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;
  • the exposure time is 15s
  • the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;
  • the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;
  • the metal is In, Sn or Al;
  • the preparation method of the lower tablet is,
  • the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;
  • the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
  • the exposure time is 20s;
  • the length of the frozen layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50-500 nm;
  • Wafer B-3 Put the backside of wafer B-2 into a potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out wafer 2, rinse it with a large amount of deionized water, and dry it to obtain Wafer B-3;
  • the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;
  • the etching temperature is 80°C; the etching time is 2h;
  • silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;
  • the thickness of silicon oxide or silicon nitride is 0.5-5 ⁇ m;
  • the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;
  • the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
  • the p-type semiconductor adopts bismuth telluride or antimony telluride
  • the thickness of the insulating layer is 30-150 nm;
  • the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;
  • the thickness of the insulating layer is 30-150 nm;
  • the pinhole pattern of the central window is transferred from the lithography mask to the front side of the wafer B-13, then developed in a positive-gel developer, and then rinsed with deionized water. surface to obtain wafer B-14;
  • the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;
  • the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
  • Assembly Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.
  • 1 is the high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy
  • 2 is the upper film
  • 3 is the lower film
  • 4 is the metal bonding layer
  • 5 is the central window
  • 51 is the central window of the upper film
  • 6 is the small hole
  • 7 is the injection port
  • 8 is the heating layer
  • 9 is the heating wire
  • 10 is the central area of the heating wire
  • 11 is the four contact electrodes
  • Example 1 Preparation of high-resolution in-situ liquid phase temperature-changing chip for transmission electron microscopy
  • the preparation method of the top sheet is,
  • the thickness of silicon nitride at the small hole on the back of wafer A-3 is etched to 10nm-15nm, and the size of the small hole is 0.5 ⁇ m-5 ⁇ m; -3 was soaked in acetone with the front side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
  • the wafer A-6 is vapor-deposited with a metal bonding material to form a metal bonding layer with a thickness of 50-2000 nm to obtain wafer A-7;
  • the metal is a low melting point metal;
  • a low melting point metal is In, Sn or Al;
  • the preparation method of the lower tablet is,
  • the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;
  • wafer B-2 Put the backside of wafer B-2 into a potassium hydroxide solution with a concentration of 20% by mass to carry out wet etching (the etching temperature is 80°C, and the etching time is 2h), until the bare After the leaked base silicon is completely etched, the wafer 2 is taken out, rinsed with a large amount of deionized water, and then blown dry to obtain wafer B-3;
  • silicon oxide or silicon nitride with a thickness of 0.5-5 ⁇ m is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;
  • the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;
  • the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
  • n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type type zinc telluride or n-type bismuth selenide;
  • the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
  • the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the The thickness of the metal heating wire is 50nm-500nm;
  • the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer B-13, and then the Develop in a positive gel developer, and then rinse and clean the surface with deionized water to obtain wafer B-14;
  • Assembly Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.
  • Example 2 The use of transmission electron microscope high-resolution in-situ liquid phase temperature change chip
  • the supersaturated calcium hydroxide aqueous solution (containing trace calcium hydroxide particles in the solution) was injected into the injection port of the high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy prepared in Example 1.
  • Warm software set the chip temperature to -30 °C, and obtain the electron microscope image in Figure 7. It can be seen from A and B in Figure 7 that as the temperature increases, the solution temperature increases, the solute solubility gradually decreases, and calcium hydroxide solid is precipitated. Nanoparticles are calcium hydroxide solids precipitated during the increase in chip temperature.
  • the temperature of the solution in the chip can be monitored and controlled in real time. This temperature range can be reached for both liquid phase reactions.
  • the transmission electron microscope high-resolution in-situ liquid phase temperature change chip is used to measure the temperature reached by the chip under different output powers by using a thermometer to obtain a temperature standard curve, and then accurately control the temperature by accurately adjusting the output power of the power supply equipment.
  • the results are shown in Figure 8.
  • the slope of the line graph in FIG. 8 roughly reflects the temperature change rate of 5-6°C per second, indicating that the temperature change rate is fast.
  • the temperature range can reach -120°C to +100°C, and the maximum can reach +1000°C, indicating that the chip of the present invention has a large temperature control range, and can be used from low temperature to high temperature.
  • the conventional products only have a single function of heating and cooling or freezing and cooling.

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Abstract

L'invention concerne une puce à changement de température en phase liquide in situ à haute résolution pour microscope électronique à transmission (1) et un procédé de fabrication correspondant. Un substrat inférieur (3) de la puce (1) est muni d'une couche de support (15), d'une couche de congélation, d'une première couche isolante (16), d'une couche de chauffage (8), d'une seconde couche isolante (17), de canaux (18) et d'une fenêtre centrale (52) ; la couche de congélation comporte quatre électrodes de contact (11), un film semi-conducteur de réfrigération (19) et un film métallique électriquement conducteur (20) ; les canaux sont formés dans la zone où la fenêtre centrale (52) et le film semi-conducteur de réfrigération (19) sont situés, après que le silicium a été enlevé par gravure, et la couche de support (15) couvre les canaux (18) ; le film semi-conducteur de réfrigération (19) et le film métallique électriquement conducteur (20) sont tous deux disposés sur la couche de support (15) ; un film métallique (20) est déposé sur la couche de support (15), avec la fenêtre centrale (52) comme centre ; l'extrémité avant du film semi-conducteur de réfrigération (19) est superposée au film métallique (20), et l'extrémité arrière est connectée aux quatre électrodes de contact (11) ; la couche de congélation et la couche de chauffage (8) sont séparées par la première couche isolante (16) ; la couche de chauffage (8) comporte deux électrodes de contact (11) et un fil chauffant circulaire hélicoïdal (9) ; le fil chauffant (9) est situé au-dessus du film semi-conducteur de réfrigération (19) ; et de multiples petits trous sont formés dans la fenêtre centrale (52). La puce (1) présente les avantages de permettre une large gamme de régulation de la température, un taux de changement de température élevé et une observation dynamique in situ.
PCT/CN2020/108368 2020-08-11 2020-08-11 Puce à changement de température en phase liquide in situ à haute résolution pour microscope électronique à transmission, et son procédé de fabrication Ceased WO2022032470A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114689654A (zh) * 2022-03-31 2022-07-01 西安交通大学 一种多孔金属氧化物晶圆级微纳气体传感器及制备方法
CN116072559A (zh) * 2023-03-03 2023-05-05 江苏汇成光电有限公司 一种金凸块晶圆返工的工艺
CN117878019A (zh) * 2024-01-12 2024-04-12 韶关朗正数据半导体有限公司 一种高温特性的半导体芯片加工工艺
CN118150601A (zh) * 2024-05-13 2024-06-07 同济大学 一种用于分析有机-无机材料的界面结构及相互作用的电镜表征方法
CN119365062A (zh) * 2024-10-21 2025-01-24 中国科学院上海微系统与信息技术研究所 超导量子芯片封装结构及超导量子芯片的倒装封装方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882378A (zh) * 2015-04-09 2015-09-02 北京空间飞行器总体设计部 一种基于氧等离子体工艺的纳米介质层制备方法
JP2017004786A (ja) * 2015-06-11 2017-01-05 大日本印刷株式会社 電子顕微鏡観察用の試料保持チップ
CN109865541A (zh) * 2019-03-12 2019-06-11 厦门大学 一种扫描电镜原位电化学检测芯片及其制作方法
CN110736760A (zh) * 2019-10-28 2020-01-31 厦门超新芯科技有限公司 一种透射电镜原位电化学检测芯片及其制作方法
CN111312573A (zh) * 2020-03-12 2020-06-19 厦门超新芯科技有限公司 一种透射电镜高分辨原位液相加热芯片及其制备方法
CN111370280A (zh) * 2020-03-12 2020-07-03 厦门超新芯科技有限公司 一种透射电镜高分辨原位气相加热芯片及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882378A (zh) * 2015-04-09 2015-09-02 北京空间飞行器总体设计部 一种基于氧等离子体工艺的纳米介质层制备方法
JP2017004786A (ja) * 2015-06-11 2017-01-05 大日本印刷株式会社 電子顕微鏡観察用の試料保持チップ
CN109865541A (zh) * 2019-03-12 2019-06-11 厦门大学 一种扫描电镜原位电化学检测芯片及其制作方法
CN110736760A (zh) * 2019-10-28 2020-01-31 厦门超新芯科技有限公司 一种透射电镜原位电化学检测芯片及其制作方法
CN111312573A (zh) * 2020-03-12 2020-06-19 厦门超新芯科技有限公司 一种透射电镜高分辨原位液相加热芯片及其制备方法
CN111370280A (zh) * 2020-03-12 2020-07-03 厦门超新芯科技有限公司 一种透射电镜高分辨原位气相加热芯片及其制备方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114689654A (zh) * 2022-03-31 2022-07-01 西安交通大学 一种多孔金属氧化物晶圆级微纳气体传感器及制备方法
CN116072559A (zh) * 2023-03-03 2023-05-05 江苏汇成光电有限公司 一种金凸块晶圆返工的工艺
CN117878019A (zh) * 2024-01-12 2024-04-12 韶关朗正数据半导体有限公司 一种高温特性的半导体芯片加工工艺
CN118150601A (zh) * 2024-05-13 2024-06-07 同济大学 一种用于分析有机-无机材料的界面结构及相互作用的电镜表征方法
CN119365062A (zh) * 2024-10-21 2025-01-24 中国科学院上海微系统与信息技术研究所 超导量子芯片封装结构及超导量子芯片的倒装封装方法

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