WO2022010487A1

WO2022010487A1 - Color crosstalk compensation for flat panel displays

Info

Publication number: WO2022010487A1
Application number: PCT/US2020/041534
Authority: WO
Inventors: Sangmoo Choi; Sun-Il Chang
Original assignee: Google LLC
Current assignee: Google LLC
Priority date: 2020-07-10
Filing date: 2020-07-10
Publication date: 2022-01-13
Anticipated expiration: 2023-01-10

Abstract

An example device for controlling a display includes a memory configured to store gray values of subpixels of a pixel and a display system communicatively coupled to the memory. The display system is configured to obtain a gray value for a first subpixel of the pixel from the memory and obtain a gray value for a second subpixel of the pixel from the memory. The display system is also configured to determine, based on the gray value for the second subpixel, an adjusted gray value for the first subpixel and output the adjusted gray value for the first subpixel.

Description

COLOR CROSSTALK COMPENSATION FOR FLAT PANEL DISPLAYS

BACKGROUND

[0001] Flat panel displays are pervasive today. Flat panel displays are found in televisions, mobile phones, cameras, vehicles and many other devices. In the past few decades the resolution of flat panel displays has increased significantly. For example, flat panel displays in televisions were once standard definition, then high definition, then 4K displays became available and now 8K displays are available. Similarly, resolutions of displays for mobile phones have included 480 x 800, 640 x 1136, 720 x 1280, 750 x 1334, 1080 x 1920, 1440 x 2560, and now 2160 x 3840.

[0002] As the resolution of flat panel displays improves, pixels are being placed closer to each other. There is less room between pixels and between subpixels (each of the color components, red, blue and green (RGB) of a pixel is a subpixel) of a pixel within a screen of a similar size compared to a lower resolution display. The placement of more pixels within a screen may lead to parasitic capacitance affecting the subpixels displaying an image and therefore may negatively impact the viewing experience of a viewer.

SUMMARY

[0003] In general, techniques of this disclosure are directed to color crosstalk compensation techniques. Parasitic capacitance may not only exist within a subpixel, but may also exist between neighboring subpixels. This may be due to the closeness of a given subpixel to a neighboring subpixel. As most subpixels neighbor subpixels of a different color, the parasitic capacitance between subpixels may lead to color crosstalk.

[0004] According to the techniques of this disclosure, a display system may compensate for color crosstalk between subpixels. For example, the display system may obtain a gray value for a first subpixel and a gray value for a second subpixel. The display system may adjust the gray value for the first subpixel based on the gray value for the second subpixel and output an adjusted gray value for the first subpixel.

[0005] In one example, various aspects of the techniques are directed to a method comprising: obtaining, by a display system, obtaining, by the display system, a gray value for a first subpixel of a pixel; obtaining, by the display system, a gray value for a second subpixel of the pixel; determining, by the display system and based on the gray value for the second subpixel, an adjusted gray value for the first subpixel; and outputting, by the display system, the adjusted gray value for the first subpixel.

[0006] In another example, various aspects of the techniques are directed to a device for controlling a display comprising a memory configured to store gray values of subpixels of a pixel; and a display system communicatively coupled to the memory and being configured to: obtain a gray value for a first subpixel of the pixel from the memory; obtain a gray value for a second subpixel of the pixel from the memory; determine, based on the gray value for the second subpixel, an adjusted gray value for the first subpixel; and output the adjusted gray value for the first subpixel.

[0007] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. l is a block diagram illustrating example display system that may utilize the techniques described in this disclosure.

[0009] FIG. 2 is a conceptual diagram illustrating an example of a red subpixel.

[0010] FIG. 3 is a block diagram illustrating example pixels of an RGB (red, green, blue) stripe pixel layout in a display.

[0011] FIG. 4 is a timing diagram illustrating an example of timing of signals for the example display of FIG. 3.

[0012] FIG. 5 is a block diagram illustrating example pixels of a pentile pixel layout in a display.

[0013] FIG. 6 is a timing diagram illustrating an example of timing of signals for the example display of FIG. 5.

[0014] FIG. 7 is a circuit diagram illustrating an example of parasitic capacitance with an AMOLED (active matrix organic light emitting diode) pixel.

[0015] FIG. 8 is a timing diagram illustrating an example of the timing of the parasitic capacitance of the example of FIG. 7.

[0016] FIG. 9 is a block diagram illustrating example pixels of another pixel layout in a display for which the techniques of this disclosure may be used.

[0017] FIG. 10 is circuit diagram illustrating an example of parasitic capacitance with an AMOLED pixel and between two AMOLED subpixels. [0018] FIG. 11 is a timing diagram illustrating an example of the timing of the parasitic capacitance of the example display of FIG. 10.

[0019] FIG. 12 is a block diagram illustrating example color crosstalk compensation techniques according to the present disclosure.

[0020] FIG. 13 is a flowchart of an example of the color crosstalk compensation techniques of this disclosure.

[0021] FIG. 14 is a block diagram illustrating example pixels of another pixel layout in a display for which the techniques of this disclosure may be used.

[0022] FIG. 15 is a block diagram illustrating example pixels of another pixel layout in a display for which the techniques of this disclosure may be used.

DETAILED DESCRIPTION

[0023] As the resolution and pixel density increases and emission efficiency increases in displays (e.g., for mobile devices), a small parasitic capacitance between the emissive areas and the pixel circuit electrodes is occurring. This parasitic capacitance may cause color crosstalk between neighboring subpixels. For example, the parasitic capacitance may cause undesired changes to luminance of subpixels, including neighboring subpixels which may distort images being displayed on the display. As such, the techniques of this disclosure provide for a display system that adjusts signals output to one or more subpixels based on characteristics of one or more neighboring subpixels to offset the parasitic capacitance. In some examples, a first offset for a first subpixel may be applied to a first subpixel value to compensate for the parasitic capacitance caused by a second subpixel, while a second offset for the second subpixel may be applied to a second subpixel value to compensate for the parasitic capacitance caused by the first subpixel.

[0024] A number of different example configurations of subpixel circuitry and corresponding emissive areas are presented herein. Typically, the emissive areas of subpixels are located on top of the corresponding pixel circuitry. However, in some examples, according to the techniques of this disclosure, the emissive areas of subpixels may be located elsewhere.

[0025] FIG. l is a block diagram illustrating an example display system that may utilize the techniques described in this disclosure. In some examples, display system 10 of FIG. 1 may be part of an organic light emitting diode (OLED) or active matrix OLED (AMOLED) display or a device containing an OLED or AMOLED display. Display system 10 is coupled to display pixel array 20. Display pixel array 20 includes a plurality of pixels (not shown for simplicity purposes) arranged in an array. In this manner a pixel may be a part of an OLED or AMOLED display. Each pixel may include subpixels. For example, a pixel may include a red subpixel, a green subpixel and a blue subpixel. In some examples, different pixels may include different types of subpixels. For example, all pixels may not include a red subpixel, a green subpixel, and a blue subpixel.

[0026] The pixels of display pixel array 20 are driven by scan line driver (SLD) 18A and SLD 18B in the horizontal direction. The pixels of display pixel array 20 are also driven by column line driver 16. A timing controller 14 may provide gate driver input signals, such as clocks and/or start pulses, to SLD 18 A, SLD 18B, and column line driver 16. Display system 10 receives display image data from system on a chip (SoC) 12 to be displayed on display pixel array 20. In some examples, SoC 12 may comprise elements of a mobile telephone. In some examples, SoC may comprise a display processor, a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any combination thereof. In the example of FIG. 1, SoC 12 includes memory 8. In some examples, memory 8 may be a separate component. As used herein, display system 10 does not include a video decoder or filters typically included in a video decoder implementation, such as deblocking filters or other video decoder filters, although in some examples, SoC 12 may also include a video decoder or filters typically included in a video decoder implementation.

[0027] Because of the possible layout of subpixel circuitry and subpixel emissive areas, as well as pixel density in displays, a display may experience color crosstalk which may alter the resulting image shown on the display thereby causing undesired visual effects. Color crosstalk occurs when the intensity or gray value for a subpixel of one color affects the intensity or gray value for a neighboring subpixel of another color, for example for a single frame of display data. For example, when a red subpixel of a pixel has one gray value and a green subpixel of the pixel has a different gray value than the red subpixel, the actual displayed intensity may be affected by the displayed intensity of the neighboring green subpixel. This color crosstalk may occur because of parasitic capacitance between the neighboring subpixels which may change the voltage being applied to the affected subpixel thereby changing the intensity being displayed by the affected subpixel. The techniques of this disclosure may be used to compensate for color crosstalk.

[0028] Display system 10 of FIG. 1 may implement the techniques of this disclosure. For example, timing controller 14 may obtain a gray value for a first subpixel from SoC 12. Timing controller 14 may obtain a gray value for a second subpixel from SoC 12. Timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof may adjust the gray value for the first subpixel based on the gray value for the second subpixel. For example, timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof may change a voltage level corresponding to the obtained gray value to be supplied to first subpixel circuitry which may be part of display pixel array 20. In this manner, display system 10 may compensate for color crosstalk.

[0029] In another example, SoC 12 may obtain a gray value for a first subpixel, for example from memory 8. SoC 12 may obtain a gray value for a second subpixel from memory 8.

SoC 12 may adjust the gray value for the first subpixel based on the gray value for the second subpixel. For example, SoC 12 may change the obtained gray value for the first subpixel. In this manner, display system 10 may compensate for color crosstalk and the undesirable visual effects caused by color crosstalk

[0030] FIG. 2 is a conceptual diagram illustrating an example of a red subpixel. Red subpixel 48 may be an example of a red subpixel within display pixel array 20. Red subpixel 48 includes substrate 22. On substrate 22 is a semiconductor layer (SEMICON) 24 and an insulator layer 26. Metal layer 28 is in contact with semiconductor layer 24 through insulator layer 26, insulator layer 32, and insulator layer 34. Another metal layer 30 is disposed between insulator layer 26 and insulator layer 32.

[0031] Metal layer 28 is disposed between insulator layer 34 and insulator layer 36. Anode metal layer 38, which forms the anode for red subpixel 48, is in contact with metal layer 28 and disposed between insulator layer 36 and insulator layer 40. An emissive red OLED layer is disposed on top of insulator layer 40 and in contact with anode metal layer 38. A transparent cathode metal layer 44 may be disposed on top of insulator layer 40 and emissive red OLED layer 42. In this way, emissive red OLED layer 42 may be driven by signaling from semiconductor layer 24 through metal layer 28 and anode metal layer 38 so as to cause emissive red OLED layer 42 to emit red light in red emissive area 46. Green subpixels and blue subpixels may be similarly constructed. Red subpixel 48 may be an example of a first subpixel whose gray value may be adjusted according to the techniques of this invention.

Red subpixel 48 may alternatively be an example of a second subpixel, whose value may be used by display system 10, such as any of SoC 12, timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof, to adjust the gray value for a first subpixel.

[0032] FIG. 3 is a block diagram illustrating example pixels of an RGB (red, green, blue) stripe pixel layout in a display. In the example of FIG. 3, six pixels are shown. Each pixel in this example includes three subpixels, one red (denoted by starting with the letter R), one green (denoted by starting with the letter G) and one blue (denoted by starting with the letter B). The emissive areas of each subpixel are shown with a pattern fill. For example, the emissive area of red subpixels is shown with a diagonal pattern. The emissive area of the green subpixels is shown with a vertical striping pattern. The emissive area of the blue subpixels is shown with a cross-hatched pattern. This convention for shading and letter numbering for subpixels is used throughout this disclosure.

[0033] Pixel 50 includes subpixel R11, subpixel Gil, and subpixel B11. Pixel 52 includes subpixel R12, subpixel G12, and subpixel B12. Pixel 54 includes subpixel R13, subpixel G13, and subpixel B13. Pixel 56 includes subpixel R21, subpixel G21, and subpixel B21. Pixel 58 includes subpixel R22, subpixel G22, and subpixel B22. Pixel 60 includes subpixel R23, subpixel G23, and subpixel B23.

[0034] As can be seen, the layout of the subpixels in the example of FIG. 3 is a repetition of vertical red, green, and blue stripes. For example, subpixels R11, R12, and R13 make up a red stripe. Subpixels Gil, G12, and G13 make up a green stripe. Subpixels B11, B12, and B13 make up a blue stripe. This pattern is repeated in pixels 56, 58, and 60.

[0035] Inputs SI, S2, S3, S4, S5, and S6 are shown and provide column data signals for display to the subpixels from, for example, column line driver 16 of FIG. 1. Row scan signal lines are not shown in FIG. 3 for simplicity purposes. Input SI is coupled to subpixels R11, R12, and R13. Input S2 is coupled to subpixels G11, G12, and G13. Input S3 is coupled to subpixels B11, B12, and B13. Input S4 is coupled to subpixels R21, R22, and R23. Input S5 is coupled to subpixels G21, G22 and G23. Input S6 is coupled to subpixels B21, B22, and B23. The red subpixel of FIG. 2, may be an example of a red subpixel of FIG. 3, such as subpixel R11 of pixel 50.

[0036] The RGB stripe pixel layout may be used in a display which may implement the techniques of this disclosure. For example, display system 10, such as any of SoC 12, timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof, may obtain a gray value for a first subpixel, e.g., red subpixel R11. Display system 10 may obtain a gray value for a second subpixel, e.g., green subpixel Gil. Display system 10 may adjust the gray value for the first subpixel, e.g., red subpixel R11 based on the gray value for the second subpixel, e.g., green subpixel Gil. Display system 10 may then output the adjusted gray value for the first subpixel, e.g., red subpixel Rll. In this manner, color crosstalk that may exist between red subpixel R11 and green subpixel G11 may be compensated for.

[0037] FIG. 4 is a timing diagram illustrating an example of timing of signals for the example display of FIG. 3. Scan[l] 62, scan[2] 64 and scan[3] 66 represent driver signals from scan line drivers 18A or 18B of FIG. 1 (not shown in FIG. 3 for simplicity purposes). SI 68 and S270 represent data signals on inputs SI and S2 of FIG. 3 from, for example, column line driver 16 of FIG. 1. Scan[l] 62 drives the first row of subpixels, such as subpixels R11, G11, and B11 of pixel 50 and subpixels R21, G21, and B21 of pixel 56. SI graph 68 shows R11 being driven by the low signal of scan[l] 62 and S2 graph 70 shows G11 being driven by the low signal of scan[l] 62.

[0038] Scan[2] 64 drives the second row of subpixels, such as subpixels R12, G12, and B 12 of pixel 52 and subpixels R22, G22 and B22 of pixel 58. SI graph 68 shows R12 being driven by the low signal of scan[2] 64 and S2 graph 70 shows G12 being driven by the low signal of scan[2] 64.

[0039] Scan[3] 66 drives the third row of subpixels, such as subpixels R13, G13, and B13 of pixel 54 and subpixels R23, G23, and B23 of pixel 60. SI graph 68 shows R13 being driven by the low signal of scan[3] 66 and S2 graph 70 shows G13 being driven by the low signal of scan[3] 66. In this manner the scan line driver signals from scan line drivers 18A and 18B may drive the refresh of data in the subpixels of the pixels of display pixel array 20.

[0040] FIG. 5 is a block diagram illustrating example pixels of a pentile pixel layout in a display. The example of FIG. 5 includes six pixels. However, each pixel only includes two subpixels. Pixel 72 includes red subpixel R11 and green subpixel Gil. Pixel 74 includes blue subpixel B12 and green subpixel G12. Pixel 76 includes red subpixel R13 and green subpixel G13. Pixel 78 includes blue subpixel B21 and green subpixel G21. Pixel 80 includes red subpixel 80 and green subpixel G22. Pixel 82 includes blue subpixel B23 and green subpixel G23. As in the example of FIG. 3, each of the subpixels of the example of FIG. 5 has its emissive area located on its respective circuitry. For example, the red subpixels have a red emissive area (diagonal stripes), the green subpixels have a green emissive area (vertical stripes), and the blue subpixels have a blue emissive area (cross- hatched).

[0041] In the example of FIG. 5, rather than have a vertical striped pattern of three colored subpixels as the example of FIG. 3, the pentile layout has vertical stripes of green subpixels separated by vertical stripes made up of alternating red subpixels and blue subpixels. As can be seen, in this example, the green emissive areas are smaller than the red emissive areas and the blue emissive areas. As there are more green subpixels in such a display, the size of the emissive area of the green subpixels may be smaller while maintaining the same or similar visual impact as with the RGB striped example of FIG. 3. [0042] In the example of FIG. 5, only four inputs (SI, S2, S3, and S4) are needed for the six pixels to provide column data signals for display to the subpixels from, for example, column line driver 16 of FIG. 1. Row scan signal lines are not shown in FIG. 5 for simplicity purposes. Input SI provides data to subpixels R11, B12, and R13. Input S2 provides data to subpixels G11, G12, and G13. Input S3 provides data to subpixels B21, R22 and B23. Input S4 provides data to subpixels G21, G22, and G23.

[0043] The pentile pixel layout of the example of FIG. 5 may be used in a display which may implement the techniques of this disclosure. For example, display system 10, such as any of SoC 12, timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof, may obtain a gray value for a first subpixel, e.g., red subpixel R11. Display system 10 may obtain a gray value for a second subpixel, e.g., green subpixel Gil. Display system 10 may adjust the gray value for the first subpixel, e.g., red subpixel R11 based on the gray value for the second subpixel, e.g., green subpixel Gil. Display system 10 may then output the adjusted gray value for the first subpixel, e.g., red subpixel Rll. In this manner, color crosstalk that may exist between red subpixel R11 and green subpixel G11 may be compensated for.

[0044] FIG. 6 is a timing diagram illustrating an example of timing of signals for the example of FIG. 5. Scan[l] 84, scan[2] 86 and scan[3] 88 represent driver signals from scan line drivers 18A or 18B of FIG. 1 (not shown in FIG. 5 for simplicity purposes). SI 90 and S2 92 represent data signals on inputs SI and S2 of FIG. 5 from, for example, column line driver 16 of FIG. 1. Scan[l] 84 drives the first row of subpixels, such as subpixels R11 and G11 of pixel 72 and subpixels B21 and G21 of pixel 78. SI graph 90 shows R11 being driven by the low signal of scan[l] 84 and S2 graph 92 shows G11 being driven by the low signal of scan[l] 84.

[0045] Scan[2] 86 drives the second row of subpixels, such as subpixels B 12 and G12 of pixel 74 and subpixels R22 and G22 of pixel 80. SI graph 90 shows B12 being driven by the low signal of scan[2] 86 and S2 graph 92 shows G12 being driven by the low signal of scan[2] 86.

[0046] Scan[3] 88 drives the third row of subpixels, such as subpixels R13 and G13 of pixel 76 and subpixels B23 and G23 of pixel 82. SI graph 90 shows R13 being driven by the low signal of scan[3] 88 and S2 graph 92 shows G13 being driven by the low signal of scan[3] 88. In this manner the scan line driver signals from scan line drivers 18A and 18B may drive the refresh of data in the subpixels of the pixels of display pixel array 20. [0047] FIG. 7 is a circuit diagram illustrating an example of parasitic capacitance with an AMOLED (active matrix organic light emitting diode) pixel. Data line 94 (DATA[K]) represents the column data input line which has been described as SI - S6 in FIG. 3 and SI - S4 in FIG. 5, and is shown coupled to transistor 96. The transistor is coupled to a scan line driver signal (SCAN[N]) from scan line driver 18A or 18B. Transistor 96 may also be coupled to a compensation circuit 98 (COMP CIRCUIT). Compensation circuit 98 may be coupled to a current source circuit 100 and capacitor CST. Current source circuit 100 may be coupled to a drain voltage VDD and transistor 102. Transistor 102 may be coupled to an anode (ANODE1) of an OLED (OLED1) which may be an example of the emissive area of a subpixel. The anode may also be coupled to a capacitor (COLEDI) and transistor 104. The capacitor COLEDI and OLED1 are both coupled to a source voltage Vss. Transistor 104 may be coupled to an initialization signal (SINIT[N]) and an initialization voltage (VINIT).

[0048] Parasitic capacitance is represented in the example of FIG. 7 by capacitor Cpi shown with dotted lines connecting the anode of OLED1 (ANODE1) with one side of capacitor CST. In the typical conventional pixel structure (such as that of the example of FIG. 3), the parasitic capacitance, CPI, between G1 and ANODE 1, affects the final electrode voltage at Gl, which changes the pixel’s luminance. Therefore, the VDATA for the pixel at a specific gray level of the color is defined to include the effect of Vci, resulting in the target pixel luminance at the pixel.

[0049] FIG. 8 is a timing diagram illustrating an example of the timing of the parasitic capacitance of the example of FIG. 7. When emission control signal, EM[N] 120 goes high, transistor 102 is turned off and the voltage at ANODE1 (VANODEI 130) starts to decay. When SINIT[N] 122 and SCAN[N] 124 go low, VGI 128 drops and VANODEI 130 is initialized to low. When reprograming the Gl electrode with a new voltage data, EM[N] 120 goes low while both SCAN[N] and SINIT[N] are high, then, current source circuit 100 provides the OLED1 emission current, IOLEDI to OLED1 through transistor 102. COLEDI rises to high as COLEDI is charged by IOLEDI. The voltage VGI 128 should remain at the programmed voltage level (represented in FIG. 8 by the dot-dash line), but because of the parasitic capacitance (represented by CPI), the voltage VGI rises by voltage AVGI.

[0050] DATA[K] 126 is also shown in FIG. 8. DATA[K] 126 represents the data to be displayed, for example, from DATA[K] 94 (FIG. 7).

[0051] With reference to FIG. 10, typically, the display structure is designed such that a parasitic capacitance CP2 between programming electrode Gl of one subpixel and a neighboring subpixel’s anode (ANODE2), is minimized and negligible, so that a parasitic capacitance between two neighboring subpixels (CP2 coupled voltage change) becomes trivial. However, in some pixel designs, the emissive areas (anode areas of OLEDs) and/or circuitry physically overlap significantly with neighboring subpixels, and the CP2 affects d VGI, resulting in an undesirable visual luminance difference at OLED1.

[0052] FIG. 9 is a block diagram illustrating example pixels of another pixel layout in a display for which the techniques of this disclosure may be used. This pixel arrangement may increase fabrication yield during the display manufacturing process by separating the subpixel emissive areas as much as possible. In the example of FIG. 9, the emissive areas overlap significantly with neighboring subpixels, which may result in a visual luminance difference. In this example, six pixels are shown and each pixel includes three subpixels: one red; one green; and one blue.

[0053] Pixel 140 includes subpixel Rll, subpixel Gil, and subpixel Bll. Pixel 142 includes subpixel R12, subpixel G12, and subpixel B12. Pixel 144 includes subpixel R13, subpixel G13, and subpixel B13. Pixel 146 includes subpixel R21, subpixel G21, and subpixel B21. Pixel 148 includes subpixel R22, subpixel G22, and subpixel B22. Pixel 150 includes subpixel R23, subpixel G23, and subpixel B23.

[0054] As can be seen, the layout of the subpixel circuitry in the example of FIG. 9 is similar to that of FIG. 3, namely a repetition of vertical red, green, and blue stripes. However, in the example of FIG. 9, the emissive areas for the red and green subpixels are laid out across the space between the red and green subpixel circuitry (the subpixel circuitry represented by the respective numbered boxes beneath the emissive areas). For example, the emissive area for subpixel R11 is located partially above subpixel R11 circuitry, partially above a gap between subpixel R11 circuitry and subpixel G11 circuitry, and partially above subpixel G11 circuitry. Similarly, the emissive area of subpixel G11 is located partially above subpixel G11 circuitry, partially above the gap between subpixel G11 circuitry and subpixel R11 circuitry, and partially above subpixel R11 circuitry. This pattern is repeated in each of the pixels of the example of FIG. 9. In this manner, the red and green subpixels of the example of FIG. 9 overlap. The overlapping of the subpixels in the example of FIG. 9 may increase the likelihood of color crosstalk.

[0055] Inputs SI, S2, S3, S4, S5, and S6 are shown in FIG. 9 and provide column data signals for display to the subpixels from, for example, column line driver 16 of FIG. 1. Row scan signal lines are not shown in FIG. 9 for simplicity purposes. Input SI provides data to subpixels Rll, R12, and R13. Input S2 provides data to subpixels Gil, G12, and G13. Input S3 provides data to subpixels Bll, B12, and B13. Input S4 provides data to subpixels R21, R22, and R23. Input S5 provides data to subpixels G21, G22 and G23. Input S6 provides data to subpixels B21, B22 and B23.

[0056] The example pixel layout of FIG. 9 may be used in a display which may implement the techniques of this disclosure. For example, display system 10, such as any of SoC 12, timing controller 14, SLD 18 A, SLD 18B, column line driver 16, or any combination thereof, may obtain a gray value for a first subpixel, e.g., red subpixel R11. Display system 10 may obtain a gray value for a second subpixel, e.g., green subpixel Gil. Display system 10 may adjust the gray value for the first subpixel, e.g., red subpixel R11 based on the gray value for the second subpixel, e.g., green subpixel Gil. Display system 10 may then output the adjusted gray value for the first subpixel, e.g., red subpixel Rll. In this manner, color crosstalk that may exist between red subpixel R11 and green subpixel G11 may be compensated for.

[0057] FIG. 10 is circuit diagram illustrating an example of parasitic capacitance within an AMOLED pixel and between two AMOLED subpixels. The example of FIG. 10 is similar to the example of FIG. 7, but there is also an additional parasitic capacitance caused by a neighboring subpixel in FIG. 10. For example, subpixel G11 of FIG. 9 may cause additional parasitic capacitance to subpixel R11 of FIG. 9 due to their overlapping orientation.

[0058] Data line 160 (DATA[K]) is shown coupled to transistor 162. Transistor 162 is coupled to a scan line driver signal (SCAN[N]) from scan line driver 18A or 18B. Transistor 162 may also be coupled to a compensation circuit 164 (COMP CIRCUIT). Compensation circuit 164 may be coupled to a current source circuit 166 and capacitor CST. Current source circuit 166 may be coupled to a drain voltage VDD and transistor 168. Transistor 168 may be coupled to an anode (ANODE1) of an OLED (OLED1) which may be an example of the emissive area of a subpixel. The anode may also be coupled to a capacitor (COLEDI) and transistor 170. The capacitor COLEDI and OLED1 are both coupled to a source voltage Vss. Transistor 170 may be coupled to an initialization signal (SINIT[N]) and an initialization voltage (VINIT).

[0059] Parasitic capacitance of the subpixel is represented in the example of FIG. 10 by capacitor Cpi shown with dotted lines connecting the anode of the OLED (ANODE 1) with one side of capacitor CST. However, due to the overlapping orientation of neighboring subpixels, an additional parasitic capacitance CP2 may exist between the anode of one subpixel (ANODE1) and the anode of a neighboring subpixel (ANODE2). For example, lower pixel luminance in OLED2 can causes brighter pixel luminance in OLED1 at the same gray level. Since the neighboring subpixels are typically for different colors, this crosstalk often appears as a color crosstalk.

[0060] FIG. 11 is a timing diagram illustrating an example of the timing of the parasitic capacitance of the example of FIG. 10. When EM[N] 178 goes high, the voltage at anode 1 (VANODEI 188) starts to decay and the voltage at anode 2 (VANODE2 190) also starts to decay. When SINIT[N] 180 and SCAN[N] 182 go low, VGI 186 drops and VANODEI 188 and VANODE2 190 are initialized to low. When EM[N] 178 goes low, VANODEI 188 rises as COLEDI is charged by IOLEDI. VANODE2 190 rises as COLED2 is charged by IOLED2. In FIG. 11, the VANODE2 190 after time 192 is shown as varying because the first subpixel and the second subpixel may have different gray values or intensities. For example, a red subpixel may be brighter or dimmer than a green subpixel. The voltage VGI 128 should remain low, but because of the parasitic capacitance (represented by Cpi and by CP2), the voltage VGI rises by a AVGI, which may be greater than in the example of FIG. 8.

[0061] DATA[K] 184 is also shown in FIG. 11. DATA[K] 184 may represent data to be displayed, for example, from DATA[K] 160.

[0062] The present disclosure describes techniques for adjusting the final voltage data to a subpixel circuit, VDATA, based on the pixel luminance/image data/data voltage of the neighboring subpixels.

[0063] FIG. 12 is a block diagram illustrating example color crosstalk compensation techniques according to the present disclosure. Target pixel luminance data 300 and neighboring pixel luminance data 302 are input to new target pixel luminance data generator 304. New target pixel luminance data generator 304 may represent an example of display system 10 and may be implemented in SoC 12, timing controller 14, SLD 18 A, SLD 18B, column line driver 16, or any combination thereof. New target pixel luminance data generator 304 may determine a new target pixel luminance value and output the new target pixel luminance value to pixel circuit programming 306 so as to provide data to the subpixel for display.

[0064] For example, when a red subpixel R11 has a target pixel luminance value of 255 gray and a neighboring green subpixel G11 also has a target pixel luminance value of 255 gray, no adjustment is necessary as both subpixels are equal in gray value. In this case, the new target pixel luminance value generated by new target pixel luminance data generator 304 may be the same as the target pixel luminance value, namely 255 gray. In this example, the voltage VDATA Rii may be, for example, 3.00 volts. In another example, when a red subpixel R11 has a target pixel luminance value of 255 gray and a neighboring green subpixel G11 has a target pixel luminance value of 127 gray, the new target pixel luminance value generated by new target pixel luminance data generator 304 may be 253 gray, as the parasitic capacitance from the green subpixel G11 may increase the voltage at ANODE1. In this example, the output voltage VDATA_RII may be, for example, 2.95 volts and the actual voltage at ANODE1 may be 3.00 volts, due to the parasitic capacitance caused by green subpixel Gil.

[0065] In some examples, new target pixel luminance data generator 304 may be implemented in one or more processors, such as an application processor, a display processor, a GPU, a GPGPU, or the like, for example, in which case that new target pixel luminance data generator 304 may output a digital signal representing an adjusted gray value for the data to be displayed by a subpixel. In this manner, new target pixel luminance data generator 304 may output an adjusted gray value for the subpixel. In some examples, new target pixel luminance data generator 304 may be implemented in a display driver integrated circuit, for example, in which case new target pixel luminance data generator 304 may output an adjusted analog voltage to be provided to the subpixel. In this manner, new target pixel luminance data generator 304 may output the adjusted gray value for the subpixel. In some examples, new target pixel luminance data generator 304 may be implemented in a combination of one or more processors and a display driver integrated circuit.

[0066] In some examples, new target pixel luminance data generator 304 may determine the new target pixel luminance through a look-up table which may be stored in memory 8. For example, a technician or engineer may determine the effect different luminance values have on the parasitic capacitance between different subpixels in a laboratory setting (e.g., during a calibration process) and may determine which offset should be applied to compensate for each different parasitic capacitance at each emission value of neighboring subpixels, and provide a look-up table for new target pixel luminance data generator 304.

[0067] In other examples, a technician or engineer may determine a formula (which may be stored in memory 8) that may be applied by new target pixel luminance data generator 304 to determine the new target pixel luminance data. In some examples, new target pixel luminance data generator 304 may also determine a new target pixel luminance value for the neighboring subpixel. For example, new target pixel luminance data generator 304 may determine a first offset for a first subpixel (e.g., R11) and apply the first offset to a first subpixel value to compensate for the parasitic capacitance caused by a second subpixel (e.g., G11) and new target pixel luminance data generator 304 may also determine a second offset for the second subpixel (e.g., G11) and apply the second offset to a second subpixel value to compensate for the parasitic capacitance caused by the first subpixel (e.g., R11). [0068] FIG. 13 is a flow diagram illustrating color crosstalk compensation techniques according to this disclosure. New target pixel luminance data generator 304 may obtain a gray value for a first subpixel (320). For example, new target pixel luminance data generator 304 may obtain the gray value for the first subpixel from memory 8. New target pixel luminance data generator 304 may also obtain the gray value for a second subpixel (322).

For example, new target pixel luminance data generator 304 may obtain the gray value for the first subpixel from memory 8. In some examples, new target pixel luminance data generator 304 may determine, based on the gray value for the second subpixel, an adjust the gray value for the first subpixel (326 following the dashed arrow of FIG. 13). For example, new target pixel luminance data generator 304 may look up an offset value in a look-up table in memory 8 or apply a formula which may be stored in memory 8 to determine an offset value for the gray value for the first subpixel. New target pixel luminance data generator 304 may apply the offset value to the gray value for the first subpixel to create an adjusted gray value for the first subpixel. New target pixel luminance data generator 304 may output the adjusted gray value for the first subpixel (328). For example, new target pixel luminance data generator 304 may output a digital signal representing the adjusted gray value or output an analog voltage corresponding to the adjusted gray value.

[0069] In some examples, determining the adjusted gray value for the first subpixel is performed by a display processor, such as SoC 12 or a portion thereof, of display system 10. For example, new target pixel luminance data generator may be implemented in a display processor. In some examples, display system 10 comprises a display driver, such as SLD 18 A, SLD 18B, or column line driver 16, and outputting the adjusted gray value for the first subpixel includes, changing, by the display driver, a voltage level corresponding to the adjusted gray value to be supplied to first subpixel circuitry, such as red subpixel 48 of FIG.

2

[0070] In some examples, new target pixel luminance data generator 304 may determine, based on the gray value for the first subpixel, an adjusted gray value for the second subpixel. New target pixel luminance data generator 304 may output the adjusted gray value for the second subpixel.

[0071] In some examples, the gray value for the first subpixel and the gray value of the second subpixel are gray values for a single frame display data. In some examples, a pixel includes two or more of a red subpixel, a green subpixel, or a blue subpixel. In some examples, the first subpixel is one of the red subpixel or the blue subpixel, and the second subpixel is a different one of the red subpixel or the blue subpixel. [0072] In some examples, it may be desirable to only adjust the gray value for the first subpixel when the first subpixel and the second subpixel overlap. In this case, new target pixel luminance data generator 304 may determine whether the first subpixel and the second subpixel overlap (324). For example, new target pixel luminance data generator 304 may look up whether the first subpixel and the second subpixel are overlapping in a look-up table which may be stored in memory 8. Subpixel layouts are known to display manufacturers, so whether or not two subpixels overlap may be information that may be placed in a look-up table. If the first subpixel and the second subpixel overlap (the “YES” path of FIG. 13), new target pixel luminance data generator 304 may determine an adjusted gray value for the first subpixel based on the gray value for the second subpixel (326). For example, the adjusted gray value may be based, at least in part on whether the first subpixel and the second subpixel overlap. For example, new target pixel luminance data generator 304 may look up an offset value in a look-up table or apply a formula to determine an offset value for the gray value for the first subpixel. New target pixel luminance data generator 304 may apply the offset value to the gray value for the first subpixel to create an adjusted gray value for the first subpixel. New target pixel luminance data generator 304 may output the adjusted gray value for the first subpixel (328). For example, new target pixel luminance data generator 304 may output a digital signal representing the adjusted gray value or output an analog voltage corresponding to the adjusted gray value.

[0073] If new target pixel luminance data generator 304 determines that the first subpixel and the second subpixel do not overlap (the “NO” path of FIG. 13), new target pixel luminance data generator 304 may output the gray value for the first subpixel (330). For example, new target pixel luminance data generator 304 may output a digital signal representing the gray value or output an analog voltage corresponding to the gray value.

[0074] In some examples, new target pixel luminance data generator 304 may obtain a gray value for a third subpixel of a second pixel and obtain a gray value for a fourth subpixel of the second pixel. New target pixel luminance data generator 304 may determine that the third subpixel and the fourth subpixel do not overlap and responsive to determining that the third subpixel and the fourth subpixel do not overlap, may output the gray value for the third subpixel. For example, new target pixel luminance data generator 304 may not adjust the gray value for the third subpixel.

[0075] In some cases, the arrangement of the emissive areas (anode patterns) of pixels in a display may vary between different columns and rows. [0076] FIG. 14 is a block diagram illustrating example pixels of another pixel layout in a display for which the techniques of this disclosure may be used. This emissive area placement may enable reducing the complexity of the pattern masks for the blue emissive areas in the fabrication process, and may increase the fabrication yield of the displays. In the example of FIG. 14, six pixels are shown. Each pixel in this example includes three subpixels: one red; one green; and one blue. In the example of FIG. 14, the arrangement of the emissive areas of the pixels varies between different columns and rows.

[0077] Pixel 200 includes subpixel R11, subpixel Gil, and subpixel B11. Pixel 202 includes subpixel R12, subpixel G12, and subpixel B12. Pixel 204 includes subpixel R13, subpixel G13, and subpixel B13. Pixel 206 includes subpixel R21, subpixel G21 and subpixel B21. Pixel 208 includes subpixel R22, subpixel G22, and subpixel B22. Pixel 210 includes subpixel R23, subpixel G23, and subpixel B23.

[0078] As can be seen, the layout of the subpixel circuitry in the example of FIG. 14 is similar of that of the example of FIGS. 3 and 9, namely a repetition of vertical red, green and blue stripes. However, the emissive areas of the blue subpixels change from pixel to pixel. For example, the emissive area of blue subpixel B11 in pixel 200 overlaps the blue subpixel B11 circuitry and the green subpixel G11 circuitry. In pixel 202, the emissive area of blue subpixel B12 does not overlap the circuitry of blue subpixel B12. Instead, the emissive area of blue subpixel B12 overlaps the circuitry of red subpixel R12 and the circuitry of green subpixel G12. In this example, green subpixel G11 may be affected significantly by voltage changes at blue subpixel B 11 as they are overlapping, but not necessarily red subpixel R11 as red subpixel R11 and blue subpixel B11 are not overlapping. However, both red subpixel R12 and green subpixel G12 may be affected by blue subpixel B12 as blue subpixel B12 is overlapping with both red subpixel R12 and blue subpixel B12.

[0079] Inputs SI, S2, S3, S4, S5, and S6 are shown and provide column data signals for display to the subpixels from, for example, column line driver 16 of FIG. 1. Row scan signal lines are not shown in FIG. 14 for simplicity purposes. Input SI provides data to subpixels R11, R12, and R13. Input S2 provides data to subpixels Gil, G12, and G13. Input S3 provides data to subpixels B11, B12, and B13. Input S4 provides data to subpixels R21, R22, and R23. Input S5 provides data to subpixels G21, G22, and G23. Input S6 provides data to subpixels B21, B22, and B23.

[0080] The pixel layout of the example of FIG. 14 may be used in a display which may implement the techniques of this disclosure. For example, display system 10, such as any of SoC 12, timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof, may obtain a gray value for a first subpixel, e.g., green subpixel Gil. Display system 10 may obtain a gray value for a second subpixel, e.g., blue subpixel B11. The display system may adjust the gray value for the first subpixel, e.g., green subpixel G11 based on the gray value for the second subpixel, e.g., blue subpixel B11. Display system 10 may then output the adjusted gray value for the first subpixel, e.g., green subpixel Gil. In this manner, color crosstalk that may exist between green subpixel G11 and blue subpixel B11 may be compensated for.

[0081] FIG. 15 is a block diagram illustrating example pixels of another pixel layout in a display for which the techniques of this disclosure may be used. As with the example of FIG. 5, each pixel in this example includes two subpixels: one red or blue, and one green. Such a pixel layout may decrease dynamic power consumption compared to more conventional layouts.

[0082] Pixel 220 includes red subpixel R11 and green subpixel G11. Pixel 222 includes the circuitry of red subpixel R22 along with the emissive area of blue subpixel B12, and green subpixel G12. Pixel 224 includes red subpixel R13 and green subpixel G13. Pixel 226 includes blue subpixel B21 and green subpixel G21. Pixel 228 includes the circuitry for blue subpixel B12, but with the emissive area of red subpixel R22, and green subpixel G22. Pixel 230 includes blue subpixel B23 and green subpixel G23.

[0083] Similar to the example of FIG. 5, the green emissive areas are smaller than the red emissive areas and the blue emissive areas. As there are more green subpixels in such a display, the size of the emissive area of the green subpixels may be smaller while maintaining the same or similar visual impact as other examples presented herein.

[0084] In the example of FIG. 15, only four inputs (SI, S2, S3, and S4) are needed for the six pixels to provide column data signals for display to the subpixels from, for example, column line driver 16 of FIG. 1. Row scan signal lines are not shown in FIG. 15 for simplicity purposes. Input SI provides data to subpixels R11, R22, and R13. Input S2 provides data to subpixels Gil, G12, and G13. Input S3 provides data to subpixels B21, B12, and B23. Input S4 provides data to subpixels G21, G22, and G23.

[0085] The pixel layout of the example of FIG. 15 may be used in a display which may implement the techniques of this disclosure. For example, display system 10, such as any of SoC 12, timing controller 14, SLD 18A, SLD 18B, column line driver 16, or any combination thereof, may obtain a gray value for a first subpixel, e.g., red subpixel R22. Display system 10 may obtain a gray value for a second subpixel, e.g., blue subpixel B12. Display system 10 may adjust the gray value for the first subpixel, e.g., red subpixel R22 based on the gray value for the second subpixel, e.g., blue subpixel B12. Display system 10 may then output the adjusted gray value for the first subpixel, e.g., subpixel R22. In this manner, color crosstalk that may exist between red subpixel R22 and blue subpixel B12 may be compensated for.

[0086] In the example of FIG. 15, the red and blue pixel circuits in even row lines have overlapping emissive areas of a different color, while the pixels in odd row lines have the same color emissive areas on top of the pixel circuits. In this example, the VDATA adjustment may be performed only for the red and/or blue pixel circuits in the even row lines, for example.

[0087] By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other storage medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer- readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage mediums and media and data storage media do not include connections, carrier waves, signals, or other transient media, but are instead directed to non transient, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable medium.

[0088] Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules. Also, the techniques could be fully implemented in one or more circuits or logic elements. [0089] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

[0090] Various embodiments have been described. These and other embodiments are within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:

1. A method comprising: obtaining, by a display system, a gray value for a first subpixel of a pixel; obtaining, by the display system, a gray value for a second subpixel of the pixel; determining, by the display system and based on the gray value for the second subpixel, an adjusted gray value for the first subpixel; and outputting, by the display system, the adjusted gray value for the first subpixel.

2. The method of claim 1, further comprising: determining, by the display system, whether the first subpixel and the second subpixel overlap, wherein the adjusted gray value for the first subpixel is further based on whether the first subpixel and the second subpixel overlap.

3. The method of claim 1, further comprising: obtaining, by the display system, a gray value for a third subpixel of a second pixel; obtaining, by the display system, a gray value for a fourth subpixel of the second pixel; determining, by the display system, whether the third subpixel and the fourth subpixel overlap; and responsive to determining that the third subpixel and the fourth subpixel do not overlap, outputting the gray value for the third subpixel.

4. The method of claim 1, further comprising: determining, by the display system and based on the gray value for the first subpixel, an adjusted gray value for the second subpixel; and outputting, by the display system, the adjusted gray value for the second subpixel.

5. The method of claim 1, wherein determining the adjusted gray value for the first subpixel is performed by a display processor of the display system.

6. The method of claim 1, wherein the display system comprises a display driver, and wherein outputting the adjusted gray value for the first subpixel includes changing, by the display driver, a voltage level corresponding to the adjusted gray value to be supplied to first subpixel circuitry.

7. The method of claim 1, wherein the first subpixel and the second subpixel have overlapping emissive areas or circuitry.

8. The method of claim 1, wherein the pixel is part of an organic light emitting diode display or an active matrix organic light emitting diode display.

9. The method of claim 1, wherein the pixel includes two or more of a red subpixel, a green subpixel, or a blue subpixel, wherein the first subpixel is one of the red subpixel or the blue subpixel, and wherein the second subpixel is a different one of the red subpixel or the blue subpixel.

10. The method of claim 1, wherein the gray value for the first subpixel and the gray value for the second subpixel are gray values for a single frame of display data.

11. A device for controlling a display comprising: a memory configured to store gray values of subpixels of a pixel; and display system communicatively coupled to the memory and being configured to: obtain a gray value for a first subpixel of the pixel from the memory; obtain a gray value for a second subpixel of the pixel from the memory; determine, based on the gray value for the second subpixel, an adjusted gray value for the first subpixel; and output the adjusted gray value for the first subpixel.

12. The device of claim 11, wherein the display system is further configured to: determine whether the first subpixel and the second subpixel overlap, wherein the adjusted gray value for the first subpixel is further based on whether the first subpixel and the second subpixel overlap.

13. The device of claim 12, wherein the display system is further configured to: obtain a gray value for a third subpixel of a second pixel from the memory; obtain a gray value for a fourth subpixel of the second pixel from the memory; determine whether the third subpixel and the fourth subpixel overlap; and responsive to determining that the third subpixel and the fourth subpixel do not overlap, output the gray value for the third subpixel.

14. The device of claim 11, wherein the display system is further configured to: determine, based upon the gray value for the first subpixel, an adjusted gray value for the second subpixel; and output the adjusted gray value for the second subpixel.

15. The device of claim 11, wherein the display system comprises a display processor and wherein the display processor determines the adjusted gray value for the first subpixel.

16. The device of claim 11, wherein the display system comprises a display driver, and wherein outputting the adjusted gray value for the first subpixel includes changing, by the display driver, a voltage level corresponding to the adjusted gray value to be supplied to first subpixel circuitry.

17. The device of claim 11, wherein the first subpixel and the second subpixel have overlapping emissive areas or circuitry.

18. The device of claim 11, wherein the first subpixel is part of an organic light emitting diode display or an active matrix organic light emitting diode display.

19. The device of claim 11, wherein the pixel includes two or more of a red subpixel, a green subpixel, or a blue subpixel, wherein the first subpixel is one of the red subpixel or the blue subpixel, and wherein the second subpixel is a different one of the red subpixel or the blue subpixel.

20. The device of claim 11, wherein the gray value for the first subpixel and the gray value for the second subpixel are gray values for a single frame of display data.