WO2022041154A1 - Hold time margin detection circuit - Google Patents

Abstract

Embodiments of the present application relate to the technical field of circuits. Disclosed is a hold time margin detection circuit, mitigating the problem in the prior art of poor precision in detection for a hold time margin in a chip. The specific solution is that: the detection circuit comprises: a generator and a decision circuit; the generator comprises at least one testing circuit; each testing circuit comprises N first flip flops, N second flip flops, and N data delay units; the delay of the N data delay units increases gradually in sequence; a delay difference between two adjacent data delay units is less than or equal to a preset value; data output ends of the N first flip flops are respectively connected to input ends of the N data delay units; output ends of the N data delay units are respectively connected to data input ends of the N second flip flops; data output ends of the N second flip flops are connected to the decision circuit.

Description

A detection circuit for keeping time margin technical field

The embodiments of the present application relate to the technical field of circuits, and in particular, to a detection circuit that maintains a time margin.

Background technique

Timing design and analysis is one of the important aspects of chip design. In the design of large-scale system on chip (SOC), static timing analysis (STA) method is usually used to ensure the timeliness of the design iteration cycle. . STA is an analysis method that covers boundary conditions. For example, the boundary conditions can be covered by pessimism to simulate the performance changes of different tubes inside the chip due to process deviations, voltage drops, and temperature changes. However, if the boundary conditions are set too strict, the design difficulty will be greatly increased, and at the same time, too many Die resources will be occupied, which will reduce the competitiveness of the product. If the boundary conditions are set too loose, quality problems may occur, resulting in a series of index problems or even failure of the chip to work.

Figure 1 shows an existing intellectual property (IP) design (patent number: US7930663B2). As shown in Figure 1, the data output end Q0 of the register (flip flop, FF0) is connected to the data input end D of the register FF1 , the data output terminal Q1 of the register FF1 is connected to the data input terminal D of the register FF2, and a delay line delay0 (delay line) is formed between the clock terminal of the register FF0 and the clock terminal Clk1 of the register FF1 by using a standard cell (standard cell, stdcell). ), a delay line delay0 is formed between the clock terminal Clk1 of the register FF1 and the clock terminal Clk2 of the register FF2 through the stdcell, and the initial state of the circuit is configured to maintain a successful state. By adjusting the delay selection modules delaySel1 and delaySe2 The signal configuration, select With different delay values, until the circuit appears in the hold fail state, the peripheral circuit detects the hold success state and hold fail state of the sequence of the circuit to be tested, and then reads the test results through the bus to obtain the hold time margin. Quantity, so as to provide a basis for the upgrade of the next generation of chips.

In this IP design, the delay line (delay line) composed of the standard unit stdcell has poor accuracy in detecting the hold time. However, in the process of 28nm and below, depending on the size of the SOC, the number of timing violations caused by the uncertainty of 1ps may be one hundred thousand or even one million. Therefore, if the lack of precision is applied in practical projects, it means that it will face a great risk of timing violation, so this scheme does not have obvious practical engineering significance.

SUMMARY OF THE INVENTION

The embodiment of the present application provides a detection circuit for maintaining a time margin, which can improve the detection accuracy of maintaining the time margin.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

A first aspect of the embodiments of the present application provides a detection circuit for maintaining a time margin. The detection circuit includes: a controller, a generator, and a decision circuit; the generator includes at least one group of test circuits, and each group of test circuits includes N The first register, the N second registers, and the N data delay units, the delays of the N data delay units are sequentially increased, and the delay difference between two adjacent data delay units is less than or equal to the preset value, and N is An integer greater than 1; wherein the controller, the clock terminals of the N first registers and the clock terminals of the N second registers are connected to the same clock output terminal of the controller, and the data output terminals of the N first registers are respectively connected to the N The input ends of the data delay units are connected, the output ends of the N data delay units are respectively connected with the data input ends of the N second registers, and the data output ends of the N second registers are connected with the judgment circuit; the judgment circuit is used to detect the N second registers. The output state of the second register, and the output state of the N second registers is transmitted to the controller. Based on this solution, by setting N data delay units between the N first registers and the N second registers, and the delays of the N data delay units are sequentially increased, the delays of the data paths of the N groups of registers are different from each other. same. Since the delay of the data path from the first register to the second register is greater than the delay of the clock path, the output state of the second register is the hold-success state; when the delay of the data path from the first register to the second register is less than the clock The time delay of the path, the output state of the second register is the hold failure state. Therefore, by setting N data delay units whose delays increase sequentially between the N first registers and the N second registers, the delays of the data paths from the N first registers to the N second registers are different from each other. , so the output state of a part of the second registers in the N registers is a hold failure state, and the output state of another part of the registers is a hold success state. According to the second register from the hold failure to the hold success, the hold time margin can be detected, and this application The step accuracy of the delay increment of the N data delay units is smaller than the preset value. Therefore, based on the hold failure state and hold success state of the second register, the accuracy of the detected hold time margin is high. Based on the detection result, the It can provide a strong basis for the design of the next-generation chips, making the products of the next-generation chips more competitive. It can be understood that a first register and a second register connected to the register through a data delay unit may be referred to as a group of registers.

With reference to the first aspect, in a possible implementation manner, the N data delay units respectively include N S-shaped metal windings, and the lengths of the N S-shaped metal windings increase sequentially. Based on this solution, the lengths of the N S-shaped metal windings are sequentially increased, so that the delay of the data path of the N groups of registers is sequentially increased, and the retention time can be controlled by designing the length difference between two adjacent S-shaped metal windings. The detection accuracy of the margin makes the detection retention time margin more accurate.

With reference to the first aspect and the above possible implementation manner, in another possible implementation manner, the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings is the same. Based on this solution, the detection accuracy of the retention time margin can be controlled by setting the length difference between two adjacent S-shaped metal windings, so that the detection accuracy of the retention time margin is high. It can be understood that due to the nonlinear characteristics of metal, when the lengths of N S-shaped metal windings increase sequentially, and the two adjacent S-shaped windings increase by the same length, the delays of the N data delay units increase sequentially. , but the delay difference (stepping precision) of two adjacent data delay units is not exactly the same.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, the S-shaped metal winding includes a first turning portion, a second turning portion, and one or more splicable portions, different S-shaped metal windings. The number of spliceable parts included in the winding varies. Based on this scheme, by designing the S-shaped metal winding into a splicable module, S-shaped metal windings of different lengths can be realized by increasing the number of splicable parts. This method has good controllability and can be adjusted according to the design scale. Different, the required delay value is different, the splicing can be freely realized, and the secondary inspection is convenient, which has good practical engineering significance.

In combination with the first aspect and the above possible implementation manners, in another possible implementation manner, the first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding; or, the second turning portion Including the input end of the S-shaped metal winding and the output end of the S-shaped metal winding. Based on this solution, the input end of the S-shaped metal winding and the output end of the S-shaped metal winding can be arranged on the same side.

In combination with the first aspect and the above possible implementation manners, in another possible implementation manner, the first turning portion includes an input end of the S-shaped metal wire, and the second turning portion includes an output end of the S-shaped metal wire; or , the first turning portion includes the output end of the S-shaped metal winding, and the second turning portion includes the input end of the S-shaped metal winding. Based on this solution, the input end of the S-shaped metal winding and the output end of the S-shaped metal winding can be arranged on different sides.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, the detection circuit further includes a clock selector and a clock delay circuit, the controller and the input end of the clock selector, and the data selection end of the clock selector. , and the clock terminals of the N first registers are connected, the output terminal of the clock selector is connected to the input terminal of the clock delay circuit, and the output terminal of the clock delay circuit is connected to the clock terminals of the N second registers. Based on this solution, the clock selection module can be selected by the clock selector to perform large-scale adjustment, so that the output states of the N second registers have both a hold fail state and a hold pass state.

With reference to the first aspect and the above possible implementation manner, in another possible implementation manner, the clock delay circuit includes M clock delay units, and the M clock delay units respectively have M different delays. Based on this scheme, the delay on the clock path can be adjusted by having M clock delay units with different delays.

With reference to the first aspect and the above possible implementation manner, in another possible implementation manner, the controller is specifically configured to time-division control the clock selector to sequentially select each clock delay unit in the M clock delay units. Based on this scheme, by selecting different clock delay units by time division by the controller, large-scale adjustment can be performed, so that the output states of the N second registers have both a hold fail state and a hold pass state.

Combining the first aspect and the above possible implementation manner, in another possible implementation manner, the controller is specifically configured to: control the clock selector to select the first clock delay unit in the M clock delay units; if N second clock delay units The output states of the registers are all maintained successfully, and the controller controls the clock selector to select a second clock delay unit in the M clock delay units, and the delay of the second clock delay unit is greater than the delay of the first clock delay unit; If the output states of the N second registers are all fail to hold, the controller controls the clock selector to select a third clock delay unit among the M clock delay units, and the delay of the third clock delay unit is smaller than that of the first clock delay unit delay. Based on this solution, the controller closed-loop controls the clock selector to select the clock delay unit, so that the output states of the N second registers have both a hold fail state and a hold pass state.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, the detection circuit further includes an interface circuit, the controller is connected to the interface circuit, and the controller is further configured to transmit the output states of the N second registers. to the interface circuit. Based on this solution, the output states of the N second registers can be transmitted to the external device through the interface circuit, and based on the output states of the N second registers and the simulation results, it can be determined whether the boundary conditions in the design stage are too strict or too loose .

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, the process voltage and temperature PVT of the N first registers and the N second registers in the same group of test circuits are the same, and the PVT is a standard voltage threshold. SVT, Low Voltage Threshold LVT or Ultra Low Voltage Threshold ULVT. Based on this solution, test circuits of different PVTs can be set in the detection circuit, which can adapt to the process of different chips.

In a second aspect of the embodiments of the present application, an apparatus is provided, which includes a circuit board and a detection circuit for maintaining a time margin according to any one of the above-mentioned first aspect or possible implementation manners of the first aspect.

Description of drawings

FIG. 1 is a schematic diagram of an IP design of a detection time margin provided by an embodiment of the present application;

2 is a schematic diagram of a synchronous sequential circuit according to an embodiment of the present application;

3 is a schematic diagram of a detection circuit for maintaining a time margin provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a data delay unit according to an embodiment of the present application;

5 is a schematic diagram of the time delay and step accuracy of a data delay unit provided by an embodiment of the present application;

6 is a schematic diagram of a simulation result and a test result provided by an embodiment of the present application;

7 is a schematic diagram of another simulation result and test result provided by an embodiment of the present application;

8 is a schematic diagram of the division of an S-shaped metal winding according to an embodiment of the present application;

FIG. 9 is a schematic diagram of wiring of an S-shaped metal winding according to an embodiment of the present application;

FIG. 10 is a schematic diagram of the wiring of another S-shaped metal winding according to an embodiment of the application;

11 is a schematic diagram of another detection circuit for maintaining a time margin provided by an embodiment of the present application;

12 is a schematic diagram of another detection circuit for maintaining a time margin provided by an embodiment of the present application;

FIG. 13 is a schematic diagram of another detection circuit for maintaining a time margin provided by an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In this application, "at least one group" refers to one or more groups, and "multiple groups" refers to two or more groups. "And/or", describing the association relationship of associated objects, means that there can be three kinds of relationships, For example, A and/or B can mean that A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the associated object is a kind of " "or" relationship. "At least one of the following items" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, a, b or At least one item(s) of c, which can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b and c can be single, or It can be multiple. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used for the same items with basically the same functions and functions or Similar items are distinguished, and those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order. For example, in the first register in the embodiment of the present application, "first" and "Second" in the two registers is only used to distinguish different registers. The descriptions such as the first, the second, etc. appearing in the embodiments of this application are only for the purpose of indicating and distinguishing the description objects, and there is no order, nor does it mean that this The specific limitation on the number of devices in the application embodiment cannot constitute any limitation on the embodiment of the application.

It should be noted that, in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiment or design described in this application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

Figure 2 is a synchronous sequential circuit. As shown in Figure 2, the data output end Q of the register D1 is connected to the input end of the combinational logic, and the output end of the combinational logic is connected to the data input end D of the register D2. The clock terminal CP of the register D1 and the clock terminal CP of the register D2 are connected to the clock signal CLK. The clock valid edges of the clock terminals of the register D1 and the register D2 may be a rising edge or a falling edge. When the valid edge of the clock of register D1 and register D2 is the falling edge, when the clock terminal changes from high level to low level, register D1 or register D2 samples the data input terminal, and sends the sampled value to the data output terminal. When the clock terminal is in other conditions, the data output terminal maintains the original sampling value until the clock terminal changes from high level to low level for the second time. It can be understood that the output of the combinational logic at any moment only depends on the input at that moment, and has nothing to do with the original state of the circuit, and does not involve the processing of signal transition edges. The output of sequential logic at any time depends not only on the input at that time, but also on the original state of the circuit. When the valid edge (rising or falling edge) of the clock arrives, it is possible to make the output change.

In order to achieve proper synchronization of the circuit shown in Figure 2, the data must be stable for a period of time before the valid edge of the clock (eg, rising or falling edge), which is the setup time. The data must also be stable for a period of time after the arrival of the valid edge of the clock, which is the hold time. That is, the data input must remain stable until the actual sampling time arrives, and the data input must also remain stable for a period of time after the sampling time. That is, the circuit can only be properly synchronized if the setup and hold times are met.

It can be understood that when performing timing analysis on the circuit in Figure 2, it can be determined whether the setup time and hold time are satisfied through the delay of the data path and the clock path. timing requirements. as shown in picture 2. The data path refers to the path that data travels from the entire transmission input end to the transmission output end, and the clock path refers to the path that the clock takes to reach each register. When the delay of the data path is greater than the delay of the clock path, the hold time will meet the timing requirements. When the delay of the data path (data path) is less than the delay of the clock path (clock path), the setup time (setup time) will meet the timing requirements.

Usually, in the process of chip design, the simulation is performed based on the process file (spice model) released by the manufacturer (foundry) specializing in the production and manufacture of the chip. During the simulation, the delay delay inside the chip is fixed. However, during the manufacturing process of the chip, due to process deviation, voltage drop, and temperature changes, the delay inside the chip may not be a fixed value, but a random value. In order to make the difference between chip design and manufacturing closer, a static timing analysis (STA) method can usually be used to ensure the timeliness of the design iteration cycle.

For example, in STA, on-chip variation (OCV) can be used to simulate the performance variation between different devices within the chip due to process variation, voltage drop, and temperature variation. When analyzing hold timing violations, you can pessimistically cover the boundary conditions by multiplying the delay value on the data path by a factor less than 1, and multiplying the delay value on the clock path by a factor greater than 1. However, if the boundary conditions are set too strict, the design difficulty will be greatly increased, and at the same time, too many Die resources will be occupied, which will reduce the competitiveness of the product. If the boundary conditions are set too loose, quality problems may occur, resulting in a series of index problems or even failure of the chip to work.

In order to release part of the boundary conditions when the boundary conditions are set too strict to improve the product competitiveness of the chip, a test circuit can be set up in the chip to detect the holding time margin of the chip, and based on the holding time margin The design of the next-generation chip is adjusted so that the product competitiveness of the next-generation chip can be improved.

Figure 1 shows an IP design for detecting time margin. As shown in Figure 1, the IP mainly consists of stdcell to form a delay line, and configures the initial state of the circuit to hold pass successfully. By adjusting the signal configuration of delaySel, you can choose With different delay values, until the circuit appears in the hold fail state, the peripheral circuit detects the pass and fail states of the sequence of the circuit to be tested, and then reads the detection results through the bus to obtain the hold time margin, so as to provide the next step. The upgrade of a generation of chips provides the basis.

However, in the IP design shown in Figure 1, when the retention time margin is detected by the delay line composed of stdcell, the accuracy of the retention time detected by stdcell is ideally about 7 to 8 ps. However, in the process of 28nm and below, the number of timing violations caused by 1ps hold uncertainty may be 100,000 or even millions depending on the size of the SOC. Therefore, if the lack of 7-8ps precision is applied in practical projects, it means that it will face a great risk of timing violation, so this scheme does not have obvious practical engineering significance.

In order to improve the problem of poor detection accuracy of the retention time margin in the chip, an embodiment of the present application provides a detection circuit for maintaining the time margin. The detection circuit detects the retention time margin with high accuracy and can be used for next-generation chips The design provides a basis for improving the product competitiveness of next-generation chips.

It should be noted that, when the detection circuit provided by the following embodiments of the present application detects the holding time margin of the chip, the default chip meets the timing requirement of the setup time.

FIG. 3 is a detection circuit for maintaining a time margin provided by an embodiment of the present application. As shown in FIG. 3 , the detection circuit includes a controller, a generator, and a decision circuit. The generator includes at least one group of test circuits, and each group of test circuits includes N first registers, N second registers, and N data delay units. The delays of the N data delay units are sequentially increased, and two adjacent data delay units are delayed. The delay difference of the unit is less than or equal to the preset value, and N is an integer greater than 1. Among them, the clock terminals of the N first registers (the CP terminals of the first registers) and the clock terminals of the N second registers (the CP terminals of the second registers) are connected to the same clock output terminal of the controller, and the N first registers are connected to the same clock output terminal of the controller. The data output terminals (QN terminals of the first register) are respectively connected with the input terminals of the N data delay units, and the output terminals of the N data delay units are respectively connected with the data input terminals of the N second registers (the D terminal of the second register). ) is connected, and the data output terminals (Q terminals of the second registers) of the N second registers are connected to the decision circuit. The decision circuit is used for detecting the output states of the N second registers, and transmitting the output states of the N second registers to the controller.

Exemplarily, in FIG. 3 , only the data output terminal of the first register is the QN terminal as an example for illustration. As shown in FIG. 3 , when the data output end of the first register is the QN end, the data input end of the first register (the D end of the first register) and the data output end of the first register (the QN end of the first register) connect. Optionally, the data output terminal of the first register may also be the Q terminal. When the data output terminal of the first register is the Q terminal, the data input terminal of the first register (the D terminal of the first register) is connected to the first register. The data output terminals (Q terminals of the first register) are connected through inverters. It can be understood that the data output terminal QN of the first register is the inversion of the data input terminal D of the first register.

Exemplarily, the embodiment of the present application does not limit the specific value of N. In practical applications, the value of N can be determined in combination with the range of the clock delay. The value of N affects the delay size on the data path. The value can make the delay on the data path of some registers in the N groups of registers smaller than the delay on the clock path, and the delay on the data path of another part of the registers is greater than the delay on the clock path. It can be understood that a first register and a second register connected to the register through a data delay unit may be referred to as a group of registers. The embodiments of the present application only take N being 94 as an example for illustration.

Exemplarily, the above-mentioned N data delay units respectively include N S-shaped metal wires. The data delay unit may be made of S-shaped metal wires, and the lengths of the S-shaped metal wires of different data delay units in the N data delay units are different. It can be understood that the turning portion of the S-shaped metal winding may be a right-angle turning, an obtuse-angle turning, or a curved turning, which is not limited in the embodiments of the present application. The following embodiments are only illustrated by taking the turning part of the S-shaped metal winding as a right angle as an example.

For example, as shown in FIG. 4 , each data delay unit is made of S-shaped metal windings, and the N data delay units are respectively made of N S-shaped metal windings, and the lengths of the N S-shaped metal windings are sequentially increases, so the delays of the N data delay units are sequentially increased.

Exemplarily, the time delay difference between two adjacent data delay units in the N data delay units is related to the length difference between two adjacent S-type metal windings, and the difference between adjacent two S-type metal windings is The smaller the length difference is, the smaller the time delay difference between two adjacent data delay units is, and the higher the step accuracy of the delay time is. The greater the length difference between two adjacent S-shaped metal windings, the greater the time delay difference between two adjacent data delay units, and the lower the step accuracy of the delay time. It can be understood that, by designing the length difference between two adjacent S-shaped metal windings, the time delay difference of the two data delay units can be adjusted, so as to ensure a high detection accuracy for maintaining the time margin.

Optionally, the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings may be equal, that is, the lengths of the N S-shaped metal windings increase sequentially, and two adjacent S-shaped metal windings are The lines increase by the same length. It should be noted that, due to the nonlinear characteristics of metal, when the lengths of N S-shaped metal windings increase sequentially, and the two adjacent S-shaped windings increase by the same length, the delays of the N data delay units are sequentially increased. increase, but the delay difference (stepping accuracy) of two adjacent data delay units is not exactly the same.

For example, as shown in FIG. 5 , when the lengths of the S-shaped metal windings from the data delay unit 0 to the data delay unit 21 increase by the same value in sequence, the delays from the data delay unit 0 to the data delay unit 21 increase sequentially, but the adjacent The time delay difference between the two data delay units is nonlinear, that is, the step accuracy of the delay time of two adjacent data delay units is nonlinear. It can be seen from FIG. 5 that the step accuracy of the delay time of two adjacent data delay units is about 1.5ps, so the accuracy of the holding time margin detected by the detection circuit is relatively high.

Exemplarily, as shown in FIG. 3 and FIG. 5 , because the delay delays of the N data delay units connected between the data output terminals of the N first registers and the data input terminals of the N second registers are different, so that The delays on the data paths of the N sets of registers are different. When the delay of the data delay unit is small, if the delay of the data path from the first register to the second register is smaller than the delay of the clock path, then the output state of the second register is hold fail, that is, the chip hold time is not satisfied. timing requirements. When the delay of the data delay unit is sequentially increased to a larger delay, if the delay of the data path from the first register to the second register is greater than the delay of the clock path, the output state of the second register is hold pass, that is, Meet the timing requirements of the chip hold time.

It can be understood that since the delays on the data paths of the above N sets of registers are sequentially increased, the output states of some of the N second registers may be in the hold fail state, and the output states of another part of the registers may be in the hold fail state. The output state of can be a hold pass state. Based on the output states of the N second registers, combined with the simulation results after adding OCV during design or simulation, it can be determined whether the boundary conditions of the design are too strict or too loose.

For example, taking the test result that the output states of the second register 0 to the second register 9 are the hold fail state, and the output states of the second register 10 to the second register 93 are the hold pass state, for example, As shown in FIG. 6 , if the simulation result after adding OCV is that the output state of the second register 0 to the second register 7 is the hold fail state, and the output state of the second register 8 to the second register 93 is the hold failure state (hold pass) state. Then, according to the test results, it can be determined that the time margin reserved in the design stage is insufficient, resulting in a hold violation risk in the test results, that is, the boundary conditions in the design stage are too loose and the chip has a violation risk. It can be understood that only the simulation results and test results of the second register 0 to the second register 11 are shown in FIG. 6 . Since the delays of the data paths from the second register 0 to the second register 93 are sequentially increased, if the second The simulation result or test result of the register 11 is a hold pass, then the simulation results or test results of the second register 12 to the second register 93 are also a hold pass, which is only an exemplary illustration in FIG. 6 . The simulation results and test results of the second register 0 to the second register 11 are shown. It should be noted that Pass in Figure 6 represents hold pass, and Fail represents hold fail.

For another example, take the test result that the output state of the second register 0 to the second register 4 is a hold fail state, and the output state of the second register 5 to the second register 93 is a hold pass state as an example. 7 , if the simulation result after adding OCV is that the output states of the second register 0 to the second register 7 are hold fail states, and the output states of the second register 8 to the second register 93 are the hold fail states Success (hold pass) state. Then, according to the test results and simulation results, since the hold fail of the test is between the simulation results without OCV (without OCV) and the simulation results with OCV, the time margin reserved in the design phase can be determined. If there are too many (that is, the boundary conditions in the design stage are too strict), some constraints can be appropriately relaxed according to the test results, and some boundary conditions can be liberated, so that the next-generation chips are more competitive.

Optionally, as shown in Figure 7, if it is determined that the boundary conditions in the design stage are too strict according to the test results, the boundary conditions of the two stages can be released when designing the next-generation chip based on the test results and simulation results, so that the following Generation products are more competitive.

It can be understood that the test circuit in the embodiment of the present application arranges N S-shaped metal windings between the N first registers and the N second registers, and the lengths of the N S-shaped metal windings increase sequentially, and the The stepping accuracy is related to the length difference between two adjacent S-shaped metal windings, so by designing the length difference between two adjacent S-shaped metal windings, the detection accuracy of maintaining the time margin can be controlled, so that the detection The precision of the retention time margin is high, so based on the detection result, a strong basis can be provided for the design of the next-generation chip, which makes the product competitiveness of the next-generation chip stronger.

In the process of chip physical design, it is difficult to control the metal windings and perform secondary inspection. Therefore, the S-shaped metal windings in the embodiment of the present application can be designed into a splicable module, and the actual implementation is carried out in the top-level module. physical splicing, and indirectly obtain a step-by-step S-shaped winding.

Exemplarily, the S-shaped metal winding may include a first turning portion, a splicable portion and a second turning portion. The S-shaped metal windings can be left and right S-shaped windings or upper and lower S-shaped windings. When the S-shaped metal winding is left and right S-shaped windings, the first turning part is the turning part on the left, the second turning part is the turning part on the right, and the unturned part in the middle is the splicable part. When the S-shaped metal winding is an upper and lower S-shaped winding, the first turning part is the turning part on the upper side, the second turning part is the turning part on the lower side, and the unturned part in the middle is the splicable part.

Exemplarily, different S-shaped metal windings include different numbers of spliceable parts. FIG. 8 takes the S-shaped metal winding as an example of left and right S-shaped windings. As shown in (a) of FIG. 8 , the S-shaped metal winding includes a first turning part, a second turning part and a splicable part. As shown in (b) of FIG. 8 , the S-shaped metal winding includes a first turning portion, a second turning portion, and two splicable portions. That is, S-shaped metal wires of different lengths can be realized by increasing the number of splicable parts. The method has good controllability, can be freely spliced according to the different design scales and the required delay values, and is convenient for secondary inspection, which has good practical engineering significance. It can be understood that the application can modularize the S-shaped metal winding, and each S-shaped metal winding can include three parts (the first turning part, the splicable part and the second turning part). The number of splicable parts can be used to make S-shaped metal windings of different lengths, so that in multiple rounds of design or tape-out, the length of the S-shaped metal windings can be changed by changing the number of splicable parts to adjust the data delay unit. delay.

Exemplarily, the input end and the output end of the S-shaped metal winding may be arranged on the same side, or may be arranged on different sides. When the input end and the output end of the S-shaped metal wire are arranged on the same side, the first turning portion includes the input end and the output end of the S-shaped metal wire, or the second turning portion includes the input end and the output end of the S-shaped metal wire. output. When the input end and the output end of the S-shaped metal winding are arranged on different sides, the first turning portion includes the input end of the S-shaped metal winding, and the second turning portion includes the output end of the S-shaped metal winding; The turning portion includes the output end of the S-shaped metal wire, and the second turning portion includes the input end of the S-shaped metal wire.

It can be understood that the input end of the S-shaped metal wire is connected to the data output end QN of the first register, and the output end of the S-shaped metal wire is connected to the data input end D of the second register. That is, the input end of the S-shaped metal winding is the starting point of the S-shaped metal winding, and the output end of the S-shaped metal winding is the end point of the S-shaped metal winding.

Optionally, the input end and the output end of the S-shaped metal winding may be located on the same horizontal line, or may be located on different horizontal lines.

For example, Fig. 9 takes the S-shaped metal winding as the left and right S-shaped windings as an example. As shown in (a) of Fig. 9, the first turning part includes the input end of the S-shaped metal winding and the S-shaped metal winding. The output end, the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. As shown in (b) of FIG. 9 , the second turning portion includes the input end of the S-shaped metal wire and the output end of the S-shaped metal wire, the input end of the S-shaped metal wire and the output of the S-shaped metal wire The ends are located on different horizontal lines. As shown in (c) of FIG. 9 , the first turning portion includes the input end of the S-shaped metal wire, and the second turning portion includes the output end of the S-shaped metal wire, the input end of the S-shaped metal wire and the S-shaped metal wire. The output ends of the metal windings are located on different horizontal lines. As shown in (d) of FIG. 9 , the second turning portion includes the input end of the S-shaped metal wire, and the first turning portion includes the output end of the S-shaped metal wire, the input end of the S-shaped metal wire and the S-shaped metal wire. The output ends of the metal windings are located on different horizontal lines.

For another example, FIG. 10 takes the S-shaped metal winding as the upper and lower S-shaped windings as an example. As shown in (a) of FIG. 10 , the second turning portion includes the input end of the S-shaped metal winding and the S-shaped metal winding. The output end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on the same horizontal line. As shown in (b) of FIG. 10 , the first turning portion includes the input end of the S-shaped metal wire and the output end of the S-shaped metal wire, the input end of the S-shaped metal wire and the output of the S-shaped metal wire The ends are on the same horizontal line. As shown in (c) of FIG. 10 , the second turning portion includes the input end of the S-shaped metal wire, and the first turning portion includes the output end of the S-shaped metal wire, the input end of the S-shaped metal wire and the S-shaped metal wire. The output ends of the metal windings are located on different horizontal lines. As shown in (d) of FIG. 10 , the first turning portion includes the input end of the S-shaped metal winding, and the second turning portion includes the output end of the S-shaped metal winding, the input end of the S-shaped metal winding and the S-shaped metal winding. The output ends of the metal windings are located on different horizontal lines.

Optionally, the detection circuit provided in this embodiment of the present application may further include a clock selector and a clock delay circuit. As shown in FIG. 11 , the input terminal of the controller and the clock selector, the data selection terminal of the clock selector, and N The clock terminal of the first register is connected, the output terminal of the clock selector is connected to the input terminal of the clock delay circuit, and the output terminal of the clock delay circuit is connected to the clock terminals of the N second registers.

Exemplarily, as shown in FIG. 11 , the clock delay circuit may include M clock delay units, and the M clock delay units have different delays respectively. It should be noted that the value of M is not limited in this embodiment of the present application, and FIG. 11 only shows that M is 32 for illustration.

The controller is specifically configured to time-division and control the clock selector to sequentially select each clock delay unit in the M clock delay units.

Exemplarily, the above-mentioned clock selector may be a multiplexer MUX, and the controller may control the multiplexer MUX by time division. The MUX can be a selector for selecting 1 from M, and the number of data selection terminals A ₀ to A _k in the MUX is related to the specific value of M. For example, the controller controls the multiplexer MUX to select one clock delay unit among the 32 clock delay units at regular intervals to obtain the output state of a group of N second registers, and the controller selects the clock delay unit among the 32 clock delay units in turn. For each clock delay unit, 32 groups of output results can be obtained, and each group of output results is used to indicate the output state of each second register. It can be understood that when the clock delay circuit includes 32 clock delay units, the MUX may be a 32-to-1 selector, and the number of data selection terminals may be 5, that is, the data selection terminals may be A ₀ to A ₄ .

It should be noted that when the output results of the N second registers are all in the hold fail state or all in the hold pass state, the detection result has no practical guiding significance, and the hold time margin cannot be determined. . Only when the output states of the N second registers have both hold fail and hold pass states, can it be determined whether the boundary conditions in the design stage are based on the detection results and the simulation results in the design stage? Too tight or too loose. Therefore, by selecting different clock delay units by time-sharing by the controller, a large-scale adjustment can be performed, so that the output states of the N second registers have both a hold fail state and a hold pass state.

Optionally, the controller may also control the clock selector to select the first clock delay unit in the clock delay module; if the output states of the N second registers are all hold pass, the controller controls the clock selector to select the clock. The second clock delay unit in the delay module, the delay of the second clock delay unit is greater than the delay of the first clock delay unit; if the output states of the N second registers are all hold fail, the controller controls the clock The selector selects a third clock delay unit in the clock delay module, and the delay of the third clock delay unit is smaller than the delay of the first clock delay unit. Through the closed-loop control of the controller, the output states of the N second registers can be made to have both a hold fail state and a hold pass state.

Optionally, the detection circuit provided in this embodiment of the present application may further include an interface circuit. As shown in FIG. 12 , the controller is connected to the interface circuit, and the controller is further configured to transmit the output states of the N second registers to the interface circuit. This interface circuit is used to transmit data to other devices. For example, the interface circuit may transmit the detection results of the test circuit to an external device.

Exemplarily, the above-mentioned FIG. 3 , FIG. 8 and FIG. 9 only take the generator including a set of test circuits as an example for illustration. This embodiment of the present application does not limit the specific number of test circuits included in the generator. For example, the generator may also include two groups of test circuits or three groups of test circuits.

It should be noted that the N first registers and the N second registers included in the same set of test circuits have the same process voltage temperature (PVT), and the PVT may be a standard voltage threshold (SVT) , low voltage threshold (low voltage threshold, LVT) or ultra low voltage threshold (ultra low voltage threshold, ULVT).

For example, as shown in FIG. 13 , the generator includes three groups of test circuits, and the PVTs of the N first registers and the N second registers in the first group of test circuits are both SVTs. The PVTs of the N first registers and the N second registers in the second group of test circuits are both LVTs. The PVTs of the N first registers and the N second registers in the third group of test circuits are both ULVTs.

The test circuit in the embodiment of the present application arranges N S-shaped metal windings between the N first registers and the N second registers, and the lengths of the N S-shaped metal windings are sequentially increased, and the step accuracy of the increment is increased. It is related to the length difference between two adjacent S-shaped metal windings, so by designing the length difference between two adjacent S-shaped metal windings, the detection accuracy of the retention time margin can be controlled, so that the detection retention time margin can be controlled. Therefore, the detection results can provide a strong basis for the design of the next-generation chip, so that the product competitiveness of the next-generation chip is stronger.

The steps of the methods or algorithms described in conjunction with the disclosure of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, Erasable Programmable Read-Only Memory (Erasable Programmable ROM, EPROM), electrically erasable programmable Programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium may reside in an ASIC. Alternatively, the ASIC may be located in the core network interface device. Of course, the processor and the storage medium may also exist in the core network interface device as discrete components.

Those skilled in the art should appreciate that, in one or more of the above examples, the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

The specific embodiments described above further describe the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of the present invention shall be included within the protection scope of the present invention.

Claims (13)

A detection circuit for maintaining a time margin, characterized in that the detection circuit comprises: a controller, a generator and a decision circuit; the generator comprises at least one group of test circuits, and each group of the test circuits comprises Nth A register, N second registers, and N data delay units, the delays of the N data delay units are sequentially increased, and the delay difference between two adjacent data delay units is less than or equal to a preset value, N is an integer greater than 1; wherein, the clock terminals of the N first registers and the clock terminals of the N second registers are connected to the same clock output terminal of the controller, and the data of the N first registers The output ends are respectively connected with the input ends of the N data delay units, the output ends of the N data delay units are respectively connected with the data input ends of the N second registers, and the data of the N second registers The output end is connected with the judgment circuit; The decision circuit is configured to detect the output states of the N second registers, and transmit the output states of the N second registers to the controller. The circuit according to claim 1, wherein the N data delay units respectively comprise N S-shaped metal windings, and the lengths of the N S-shaped metal windings are sequentially increased. The circuit according to claim 2, wherein the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings is the same. The circuit according to claim 3, wherein the S-shaped metal winding includes a first turning part, a second turning part, and one or more splicable parts, and the splicable parts included in different S-shaped metal windings The number of parts varies. The circuit according to claim 4, wherein the first turning portion comprises an input end of the S-shaped metal wire and an output end of the S-shaped metal wire; or, the second turning portion It includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding. The circuit of claim 4, wherein the first inflection portion includes an input end of the S-shaped metal wire, and the second inflection portion includes an output end of the S-shaped metal wire; or , the first turning portion includes the output end of the S-shaped metal winding, and the second turning portion includes the input end of the S-shaped metal winding. The circuit according to any one of claims 1-6, characterized in that, the detection circuit further comprises a clock selector and a clock delay circuit, the controller and the input end of the clock selector, the clock The data selection terminal of the selector is connected to the clock terminal of the N first registers, the output terminal of the clock selector is connected to the input terminal of the clock delay circuit, and the output terminal of the clock delay circuit is connected to the input terminal of the clock delay circuit. The clock terminals of the N second registers are connected. The circuit according to claim 7, wherein the clock delay circuit comprises M clock delay units, and the M clock delay units respectively have M different time delays. The circuit according to claim 8, wherein the controller is specifically configured to time-divisionally control the clock selector to sequentially select each clock delay unit in the M clock delay units. The circuit according to claim 8, wherein the controller is specifically configured to: controlling the clock selector to select a first clock delay unit in the M clock delay units; If the output states of the N second registers are all maintained successfully, the controller controls the clock selector to select the second clock delay unit among the M clock delay units, and the second clock delay unit of the second clock delay unit The delay is greater than the delay of the first clock delay unit; If the output states of the N second registers are all fail to hold, the controller controls the clock selector to select a third clock delay unit among the M clock delay units, and the third clock delay unit The delay is smaller than the delay of the first clock delay unit. The circuit according to any one of claims 1-10, wherein the detection circuit further comprises an interface circuit, the controller is connected to the interface circuit, and the controller is further configured to connect the N The output state of the second register is transmitted to the interface circuit. The circuit according to any one of claims 1-11, wherein the process voltage and temperature PVT of the N first registers and the N second registers in the same group of the test circuits are the same, and the PVT is a standard Voltage Threshold SVT, Low Voltage Threshold LVT or Ultra Low Voltage Threshold ULVT. A device, characterized in that the device comprises a circuit board and the detection circuit for maintaining a time margin according to any one of claims 1-12.

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