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WO2021209789A1 - Structure modificatrice de réseaux neuronaux artificiels en colocalisant des paramètres - Google Patents

Structure modificatrice de réseaux neuronaux artificiels en colocalisant des paramètres Download PDF

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Publication number
WO2021209789A1
WO2021209789A1 PCT/IB2020/053561 IB2020053561W WO2021209789A1 WO 2021209789 A1 WO2021209789 A1 WO 2021209789A1 IB 2020053561 W IB2020053561 W IB 2020053561W WO 2021209789 A1 WO2021209789 A1 WO 2021209789A1
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weights
arrays
ann
neurons
array
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Ludovic Larzul
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Mipsology SAS
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Mipsology SAS
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Priority to EP20727700.5A priority patent/EP4136584A1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections

Definitions

  • ANNs Artificial Neural Networks
  • the human brain contains 10-20 billion neurons connected through synapses. Electrical and chemical messages are passed from neurons to neurons based on input information and their resistance to passing information.
  • a neuron can be represented by a node performing a simple operation of addition coupled with a saturation function.
  • a synapse can be represented by a connection between two nodes.
  • Each of the connections can be associated with an operation of multiplication by a constant.
  • the ANNs are particularly useful for solving problems that cannot be easily solved by classical computer programs. [0003] While forms of the ANNs may vary, they all have the same basic elements similar to the human brain. A typical ANN can be organized into layers, and each of the layers may include many neurons sharing similar functionality. The inputs of a layer may come from a previous layer, multiple previous layers, any other layers, or even the layer itself.
  • Major architectures of ANNs include Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), and Long Term Short Memory (LTSM) network, but other architectures of ANN can be developed for specific applications.
  • CNN Convolutional Neural Network
  • RNN Recurrent Neural Network
  • LTSM Long Term Short Memory
  • ANNs can then be computed in parallel on many different computing elements similar to neurons of the brain.
  • a single ANN may have hundreds of layers. Each of the layers can involve millions of connections. Thus, a single ANN may potentially require billions of simple operations like multiplications and additions. [0004] Because of the larger number of operations and their parallel nature, ANNs can result in a very heavy load for processing units (e.g., CPU), even ones running at high rates.
  • processing units e.g., CPU
  • GPUs graphics processing units
  • GPUs graphics processing units
  • GPUs appear to be more efficient in the computations of ANNs than the CPUs.
  • GPUs are not well suited to the computations of ANNs because the GPUs have been specifically designed to compute graphical images.
  • the GPUs may provide a certain level of parallelism in computations.
  • the GPUs are constraining the computations in long pipes implying latency and lack of reactivity.
  • very large GPUs can be used, which may involve excessive power consumption, which is a typical issue of GPUs. Since the GPUs may require more power consumption for the computations of ANNs, the deployment of GPUs can be difficult.
  • CPUs provide a very generic engine that can execute very few sequences of instructions with a minimum effort in terms of programming, but lack the power of computing for ANN.
  • the GPUs are slightly more parallel and require a larger effort of programming than CPUs, which can be hidden behind libraries with some performance costs but are not very suitable for ANNs.
  • Field Programmable Gate Arrays FPGAs are professional components that can be programmed at the hardware level after they are manufactured. The FPGAs can be configured to perform computations in parallel. Therefore, FPGAs can be well suited to compute ANNs.
  • One of the challenges of FPGAs is the programming, which requires a much larger effort than programming CPUs and GPUs.
  • Adaption of FPGAs to perform ANN computations can be more challenging than for CPUs and GPUs.
  • Most attempts in programming FPGAs to compute ANNs have been focusing on a specific ANN or a subset of ANNs requiring modification of the ANN structure to fit into a specific limited accelerator or providing a basic functionality without solving the problem of computing ANN on FPGAs globally.
  • the computation scale is typically not considered for existing FPGA solutions, with much of the research being limited to a single or few computation engines, which could be replicated.
  • the existing FPGA solutions do not solve the problem of massive data movement required at large scale for the actual ANN involved in real industrial applications.
  • the inputs to be computed with an ANN are typically provided by an artificial intelligence (AI) framework.
  • AI artificial intelligence
  • a system for modifying structure of an ANN by collocating parameters may include one or more processing units.
  • the processing units may receive a plurality of arrays of weights associated with the ANN.
  • the processing units can modify the plurality of arrays of weights to generate a further plurality of further arrays of weights.
  • the modification includes changing locations of weights in the arrays.
  • the weights with changed locations may satisfy criteria for reducing the amount of operations involving the weights in computations of the ANN.
  • Reducing the amount of computation of the ANN can include skipping operations involving the weights.
  • Reducing the amount of computation of the ANN includes positioning the weights at the same position in the arrays to allow performance of operations involving the weights in a single computational cycle.
  • an amount of operations required for computing neurons of the ANN using the further plurality of further arrays of weights can be less than an amount of operations required for computing same neurons of the ANN using the plurality of arrays of weights and 2) outputs of the neurons of the ANN computed using the plurality of arrays of weights are substantially equal to further outputs of the neurons of the ANN computed using the further plurality of further arrays of weights.
  • the processing units can receive a plurality of input values for the ANN.
  • the processing units perform computations of the neurons of the ANN based on the plurality of input values and the further plurality of further arrays of weights by performing the operations to obtain an output of the ANN.
  • the further plurality of the further arrays of weights include a series of weights such that: 1) the operations involving the series of weights and corresponding input values to the neurons are performed in a single computational cycle of computation of the ANN; and 2) each weight of the series of weights satisfies criteria for reducing the operations involving the weight in the computation of the ANN.
  • Reducing the operations can include grouping multiple operations together during the computation of the ANN. Reduction of the operations may include skipping operations in the computations of the ANN.
  • the processing units can determine that the weight satisfies the criteria by comparing the weight to one or more pre-determined reference value. For determining that an operation involving the weights can be skipped, the pre- determined reference values may be set to zero.
  • the operations may include a multiplication or an addition.
  • the modification of the plurality of arrays of weights may include changing an order of arrays in the plurality of arrays of weights.
  • the modification of the plurality of arrays of weights may include inserting at least one additional array of values between two arrays in the plurality of arrays of weights.
  • the modification of the plurality of arrays of weights may include splitting an array of the plurality of arrays of weights into a first array and at least one second array, wherein a size of the first array is less than a size of the array, and wherein the further plurality of further arrays of weights includes the first array.
  • the modification of the plurality of arrays of weights may include determining that each of the plurality of arrays of weights includes a subset of weights, wherein each of the subset of weights satisfies a criterion for skipping the weights from computation of the neurons of the ANN.
  • Modifying each of the plurality of arrays of weights may include removing the subset of weights and realigning the rest of the weights in all the plurality of arrays.
  • the plurality of arrays of weights can be modified to decrease lengths of one of the following: sequences of zero weights located at a same position in subsequent arrays of weights in the plurality of arrays of weights or sequences of non-zero weights located at the same position in subsequent arrays of weights in the plurality of arrays of weights.
  • the processing units can generate an identifier related to an array of weights of the plurality of arrays of weights and associate the identifier with a weight from an array of weights in the further plurality of further arrays of weights.
  • the processing units can identify, based on the identifier, an accumulator for accumulating a result of a multiplication between an input value and the weight of the array of the weights in the further plurality of arrays of weights.
  • the plurality of arrays may include kernels for calculating feature maps in a convolution.
  • a method for modifying structure of an ANN is provided. The method may include receiving, by one or more processing units, a plurality of arrays of weights associated with the ANN. The method may allow modifying, by the one or more processing units, the plurality of arrays of weights to generate a further plurality of further arrays of weights. The modification includes changing locations of weights in arrays.
  • the weights with changed locations satisfy criteria for reducing the amount of operations involving the weights in computation of ANN.
  • Reducing the amount of computations of the ANN may include skipping operations involving the weight.
  • the following conditions are satisfied: 1) an amount of operations required for computing neurons of the ANN using the further plurality of further arrays of weights can be less than an amount of operations required for computing same neurons of the ANN using the plurality of arrays of weights and 2) outputs of the neurons of the ANN computed using the plurality of arrays of weights are substantially equal to further outputs of the neurons of the ANN using the further plurality of further arrays of weights.
  • the method may include receiving, by the one or more processing units, a plurality of input values for the ANN and performing, by the one or more processing units, computations of the neurons of the ANN based on the plurality of input values and the further plurality of further arrays of weights by performing the operations to obtain an output of the ANN.
  • FIG.1 is a block diagram showing an example system wherein a method for modifying structure of ANNs by collocating parameters can be implemented, according to some example embodiments.
  • FIG.2 shows an ANN, neuron, and transfer function, according to an example embodiment.
  • FIG.3 is a flow chart showing training and inference of an ANN, according to some example embodiments.
  • FIG.4 is a block diagram showing an example system for calculating neurons of ANNs, according to an example embodiment.
  • FIG.5 is a block diagram showing an example structure of a convolutional neural network, according to some example embodiments.
  • FIG.6 is a block diagram showing an example modification of an ANN by reordering of kernels, according to an example embodiment.
  • FIG.7 is a block diagram showing an example modification of an ANN by splitting kernels, according to an example embodiment.
  • FIG.8 is a block diagram showing an example complex modification of an ANN, according to an example embodiment.
  • FIG.9 is a block diagram showing an example modification of an ANN by inserting kernels, according to an example embodiment.
  • FIG.10 is a block diagram showing time of computations of neurons of an ANN, according to an example embodiment.
  • FIG.11 is a block diagram showing an example modification of an ANN by reducing size of kernels, according to an example embodiment.
  • FIG.12 is a block diagram showing an example modification of an ANN by aggregating kernels, according to an example embodiment.
  • FIG.13 is a flow chart showing steps of a method for modifying structure of an ANN, according to some example embodiments.
  • FIG.14 shows a computing system that can be used to implement embodiments of the disclosed technology.
  • the terms “or” and “and” shall mean “and/or” unless stated otherwise or clearly intended otherwise by the context of their use.
  • the term “a” shall mean “one or more” unless stated otherwise or where the use of “one or more” is clearly inappropriate.
  • the terms “comprise,” “comprising,” “include,” and “including” are interchangeable and not intended to be limiting.
  • the term “including” shall be interpreted to mean “including, but not limited to.”
  • Embodiments of the present disclosure can be implemented using integrated circuits, for example, CPU, GPU, application-specific integrated circuits (ASICs) or FPGAs.
  • the present technology may be also practiced with programmable logic devices, transistor-based circuits, or various combinations thereof.
  • the methods described herein can be also implemented by hardware modules, software modules, or combinations of both.
  • the methods can also be embodied in computer-readable instructions stored on computer-readable media.
  • module shall be construed to mean a hardware device, software, or a combination of both.
  • a hardware-based module can use one or more microprocessors, FPGAs, ASICs, programmable logic devices, transistor-based circuits, or various combinations thereof.
  • Software-based modules can constitute computer programs, computer program procedures, computer program functions, and the like.
  • a module of a system can be implemented by a computer or server, or by multiple computers or servers interconnected into a network.
  • module may also refer to a subpart of a computer system, a hardware device, an integrated circuit, or a computer program.
  • a system for performing multiple ANN computations may include one or more processing units.
  • the processing units may receive a plurality of arrays of weights associated with the ANN.
  • the processing units may modify the plurality of arrays of weights to generate a further plurality of further arrays of weights.
  • the modification includes changing locations of weights in the array.
  • the weights with changed locations can satisfy criteria for reducing the amount of operations involving the weights in computations of the ANN.
  • reducing the amount of computation of the ANN includes skipping operations involving the weights in computation of the ANN.
  • reducing the amount of computations of the ANN includes locating the weights at the same position in the further arrays.
  • the processing units may receive a plurality of input values for the ANN and perform computations of the neurons of the ANN based on the plurality of input values and the further plurality of further arrays of weights by performing the operations to obtain an output of the ANN.
  • the further plurality of the further arrays of weights may include a series of weights such that: 1) the operations involving the series of weights and corresponding input values to the neurons are performed in a single computational cycle of computation of the ANN; 2) each weight of the series of weights satisfies criteria for reducing the operations involving the weight from the computation of ANN.
  • Technical effects of certain embodiments of the present disclosure can include configuring integrated circuits, ASICs, CPUs, GPUs, FPGAs, or computer systems to perform ANN computations without execution of redundant and unnecessary operations or allowing an increase in a number of operations to be performed in parallel, thereby accelerating the ANN computations.
  • FIG.1 is a block diagram showing an example system 100 for modifying structure of ANNs, according to some example embodiments.
  • the system 100 can be part of a computing system, such as a personal computer, a server, a cloud-based computing recourse, and the like.
  • the system 100 may include one or more processing unit(s) 110 and a memory 120.
  • the memory 120 may include computer-readable instructions for execution by the processing unit(s) 110.
  • the processing unit(s) 110 may include a programmable processor, such as a microcontroller, central processing unit (CPU), and so forth.
  • the processing unit(s) 110 may include an application-specific integrated circuit(s), such as a CPU or a GPU, or programmable logic array(s), such as an FPGA(s), designed to implement the functions performed by the system 100.
  • the system 100 may be installed on a remote server or may be provided via a cloud service residing in a cloud storage.
  • the processing unit(s) 110 may be configured to receive a plurality of arrays of weights associated with the ANN.
  • the processing unit(s) 110 may modify the plurality of arrays of weights to generate a further plurality of further arrays of weights. After the modification, an amount of operations required for computing neurons of the ANN using the further plurality of further arrays of weights is less than an amount of operations required for computing the same neurons of the ANN using the plurality of arrays of weights.
  • outputs of the neurons of the ANN computed using the plurality of arrays of weights are substantially equal to further outputs of the neurons of the ANN computed using the further plurality of further arrays of weights.
  • the amount of operations refers to a total computational complexity of evaluation of neurons of the ANN.
  • the computational complexity of the ANN may depend on a number of mathematical operations required to compute the neurons, computational complexity of the mathematical operations required to compute the neurons, a degree of parallelism that can be achieved in performing the operations of the neurons, and other computational complexity metrics.
  • FIG.2 shows ANN 210, neuron 220, and transfer function 230, according to some example embodiments.
  • the ANN 210 may include one or more input layers 240, one or more hidden layers 250, and one or more output layers 260.
  • Each of the input layers 240, hidden layers 250, and output layers 260 may include one or more (artificial) neurons 220. The number of neurons can be different for different layers.
  • Each of neurons 220 may represent a calculation of a mathematical function [0049] wherein V[i] are neuron input values to a neuron, W[i] are weights assigned to input values to the neuron, and F(X) is a transfer function 230 (also referred as to an activation function 230). Typically, the transfer function 230 F(X) is selected to be zero for X ⁇ 0 and have a limit of zero as X approaches zero.
  • the transfer function F(X) can be linear, in the form of a sigmoid, binary step function, or other activation function used in ANN computations.
  • the result of calculation of a neuron propagates as an input value of further neurons in the ANN.
  • the further neurons can belong to either the next layer, previous layer, or the same layer.
  • FIG.3 is a flow chart 300 showing training 310 and inference 325 of an ANN, according to some example embodiments.
  • the training 310 (also known as learning) is a process of teaching ANN 305 to output a proper result based on a given set of training data 315.
  • the process of training may include determining weights 320 of neurons of the ANN 305 based on training data 315.
  • the training data 315 may include samples. Each of the samples may be represented as a pair of input values and an expected output.
  • the training data 315 may include hundreds to millions of samples. While the training 310 is required to be performed only once, it may require a significant amount of computations and take a considerable time.
  • the ANNs can be configured to solve different tasks including, for example, image recognition, speech recognition, handwriting recognition, machine translation, social network filtering, video games, medical diagnosis, and so forth.
  • the inference 325 is a process of computation of an ANN.
  • the inference 325 uses the trained ANN weights 320 and new data 330 including new sets of input values. For each new set of input values, the computation of the ANN provides a new output which answers the problem that the ANN is supposed to solve.
  • an ANN can be trained to recognize various animals in images.
  • the ANN can be trained on millions of images of animals. Submitting a new image to the ANN would provide the information for animals in the new image (this process being known as image tagging). While the inference for each image takes less computations than training, a number of inferences can be large because new images can be received from billions of sources.
  • the inference 325 includes multiple computations of sum of products: [0054] wherein the V[i] are new input values to a neuron of ANN and W[i] are weights associated with the input values to the neuron.
  • Some previous approaches for performing inference include inspection of the weights W[i] and replacing some of the weights W[i] with zero values if a value of the weight is relatively small when compared to other weights of the ANN. In FIG.3, this process is shown as pruning 335.
  • the pruning 335 generates new weights 340 that then can be used in inference 325 instead of the weights 320. Replacing the weights with zero values may allow decreasing the number of computations of the ANN, since multiplications by zero can be avoided in computations.
  • FIG.4 is a block diagram showing an example system 400 for calculating neurons of ANNs, according to an example embodiment.
  • the system 400 is carried out as a hardware unit.
  • the modifications of arrays of weights described herein involve changing locations of weights within the arrays, changing an order of arrays of weights, extracting common parts in the arrays, and truncating arrays. However, modifications of the arrays described herein do not require changing values of the weights, for example, setting some of the weights to zeros.
  • the modifications of array of weights described herein do not require knowledge of input values for neurons and training sets for ANN.
  • W 1k , W 2k , ... , W Nk the multiplication W 1k ⁇ V l can be omitted, and, hence, only accumulation is needed.
  • the reduction of operations required for computations of the ANN can be also achieved by reducing an amount of “read” operations performed with the memories including memory 120.
  • the modifications of arrays of weights, generating identifiers for arrays of weights, and assigning the identifiers to weights in the modified arrays of weights, and selecting, based on the identifiers, accumulators, can be carried out by one or more processing units 110.
  • the system 400 can be integrated into the system 100 as one of the processing units 110.
  • FIG.5 is a block diagram showing a structure 500 of a single convolution 505 of a CNN, according to some example embodiments.
  • the structure 500 may include input channels 510 and kernels 520.
  • the input channels include input values V ij to neurons of the CNN.
  • the kernels 520 include weight W lk for the input values.
  • the kernels 520 can be less in size than the input channels 510.
  • the results of multiplications of the weights in kernels 520 and the input values in input channels 510 are stored in feature maps 530.
  • Each result F rs is a sum of products of weights of one of kernels 520 and input values in a sliding window within one of the input channels 510, wherein the dimensions of the sliding window correspond to dimensions of the kernels 520.
  • the kernels 520 may include both zero and non-zero weights W lk .
  • the structure of the kernels 520 (which are two- dimensional arrays of weights) can be modified to balance number of zero weights W lk and number of the non-zero weights W lk across the series of the kernels 520.
  • the balancing may allow to arrange some of weights W' kl across the series of the kernels in a such way, that the weights W' kl can be multiplied with corresponding input values V ij in a single computational cycle of a system for performing neuron computations, for example the system 400 shown in FIG.4.
  • FIG.6 is a block diagram showing an example modification of an ANN 600 by reordering of kernels, according to an example embodiment.
  • the ANN 600 include kernels 1, 2, 3, 4, 5, and 6.
  • the kernel 5 and kernel 2 can be changed in order to balance number of zero weights across the series of the kernels.
  • changing order in the kernels 1, 2, 3, 4, 5, and 6 can be carried out to decrease lengths of sequences of non-zero weights located at a same position in subsequent kernels in kernels 810.
  • FIG.7 is a block diagram showing an example modification of an ANN 600 by splitting kernels, according to an example embodiment.
  • each the kernels 520 has Y rows and X columns.
  • Each of the kernels 520 includes submatrices of Y-B rows and X-A columns (A>0, B>0), wherein the submatrices include non-zero weights W lk .
  • Each of the kernels 520 includes submatrix of Y-B columns and A rows, wherein all weight W lk are zero.
  • the kernels 520 can be split in kernels 710-1, kernels 710-2, and kernels 710-K.
  • the kernels 710-1 has Y-B rows and X-A columns and include corresponding weights located in first Y-B rows and X-A columns of original kernels 520.
  • the kernel 710-2 has B rows and first X-A columns and include corresponding weights located in the last B rows and the first X-A columns of original kernels 520.
  • the kernels 710-K have B rows and A columns and include corresponding weights located in the last B rows and the last A columns of the original kernels 520.
  • the weights located in the first Y-B rows and the last A columns of the original kernels 520 can be excluded from computations of ANN 700.
  • the computations of ANN can further proceed with the kernels 710-1, 710-2, and 710-K only.
  • FIG.8 is a block diagram showing an example complex modification of an ANN 800, according to an example embodiment.
  • the ANN 800 includes kernels 520.
  • the kernels 520 includes a series of kernels 1, 2, 3, 4, 5, and 6.
  • the modification of the kernels may start with dividing the kernels 520 in the kernels 810 and the kernels 820.
  • the kernels 810 may include a series of kernels 1, 2, 4, and 6 of the original kernels 520.
  • the kernels 820 may include a series of kernels 3 and 5 of the original kernels 520. [0068]
  • the separation of the kernels 520 into kernels 810 and kernels 820 can be performed, for example, to collocate zero elements at the same positions in subsequent kernels.
  • the kernels 810 can be then reduced in size to obtain kernels 830.
  • the kernels 830 may include a series of kernels 1’, 2’, 4’, and 6’.
  • the kernels 820 can be then split into kernels 840 and kernels 850.
  • the kernels 840 may include series of kernels 3’ and 5’.
  • the kernels 840 may include series of kernels 3'' and 5''.
  • the kernels 3’, 5’, 3'', and 5'' are smaller in size than the kernels 3 and 5.
  • the kernels 3’, 5’, 3’’, and 5’’ can include submatrices of the kernels 3 and 5. Some of zero weights of the kernels 3 and 5 may not be included in the kernels 3’, 5’, 3’’, and 5’’.
  • FIG.9 is a block diagram showing an example modification of an ANN 900 by inserting kernels, according to an example embodiment.
  • the ANN 800 includes a series of kernels 520.
  • the kernels 520 include kernels 1, 2, 3, 4, 5, and 6.
  • the series of kernels 520 are modified to insert kernel 2’ between original kernels 2 and 3 and kernel 4’ between original kernels 4 and 5.
  • the kernels 2’ and 4’ may include only zero weights.
  • the kernels 2 and 2’ resulting from inserting kernel 2’ can be equivalent to the original kernel 2.
  • the resulting kernels 910 may include a series of kernels 1, 2, 2’, 3, 4, 4’, 5, and 6, wherein number of zero weights and number of non- zero weights are balanced across the series. Balancing numbers of zero and non-zero weights across the kernels may increase times needed for processing of some streams formed by weights of kernels 520. However, the balancing numbers of the zero and non-zero weights across the kernels 910 may reduce total time for processing of all streams of weights of the kernels 520 in ANN.
  • FIG.10 is a block diagram 1000 showing time of computations of neurons of the ANN 900, according to an example embodiment.
  • FIG.11 is a block diagram showing an example modification of an ANN 1100 by reducing size of kernels, according to an example embodiment.
  • the ANN 1100 may include kernels 1110.
  • the kernels 1110 may include a series of kernels 1, 2, 3, and 4.
  • the kernels 1110 can be modified to collocate columns and/or rows including zero weights.
  • the results of modification of kernels 1110 are kernels 1120 including a series of kernels 1’, 2’, 3’, and 4’.
  • the kernels 1120 can be reduced in size by truncating rows and/or columns including only zero weights.
  • the results of modification of the kernels 1120 are kernels 1130.
  • the kernels 1130 include kernel 1'', 2'', 3'', and 4''.
  • the kernel 3'' and 4'' can be further reduced in size by truncated columns including only zero weights.
  • computations of ANN 1100 using the kernels 1130 may require less multiplications than computation of ANN 1100 using the original kernels 1110.
  • FIG.12 is a block diagram showing an example modification of an ANN 1200 by aggregating kernels, according to an example embodiment.
  • the ANN 1200 includes kernels 1210.
  • the kernels 1210 includes a series of kernels 1, 2, 3, 4, 5, and 6.
  • the kernels 1210 can be aggregated to for a single kernel 1220.
  • the kernel 1220 incudes sequences of weights 1230, 1240, and 1250.
  • the sequence 1230 includes zero weights of original kernels 1 and 2.
  • the sequence 1240 includes zero weights of the original kernel 2 and 3.
  • the sequence 1250 includes zero weights of the original kernel 4 and 5.
  • FIG.13 is a flow chart showing steps of a method for modifying structure of artificial neural networks, according to some example embodiments.
  • the method 1300 may be implemented by system 100.
  • the method 1300 may commence in block 1305 with receiving, by one or more processing units, a plurality of arrays of weights associated with the ANN. [0078] In block 1310, the method 1300 may include modifying, by the one or more processing units, the plurality of arrays of weights to generate a further plurality of further arrays of weights. The modification may change locations of weights. The weights with the changed locations may satisfy criteria for reducing operations required for computation of ANN.
  • an amount of operations required for computing neurons of the ANN using the further plurality of further arrays of weights is less than an amount of operations required for computing same neurons of the ANN using the plurality of arrays of weights; and 2) outputs of the neurons of the ANN computed using the plurality of arrays of weights are substantially equal to further outputs of the neurons of the ANN using the further plurality of further arrays of weights.
  • the further plurality of the further arrays of weights include a series of weights such that: 1) the operations involving the series of weights and corresponding input values to the neurons are performed in a single computational cycle of computation of the ANN; and 2) each weight of the series of weights satisfies criteria for reducing the operations involving the weight in the computation of ANN.
  • the plurality of arrays of weights is modified to decrease lengths of sequences of zero weights located at the same position in subsequent arrays of weights in the plurality of arrays of weights.
  • the plurality of arrays of weights is modified sequences of non-zero weights located at the same position in subsequent arrays of weights in the plurality of arrays of weights.
  • the modification of the plurality of arrays of weights may changing an order of arrays in the plurality of arrays of weights.
  • the modification of the plurality of arrays of weights may include splitting an array of the plurality of arrays of weights into a first array and at least one second array, wherein a size of the first array is less than a size of the array, and wherein the further plurality of further arrays of weights includes the first array.
  • the modification of the plurality of arrays of weights may include inserting at least one additional array of values between two arrays in the plurality of arrays of weights.
  • the method 1300 may include receiving, by the one or more processing units, a plurality of input values for the ANN.
  • the method 1300 may include performing, by the one or more processing units, computations of the neurons of the ANN based on the plurality of input values and the further plurality of further arrays of weights by performing the operations to obtain an output of the ANN.
  • FIG.14 illustrates an example computing system 1400 that may be used to implement embodiments described herein.
  • the example computing system 1400 of FIG. 14 may include one or more processors 1410 and memory 1420.
  • Memory 1420 may store, in part, instructions and data for execution by the one or more processors 1410.
  • Memory 1420 can store the executable code when the exemplary computing system 1400 is in operation.
  • the processor 1410 may include internal accelerators like a GPU, a FPGA, or similar accelerators that may be suitable for use with embodiments described herein.
  • the memory 1420 may include internal accelerators like a GPU, a FPGA, or similar accelerators that may be suitable for use with embodiments described herein.
  • the example computing system 1400 of FIG. 14 may further include a mass storage 1430, portable storage 1440, one or more output devices 1450, one or more input devices 1460, a network interface 1470, and one or more peripheral devices 1480. [0085]
  • the components shown in FIG.14 are depicted as being connected via a single bus 1490. The components may be connected through one or more data transport means.
  • Mass storage 1430 which may be implemented with a magnetic disk drive, an optical disk drive, or a solid state drive (SSD), is a non-volatile storage device for storing data and instructions for use by a magnetic disk, an optical disk drive, or SSD, which in turn may be used by one or more processors 1410. Mass storage 1430 can store the system software for implementing embodiments described herein for purposes of loading that software into memory 1420.
  • the mass storage 1430 may also include internal accelerators like a GPU, a FPGA, or similar accelerators that may be suitable for use with embodiments described herein.
  • Portable storage 1440 may operate in conjunction with a portable non-volatile storage medium, such as a compact disk (CD) or digital video disc (DVD), to input and output data and code to and from the computing system 1400 of FIG. 14.
  • the system software for implementing embodiments described herein may be stored on such a portable medium and input to the computing system 1400 via the portable storage 1440.
  • One or more input devices 1460 provide a portion of a user interface.
  • the one or more input devices 1460 may include an alphanumeric keypad, such as a keyboard, for inputting alphanumeric and other information, or a pointing device, such as a mouse, a trackball, a stylus, or cursor direction keys. Additionally, the computing system 1400 as shown in FIG.14 includes one or more output devices 1450. Suitable one or more output devices 1450 include speakers, printers, network interfaces, and monitors.
  • Network interface 1470 can be utilized to communicate with external devices, external computing devices, servers, and networked systems via one or more communications networks such as one or more wired, wireless, or optical networks including, for example, the Internet, intranet, LAN, WAN, cellular phone networks (e.g., Global System for Mobile communications network, packet switching communications network, circuit switching communications network), Bluetooth radio, and an IEEE 802.11-based radio frequency network, among others.
  • Network interface 1470 may be a network interface card, such as an Ethernet card, optical transceiver, radio frequency transceiver, or any other type of device that can send and receive information.
  • Other examples of such network interfaces may include Bluetooth ® , 3G, 4G, and WiFi ® radios in mobile computing devices as well as a USB.
  • One or more peripheral devices 1480 may include any type of computer support device to add additional functionality to the computing system.
  • the one or more peripheral devices 1480 may include a modem or a router.
  • the example computing system 1400 of FIG.14 may also include one or more accelerator devices 1485.
  • the accelerator devices 1485 may include PCIe-form-factor boards or storage-form-factor boards, or any electronic board equipped with a specific electronic component like a GPU, a Neural Processing Unit, a Multi-CPU component, a FPGA component, or similar accelerating electronic or photonic components, that may be suitable for use with embodiments described herein.
  • the exemplary computing system 1400 of FIG.14 can be a personal computer, handheld computing device, telephone, mobile computing device, workstation, server, minicomputer, mainframe computer, or any other computing device.
  • the computer can also include different bus configurations, networked platforms, multi-processor platforms, and so forth.
  • Various operating systems (OS) can be used including UNIX, Linux, Windows, Macintosh OS, Palm OS, and other suitable operating systems.
  • OS operating systems
  • Some of the above-described functions may be composed of instructions that are stored on storage media (e.g., computer-readable medium).
  • the instructions may be retrieved and executed by the processor.
  • Some examples of storage media are memory devices, tapes, disks, and the like.
  • the instructions are operational when executed by the processor to direct the processor to operate in accord with the example embodiments.
  • Those skilled in the art are familiar with instructions, processor(s), and storage media.
  • any hardware platform suitable for performing the processing described herein is suitable for use with the example embodiments.
  • the terms “computer-readable storage medium” and “computer-readable storage media” as used herein refer to any medium or media that participate in providing instructions to a CPU for execution. Such media can take many forms, including, but not limited to, non- volatile media, volatile media, and transmission media.
  • Non-volatile media include, for example, optical or magnetic disks, such as a fixed disk.
  • Volatile media include dynamic memory, such as RAM.
  • Transmission media include coaxial cables, copper wire, and fiber optics, among others, including the wires that include one embodiment of a bus. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency and infrared data communications.
  • Computer-readable media include, for example, a floppy disk, a flexible disk, a hard disk, magnetic tape, any other magnetic medium, SSD, a CD-read-only memory (ROM) disk, DVD, any other optical medium, any other physical medium with patterns of marks or holes, a RAM, a PROM, an EPROM, an EEPROM, a FLASHEPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.
  • Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to a CPU for execution.
  • a bus carries the data to system RAM, from which a CPU retrieves and executes the instructions.
  • system RAM can optionally be stored on a fixed disk either before or after execution by a CPU.
  • the instructions or data may not be used by the CPU but be accessed in writing or reading from the other devices without having the CPU directing them.

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Abstract

L'invention concerne des systèmes et des procédés destinés à modifier la structure d'un réseau neuronal artificiel (ANN). Un procédé illustratif consiste à recevoir, par une ou plusieurs unités de traitement, une pluralité de matrices de poids associés à l'ANN, à modifier, par les unités de traitement, la pluralité de matrices de poids pour générer une autre pluralité d'autres matrices de poids. Après la modification, les conditions suivantes sont satisfaites : une quantité d'opérations requises pour calculer des neurones de l'ANN au moyen de l'autre pluralité d'autres matrices de poids est inférieure à une quantité d'opérations requises pour calculer les mêmes neurones de l'ANN au moyen de la pluralité de matrices de poids ; et des sorties des neurones de l'ANN calculés au moyen de la pluralité de matrices de poids sont sensiblement égales à d'autres sorties des neurones de l'ANN au moyen de l'autre pluralité d'autres matrices de poids.
PCT/IB2020/053561 2020-04-15 2020-04-15 Structure modificatrice de réseaux neuronaux artificiels en colocalisant des paramètres Ceased WO2021209789A1 (fr)

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